On Thu, Oct 13, 2011 at 11:43:35AM -0700, Richard Henderson wrote:
On 10/13/2011 11:36 AM, David Edelsohn wrote:
Are there testcases in the GCC testsuite that exercise these patterns?
I thought the vectorizer would use them. E.g. gcc.dg/vect/vect-shift-3.c.
I see that I should have added
On Wed, Oct 12, 2011 at 6:32 PM, Richard Henderson r...@redhat.com wrote:
I suppose technically the middle-end could be improved to implement
ashlmode as vashlmode by broadcasting the scalar, but Altivec
is the only extant SIMD ISA that would make use of this. All of
the others can arrange
On Wed, Oct 12, 2011 at 6:32 PM, Richard Henderson r...@redhat.com wrote:
I suppose technically the middle-end could be improved to implement
ashlmode as vashlmode by broadcasting the scalar, but Altivec
is the only extant SIMD ISA that would make use of this. All of
the others can arrange
From: Richard Henderson r...@redhat.com
Date: Wed, 12 Oct 2011 15:32:46 -0700
I suppose technically the middle-end could be improved to implement
ashlmode as vashlmode by broadcasting the scalar, but Altivec
is the only extant SIMD ISA that would make use of this. All of
the others can
On 10/12/2011 03:37 PM, David Miller wrote:
From: Richard Henderson r...@redhat.com
Date: Wed, 12 Oct 2011 15:32:46 -0700
I suppose technically the middle-end could be improved to implement
ashlmode as vashlmode by broadcasting the scalar, but Altivec
is the only extant SIMD ISA that would
From: Richard Henderson r...@redhat.com
Date: Wed, 12 Oct 2011 15:49:28 -0700
Ok, if I read the rtl correctly, you can perform a vector shift,
where each shift count comes from the corresponding element of op2.
But VIS has no vector shift where the shift count comes from a
single scalar
