After all that, I forgot to mention the line length. Rule of thumb: if
the first reflection gets back to the driver before the driver has
finished transitioning, then you probably don't have a problem, and you
don't need termination. In your case, that's 12", or about 1ns. So, if
your drivers h
The schematics printed with gschem used to have a very elegant and polished
style. Now, after having upgraded to the latest and greatest version, I notice
that graphic lines (including component symbols) are much lighter/thinner than
nets, thus degrading elegance and readability. The problem is
On Wednesday 20 September 2006 22:42, Stuart Brorson wrote:
> I suspect user error, and think he should do some more
> reading and investigating before posting bleats to geda-user.
Even if it is user error, it deserves attention. Almost 100% of the bug
reports for gnucap since its beginning hav
kmk wrote:
Arthur Baldwin wrote:
Minor details are just that: Minor details.
They won't swing much opinion. After all, we are not talking about the
average windows Joe, but EEs who already experienced some other EDA
application. To them other arguments matter more: Can my former
schematics, la
"John Luciani" <[EMAIL PROTECTED]> writes:
> Why couldn't you replace the diodes with shorts and use BJT's rather than
> MOSFETs?
I prototyped a circuit with one NPN and one PNP transistor, with an
LED/resistor between their collectors. With even a 1M resistor
between the bases (and no other con
> Yeah, I can understand that. The lines do work, but they're a bit
> tricky, since you have to account for line width when figuring out
> the length. Thanks for your help!
Ok, I just checked in a patch to convert rectangular polygons to pads
also. It doesn't do the reverse because you'll lose
Hi
On 9/21/06, Francisco Colinas <[EMAIL PROTECTED]> wrote:
Hello everybody,
I have just installed gEDA Suite over cygwin but, although I can run gschem,
pcb-bin, etc, I can't or I don't know how to launch gSpiceUI. I mean I must
run before nspice, after, with some parmeters (I have done it in
So, for this project I'm doing, I wanted a footprint providing a hole
for #4 hardware, with a pad that would clear the corners of a hex
stand-off that is 1/4 inch across the flats.
Of course, being an Old Time Unix Programmer(TM), instead of creating a
trivial 4-line text file with vi, before
On Thu, 2006-09-21 at 10:14, ptay wrote:
> Vaughn Treude wrote:
>
> > pads into something the program would understand. It sure would be cool
> > if you could create pads using the rectangle tool.
>
Thanks for the suggestion. I actually did do a couple of them by the
text method, but it was t
> Yeah, I can understand that. The lines do work, but they're a bit
> tricky, since you have to account for line width when figuring out
> the length. Thanks for your help!
Why do you think I write scripts to do it for me ? ;-)
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On Thu, 2006-09-21 at 09:07, DJ Delorie wrote:
> > I was hoping there was some arcane command that could convert
> > the pads into something the program would understand. It sure would
> > be cool if you could create pads using the rectangle tool.
>
> Yeah, that would be cool. However, rectangl
> I believe that because some board fab houses refuse to apply rs274x
> erasures to silk layers, the silk clipping was intentionally
> removed.
Right. Even 4pcb puts a hold on orders with silk overlapping mask
holes (they can cut them or leave them, but they ask first), so we
stopped trying to c
I cleaned up all my footprints so there are no ElementLines on the
pads, and put the refdes's in good locations, but on a tight board you
usually just have to turn-off the refedes, when it barely clips the
pad or mask openings. It'd be great if PCB would clip these things to
guarantee clea
> If you can afford a 4 layer, you can definitely afford a faster scope.
It's not just the cost, it's the justification and size. I just got a
500MHz logic analyzer that's the size of my hand (Intronix Logicport)
and I have a 32Ms/s parallel-port scope (er, about 10-15MHz) and a Tek
561A (er, ab
On Thu, Sep 21, 2006 at 01:48:48PM -0400, DJ Delorie wrote:
>
> > > Double sided, 0.062.
> >
> > How quaint. ;-)
>
> Yeah, well, it's just going to sit on my desk anyway. Plus, it's
> panelized with the challenge boards, so cost is an issue. I was extra
> careful about adding planes to the bo
Günter Dannoritzer wrote:
> Where does this ivl_lval_width come from? I did a search through the
> source and it is defined as extern?
>
> How can I resolve that compile problem?
Try adding ivl_lval_width to the ivl.def file in the main source
directory, then rebuild from the top down. It looks
Hi,
I tried to compile Icarus Verilog snapshot 20060809 under cygwin. I
found a bug report about that setup not to compile correct. Along with
that bug report came the patch pr1541452.patch which is applied to the
source.
When I compile the code I am getting a linker error for the tgt-vvp folder:
DJ Delorie wrote:
> That was me.
Good job!
To each saint his candle.
---<(kaimartin)>---
--
Kai-Martin Knaak
[EMAIL PROTECTED]
http://lilalaser.de/blog
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Harry Eaton wrote:
> That would be like the insert point tool.
> Use all-direction lines mode if you want to bend the lines at any
> arbitrary angle.
Thank you for hinting. For some reason the insert point tool was under
my radar.
> All this is to say that the capability exists now although it
> Only if it was created in the last five minutes. "I just checked
> in..."
He He, oops :-)
OK thanks, I applied the patch to the pcb-20060822 tar ball. It fixed
the problem and I generated my Gerbers OK. Thank you very much - I
really appreciate the fast fix!
Cheers,
David
__
Arthur Baldwin wrote:
> But most apps that either come with Fedora or are popular "add ons"
> for Fedora also have GUI installers that work 10 times better
Funny, I always thought the whole concept of installers is incompatible
with the distro way of application management. Come to think of it,
> Does the 20060907 gEDA ISO include these patches? I was thinking that
> might be the easiest way to update.
Only if it was created in the last five minutes. "I just checked
in..."
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Thank you for both replies DJ.
Does the 20060907 gEDA ISO include these patches? I was thinking that
might be the easiest way to update.
- David
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> > things I love about PCB is the fact that
> > there are single key commands, to switch layers, and choose
> > tools, etc. This means I can work two handed, making it faster,
> > and reducing RSI.
>
> Full ack.
> pcb excels in this.
> Being able to increment sizes with a single key is a big bon
Hugo Elias wrote:
> things I love about PCB is the fact that
> there are single key commands, to switch layers, and choose
> tools, etc. This means I can work two handed, making it faster,
> and reducing RSI.
Full ack.
pcb excels in this.
Being able to increment sizes with a single key is a big b
DJ Delorie wrote:
I'm thinking I should design in some series resistors on the address
and data lines for my RAM expansion board (30MHz, about 6" of 8 mil
trace on DS FR4, 5v). How does one go about calculating an ideal
resistance? The mcu spec doesn't have a min rise time spec, the ram
chips a
I've checked in two patches for this; either would fix the problem.
Here's the shorter one:
Index: mymem.c
===
RCS file: /cvsroot/pcb/pcb/src/mymem.c,v
retrieving revision 1.21
diff -p -U2 -r1.21 mymem.c
--- mymem.c 2 Aug 2006 15
Hi,
I am using PCB version 20060822. When I try and generate gerbers from
this PCB file:
http://www.rowetel.com/ucasterisk/downloads/fxsmod.pcb
PCB exits immediately with this message:
$ pcb-bin (3397): fatal, out of memory during realloc() in
'RoundDrillInfo'()
Can anyone pls suggest a work
Export it to the "bom" exporter. That generates bill-of-materials
(*.bom) and X-Y (*.xy) text files.
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Hi,
I am using PCB version 20060822. How do I generate a pick and place
file? On previous versions of PCB this seemed to be generated when I
generated gerbers.
However on this version when I hit File-Export (press Gerber button) I
get these files:
-rw-rw-r-- 1 david david 85266 Sep 22 05:4
> Precisely -- maybe PCB already does this (?),
No, just saying what you should be asking for ;-)
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joeft wrote:
Phil,
You didn't mention whether this was "incidental" silkscreen like a
"ElementLine" that overlapped the pad or something related to the pad
itself.. A previous version of pcb would in some cases generate
silkscreen rectangles in the gerber output on some surface mount pads
Phil,
You didn't mention whether this was "incidental" silkscreen like a
"ElementLine" that overlapped the pad or something related to the pad
itself.. A previous version of pcb would in some cases generate
silkscreen rectangles in the gerber output on some surface mount pads.
I was never
DJ Delorie wrote:
What you want is a DRC check that silk shouldn't overlap mask
openings.
Precisely -- maybe PCB already does this (?), a year ago it did not
appear to. I suspect it runs into the complication of the mask
exclusion layer situation, one of the things that PCB cannot do
intu
> About a year ago I got some boards back with silkscreen printed over
> some pads. Since, I've manually kept the silkscreen off the pads. ...
> Does MinMaskGap work on silk too?
No, it just adjusts the Mask setting in each pad, it doesn't try to
clip anything else on the board.
What you wan
DJ,
About a year ago I got some boards back with silkscreen printed over
some pads. Since, I've manually kept the silkscreen off the pads. ...
Does MinMaskGap work on silk too?
Phil
DJ Delorie wrote:
F.1.41 MinMaskGap
MinMaskGap(delta)
MinMaskGap(Selected, delta)
Ensures the mask i
> Why couldn't you replace the diodes with shorts and use BJT's rather than
> MOSFETs?
I worry that Ibe (Or Ir) would be enough to turn on the other
transistor. The tricky part is tri-stating the output when the input
is tri-stated; it's intended to be a tri-state amplifier, not a
bi-state ampli
On 9/21/06, DJ Delorie <[EMAIL PROTECTED]> wrote:
Been thinking about what it would take to convert to all 3.3v (outside
the last stage I/O drivers) in the furnace project. I was thinking
how hard it would be to get mosfets with a small enough Vgs for my
last I/O port plan (Vgs would need to be
Hello everybody, I have just installed gEDA Suite over cygwin but, although I can run gschem, pcb-bin, etc, I can't or I don't know how to launch gSpiceUI. I mean I must run before nspice, after, with some parmeters (I have done it in the two ways...) The docs of gSpice is unaccesible today
Hello everybody, I have just installed gEDA Suite over cygwin but, although I can run gschem, pcb-bin, etc, I can't or I don't know how to launch gSpiceUI. I mean I must run before nspice, after, with some parmeters (I have done it in the two ways...) The docs of gSpice is unaccesible today
> > Double sided, 0.062.
>
> How quaint. ;-)
Yeah, well, it's just going to sit on my desk anyway. Plus, it's
panelized with the challenge boards, so cost is an issue. I was extra
careful about adding planes to the bottom side, and bypassing all over
the place.
The proto-pcb industry is star
Been thinking about what it would take to convert to all 3.3v (outside
the last stage I/O drivers) in the furnace project. I was thinking
how hard it would be to get mosfets with a small enough Vgs for my
last I/O port plan (Vgs would need to be less than 1v) when it
occurred to me that I can use
DJ -
On Thu, Sep 21, 2006 at 12:18:46PM -0400, DJ Delorie wrote:
> Double sided, 0.062.
How quaint. ;-)
The board I'm in the middle of bringing up is 6-layer, 0.045.
I've probably linked to it before:
http://recycle.lbl.gov/llrf4/
So the distance between a trace and its ground plane is
an orde
On Thursday 21 September 2006 16:08, Dave McGuire wrote:
> On Sep 21, 2006, at 10:32 AM, Giorgenes Gelatti wrote:
> > I'm new to electronics, geda and this list.
> > I've read some tutorial in the net but end up with this question:
> > I've done a simple schematic in geda and exported it to PCB via
Vaughn Treude wrote:
pads into something the program would understand. It sure would be cool
if you could create pads using the rectangle tool.
There is the sheet explaining the footprints I read to learn the
footprints ... you learn it and writing footprints by hand is pretty
easy until
I'd say that you definately want to include Icarus Verilog and
GTKwave. They are both very useful apps, and belong in the toolbox
of a budding EE.
As for VBS, I have a feeling it is a dead project, and has been for
some time.
Stuart
On Thu, 21 Sep 2006, Peter Clifton wrote:
Hi,
I'm just p
Hi,
I'm just putting together the list of packages to stick on our CD. Does
anyone know if "vbs" version 1.4.0 is useful. I've not used it
personally, but believe it may be handy?
These are the versions I'm looking to include so far:
(=== is already compiled it)
(+++ is needs doing)
(??? is unde
> 5 Volts? How quaint.
Yeah, well, that's what the eval board uses. My furnace controller
uses 5v too, because that's what the LCD panels need. It throws in a
bunch of issues about level converting, though.
> You didn't give the thickness of the FR4 between the trace and the
> ground plane.
DJ -
On Thu, Sep 21, 2006 at 11:47:38AM -0400, DJ Delorie wrote:
> I'm thinking I should design in some series resistors on the address
> and data lines for my RAM expansion board (30MHz, about 6" of 8 mil
> trace on DS FR4, 5v).
5 Volts? How quaint.
You didn't give the thickness of the FR4 bet
> I was hoping there was some arcane command that could convert
> the pads into something the program would understand. It sure would
> be cool if you could create pads using the rectangle tool.
Yeah, that would be cool. However, rectangles are just one
simplification of polygons; they're stor
I installed geda and related packages just now on my Debian Etch machine:
$> sudo apt-get install geda geda-utils geda-gsymcheck geda-examples
geda-gattrib gerbv
But when I try to start gschem, I get:
--
$> gschem
gEDA/gschem ve
On Thu, 2006-09-21 at 07:26, DJ Delorie wrote:
> > I am trying to create a
> > footprint for an SMT device (it's an SDIP, which doesn't appear to be in
> > the library.) The manufacturer spec gave me the exact dimensions for
>
> http://www.gedasymbols.org/user/dj_delorie/tools/dilpad.html
>
> >
I'm thinking I should design in some series resistors on the address
and data lines for my RAM expansion board (30MHz, about 6" of 8 mil
trace on DS FR4, 5v). How does one go about calculating an ideal
resistance? The mcu spec doesn't have a min rise time spec, the ram
chips are 20ns (50MHz) and
Stuart Brorson wrote:
On Thu, 21 Sep 2006, Alessandro Baretta wrote:
(component-library "${PWD}")
I don't know if guile is clueful enough to expand and evaluate ${PWD}.
Try putting in the actual directory name
(i.e. "/foo/bar/baz"). Alternately, look up the Scheme function which
returns the
On Sep 21, 2006, at 9:09 AM, Vaughn Treude wrote:
I didn't mean to imply that it was badly designed, just that it was
the
earliest program in the suite, and it was written for an OS that's
not
(to my knowledge) in common use anymore. Therefore it may have been
designed to different standards.
Thanks to DJ and John for quick responses.
As you both guessed, I once again proved that I am a bonehead. After
posting, I discovered two additional rats hiding in the corner of the
board. I connected those two nets, and then when I hit "o" to refresh
the rats I got the "congratulations, you ar
On Sep 21, 2006, at 10:32 AM, Giorgenes Gelatti wrote:
I'm new to electronics, geda and this list.
I've read some tutorial in the net but end up with this question:
I've done a simple schematic in geda and exported it to PCB via
gsch2pcb.
After drawing the soldering lines by hand in pcb I got t
On 9/21/06, Igor2 <[EMAIL PROTECTED]> wrote:
Of course, it would make more sense if HIDs could be loaded runtime
:) Before that, there could be 2 binaries and on download and/or install
and/or ./configure the user could choose. I'm not sure how comfortable to
manage 2 branches of the mostly same
On Sep 21, 2006, at 8:46 AM, DJ Delorie wrote:
I didn't mean to imply that it was badly designed, just that it was
the
earliest program in the suite, and it was written for an OS that's
not
(to my knowledge) in common use anymore. Therefore it may have been
designed to different standards.
On 9/21/06, Stuart Brorson <[EMAIL PROTECTED]> wrote:
PCB gurus,
I am editing a PCB design I created some months ago. I made some mods
to my schematic, re-ran gsch2pcb, imported the changes (both
footprints and netlist), put down teh new footprints and re-drew the
tracks.
Now I think I am done
On Sep 21, 2006, at 8:36 AM, Alessandro Baretta wrote:
Hello gentlemen.
Could not find [starglazing-my2006_1.sch] in any SourceLibrary
Cannot find source [starglazing-my2006_1.sch]
This is the error message gschem produces in the status pane when I
execute Hierarchy -> Down Schematic (Shi
> Now I think I am done with the board. With a new board PCB
> will pop up a "routing complete" message when all connections are
> made. However, I am not getting that message, even though I see no
> rats anywhere.
Make sure the message dialog is already open, and cleared. Hit 'o'.
If no messa
Alessandro Baretta wrote:
Hello gentlemen.
Could not find [starglazing-my2006_1.sch] in any SourceLibrary Cannot find
source [starglazing-my2006_1.sch]
(component-library "${PWD}")
The current library is effectively included in the path: it appears in the
"Select Component..." dialog box, ye
PCB gurus,
I am editing a PCB design I created some months ago. I made some mods
to my schematic, re-ran gsch2pcb, imported the changes (both
footprints and netlist), put down teh new footprints and re-drew the
tracks.
Now I think I am done with the board. With a new board PCB
will pop up a "r
On Thu, 21 Sep 2006, Alessandro Baretta wrote:
Hello gentlemen.
Could not find [starglazing-my2006_1.sch] in any SourceLibrary
Cannot find source [starglazing-my2006_1.sch]
This is the error message gschem produces in the status pane when I execute
Hierarchy -> Down Schematic (Shift Hd) o
Hello gentlemen.
Could not find [starglazing-my2006_1.sch] in any SourceLibrary
Cannot find source [starglazing-my2006_1.sch]
This is the error message gschem produces in the status pane when I execute
Hierarchy -> Down Schematic (Shift Hd) on a symbol having the source attribute
set to 'sta
> And I couldn't find a way to make a "jump" over the other lines.
Create or use a new layer for "jumpers". Use vias to get to that
layer. When you make the board, just ignore that layer and add the
jumpers between the vias.
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Hi there,
I'm new to electronics, geda and this list.
I've read some tutorial in the net but end up with this question:
I've done a simple schematic in geda and exported it to PCB via gsch2pcb.
After drawing the soldering lines by hand in pcb I got to a situation
where there
was no path to connec
On Thu, 21 Sep 2006, Samuel A. Falvo II wrote:
>Here's a possible suggestion for compromise:-
>
>Retain the current, keyboard-centric user interface. There is no need
>to change it, and on top of that, you'd P-off a whole lot of currently
>happy users. But for those who are new to the product,
> I am trying to create a
> footprint for an SMT device (it's an SDIP, which doesn't appear to be in
> the library.) The manufacturer spec gave me the exact dimensions for
http://www.gedasymbols.org/user/dj_delorie/tools/dilpad.html
> the pads, which I created using the rectangle tool.
No, use
Hello everyone:
This time I have a very specific question. I am trying to create a
footprint for an SMT device (it's an SDIP, which doesn't appear to be in
the library.) The manufacturer spec gave me the exact dimensions for
the pads, which I created using the rectangle tool. After creating the
On 9/21/06, DJ Delorie <[EMAIL PROTECTED]> wrote:
The Atari ST isn't in common use anymore. Read the "History" section
of the pcb manual.
And the Atari ST's UI norms were much closer to MacOS's norms (being
built around GEM), which all but eschews the use of the keyboard. So
that blows THAT t
On Wed, 2006-09-20 at 21:51, Dave McGuire wrote:
> On Sep 21, 2006, at 12:49 AM, Vaughn Treude wrote:
> >>Yes, I agree. A large number of PCB beginners, however, complain
> >> about the UI and assume it's "unusual" because it was thrown together
> >> without any sort of attention, while I'm ce
> > I didn't mean to imply that it was badly designed, just that it was the
> > earliest program in the suite, and it was written for an OS that's not
> > (to my knowledge) in common use anymore. Therefore it may have been
> > designed to different standards.
>
>UNIX isn't in common use anym
Dan McMahill wrote:
gsymcheck is for symbols files not schematic files. So the complaint
is because the file contains multiple footprint= (because you have
multiple components).
Aah, thanks. Someone here told me I could
run it on .sch too.
Hugo
Stuart Brorson wrote:
We do strive to make gEDA accessible to newbies. However, experience
shows that we can't make everybody happy. ..
We do work towards user friendliness, but since the program is used by
people who live on the command line, we don't always incorporate every
point-and-droo
Hugo Elias wrote:
Hi all,
can anyone tell me what I am doing wrong?
I have a schematic containing two components:
v 20060123 1
C 56700 52700 1 0 0 resistor-1.sym
{
T 56900 53000 5 10 1 1 0 0 1
refdes=R1
T 56700 52700 5 10 0 0 0 0 1
footprint=SMD_0603
T 56700 52700 5 10 0 0 0 0 1
device=Resisto
> As a matter of fact ...I know how to create desktop icons and edit
the properties. I also know how to transfer them to the toolbars.
But most apps that either come with Fedora or are popular "add ons"
for Fedora also have GUI installers that work 10 times better (if not
more) than the gEDA in
Hi all,
can anyone tell me what I am doing wrong?
I have a schematic containing two components:
v 20060123 1
C 56700 52700 1 0 0 resistor-1.sym
{
T 56900 53000 5 10 1 1 0 0 1
refdes=R1
T 56700 52700 5 10 0 0 0 0 1
footprint=SMD_0603
T 56700 52700 5 10 0 0 0 0 1
device=Resistor
}
C 56700 52100 1
Let's not even THINK about dumbing down the impressive power of PCB
by changing its UI to make it take a few hours instead of a few days to
learn. The trade-off is one that every serious engineer or even
spare-time tinkerer should be more than willing to make.
-Dave
I a
On Thursday 21 September 2006 06:12, Arthur Baldwin wrote:
> As a matter of fact ...I know how to create desktop icons and edit the
> properties. I also know how to transfer them to the toolbars. But most
> apps that either come with Fedora or are popular "add ons" for Fedora also
> have GUI inst
> Certain people maintain 'backports' of packages that way.
You should take a look on this page.
http://www.backports.org/dokuwiki/doku.php
Levente
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