Wow! Prompt response! Thank you, Steve!
Are both the errors because of the latch? Or does iv always require the else clause? In my second example the else clause error went away when I added the else...
Well, I am trying to sythesize a latch. Could you please give me some idea how complex a job it might be to add latch synthesis? I am not requesting this feature, just trying to determine the magnitude of the effort, if I for example, attempt to add this...
Cordially, CN
On Tue, 28 Jun 2005 11:41:59 -0700, Stephen Williams wrote:
CN wrote:
| --
| module latch1 (clk, d, q);
| input clk, d;
| output q;
| reg q;
|
| always @ (clk or d) begin
|if (clk == 1'b1) begin
| q = d;
|end
| end
|
| endmodule
| --
|
| With the command line
| iverilog -tfpga -parch=virtex latch1a.v
|
| get the errors:
| latch1a.v:7: error: Asynchronous if statement is missing the else clause.
| latch1a.v:6: internal error: is_asynchronous does not match sync_async results.
|
| Is this to be expected? What am I doing wrong?
Icarus Verilog doesn't know how to synthesize latches.
If you are just trying to simulate your program, then use the -tvvp
flag instead.
--
Steve Williams"The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
