[gem5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick

* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic passed. *

[gem5-dev] SVC Instruction

Hi all I would like to know how svc (trap) instruction is implemented in gem5. In particular I want to know on what condition the register values are changed when svc syscall is executed. It seems to me that at the end of svc instruction, R0 is being updated. On what case is R0 changed? Thanks

Re: [gem5-dev] Ruby slow down

I found the problem. I need to run some more tests, and then I'll commit the patch. -- Nilay On Thu, 4 Sep 2014, Nilay Vaish wrote: Thanks for the information. I'll take a look today. -- Nilay On Thu, 4 Sep 2014, Andreas Hansson via gem5-dev wrote: Hi all, I suspect the last

Re: [gem5-dev] Ethernet device doesn't work with O3 cpu model in X86 ISA

I don't know exactly what the problem is, but it's very suspicious that the device would receive a cache-block-sized access when it's in uncacheable memory space. My guess is that O3 is for some reason issuing a misspeculated cacheable access to the physical address where the device lives.