Re: [gem5-dev] how can I add cache in tgen-simple-mem

Dear Sensen, If you take a look at *src/sim/ClockedObject.py*, you can see that the parameter *clk_domain* is by default inherited from the parent. This means that: For all classes which are inherited from the ClockedObject class (including CPU, memories, ...), if you do not specify any value

Re: [gem5-dev] Review Request 2668: config: Support full-system with SST's memory system

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2668/#review5914 --- Took me longer to review this just because I'm not sure what to think of

[gem5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick

See /z/m5/regression/regress-2015-02-25-03:00:01 for details. ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev