Hi Jason,
Other ISAs don't support vector registers at this time; they would have to
undergo some significant rewrites for this code to affect them.
Curtis
-Original Message-
From: gem5-dev [mailto:gem5-dev-boun...@gem5.org] On Behalf Of Jason Lowe-Power
Sent: Friday, June 16, 2017
Hi Yasir,
The short answer: You need to configure your gem5 simulation properly.
You can configure address ranges in the ExternalSlave object (see src/mem/
ExternalSlave.py). You will also need to configure your MMU to implement the
right address mappings. I am not sure how this works in SE
Hi All,
I am trying to setup a GEM5-to-TLM simulation with GEM5 in ARM SE mode and
SimpleMemory as the physical memory. I intend to model an accelerator in
SystemC in the TLM world. I want my accelerator to start when I signal it
through some memory mapped register (effectively addressing a
Gedare Bloom has submitted this change and it was merged. (
https://gem5-review.googlesource.com/3263 )
Change subject: arm: ignore writes to the reset_ctl register
..
arm: ignore writes to the reset_ctl register
Change-Id:
Gedare Bloom has submitted this change and it was merged. (
https://gem5-review.googlesource.com/3262 )
Change subject: dev, arm: add a9mpcore global timer device
..
dev, arm: add a9mpcore global timer device
Change-Id:
Gedare Bloom has submitted this change and it was merged. (
https://gem5-review.googlesource.com/3264 )
Change subject: configs, arm: add option to enable security extensions
..
configs, arm: add option to enable security
Hello Andreas Sandberg,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/3520
to look at the new patch set (#4).
Change subject: arch-arm: fix ldm of pc interswitching branch
..
Hello Curtis Dunham, Andreas Sandberg,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/3262
to look at the new patch set (#6).
Change subject: dev, arm: add a9mpcore global timer device
* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/minor-timing: FAILED!
* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-atomic: FAILED!
* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing: FAILED!
*** diff[simout]: SKIPPED*
