[gem5-dev] Re: bug squashing renamed pinned registers in o3?

Hi Giacomo, thanks for your reply. To answer your questions, it looks like no for 1 (unless my grep was bad), and checkpoint save/restore for 2. I think we've been able to reproduce this problem much more easily with older versions of gem5, likely missing that fix, although I think we may have

[gem5-dev] Change in gem5/gem5[develop]: configs: Updated DTB warnings in fs.py for Arm platforms.

Hello Giacomo Travaglini, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/30575 to review the following change. Change subject: configs: Updated DTB warnings in fs.py for Arm platforms.

[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Verify number of CPUs when restoring Generic Timer Cpts.

Hello Giacomo Travaglini, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/30576 to review the following change. Change subject: dev-arm: Verify number of CPUs when restoring Generic Timer Cpts.

[gem5-dev] Change in gem5/gem5[develop]: ext: TestStdout and TestStderr

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/30574 ) Change subject: ext: TestStdout and TestStderr .. ext: TestStdout and TestStderr This is actually not

[gem5-dev] Re: bug squashing renamed pinned registers in o3?

Hi Gabe, We are encountering the same problem on top of develop but it’s still worth asking: 1. Do you have https://gem5-review.googlesource.com/c/public/gem5/+/25743 ? 2. Are you encountering this in a simulation which is using a CPU switch or checkpoint save/restore Kind Regards

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: Avoid passing ReExec 'faults' on CPU tracing interface

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/30554 ) Change subject: cpu-o3: Avoid passing ReExec 'faults' on CPU tracing interface .. cpu-o3: Avoid