class BaseReplacementPolicy;
class ThreadContext;
@@ -531,7 +527,6 @@
Addr ipaddress;
Addr s1_physaddr;
Addr s2_physaddr;
-AccType acctype;
bool wasaligned;
bool hwupdatewalk;
bool s2fs1walk;
@@ -604,9 +599,6 @@
Addr ptw_desc_addr;
uint64_t ptw_desc_value;
-void tickLimitReached();
-EventFunctionWrapper* tickLimitReachedEvent;
-
bool isFetch() {
return (mode == Execute);
}
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index c66921f..9263524 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -343,6 +343,7 @@
self._tlb_ports['l2tlb'] = 'mmu.stage1_walker'
else:
self.l2stage2_tlb = l2tlb
+self.l2tlb.stage2tlb = self.l2stage2_tlb
self.istage2_tlb.next_tlb = self.l2stage2_tlb
self.dstage2_tlb.next_tlb = self.l2stage2_tlb
self.mmu.stage2_tlbs = [self.istage2_tlb,
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// TLB and update the record field in TranslationState structure.
// FALSE otherwise
-bool lookup(TranslationStatePtr, bool,
+bool lookup(TranslationState*, bool,
bool functional=true, bool from_ptw=false);
// Insert an entry for the specified address
- void insert
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Change subject: Fix for the DerivO3CPU. Now passing 1728 tests in
V8MEM/V8CORE_IP
..
Fix for the DerivO3CPU.
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Change subject: Keeping TlbEntry as default implementation
..
Keeping TlbEntry as default implementation
he specified 'AccType'
-// FALSE otherwise
-bool hasAcctype(AccType);
-
-bool isPartial;
-
TranslationState(TLB*);
~TranslationState();
};
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:PCState& target, ThreadID tid)
override;
+
+void genIndirectInfo(ThreadID tid, Addr pc,
+ void* & indirect_history) override;
+
+void updateDirectionInfo(ThreadID tid, bool taken, void *
indirect_history,
+ const StaticInstPt
em5
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PC of the instruction being retired
+ */
+void notifyRetiredInst(const Addr pc) override;
+
+public:
+PIFPrefetcher(const PIFPrefetcherParams *p);
+~PIFPrefetcher() {}
+
+void calculatePrefetch(const PrefetchInfo ,
+ std::vect
override;
+};
+
+#endif // __MEM_CACHE_PREFETCH_SBOOE_HH__
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cketPtr& pkt) override;
+
+public:
+
+BOPPrefetcher(const BOPPrefetcherParams *p);
+ ~BOPPrefetcher() {}
+
+void calculatePrefetch(const PrefetchInfo ,
+ std::vector );
+};
+
+#endif /* __MEM_CACHE_PREFETCH_BOP_HH__ */
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; hd; // Only defined for VTCR_EL2
EndBitUnion(VTCR_t)
BitUnion32(PRRR)
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lculatePrefetch(const PacketPtr ,
+std::vector );
+};
+
+#endif /* __MEM_CACHE_PREFETCH_BOP_HH__ */
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Change subject: arch-arm: Reverting some changes in the headers for tlb and
table_walker files to ease the review with the previous implementation and
reverting miscregs_types.hh
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+
# Enable Ruby
parser.add_option("--ruby", action="store_true")
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