On Mon, Aug 9, 2021 at 1:02 PM Giacomo Travaglini <
giacomo.travagl...@arm.com> wrote:
> Hi Gabe,
>
> > -Original Message-
> > From: Gabe Black via gem5-dev
> > Sent: 09 August 2021 11:02
> > To: gem5 Developer List
> > Cc: Gabe Black
> >
Hi Gabe,
> -Original Message-
> From: Gabe Black via gem5-dev
> Sent: 09 August 2021 11:02
> To: gem5 Developer List
> Cc: Gabe Black
> Subject: [gem5-dev] Re: overview/documentation/tests for vector register
> related stuff?
>
> I've done a bit of diggi
I've done a bit of digging so far, and I think I've figured out a bit about
the rename mode.
1. This is only used by ARM to handle the difference in how registers are
renamed in aarch64 vs otherwise.
2. This is handled in O3 by detecting a squash in the CPU and then checking
the aarch64 bit of
