[gem5-dev] Change in gem5/gem5[master]: system-arm: bigLITTLE with VExpress_GEM5_V2 in dtb
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/24083 ) Change subject: system-arm: bigLITTLE with VExpress_GEM5_V2 in dtb .. system-arm: bigLITTLE with VExpress_GEM5_V2 in dtb This patch adds targets in the device tree Makefile for using bigLITTLE DTS with VExpress_GEM5_V2 platform. Change-Id: I7a424a36c78a24b96224526aa112ac5d060f790b Reviewed-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24083 Reviewed-by: Ciro Santilli Maintainer: Giacomo Travaglini Tested-by: kokoro --- M system/arm/dt/Makefile 1 file changed, 8 insertions(+), 2 deletions(-) Approvals: Ciro Santilli: Looks good to me, approved Giacomo Travaglini: Looks good to me, approved kokoro: Regressions pass diff --git a/system/arm/dt/Makefile b/system/arm/dt/Makefile index 2d8ca6e..1bb6870 100644 --- a/system/arm/dt/Makefile +++ b/system/arm/dt/Makefile @@ -1,4 +1,4 @@ -# Copyright (c) 2015-2016, 2019 ARM Limited +# Copyright (c) 2015-2016, 2019-2020 ARM Limited # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -43,7 +43,9 @@ TARGETS=\ $(foreach prefix, $(TARGET_PREFIX), $(call CREATE_TARGET, $(prefix))) \ armv8_gem5_v1_big_little_2_2.dtb \ - armv8_gem5_v1_big_little_2_4.dtb + armv8_gem5_v1_big_little_2_4.dtb \ + armv8_gem5_v2_big_little_2_2.dtb \ + armv8_gem5_v2_big_little_2_4.dtb VEXPRESS_GEM5_V1_DTSIS=\ platforms/vexpress_gem5_v1.dtsi \ @@ -75,6 +77,10 @@ $(VEXPRESS_GEM5_V1_DTSIS) $(call GEN_DTS,vexpress_gem5_v1.dtsi,$*) +.gen/armv8_gem5_v2_big_little%.dts: armv8_big_little.dts \ + $(VEXPRESS_GEM5_V2_DTSIS) + $(call GEN_DTS,vexpress_gem5_v2.dtsi,$*) + %.dtb: .gen/%.dts $(DTC) -I dts -O dtb -o $@ $< -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/24083 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I7a424a36c78a24b96224526aa112ac5d060f790b Gerrit-Change-Number: 24083 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Ciro Santilli Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: tests: Removed 50.vortex tests
Bobby R. Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/24387 ) Change subject: tests: Removed 50.vortex tests .. tests: Removed 50.vortex tests In an effort to cleanup the old tests, and migrate useful tests to be executed via `test/main.py`, it has been decided that the `test/long/se/50.vortex` tests should be removed. Jira: https://gem5.atlassian.net/browse/GEM5-109 Change-Id: I9c40ca74aad11a80bd2a91bd67c9561ffa76e78f --- D tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini D tests/long/se/50.vortex/ref/arm/linux/minor-timing/simerr D tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout D tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt D tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini D tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr D tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout D tests/long/se/50.vortex/ref/arm/linux/o3-timing/smred.out D tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt D tests/long/se/50.vortex/test.py 10 files changed, 0 insertions(+), 4,501 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/24387 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I9c40ca74aad11a80bd2a91bd67c9561ffa76e78f Gerrit-Change-Number: 24387 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby R. Bruce Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: tests: Removed 70.twolf tests
Bobby R. Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/24383 ) Change subject: tests: Removed 70.twolf tests .. tests: Removed 70.twolf tests In an effort to cleanup the old tests, and migrate useful tests to be executed via `test/main.py`, it has been decided that the `test/quick/70.twolf` tests should be removed. Jira: https://gem5.atlassian.net/browse/GEM5-109 Change-Id: I19f2e20298e14a92f49adf0b8369e1fa09e0c1bc --- D tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/config.ini D tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simerr D tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simout D tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/smred.out D tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt D tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini D tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simerr D tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simout D tests/quick/se/70.twolf/ref/arm/linux/simple-timing/smred.out D tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt D tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini D tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simerr D tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simout D tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.out D tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pin D tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1 D tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2 D tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sav D tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2 D tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.twf D tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt D tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini D tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simerr D tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simout D tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.out D tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.pin D tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl1 D tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl2 D tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.sav D tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.sv2 D tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.twf D tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt D tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini D tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simerr D tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simout D tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.out D tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.pin D tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl1 D tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl2 D tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.sav D tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.sv2 D tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.twf D tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt D tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini D tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simerr D tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simout D tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.out D tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.pin D tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.pl1 D tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.pl2 D tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.sav D tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.sv2 D tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.twf D tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt D tests/quick/se/70.twolf/test.py 55 files changed, 0 insertions(+), 6,679 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/24383 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I19f2e20298e14a92f49adf0b8369e1fa09e0c1bc Gerrit-Change-Number: 24383 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby R. Bruce Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: tests: Removed 40.perlbmk tests
Bobby R. Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/24403 ) Change subject: tests: Removed 40.perlbmk tests .. tests: Removed 40.perlbmk tests In an effort to cleanup the old tests, and migrate useful tests to be executed via `test/main.py`, it has been decided that the `test/long/se/40.perlbmk` tests should be removed. Jira: https://gem5.atlassian.net/browse/GEM5-109 Change-Id: I3c7ea79717c90acf0656f30b878eb3f9f33fdb70 --- D tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini D tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simerr D tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout D tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt D tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini D tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr D tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout D tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt D tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini D tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr D tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout D tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt D tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini D tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr D tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout D tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt D tests/long/se/40.perlbmk/test.py 17 files changed, 0 insertions(+), 8,624 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/24403 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I3c7ea79717c90acf0656f30b878eb3f9f33fdb70 Gerrit-Change-Number: 24403 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby R. Bruce Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: tests: Removed 20.parser tests
Bobby R. Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/24384 ) Change subject: tests: Removed 20.parser tests .. tests: Removed 20.parser tests In an effort to cleanup the old tests, and migrate useful tests to be executed via `test/main.py`, it has been decided that the `test/long/se/70.twolf` tests should be removed. Jira: https://gem5.atlassian.net/browse/GEM5-109 Change-Id: Ie0c0cd310ee51a37e80a84af3bf1cb603061da7c --- D tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini D tests/long/se/20.parser/ref/arm/linux/minor-timing/simerr D tests/long/se/20.parser/ref/arm/linux/minor-timing/simout D tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt D tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini D tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr D tests/long/se/20.parser/ref/arm/linux/o3-timing/simout D tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt D tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini D tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr D tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout D tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt D tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini D tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr D tests/long/se/20.parser/ref/arm/linux/simple-timing/simout D tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt D tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini D tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr D tests/long/se/20.parser/ref/x86/linux/o3-timing/simout D tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt D tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini D tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr D tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout D tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt D tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini D tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr D tests/long/se/20.parser/ref/x86/linux/simple-timing/simout D tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt D tests/long/se/20.parser/test.py 29 files changed, 0 insertions(+), 9,941 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/24384 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ie0c0cd310ee51a37e80a84af3bf1cb603061da7c Gerrit-Change-Number: 24384 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby R. Bruce Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: tests: Removed 60.bzip2 tests
Bobby R. Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/24385 ) Change subject: tests: Removed 60.bzip2 tests .. tests: Removed 60.bzip2 tests In an effort to cleanup the old tests, and migrate useful tests to be executed via `test/main.py`, it has been decided that the `test/quick/60.bzip2` tests should be removed. Jira: https://gem5.atlassian.net/browse/GEM5-109 Change-Id: I8469814a2f4715655960b9049182e426e10380ed --- D tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini D tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simerr D tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout D tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt D tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini D tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr D tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout D tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt D tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini D tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr D tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout D tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt D tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini D tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr D tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout D tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt D tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini D tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr D tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout D tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt D tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini D tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr D tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout D tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt D tests/long/se/60.bzip2/test.py 25 files changed, 0 insertions(+), 7,577 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/24385 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I8469814a2f4715655960b9049182e426e10380ed Gerrit-Change-Number: 24385 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby R. Bruce Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: tests: Removed 30.eon tests
Bobby R. Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/24386 ) Change subject: tests: Removed 30.eon tests .. tests: Removed 30.eon tests In an effort to cleanup the old tests, and migrate useful tests to be executed via `test/main.py`, it has been decided that the `test/long/se/30.eon` tests should be removed. Jira: https://gem5.atlassian.net/browse/GEM5-109 Change-Id: Ieb32196a5f0ed3b3375ede5aec6f8fb8d162a865 --- D tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini D tests/long/se/30.eon/ref/arm/linux/minor-timing/simerr D tests/long/se/30.eon/ref/arm/linux/minor-timing/simout D tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt D tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini D tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr D tests/long/se/30.eon/ref/arm/linux/o3-timing/simout D tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt D tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini D tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr D tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout D tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt D tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini D tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr D tests/long/se/30.eon/ref/arm/linux/simple-timing/simout D tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt D tests/long/se/30.eon/test.py 17 files changed, 0 insertions(+), 6,196 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/24386 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ieb32196a5f0ed3b3375ede5aec6f8fb8d162a865 Gerrit-Change-Number: 24386 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby R. Bruce Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: tests: Removed the old ALPHA tests
Bobby R. Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/24388 ) Change subject: tests: Removed the old ALPHA tests .. tests: Removed the old ALPHA tests Jira: https://gem5.atlassian.net/browse/GEM5-109 Change-Id: Id24c84c70d977f7dbd2815b862af9b7eab638aca --- D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simerr D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/EMPTY D tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini D tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr D tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout D tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt D tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal D tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini D tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr D tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout D tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt D tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal D tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini D tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr D tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout D tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt D tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal D tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini D tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr D tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout D tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt D tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal D tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini D tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal D tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr D tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout D tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt D tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal D tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini D tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simerr D tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout D tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt D tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini D tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr D tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout D tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt D tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini D tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr D tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout D tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt D tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini D tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr D tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout D tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt D tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini D tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr D tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout D
Re: [gem5-dev] Stop checkpointing ARM TLB state
Ok, thanks. I'll put together a CL removing the checkpointing. It should be backwards compatible with old checkpoints still since new versions of gem5 will just ignore the extra state in the checkpoint. Gabe On Tue, Jan 14, 2020 at 1:37 AM Giacomo Travaglini < giacomo.travagl...@arm.com> wrote: > Hi Gabe, you are definitely right. > The only reason I could think of about why we are checkpointing TLB > entries is because we want to be able to restore the TLB in a wam state. > > In theory you could get away with it in FM by instantiating an empty TLB > which is saving invalid entries (when serializing) and it is restoring > entries > with no effect (when unserializing). > > Having said that I am fine on removing chechkpointing capabilities from > the TLB. > I guess the system will already be in a cold state because of caches. > > Giacomo > -- > *From:* gem5-dev on behalf of Gabe Black < > gabebl...@google.com> > *Sent:* 14 January 2020 02:13 > *To:* gem5 Developer List > *Subject:* Re: [gem5-dev] Stop checkpointing ARM TLB state > > Similarly, the interrupts object checkpoints both an array of bools > (interrupts), and a scalar bit vector (intStatus) which hold the same > information. That information *does* need to be in the checkpoint as far as > I can tell, but it doesn't need to be in there twice. > > Gabe > > On Mon, Jan 13, 2020 at 6:11 PM Gabe Black wrote: > > > Hi folks. I'm looking at checkpointing fast models, and one thing I'll > > have to put into the checkpoint is something for the TLBs. I was looking > at > > what they checkpoint, and I think all of it should be removed from > > checkpoints. > > > > As far as I know: > > > > _attr: A cached value which is an implementation detail and not > > architecturally visible. > > haveLPAE: A setting which is not architectural/software visible state. > > directToStage2: Derived state which comes from miscregs. Can be recovered > > on first use by updateMiscRegs if miscRegValid is false (which it is on > > construction). > > stage2Reg, stage2DescReq: Information about in flight translations? These > > should not be in flight when a checkpoint is taken since state should > have > > drained. > > > > TLB entries which can be reloaded in the new TLB. The new TLB won't > > necessarily have the same size as the old one, and so can't necessarily > > have the same table of entries. The entries are not (as far as I know) > > architecturally visible. > > > > All of this state can and should be removed from checkpoints as far as I > > can tell. Please let me know if I'm wrong about some bit of this. > > > > Gabe > > > ___ > gem5-dev mailing list > gem5-dev@gem5.org > http://m5sim.org/mailman/listinfo/gem5-dev > IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. IMPORTANT NOTICE: The contents of > this email and any attachments are confidential and may also be privileged. > If you are not the intended recipient, please notify the sender immediately > and do not disclose the contents to any other person, use it for any > purpose, or store or copy the information in any medium. Thank you. > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arm: Remove checkpointing from the ARM TLBs.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/24389 )
Change subject: arm: Remove checkpointing from the ARM TLBs.
..
arm: Remove checkpointing from the ARM TLBs.
All of the state being checkpointed would either be provided by the
config directly, or would be brought into the TLB through normal fill
operations. Having this state in the checkpoint complicates the
checkpoint and significantly decreases compatibility with other TLB
implementations, or even variations of the same TLB, for instance if
the size was changed.
Change-Id: I4ea079dd01ff18fbc458b3aaaf88519dbcfdd869
---
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
2 files changed, 0 insertions(+), 38 deletions(-)
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 1e4904c..af0f862 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -405,40 +405,6 @@
}
void
-TLB::serialize(CheckpointOut ) const
-{
-DPRINTF(Checkpoint, "Serializing Arm TLB\n");
-
-SERIALIZE_SCALAR(_attr);
-SERIALIZE_SCALAR(haveLPAE);
-SERIALIZE_SCALAR(directToStage2);
-SERIALIZE_SCALAR(stage2Req);
-SERIALIZE_SCALAR(stage2DescReq);
-
-int num_entries = size;
-SERIALIZE_SCALAR(num_entries);
-for (int i = 0; i < size; i++)
-table[i].serializeSection(cp, csprintf("TlbEntry%d", i));
-}
-
-void
-TLB::unserialize(CheckpointIn )
-{
-DPRINTF(Checkpoint, "Unserializing Arm TLB\n");
-
-UNSERIALIZE_SCALAR(_attr);
-UNSERIALIZE_SCALAR(haveLPAE);
-UNSERIALIZE_SCALAR(directToStage2);
-UNSERIALIZE_SCALAR(stage2Req);
-UNSERIALIZE_SCALAR(stage2DescReq);
-
-int num_entries;
-UNSERIALIZE_SCALAR(num_entries);
-for (int i = 0; i < min(size, num_entries); i++)
-table[i].unserializeSection(cp, csprintf("TlbEntry%d", i));
-}
-
-void
TLB::regStats()
{
BaseTLB::regStats();
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index ea78a21..6314ef2 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -383,10 +383,6 @@
void drainResume() override;
-// Checkpointing
-void serialize(CheckpointOut ) const override;
-void unserialize(CheckpointIn ) override;
-
void regStats() override;
void regProbePoints() override;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/24389
To unsubscribe, or for help writing mail filters, visit
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I4ea079dd01ff18fbc458b3aaaf88519dbcfdd869
Gerrit-Change-Number: 24389
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: arm: Don't checkpoint the SystemCounter's "_period" value.
Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/24390 ) Change subject: arm: Don't checkpoint the SystemCounter's "_period" value. .. arm: Don't checkpoint the SystemCounter's "_period" value. This value is just a cached inverse of _freq and can be recalculated easily once the checkpoint is restored. The actual value of _period actually depends on the global resolution of time (ie how much time a Tick represents), and so saving the value of _period is also not technically correct, even though in practice that will very rarely cause a problem. Change-Id: I21e63ba25ac4e189417905e532981f3d80723f19 --- M src/dev/arm/generic_timer.cc 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/dev/arm/generic_timer.cc b/src/dev/arm/generic_timer.cc index 7c1f09a..3df8768 100644 --- a/src/dev/arm/generic_timer.cc +++ b/src/dev/arm/generic_timer.cc @@ -83,7 +83,6 @@ SERIALIZE_SCALAR(_regCntkctl); SERIALIZE_SCALAR(_regCnthctl); SERIALIZE_SCALAR(_freq); -SERIALIZE_SCALAR(_period); SERIALIZE_SCALAR(_resetTick); } @@ -97,7 +96,7 @@ if (!UNSERIALIZE_OPT_SCALAR(_regCnthctl)) _regCnthctl = 0; UNSERIALIZE_SCALAR(_freq); -UNSERIALIZE_SCALAR(_period); +_period = (1.0 / _freq) * SimClock::Frequency; UNSERIALIZE_SCALAR(_resetTick); } -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/24390 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I21e63ba25ac4e189417905e532981f3d80723f19 Gerrit-Change-Number: 24390 Gerrit-PatchSet: 1 Gerrit-Owner: Gabe Black Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Stop checkpointing ARM TLB state
Hi Gabe, you are definitely right. The only reason I could think of about why we are checkpointing TLB entries is because we want to be able to restore the TLB in a wam state. In theory you could get away with it in FM by instantiating an empty TLB which is saving invalid entries (when serializing) and it is restoring entries with no effect (when unserializing). Having said that I am fine on removing chechkpointing capabilities from the TLB. I guess the system will already be in a cold state because of caches. Giacomo From: gem5-dev on behalf of Gabe Black Sent: 14 January 2020 02:13 To: gem5 Developer List Subject: Re: [gem5-dev] Stop checkpointing ARM TLB state Similarly, the interrupts object checkpoints both an array of bools (interrupts), and a scalar bit vector (intStatus) which hold the same information. That information *does* need to be in the checkpoint as far as I can tell, but it doesn't need to be in there twice. Gabe On Mon, Jan 13, 2020 at 6:11 PM Gabe Black wrote: > Hi folks. I'm looking at checkpointing fast models, and one thing I'll > have to put into the checkpoint is something for the TLBs. I was looking at > what they checkpoint, and I think all of it should be removed from > checkpoints. > > As far as I know: > > _attr: A cached value which is an implementation detail and not > architecturally visible. > haveLPAE: A setting which is not architectural/software visible state. > directToStage2: Derived state which comes from miscregs. Can be recovered > on first use by updateMiscRegs if miscRegValid is false (which it is on > construction). > stage2Reg, stage2DescReq: Information about in flight translations? These > should not be in flight when a checkpoint is taken since state should have > drained. > > TLB entries which can be reloaded in the new TLB. The new TLB won't > necessarily have the same size as the old one, and so can't necessarily > have the same table of entries. The entries are not (as far as I know) > architecturally visible. > > All of this state can and should be removed from checkpoints as far as I > can tell. Please let me know if I'm wrong about some bit of this. > > Gabe > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] The memory dependence predictor misses dependencies following fences
Hi Everybody,
We are working on Atomic instructions in X86 ISA and how they are
handled by gem5.
During running a simple benchmark which executes an Atomic_Increment
within a loop for 1M iterations,
we have encountered 2 MILLION TIMES OF MEMORY_ORDER_VIOLATIONS which
results in 2 Million times of squashing a LD_Inst _because of a
missed memory dependence with a previous store_ !!!
After delving into the code of "_src/cpu/o3/mem_dep_unit_impl._hh",
we have found the following observations which cause the
abovementioned problem:
1) The function INSERT(DYNINSTPTR ), is responsible to insert
the new Inst into the Inst_Queue.
2) If the coming Inst is a LD_Inst, then insert function tries to
find out whether the LD_Inst has a dependency with an in-flight
Memory Barriers or a preceding ST_Inst or not.
3) If yes, then it adds the LD_Inst into the dependent_vector_list
of that Mem_Barrier or ST_Inst. (THE PROBLEM IS HERE)
THE PROBLEM: the default order which gem5 looks for a
producing_store for the LD_Inst is that it gives priority to
Mem_Barriers, and
only if we do not have a Mem_Barrier then we take a look at
store_set mem_predictor to find the latest preceding store
associates with the LD_Inst.
This order of finding the producing_store results in many numbers of
Mem_Order_violations in the following example:
Example benchmark:
for(int i=0; i < 1M ; i++)
{
/* This assambly represents a simple atomic_Increment in a loop */
-- Mem_Fence
-- Store _x_
-- Load _x_
}
Regarding the above snippet, _in theory_, Load _x_ should
be _dependent_ on Store x, however, _according to the gem5
implementation_, the Mem_Fence is selected as the _dependent
instruction and the dependence between the load and the store is
obviated_;
_Having just the Load dependent only on the Mem_Fence_ in the above
code, which is our simple benchmark, brings about 2 Million times of
Squashes (i.e., Mem_Order_Violations) that degrades the performance
significantly.
THE SOLUTION:
- _adding the dependence between the store and the load solves_ the
problem, causeing the number of squashes (i.e.,
Mem_Order_Violations) to drop from 2 Millions to only 900_, and
reducing execution time._
We want to ask whether our observation regarding how _to add
dependencies for_ LD_Inst in "_src/cpu/o3/mem_dep_unit_impl._hh" is
correct or not.
In another word, we want to ask if adding also the dependence to the
store (apart from the fence) can be done in gem5 with minor
modifications?
Thanks a lot for reading our email and appreciate a lot your considerations.
Sincerely,
Ashkan Asgharzadeh,
Ph.D. Student at the CS Faculty,
University of Murcia, Spain
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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Minor Ruby Prefetcher fixes
Hello Timothy Hayes,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/24363
to review the following change.
Change subject: mem-ruby: Minor Ruby Prefetcher fixes
..
mem-ruby: Minor Ruby Prefetcher fixes
Minor fixes to the Ruby stride prefetcher. This includes removing unused
statistics and changing where/when some statistics are updated.
Change-Id: If758bf009f53fad277cb3cd754d57a0b10737599
---
M src/mem/ruby/structures/Prefetcher.cc
M src/mem/ruby/structures/Prefetcher.hh
M src/mem/ruby/structures/RubyPrefetcher.py
3 files changed, 42 insertions(+), 20 deletions(-)
diff --git a/src/mem/ruby/structures/Prefetcher.cc
b/src/mem/ruby/structures/Prefetcher.cc
index 70b3035..a8b2d85 100644
--- a/src/mem/ruby/structures/Prefetcher.cc
+++ b/src/mem/ruby/structures/Prefetcher.cc
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
* All rights reserved.
*
@@ -105,19 +117,9 @@
.desc("number of prefetch requests made")
;
-numPrefetchAccepted
-.name(name() + ".prefetches_accepted")
-.desc("number of prefetch requests accepted")
-;
-
-numDroppedPrefetches
-.name(name() + ".dropped_prefetches")
-.desc("number of prefetch requests dropped")
-;
-
numHits
.name(name() + ".hits")
-.desc("number of prefetched blocks accessed")
+.desc("number of prefetched blocks accessed (for the first time)")
;
numPartialHits
@@ -157,7 +159,7 @@
// The controller has issued the prefetch request,
// but the request for the block arrived earlier.
numPartialHits++;
-observePfHit(line_addr);
+observePfMiss(line_addr);
return;
}
} else {
@@ -242,16 +244,17 @@
// possibly stop prefetching at page boundaries
if (page_addr != pageAddress(line_addr)) {
-numPagesCrossed++;
if (!m_prefetch_cross_pages) {
// Deallocate the stream since we are not prefetching
// across page boundries
stream->m_is_valid = false;
return;
}
+numPagesCrossed++;
}
// launch next prefetch
+numPrefetchRequested++;
stream->m_address = line_addr;
stream->m_use_time = m_controller->curCycle();
DPRINTF(RubyPrefetcher, "Requesting prefetch for %#x\n", line_addr);
@@ -308,12 +311,12 @@
line_addr = makeNextStrideAddress(line_addr, stride);
// possibly stop prefetching at page boundaries
if (page_addr != pageAddress(line_addr)) {
-numPagesCrossed++;
if (!m_prefetch_cross_pages) {
// deallocate this stream prefetcher
mystream->m_is_valid = false;
return;
}
+numPagesCrossed++;
}
// launch prefetch
diff --git a/src/mem/ruby/structures/Prefetcher.hh
b/src/mem/ruby/structures/Prefetcher.hh
index 9c3c068..89c0186 100644
--- a/src/mem/ruby/structures/Prefetcher.hh
+++ b/src/mem/ruby/structures/Prefetcher.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
* All rights reserved.
*
@@ -166,7 +178,7 @@
//! have been hit
uint32_t *m_unit_filter_hit;
-//! a negative nit stride filter array: helps reduce BW requirement
+//! a negative unit stride filter array: helps reduce BW
requirement
//! of prefetching
std::vector m_negative_filter;
/// a round robin pointer into the negative
