[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: make sure only supported modes can be set in SATP.
Nils Asmussen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/26983 )
Change subject: arch-riscv: make sure only supported modes can be set in
SATP.
..
arch-riscv: make sure only supported modes can be set in SATP.
Change-Id: I37c67e491d64bf03d1125e23db28611fa0b16038
---
M src/arch/riscv/isa.cc
1 file changed, 14 insertions(+), 0 deletions(-)
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index ca3358e..a71733b 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -1,6 +1,7 @@
/*
* Copyright (c) 2016 RISC-V Foundation
* Copyright (c) 2016 The University of Virginia
+ * Copyright (c) 2020 Barkhausen Institut
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -34,6 +35,7 @@
#include
#include "arch/riscv/interrupts.hh"
+#include "arch/riscv/pagetable.hh"
#include "arch/riscv/registers.hh"
#include "base/bitfield.hh"
#include "cpu/base.hh"
@@ -204,6 +206,18 @@
ic->setIE(val);
}
break;
+ case MISCREG_SATP:
+{
+// we only support bare and Sv39 mode; setting a different
mode
+// shall have no effect (see 4.1.12 in priv ISA manual)
+SATP cur_val = readMiscRegNoEffect(misc_reg);
+SATP new_val = val;
+if (new_val.mode != AddrXlateMode::BARE &&
+new_val.mode != AddrXlateMode::SV39)
+new_val.mode = cur_val.mode;
+setMiscRegNoEffect(misc_reg, new_val);
+}
+break;
default:
setMiscRegNoEffect(misc_reg, val);
}
--
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv, configs: add support for the walker cache.
Nils Asmussen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/26988 )
Change subject: arch-riscv,configs: add support for the walker cache.
..
arch-riscv,configs: add support for the walker cache.
Change-Id: I19b1dd9e3c55c433c897988d36e6715017273c66
---
M configs/common/CacheConfig.py
M configs/common/Caches.py
M src/cpu/BaseCPU.py
3 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index 91087fb..05c38e0 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -1,4 +1,5 @@
# Copyright (c) 2012-2013, 2015-2016 ARM Limited
+# Copyright (c) 2020 Barkhausen Institut
# All rights reserved
#
# The license below extends only to copyright in the software and shall
@@ -79,7 +80,7 @@
dcache_class, icache_class, l2_cache_class, walk_cache_class = \
L1_DCache, L1_ICache, L2Cache, None
-if buildEnv['TARGET_ISA'] == 'x86':
+if buildEnv['TARGET_ISA'] in ['x86', 'riscv']:
walk_cache_class = PageTableWalkerCache
# Set the cache line size of the system
@@ -181,7 +182,7 @@
# on these names. For simplicity, we would advise configuring
# it to use this naming scheme; if this isn't possible, change
# the names below.
-if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
+if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']:
system.cpu[i].addPrivateSplitL1Caches(
ExternalCache("cpu%d.icache" % i),
ExternalCache("cpu%d.dcache" % i),
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 123fea4..77213e8 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -1,4 +1,5 @@
# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2020 Barkhausen Institut
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -92,7 +93,7 @@
tgts_per_mshr = 12
# the x86 table walker actually writes to the table-walker cache
-if buildEnv['TARGET_ISA'] == 'x86':
+if buildEnv['TARGET_ISA'] in ['x86', 'riscv']:
is_read_only = False
else:
is_read_only = True
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 53652bf..67d95d0 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -1,4 +1,5 @@
# Copyright (c) 2012-2013, 2015-2017 ARM Limited
+# Copyright (c) 2020 Barkhausen Institut
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -181,7 +182,7 @@
dcache_port = MasterPort("Data Port")
_cached_ports = ['icache_port', 'dcache_port']
-if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
+if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']:
_cached_ports += ["itb.walker.port", "dtb.walker.port"]
_uncached_slave_ports = []
@@ -216,7 +217,7 @@
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
-if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
+if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']:
if iwc and dwc:
self.itb_walker_cache = iwc
self.dtb_walker_cache = dwc
--
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: removed unused files.
Nils Asmussen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/26987 )
Change subject: arch-riscv: removed unused files.
..
arch-riscv: removed unused files.
Change-Id: I4fca7f9b9bd697c044facedfca979fe828bfd27f
---
D src/arch/riscv/bare_metal/system.cc
D src/arch/riscv/bare_metal/system.hh
2 files changed, 0 insertions(+), 122 deletions(-)
diff --git a/src/arch/riscv/bare_metal/system.cc
b/src/arch/riscv/bare_metal/system.cc
deleted file mode 100644
index 1ca8ed9..000
--- a/src/arch/riscv/bare_metal/system.cc
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Copyright (c) 2018 TU Dresden
- * All rights reserved
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "arch/riscv/bare_metal/system.hh"
-
-#include "arch/riscv/faults.hh"
-#include "base/loader/object_file.hh"
-
-BareMetalRiscvSystem::BareMetalRiscvSystem(Params *p)
-: RiscvSystem(p),
- bootloader(createObjectFile(p->bootloader))
-{
-if (bootloader == NULL) {
- fatal("Could not load bootloader file %s", p->bootloader);
-}
-
-_resetVect = bootloader->entryPoint();
-}
-
-BareMetalRiscvSystem::~BareMetalRiscvSystem()
-{
-delete bootloader;
-}
-
-void
-BareMetalRiscvSystem::initState()
-{
-// Call the initialisation of the super class
-RiscvSystem::initState();
-
-for (auto *tc: threadContexts) {
-RiscvISA::Reset().invoke(tc);
-tc->activate();
-}
-
-// load program sections into memory
-if (!bootloader->buildImage().write(physProxy)) {
-warn("could not load sections to memory");
-}
-}
-
-BareMetalRiscvSystem *
-BareMetalRiscvSystemParams::create()
-{
-return new BareMetalRiscvSystem(this);
-}
-
diff --git a/src/arch/riscv/bare_metal/system.hh
b/src/arch/riscv/bare_metal/system.hh
deleted file mode 100644
index 1f665be..000
--- a/src/arch/riscv/bare_metal/system.hh
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Copyright (c) 2018 TU Dresden
- * All rights reserved
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fixed formatting.
Nils Asmussen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/26986 )
Change subject: arch-riscv: fixed formatting.
..
arch-riscv: fixed formatting.
Change-Id: I134993a4aced07e75bf62fec56081b0f9d8fc18c
---
M src/arch/riscv/isa.hh
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 4bf0fdb..9d34242 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -4,6 +4,7 @@
* Copyright (c) 2014 Sven Karlsson
* Copyright (c) 2016 RISC-V Foundation
* Copyright (c) 2016 The University of Virginia
+ * Copyright (c) 2020 Barkhausen Institut
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -52,7 +53,8 @@
namespace RiscvISA
{
-enum PrivilegeMode {
+enum PrivilegeMode
+{
PRV_U = 0,
PRV_S = 1,
PRV_M = 3
--
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: implement sfence.vma to flush TLBs.
Nils Asmussen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/26984 )
Change subject: arch-riscv: implement sfence.vma to flush TLBs.
..
arch-riscv: implement sfence.vma to flush TLBs.
Change-Id: I424123d3c94c9673269f922cd6755f0bbf5b6cc0
---
M src/arch/riscv/insts/standard.cc
M src/arch/riscv/insts/standard.hh
M src/arch/riscv/isa/decoder.isa
3 files changed, 55 insertions(+), 33 deletions(-)
diff --git a/src/arch/riscv/insts/standard.cc
b/src/arch/riscv/insts/standard.cc
index 1e7d22e..166501f 100644
--- a/src/arch/riscv/insts/standard.cc
+++ b/src/arch/riscv/insts/standard.cc
@@ -1,6 +1,7 @@
/*
* Copyright (c) 2015 RISC-V Foundation
* Copyright (c) 2017 The University of Virginia
+ * Copyright (c) 2020 Barkhausen Institut
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -66,4 +67,17 @@
return ss.str();
}
+string
+SystemOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+if (strcmp(mnemonic, "fence_vma") == 0) {
+stringstream ss;
+ss << mnemonic << ' ' << registerName(_srcRegIdx[0]) << ", " <<
+registerName(_srcRegIdx[1]);
+return ss.str();
+}
+
+return mnemonic;
+}
+
}
diff --git a/src/arch/riscv/insts/standard.hh
b/src/arch/riscv/insts/standard.hh
index a956d77..a1c5911 100644
--- a/src/arch/riscv/insts/standard.hh
+++ b/src/arch/riscv/insts/standard.hh
@@ -1,6 +1,7 @@
/*
* Copyright (c) 2015 RISC-V Foundation
* Copyright (c) 2017 The University of Virginia
+ * Copyright (c) 2020 Barkhausen Institut
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -75,10 +76,7 @@
using RiscvStaticInst::RiscvStaticInst;
std::string
-generateDisassembly(Addr pc, const SymbolTable *symtab) const override
-{
-return mnemonic;
-}
+generateDisassembly(Addr pc, const SymbolTable *symtab) const override;
};
/**
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 4f8fea2..04f0319 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -1758,38 +1758,48 @@
0x1c: decode FUNCT3 {
format SystemOp {
-0x0: decode FUNCT12 {
-0x0: ecall({{
-fault = make_shared(
+0x0: decode FUNCT7 {
+0x0: decode RS2 {
+0x0: ecall({{
+fault = make_shared(
(PrivilegeMode)xc->readMiscReg(MISCREG_PRV));
-}}, IsSerializeAfter, IsNonSpeculative, IsSyscall,
-No_OpClass);
-0x1: ebreak({{
-fault =
make_shared(xc->pcState());
-}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
-0x2: uret({{
-STATUS status = xc->readMiscReg(MISCREG_STATUS);
-status.uie = status.upie;
-status.upie = 1;
-xc->setMiscReg(MISCREG_STATUS, status);
-NPC = xc->readMiscReg(MISCREG_UEPC);
-}}, IsReturn);
-0x102: sret({{
-if (xc->readMiscReg(MISCREG_PRV) == PRV_U) {
-fault = make_shared(
-"sret in user mode", machInst);
-NPC = NPC;
-} else {
+}}, IsSerializeAfter, IsNonSpeculative, IsSyscall,
+No_OpClass);
+0x1: ebreak({{
+fault = make_shared(
+xc->pcState());
+}}, IsSerializeAfter, IsNonSpeculative,
No_OpClass);
+0x2: uret({{
STATUS status =
xc->readMiscReg(MISCREG_STATUS);
-xc->setMiscReg(MISCREG_PRV, status.spp);
-status.sie = status.spie;
-status.spie = 1;
-status.spp = PRV_U;
+status.uie = status.upie;
+status.upie = 1;
xc->setMiscReg(MISCREG_STATUS, status);
-NPC = xc->readMiscReg(MISCREG_SEPC);
-}
-}}, IsReturn);
-0x302: mret({{
+NPC = xc->readMiscReg(MISCREG_UEPC);
+}}, IsReturn);
+}
+0x8: decode RS2 {
+0x2: sret({{
+if (xc->readMiscReg(MISCREG_PRV) == PRV_U) {
+fault =
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv, configs: added bare metal FS support.
Nils Asmussen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/26989 )
Change subject: arch-riscv,configs: added bare metal FS support.
..
arch-riscv,configs: added bare metal FS support.
Change-Id: Id412186d868680b9af97503a5337fc394fd84f68
---
M configs/common/FSConfig.py
M configs/example/fs.py
2 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 3ae00ad..f03e514 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -1,4 +1,5 @@
# Copyright (c) 2010-2012, 2015-2019 ARM Limited
+# Copyright (c) 2020 Barkhausen Institut
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -48,6 +49,7 @@
# Populate to reflect supported os types per target ISA
os_types = { 'mips' : [ 'linux' ],
+ 'riscv' : [ 'linux' ], # TODO that's a lie
'sparc' : [ 'linux' ],
'x86' : [ 'linux' ],
'arm' : [ 'linux',
@@ -626,6 +628,28 @@
self.workload.command_line = fillInCmdline(mdesc, cmdline)
return self
+def makeBareMetalRiscvSystem(mem_mode, mdesc=None, cmdline=None):
+self = RiscvSystem()
+if not mdesc:
+# generic system
+mdesc = SysConfig()
+self.mem_mode = mem_mode
+self.mem_ranges = [AddrRange(mdesc.mem())]
+
+self.workload = RiscvBareMetal()
+
+self.iobus = IOXBar()
+self.membus = MemBus()
+
+self.bridge = Bridge(delay='50ns')
+self.bridge.master = self.iobus.slave
+self.bridge.slave = self.membus.master
+# Sv39 has 56 bit physical addresses; use the upper 8 bit for the IO
space
+IO_address_space_base = 0x00FF
+self.bridge.ranges = [AddrRange(IO_address_space_base, Addr.max)]
+
+self.system_port = self.membus.slave
+return self
def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
self = Root(full_system = full_system)
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 5264aa5..6643d35 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -1,4 +1,5 @@
# Copyright (c) 2010-2013, 2016, 2019 ARM Limited
+# Copyright (c) 2020 Barkhausen Institut
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -82,6 +83,9 @@
test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0],
cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "sparc":
test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
+elif buildEnv['TARGET_ISA'] == "riscv":
+test_sys = makeBareMetalRiscvSystem(test_mem_mode, bm[0],
+cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "x86":
test_sys = makeLinuxX86System(test_mem_mode, np, bm[0],
options.ruby,
cmdline=cmdline)
@@ -123,7 +127,9 @@
voltage_domain =
test_sys.cpu_voltage_domain)
-if options.kernel is not None:
+if buildEnv['TARGET_ISA'] == 'riscv':
+test_sys.workload.bootloader = options.kernel
+elif options.kernel is not None:
test_sys.workload.object_file = binary(options.kernel)
if options.script is not None:
--
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: implement RemoteGDB::acc for FS mode.
Nils Asmussen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/26985 )
Change subject: arch-riscv: implement RemoteGDB::acc for FS mode.
..
arch-riscv: implement RemoteGDB::acc for FS mode.
Change-Id: I78b37db43fbb16d4dafa74294117e8beba62f903
---
M src/arch/riscv/remote_gdb.cc
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/src/arch/riscv/remote_gdb.cc b/src/arch/riscv/remote_gdb.cc
index 16b4585..7da666d 100644
--- a/src/arch/riscv/remote_gdb.cc
+++ b/src/arch/riscv/remote_gdb.cc
@@ -2,6 +2,7 @@
* Copyright 2015 LabWare
* Copyright 2014 Google, Inc.
* Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2020 Barkhausen Institut
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -133,7 +134,9 @@
#include
+#include "arch/riscv/pagetable_walker.hh"
#include "arch/riscv/registers.hh"
+#include "arch/riscv/tlb.hh"
#include "cpu/thread_state.hh"
#include "debug/GDBAcc.hh"
#include "mem/page_table.hh"
@@ -150,7 +153,25 @@
bool
RemoteGDB::acc(Addr va, size_t len)
{
-panic_if(FullSystem, "acc not implemented for RISCV FS!");
+if (FullSystem)
+{
+TLB *tlb = dynamic_cast(context()->getDTBPtr());
+unsigned logBytes;
+Addr paddr = va;
+
+PrivilegeMode pmode = tlb->getMemPriv(context(), BaseTLB::Read);
+SATP satp = context()->readMiscReg(MISCREG_SATP);
+if (pmode != PrivilegeMode::PRV_M &&
+satp.mode != AddrXlateMode::BARE) {
+Walker *walker = tlb->getWalker();
+Fault fault = walker->startFunctional(
+context(), paddr, logBytes, BaseTLB::Read);
+if (fault != NoFault)
+return false;
+}
+return true;
+}
+
return context()->getProcessPtr()->pTable->lookup(va) != nullptr;
}
--
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Gerrit-Project: public/gem5
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Gerrit-Change-Id: I78b37db43fbb16d4dafa74294117e8beba62f903
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[gem5-dev] Change in gem5/gem5[develop]: util: Add some settings files for build_cross_gcc.
Gabe Black has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/26764 ) Change subject: util: Add some settings files for build_cross_gcc. .. util: Add some settings files for build_cross_gcc. These files have settings for 32 and 64 bit ARM, MIPS, POWER, RISCV, and SPARC. When used with the versions of toolchain components below, they all generate working hello world binaries. binutils-2.34 gcc-9.3.0 glibc-2.31 linux-5.5.9 gdb-9.1 The script was unable to install the c++ standard headers (step 8) because a constant was not found when building one of the sanitizers. I don't know exactly why this happens, but I suspect it's independent of the build process. Change-Id: I9f0068b77edf338ed63b95f007454c07651aa42a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26764 Maintainer: Gabe Black Tested-by: Gem5 Cloud Project GCB service account <345032938...@cloudbuild.gserviceaccount.com> Reviewed-by: Jason Lowe-Power --- A util/build_cross_gcc/settings.aarch64 A util/build_cross_gcc/settings.arm A util/build_cross_gcc/settings.mips A util/build_cross_gcc/settings.power A util/build_cross_gcc/settings.riscv A util/build_cross_gcc/settings.sparc 6 files changed, 12 insertions(+), 0 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved Gabe Black: Looks good to me, approved Gem5 Cloud Project GCB service account: Regressions pass diff --git a/util/build_cross_gcc/settings.aarch64 b/util/build_cross_gcc/settings.aarch64 new file mode 100644 index 000..d2b21f6 --- /dev/null +++ b/util/build_cross_gcc/settings.aarch64 @@ -0,0 +1,2 @@ +TARGET=aarch64-linux-gnu +LINUX_ARCH=arm64 diff --git a/util/build_cross_gcc/settings.arm b/util/build_cross_gcc/settings.arm new file mode 100644 index 000..7f3eff3 --- /dev/null +++ b/util/build_cross_gcc/settings.arm @@ -0,0 +1,2 @@ +TARGET=arm-linux-gnueabihf +LINUX_ARCH=arm diff --git a/util/build_cross_gcc/settings.mips b/util/build_cross_gcc/settings.mips new file mode 100644 index 000..c29e4ad --- /dev/null +++ b/util/build_cross_gcc/settings.mips @@ -0,0 +1,2 @@ +TARGET=mipsel-linux-gnu +LINUX_ARCH=mips diff --git a/util/build_cross_gcc/settings.power b/util/build_cross_gcc/settings.power new file mode 100644 index 000..998a2bc --- /dev/null +++ b/util/build_cross_gcc/settings.power @@ -0,0 +1,2 @@ +TARGET=powerpc-linux-gnu +LINUX_ARCH=powerpc diff --git a/util/build_cross_gcc/settings.riscv b/util/build_cross_gcc/settings.riscv new file mode 100644 index 000..d1910e8 --- /dev/null +++ b/util/build_cross_gcc/settings.riscv @@ -0,0 +1,2 @@ +TARGET=riscv64-linux-gnu +LINUX_ARCH=riscv diff --git a/util/build_cross_gcc/settings.sparc b/util/build_cross_gcc/settings.sparc new file mode 100644 index 000..cc96530 --- /dev/null +++ b/util/build_cross_gcc/settings.sparc @@ -0,0 +1,2 @@ +TARGET=sparc64-linux-gnu +LINUX_ARCH=sparc -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/26764 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I9f0068b77edf338ed63b95f007454c07651aa42a Gerrit-Change-Number: 26764 Gerrit-PatchSet: 8 Gerrit-Owner: Gabe Black Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Brandon Potter Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Gem5 Cloud Project GCB service account <345032938...@cloudbuild.gserviceaccount.com> Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-CC: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
