[gem5-dev] Change in gem5/gem5[develop]: mem-cache: prevent prefetcher from saturating the write buffer
Tommaso Marinelli has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/29615 )
Change subject: mem-cache: prevent prefetcher from saturating the write
buffer
..
mem-cache: prevent prefetcher from saturating the write buffer
When the write buffer is full, it still has space to store an additional
number of entries (reserve) equal to the number of MSHRs so that if any
of them requires a writeback this can be handled. Even if the slave port
is blocked, a prefetcher can generate new MSHR entries that may lead to
additional writebacks and eventually saturate the reserve space. This is
solved by checking if the cache is blocked for accesses before
prefetching data.
Change-Id: Iaad04dd6786a09eab7afae4a53d1b1299c341f33
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29615
Reviewed-by: Daniel Carvalho
Reviewed-by: Nikos Nikoleris
Maintainer: Nikos Nikoleris
Tested-by: kokoro
---
M src/mem/cache/base.cc
1 file changed, 3 insertions(+), 3 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 1e16008..0187703 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -514,7 +514,7 @@
// Request the bus for a prefetch if this deallocation freed enough
// MSHRs for a prefetch to take place
-if (prefetcher && mshrQueue.canPrefetch()) {
+if (prefetcher && mshrQueue.canPrefetch() && !isBlocked()) {
Tick next_pf_time =
std::max(prefetcher->nextPrefetchReadyTime(),
clockEdge());
if (next_pf_time != MaxTick)
@@ -764,7 +764,7 @@
// fall through... no pending requests. Try a prefetch.
assert(!miss_mshr && !wq_entry);
-if (prefetcher && mshrQueue.canPrefetch()) {
+if (prefetcher && mshrQueue.canPrefetch() && !isBlocked()) {
// If we have a miss queue slot, we can try a prefetch
PacketPtr pkt = prefetcher->getPacket();
if (pkt) {
@@ -1643,7 +1643,7 @@
// Don't signal prefetch ready time if no MSHRs available
// Will signal once enoguh MSHRs are deallocated
-if (prefetcher && mshrQueue.canPrefetch()) {
+if (prefetcher && mshrQueue.canPrefetch() && !isBlocked()) {
nextReady = std::min(nextReady,
prefetcher->nextPrefetchReadyTime());
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iaad04dd6786a09eab7afae4a53d1b1299c341f33
Gerrit-Change-Number: 29615
Gerrit-PatchSet: 6
Gerrit-Owner: Tommaso Marinelli
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: Tommaso Marinelli
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: systemc: Replace include of eventq_impl.hh with eventq.hh.
Gabe Black has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/30014 ) Change subject: systemc: Replace include of eventq_impl.hh with eventq.hh. .. systemc: Replace include of eventq_impl.hh with eventq.hh. eventq_impl.hh has been merged back into eventq.hh, but that change passed another change which started using eventq_impl.hh in systemc. Change-Id: I2e9be5f993fe6a6712a121cd955b0c56a33c87e3 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30014 Reviewed-by: Giacomo Travaglini Maintainer: Gabe Black Tested-by: kokoro --- M src/systemc/core/scheduler.hh 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Giacomo Travaglini: Looks good to me, approved Gabe Black: Looks good to me, approved kokoro: Regressions pass diff --git a/src/systemc/core/scheduler.hh b/src/systemc/core/scheduler.hh index 31cc35e..c9ca161 100644 --- a/src/systemc/core/scheduler.hh +++ b/src/systemc/core/scheduler.hh @@ -36,7 +36,7 @@ #include "base/logging.hh" #include "sim/core.hh" -#include "sim/eventq_impl.hh" +#include "sim/eventq.hh" #include "systemc/core/channel.hh" #include "systemc/core/list.hh" #include "systemc/core/process.hh" -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/30014 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I2e9be5f993fe6a6712a121cd955b0c56a33c87e3 Gerrit-Change-Number: 30014 Gerrit-PatchSet: 2 Gerrit-Owner: Gabe Black Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: misc: Remove any reference to the ALPHA ISA
Hello Nikos Nikoleris,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/30015
to review the following change.
Change subject: misc: Remove any reference to the ALPHA ISA
..
misc: Remove any reference to the ALPHA ISA
Change-Id: Ie761cd69ae0e8e632ca2b92e63a404e8804f0e6f
Signed-off-by: Giacomo Travaglini
Reviewed-by: Nikos Nikoleris
---
M MAINTAINERS
M SConstruct
M src/arch/mips/idle_event.hh
M src/arch/sparc/kernel_stats.hh
M tests/gem5/.testignore
M tests/gem5/hello_se/test_hello_se.py
M tests/testing/tests.py
M util/checkpoint-tester.py
M util/compile
M util/cpt_upgraders/isa-is-simobject.py
M util/git-commit-msg.py
11 files changed, 14 insertions(+), 74 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 436e661..9a4d7fc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -102,7 +102,6 @@
stats: Updates to statistics for regressions
system: System boot code and related components
-system-alpha:
system-arm:
Andreas Sandberg
Giacomo Travaglini
diff --git a/SConstruct b/SConstruct
index 370cd60..3a03af4 100755
--- a/SConstruct
+++ b/SConstruct
@@ -988,7 +988,7 @@
all_gpu_isa_list.sort()
sticky_vars.AddVariables(
-EnumVariable('TARGET_ISA', 'Target ISA', 'alpha', all_isa_list),
+EnumVariable('TARGET_ISA', 'Target ISA', 'null', all_isa_list),
EnumVariable('TARGET_GPU_ISA', 'Target GPU ISA', 'hsail',
all_gpu_isa_list),
ListVariable('CPU_MODELS', 'CPU models',
sorted(n for n,m in CpuModel.dict.items() if m.default),
diff --git a/src/arch/mips/idle_event.hh b/src/arch/mips/idle_event.hh
index 1401918..d332b87 100644
--- a/src/arch/mips/idle_event.hh
+++ b/src/arch/mips/idle_event.hh
@@ -26,8 +26,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __KERN_MIPS_IDLE_EVENT_HH__
-#define __KERN_MIPS_IDLE_EVENT_HH__
+#ifndef __ARCH_MIPS_IDLE_EVENT_HH__
+#define __ARCH_MIPS_IDLE_EVENT_HH__
#include "cpu/pc_event.hh"
@@ -40,4 +40,4 @@
virtual void process(ThreadContext *tc);
};
-#endif // __KERN_ALPHA_IDLE_EVENT_HH__
+#endif // __ARCH_MIPS_IDLE_EVENT_HH__
diff --git a/src/arch/sparc/kernel_stats.hh b/src/arch/sparc/kernel_stats.hh
index 80b8a04..41a8dd0 100644
--- a/src/arch/sparc/kernel_stats.hh
+++ b/src/arch/sparc/kernel_stats.hh
@@ -46,7 +46,7 @@
{}
};
-} // namespace AlphaISA::Kernel
-} // namespace AlphaISA
+} // namespace SparcISA::Kernel
+} // namespace SparcISA
#endif // __ARCH_SPARC_KERNEL_STATS_HH__
diff --git a/tests/gem5/.testignore b/tests/gem5/.testignore
index b8cfc7f..c76d7c6 100644
--- a/tests/gem5/.testignore
+++ b/tests/gem5/.testignore
@@ -93,95 +93,59 @@
test-insttest-linux-AtomicSimpleCPU-SPARC-i386-fast
test-insttest-linux-TimingSimpleCPU-SPARC-i386-fast
test-hello-linux-MinorCPU-RISCV-x86_64-debug
-test-hello-linux-MinorCPU-ALPHA-x86_64-debug
test-hello-linux-TimingSimpleCPU-SPARC-x86_64-debug
test-hello-linux-AtomicSimpleCPU-SPARC-x86_64-debug
test-hello-linux-TimingSimpleCPU-MIPS-x86_64-debug
test-hello-linux-AtomicSimpleCPU-MIPS-x86_64-debug
test-hello-linux-DerivO3CPU-MIPS-x86_64-debug
-test-hello-linux-TimingSimpleCPU-ALPHA-x86_64-debug
-test-hello-linux-AtomicSimpleCPU-ALPHA-x86_64-debug
-test-hello-linux-DerivO3CPU-ALPHA-x86_64-debug
test-hello-linux-MinorCPU-RISCV-x86_64-fast
-test-hello-linux-MinorCPU-ALPHA-x86_64-fast
test-hello-linux-TimingSimpleCPU-SPARC-x86_64-fast
test-hello-linux-AtomicSimpleCPU-SPARC-x86_64-fast
test-hello-linux-TimingSimpleCPU-MIPS-x86_64-fast
test-hello-linux-AtomicSimpleCPU-MIPS-x86_64-fast
test-hello-linux-DerivO3CPU-MIPS-x86_64-fast
-test-hello-linux-TimingSimpleCPU-ALPHA-x86_64-fast
-test-hello-linux-AtomicSimpleCPU-ALPHA-x86_64-fast
-test-hello-linux-DerivO3CPU-ALPHA-x86_64-fast
test-hello-linux-MinorCPU-RISCV-x86_64-opt
-test-hello-linux-MinorCPU-ALPHA-x86_64-opt
test-hello-linux-TimingSimpleCPU-SPARC-x86_64-opt
test-hello-linux-AtomicSimpleCPU-SPARC-x86_64-opt
test-hello-linux-TimingSimpleCPU-MIPS-x86_64-opt
test-hello-linux-AtomicSimpleCPU-MIPS-x86_64-opt
test-hello-linux-DerivO3CPU-MIPS-x86_64-opt
-test-hello-linux-TimingSimpleCPU-ALPHA-x86_64-opt
-test-hello-linux-AtomicSimpleCPU-ALPHA-x86_64-opt
-test-hello-linux-DerivO3CPU-ALPHA-x86_64-opt
test-hello-linux-MinorCPU-RISCV-arch64-debug
-test-hello-linux-MinorCPU-ALPHA-arch64-debug
test-hello-linux-TimingSimpleCPU-SPARC-arch64-debug
test-hello-linux-AtomicSimpleCPU-SPARC-arch64-debug
test-hello-linux-TimingSimpleCPU-MIPS-arch64-debug
test-hello-linux-AtomicSimpleCPU-MIPS-arch64-debug
test-hello-linux-DerivO3CPU-MIPS-arch64-debug
-test-hello-linux-TimingSimpleCPU-ALPHA-arch64-debug
-test-hello-linux-AtomicSimpleCPU-ALPHA-arch64-debug
-test-hello-linux-DerivO3CPU-ALPHA-arch64-debug
test-hello-linux-MinorCPU-RISCV-arch64-fast
-test-hello-linux-MinorCPU-ALPHA-arch64-fast
test-hello-linux-TimingSimpleCPU-SPARC-arch64-fast
[gem5-dev] Change in gem5/gem5[develop]: scons: Add MARSHAL_XXFLAGS_EXTRA for the marshal object
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/30016 )
Change subject: scons: Add MARSHAL_XXFLAGS_EXTRA for the marshal object
..
scons: Add MARSHAL_XXFLAGS_EXTRA for the marshal object
We already provide to the user the CCFLAGS_EXTRA, LDFLAGS_EXTRA
variables to pass flags to scons when compiling/linking gem5.
Those variables are not passed to the marshal object.
We add an extra pair:
MARSHAL_CCFLAGS_EXTRA, MARSHAL_LDFLAGS_EXTRA
to add flag injection capabilities to the marshal object.
The patch is also renaming base_py_env to marshal_env.
This happens for 2 reasons:
1) At the moment the marshal compilation is the only task
making use of the base python environment.
2) Consistency with the EXTRA variable names added with this patch.
I could have named them as BASE_XXFLAGS_EXTRA, but it seems too much
generic and users might be confused by that, as they might think
the BASE_XXFLAGS_EXTRA is a subset of the XXFLAGS_EXTRA so that
setting it will affect gem5 compilation as well.
Change-Id: I3e420caa897059455ff8f35462db2b38da050e93
Signed-off-by: Giacomo Travaglini
---
M SConstruct
M src/SConscript
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/SConstruct b/SConstruct
index 3a03af4..5a66bba 100755
--- a/SConstruct
+++ b/SConstruct
@@ -276,6 +276,8 @@
('CXX', 'C++ compiler', environ.get('CXX', main['CXX'])),
('CCFLAGS_EXTRA', 'Extra C and C++ compiler flags', ''),
('LDFLAGS_EXTRA', 'Extra linker flags', ''),
+('MARSHAL_CCFLAGS_EXTRA', 'Extra C and C++ marshal compiler
flags', ''),
+('MARSHAL_LDFLAGS_EXTRA', 'Extra marshal linker flags', ''),
('PYTHON_CONFIG', 'Python config binary to use',
[ 'python2.7-config', 'python-config', 'python3-config' ]),
('PROTOC', 'protoc tool', environ.get('PROTOC', 'protoc')),
@@ -734,7 +736,9 @@
main.Prepend(CPPPATH=Dir('ext/pybind11/include/'))
# Bare minimum environment that only includes python
-base_py_env = main.Clone()
+marshal_env = main.Clone()
+marshal_env.Append(CCFLAGS='$MARSHAL_CCFLAGS_EXTRA')
+marshal_env.Append(LINKFLAGS='$MARSHAL_LDFLAGS_EXTRA')
# On Solaris you need to use libsocket for socket ops
if not
conf.CheckLibWithHeader(None, 'sys/socket.h', 'C++', 'accept(0,0,0);'):
@@ -1285,7 +1289,7 @@
# to the configured variables. It returns a list of environments,
# one for each variant build (debug, opt, etc.)
SConscript('src/SConscript', variant_dir=variant_path,
- exports=['env', 'base_py_env'])
+ exports=['env', 'marshal_env'])
# base help text
Help('''
diff --git a/src/SConscript b/src/SConscript
index 7cd628a..aa233c8 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -1140,7 +1140,7 @@
# Build a small helper that marshals the Python code using the same
# version of Python as gem5. This is in an unorthodox location to
# avoid building it for every variant.
-py_marshal = base_py_env.Program('marshal', 'python/marshal.cc')[0]
+py_marshal = marshal_env.Program('marshal', 'python/marshal.cc')[0]
# Embed python files. All .py files that have been indicated by a
# PySource() call in a SConscript need to be embedded into the M5
@@ -1196,7 +1196,7 @@
code.write(str(target[0]))
for source in PySource.all:
-base_py_env.Command(source.cpp, [ py_marshal, source.tnode ],
+marshal_env.Command(source.cpp, [ py_marshal, source.tnode ],
MakeAction(embedPyFile, Transform("EMBED PY")))
Source(source.cpp, tags=source.tags, add_tags='python')
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/30016
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3e420caa897059455ff8f35462db2b38da050e93
Gerrit-Change-Number: 30016
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: systemc: Replace include of eventq_impl.hh with eventq.hh.
Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/30014 ) Change subject: systemc: Replace include of eventq_impl.hh with eventq.hh. .. systemc: Replace include of eventq_impl.hh with eventq.hh. eventq_impl.hh has been merged back into eventq.hh, but that change passed another change which started using eventq_impl.hh in systemc. Change-Id: I2e9be5f993fe6a6712a121cd955b0c56a33c87e3 --- M src/systemc/core/scheduler.hh 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/systemc/core/scheduler.hh b/src/systemc/core/scheduler.hh index 31cc35e..c9ca161 100644 --- a/src/systemc/core/scheduler.hh +++ b/src/systemc/core/scheduler.hh @@ -36,7 +36,7 @@ #include "base/logging.hh" #include "sim/core.hh" -#include "sim/eventq_impl.hh" +#include "sim/eventq.hh" #include "systemc/core/channel.hh" #include "systemc/core/list.hh" #include "systemc/core/process.hh" -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/30014 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I2e9be5f993fe6a6712a121cd955b0c56a33c87e3 Gerrit-Change-Number: 30014 Gerrit-PatchSet: 1 Gerrit-Owner: Gabe Black Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
