[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Transactional Memory Extension (TME)

2020-06-15 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Hello Timothy Hayes,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/30329

to review the following change.


Change subject: arch-arm: Transactional Memory Extension (TME)
..

arch-arm: Transactional Memory Extension (TME)

This patch extends the generic hardware transactional memory support in
Ruby and the O3/TimingSimpleCPU cores with the Arm-specific hardware
transactional memory architectural extensions (TME).

JIRA: https://gem5.atlassian.net/browse/GEM5-588

Change-Id: I8c663da977ed3e8c94635fcb11834bd001e92054
---
M src/arch/arm/ArmISA.py
M src/arch/arm/ArmSystem.py
M src/arch/arm/SConscript
M src/arch/arm/faults.cc
A src/arch/arm/htm.cc
M src/arch/arm/htm.hh
M src/arch/arm/insts/misc64.cc
M src/arch/arm/insts/misc64.hh
A src/arch/arm/insts/tme64.cc
A src/arch/arm/insts/tme64.hh
A src/arch/arm/insts/tme64classic.cc
A src/arch/arm/insts/tme64ruby.cc
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa/insts/branch64.isa
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/isa/insts/misc64.isa
M src/arch/arm/isa/templates/misc64.isa
M src/arch/arm/isa_traits.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
23 files changed, 1,115 insertions(+), 13 deletions(-)



diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 2641ec3..53cdf60 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -97,8 +97,8 @@
 id_aa64dfr1_el1 = Param.UInt64(0x,
 "AArch64 Debug Feature Register 1")

-# !CRC32 | !SHA2 | !SHA1 | !AES
-id_aa64isar0_el1 = Param.UInt64(0x,
+# TME | !Atomic | !CRC32 | !SHA2 | !SHA1 | !AES
+id_aa64isar0_el1 = Param.UInt64(0x0100,
 "AArch64 Instruction Set Attribute Register 0")

 # GPI = 0x0 | GPA = 0x1| API=0x0 | APA=0x1 | FCMA
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 6555ea9..6efc1e0 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -75,7 +75,8 @@
 "True if LSE is implemented (ARMv8.1)")
 have_pan = Param.Bool(True,
 "True if Priviledge Access Never is implemented (ARMv8.1)")
-
+have_tme = Param.Bool(True,
+"True if transactional memory extension (TME) is implemented")
 semihosting = Param.ArmSemihosting(NULL,
 "Enable support for the Arm semihosting by settings this  
parameter")


diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index 73ebcac..c57ba84 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -1,6 +1,6 @@
 # -*- mode:python -*-

-# Copyright (c) 2009, 2012-2013, 2017-2018 ARM Limited
+# Copyright (c) 2009, 2012-2013, 2017-2018, 2020 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -48,6 +48,7 @@
 GTest('aapcs64.test', 'aapcs64.test.cc')
 Source('decoder.cc')
 Source('faults.cc')
+Source('htm.cc')
 Source('insts/branch.cc')
 Source('insts/branch64.cc')
 Source('insts/data64.cc')
@@ -64,6 +65,11 @@
 Source('insts/vfp.cc')
 Source('insts/fplib.cc')
 Source('insts/crypto.cc')
+Source('insts/tme64.cc')
+if env['PROTOCOL'] == 'MESI_Three_Level':
+Source('insts/tme64ruby.cc')
+else:
+Source('insts/tme64classic.cc')
 Source('interrupts.cc')
 Source('isa.cc')
 Source('isa_device.cc')
@@ -101,6 +107,7 @@
 SimObject('ArmPMU.py')

 DebugFlag('Arm')
+DebugFlag('ArmTme', 'Transactional Memory Extension')
 DebugFlag('Semihosting')
 DebugFlag('Decoder', "Instructions returned by the predecoder")
 DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 22894f3..07d3a2b 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -41,13 +41,17 @@

 #include "arch/arm/faults.hh"

+#include "arch/arm/decoder.hh"
+#include "arch/arm/htm.hh"
 #include "arch/arm/insts/static_inst.hh"
+#include "arch/arm/locked_mem.hh"
 #include "arch/arm/system.hh"
 #include "arch/arm/utility.hh"
 #include "base/compiler.hh"
 #include "base/trace.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
+#include "debug/ArmTme.hh"
 #include "debug/Faults.hh"
 #include "sim/full_system.hh"

diff --git a/src/arch/arm/htm.cc b/src/arch/arm/htm.cc
new file mode 100644
index 000..0f865ea
--- /dev/null
+++ b/src/arch/arm/htm.cc
@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the 

[gem5-dev] Change in gem5/gem5[develop]: mem: Relax packet limit in packet queue

2020-06-15 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Hello Timothy Hayes,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/30317

to review the following change.


Change subject: mem: Relax packet limit in packet queue
..

mem: Relax packet limit in packet queue

JIRA: https://gem5.atlassian.net/browse/GEM5-587

Change-Id: I4ac24bf18a0aff08a5b33c48179b882b27ef910c
Signed-off-by: Giacomo Travaglini 
---
M src/mem/packet_queue.cc
1 file changed, 3 insertions(+), 3 deletions(-)



diff --git a/src/mem/packet_queue.cc b/src/mem/packet_queue.cc
index acf29dd..f49d226 100644
--- a/src/mem/packet_queue.cc
+++ b/src/mem/packet_queue.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012,2015,2018 ARM Limited
+ * Copyright (c) 2012,2015,2018-2020 ARM Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -115,8 +115,8 @@

 // add a very basic sanity check on the port to ensure the
 // invisible buffer is not growing beyond reasonable limits
-if (!_disableSanityCheck && transmitList.size() > 100) {
-panic("Packet queue %s has grown beyond 100 packets\n",
+if (!_disableSanityCheck && transmitList.size() > 1000) {
+panic("Packet queue %s has grown beyond 1000 packets\n",
   name());
 }


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4ac24bf18a0aff08a5b33c48179b882b27ef910c
Gerrit-Change-Number: 30317
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Timothy Hayes 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: gpu-compute, mem-ruby, configs: Add GCN3 ISA support to GPU model

2020-06-15 Thread Anthony Gutierrez (Gerrit) via gem5-dev
Anthony Gutierrez has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/29912 )


Change subject: gpu-compute, mem-ruby, configs: Add GCN3 ISA support to GPU  
model

..

gpu-compute, mem-ruby, configs: Add GCN3 ISA support to GPU model

Change-Id: Ibe46970f3ba25d62ca2ade5cbc2054ad746b2254
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29912
Reviewed-by: Anthony Gutierrez 
Reviewed-by: Jason Lowe-Power 
Maintainer: Anthony Gutierrez 
Tested-by: kokoro 
---
A build_opts/GCN3_X86
M configs/common/GPUTLBConfig.py
M src/arch/gcn3/insts/instructions.cc
M src/arch/gcn3/insts/op_encodings.hh
M src/arch/gcn3/operand.hh
M src/dev/hsa/hsa_device.cc
M src/dev/hsa/hsa_driver.cc
M src/dev/hsa/hsa_driver.hh
M src/dev/hsa/hsa_packet_processor.cc
M src/dev/hsa/hw_scheduler.cc
M src/gpu-compute/GPU.py
M src/gpu-compute/GPUStaticInstFlags.py
M src/gpu-compute/SConscript
M src/gpu-compute/compute_unit.cc
M src/gpu-compute/compute_unit.hh
M src/gpu-compute/dispatcher.cc
M src/gpu-compute/dispatcher.hh
M src/gpu-compute/exec_stage.cc
M src/gpu-compute/exec_stage.hh
M src/gpu-compute/fetch_stage.cc
M src/gpu-compute/fetch_stage.hh
M src/gpu-compute/fetch_unit.cc
M src/gpu-compute/fetch_unit.hh
M src/gpu-compute/global_memory_pipeline.cc
M src/gpu-compute/global_memory_pipeline.hh
A src/gpu-compute/gpu_command_processor.cc
A src/gpu-compute/gpu_command_processor.hh
A src/gpu-compute/gpu_compute_driver.cc
A src/gpu-compute/gpu_compute_driver.hh
M src/gpu-compute/gpu_dyn_inst.cc
M src/gpu-compute/gpu_dyn_inst.hh
M src/gpu-compute/gpu_exec_context.cc
M src/gpu-compute/gpu_static_inst.cc
M src/gpu-compute/gpu_static_inst.hh
M src/gpu-compute/gpu_tlb.cc
M src/gpu-compute/gpu_tlb.hh
A src/gpu-compute/hsa_queue_entry.hh
A src/gpu-compute/kernel_code.hh
M src/gpu-compute/lds_state.cc
M src/gpu-compute/lds_state.hh
M src/gpu-compute/local_memory_pipeline.cc
M src/gpu-compute/local_memory_pipeline.hh
M src/gpu-compute/misc.hh
M src/gpu-compute/pool_manager.cc
M src/gpu-compute/pool_manager.hh
A src/gpu-compute/register_file.cc
A src/gpu-compute/register_file.hh
A src/gpu-compute/register_manager.cc
A src/gpu-compute/register_manager.hh
A src/gpu-compute/register_manager_policy.hh
M src/gpu-compute/rr_scheduling_policy.hh
A src/gpu-compute/scalar_memory_pipeline.cc
A src/gpu-compute/scalar_memory_pipeline.hh
A src/gpu-compute/scalar_register_file.cc
A src/gpu-compute/scalar_register_file.hh
M src/gpu-compute/schedule_stage.cc
M src/gpu-compute/schedule_stage.hh
M src/gpu-compute/scoreboard_check_stage.cc
M src/gpu-compute/scoreboard_check_stage.hh
M src/gpu-compute/shader.cc
M src/gpu-compute/shader.hh
M src/gpu-compute/simple_pool_manager.cc
M src/gpu-compute/simple_pool_manager.hh
A src/gpu-compute/static_register_manager_policy.cc
A src/gpu-compute/static_register_manager_policy.hh
M src/gpu-compute/tlb_coalescer.cc
M src/gpu-compute/tlb_coalescer.hh
M src/gpu-compute/vector_register_file.cc
M src/gpu-compute/vector_register_file.hh
M src/gpu-compute/wavefront.cc
M src/gpu-compute/wavefront.hh
M src/mem/packet.cc
M src/mem/packet.hh
M src/mem/ruby/protocol/GPU_VIPER-TCP.sm
A src/mem/ruby/protocol/GPU_VIPER-msg.sm
M src/mem/ruby/protocol/GPU_VIPER.slicc
M src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
M src/mem/ruby/protocol/RubySlicc_Exports.sm
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/ruby/slicc_interface/RubyRequest.hh
M src/mem/ruby/system/GPUCoalescer.cc
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/ruby/system/GPUCoalescer.py
M src/mem/ruby/system/VIPERCoalescer.hh
M src/mem/ruby/system/VIPERCoalescer.py
86 files changed, 10,299 insertions(+), 3,734 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Anthony Gutierrez: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibe46970f3ba25d62ca2ade5cbc2054ad746b2254
Gerrit-Change-Number: 29912
Gerrit-PatchSet: 8
Gerrit-Owner: Anthony Gutierrez 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Bradford Beckmann 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: Tony Gutierrez 
Gerrit-Reviewer: Tuan Ta 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Fixing HSA's barrier bit implementation

2020-06-15 Thread Matt Sinclair (Gerrit) via gem5-dev
Matt Sinclair has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30354 )



Change subject: gpu-compute: Fixing HSA's barrier bit implementation
..

gpu-compute: Fixing HSA's barrier bit implementation

This changeset fixes several bugs in the HSA barrier bit implementation.

1. Forces AQL packet launch to wait for completion of all previous packets
2. Enforces barrier bit blocking only if there are packets pending  
completion

3. Barrier bit unblocking is correclty done by the last pending packet
4. Implementing barrier bit for all packets to conform to HSA spec

Change-Id: I62ce589dff57dcde4d64054a1b6ffd962acd5eb8
---
M src/dev/hsa/hsa_packet_processor.cc
M src/dev/hsa/hsa_packet_processor.hh
2 files changed, 84 insertions(+), 14 deletions(-)



diff --git a/src/dev/hsa/hsa_packet_processor.cc  
b/src/dev/hsa/hsa_packet_processor.cc

index f9880e4..4183d6d 100644
--- a/src/dev/hsa/hsa_packet_processor.cc
+++ b/src/dev/hsa/hsa_packet_processor.cc
@@ -277,11 +277,11 @@
 }

 void
-HSAPacketProcessor::schedAQLProcessing(uint32_t rl_idx)
+HSAPacketProcessor::schedAQLProcessing(uint32_t rl_idx, Tick delay)
 {
 RQLEntry *queue = regdQList[rl_idx];
 if (!queue->aqlProcessEvent.scheduled()) {
-Tick processingTick = curTick() + pktProcessDelay;
+Tick processingTick = curTick() + delay;
 schedule(queue->aqlProcessEvent, processingTick);
 DPRINTF(HSAPacketProcessor, "AQL processing scheduled at  
tick: %d\n",

 processingTick);
@@ -290,32 +290,48 @@
 }
 }

-bool
-HSAPacketProcessor::processPkt(void* pkt, uint32_t rl_idx, Addr  
host_pkt_addr)

+void
+HSAPacketProcessor::schedAQLProcessing(uint32_t rl_idx)
 {
-bool is_submitted = false;
+schedAQLProcessing(rl_idx, pktProcessDelay);
+}
+
+Q_STATE HSAPacketProcessor::processPkt(void* pkt, uint32_t rl_idx,
+   Addr host_pkt_addr)
+{
+Q_STATE is_submitted = BLOCKED_BPKT;
 SignalState *dep_sgnl_rd_st = &(regdQList[rl_idx]->depSignalRdState);
 // Dependency signals are not read yet. And this can only be a retry.
 // The retry logic will schedule the packet processor wakeup
 if (dep_sgnl_rd_st->pendingReads != 0) {
-return false;
+return BLOCKED_BPKT;
 }
 // `pkt` can be typecasted to any type of AQL packet since they all
 // have header information at offset zero
 auto disp_pkt = (_hsa_dispatch_packet_t *)pkt;
 hsa_packet_type_t pkt_type = PKT_TYPE(disp_pkt);
+if (IS_BARRIER(disp_pkt) &&
+regdQList[rl_idx]->compltnPending() > 0) {
+// If this packet is using the "barrier bit" to enforce ordering  
with

+// previous packets, and if there are outstanding packets, set the
+// barrier bit for this queue and block the queue.
+DPRINTF(HSAPacketProcessor, "%s: setting barrier bit for active" \
+" list ID = %d\n", __FUNCTION__, rl_idx);
+regdQList[rl_idx]->setBarrierBit(true);
+return BLOCKED_BBIT;
+}
 if (pkt_type == HSA_PACKET_TYPE_VENDOR_SPECIFIC) {
 DPRINTF(HSAPacketProcessor, "%s: submitting vendor specific pkt" \
 " active list ID = %d\n", __FUNCTION__, rl_idx);
 // Submit packet to HSA device (dispatcher)
 hsa_device->submitVendorPkt((void *)disp_pkt, rl_idx,  
host_pkt_addr);

-is_submitted = true;
+is_submitted = UNBLOCKED;
 } else if (pkt_type == HSA_PACKET_TYPE_KERNEL_DISPATCH) {
 DPRINTF(HSAPacketProcessor, "%s: submitting kernel dispatch pkt" \
 " active list ID = %d\n", __FUNCTION__, rl_idx);
 // Submit packet to HSA device (dispatcher)
 hsa_device->submitDispatchPkt((void *)disp_pkt, rl_idx,  
host_pkt_addr);

-is_submitted = true;
+is_submitted = UNBLOCKED;
 } else if (pkt_type == HSA_PACKET_TYPE_BARRIER_AND) {
 DPRINTF(HSAPacketProcessor, "%s: Processing barrier packet" \
 " active list ID = %d\n", __FUNCTION__, rl_idx);
@@ -372,7 +388,7 @@
 // TODO: Completion signal of barrier packet to be
 // atomically decremented here
 finishPkt((void*)bar_and_pkt, rl_idx);
-is_submitted = true;
+is_submitted = UNBLOCKED;
 // Reset signal values
 dep_sgnl_rd_st->resetSigVals();
 // The completion signal is connected
@@ -432,6 +448,13 @@
 " dispIdx %d, active list ID = %d\n",
 __FUNCTION__, aqlRingBuffer->rdIdx(),
 aqlRingBuffer->wrIdx(), aqlRingBuffer->dispIdx(), rqIdx);
+// If barrier bit is set, then this wakeup is a dummy wakeup
+// just to model the processing time. Do nothing.
+if (hsaPP->regdQList[rqIdx]->getBarrierBit()) {
+DPRINTF(HSAPacketProcessor,
+"Dummy wakeup with barrier bit for rdIdx %d\n", rqIdx);
+

[gem5-dev] Change in gem5/gem5[develop]: cpu: Add HTM CPU API

2020-06-15 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Hello Timothy Hayes,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/30322

to review the following change.


Change subject: cpu: Add HTM CPU API
..

cpu: Add HTM CPU API

JIRA: https://gem5.atlassian.net/browse/GEM5-587

Change-Id: Iff95eb97603b4cb9629c04382a824b02594ee5c7
Signed-off-by: Giacomo Travaglini 
---
M src/cpu/checker/cpu.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/simple/atomic.hh
M src/cpu/simple/base.hh
M src/cpu/simple/timing.cc
M src/cpu/simple/timing.hh
7 files changed, 68 insertions(+), 4 deletions(-)



diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 6bd7022..24fad1c 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -434,6 +434,12 @@
 thread->setMemAccPredicate(val);
 }

+Fault initiateHtmCmd(Request::Flags flags) override
+{
+panic("not yet supported!");
+return NoFault;
+}
+
 TheISA::PCState pcState() const override { return thread->pcState(); }
 void
 pcState(const TheISA::PCState ) override
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index b3faf31..79fd1d7 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1833,5 +1833,13 @@
 }
 }

+template 
+void
+FullO3CPU::htmSendAbortSignal(ThreadID tid, uint64_t htmUid,
+ HtmFailureFaultCause cause)
+{
+panic("not yet supported!");
+}
+
 // Forward declaration of FullO3CPU.
 template class FullO3CPU;
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index c3d911b..61bbdbd 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -788,6 +788,11 @@
 //number of misc
 Stats::Scalar miscRegfileReads;
 Stats::Scalar miscRegfileWrites;
+
+  public:
+// hardware transactional memory
+void htmSendAbortSignal(ThreadID tid, uint64_t htm_uid,
+HtmFailureFaultCause cause);
 };

 #endif // __CPU_O3_CPU_HH__
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 53fe0fc..e35cfaa 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2013, 2015, 2018 ARM Limited
+ * Copyright (c) 2012-2013, 2015, 2018-2019 ARM Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -219,6 +219,18 @@
   const std::vector& byte_enable =  
std::vector())

 override;

+Fault initiateHtmCmd(Request::Flags flags) override
+{
+panic("initiateHtmCmd() is for timing accesses, and should "
+  "never be called on AtomicSimpleCPU.\n");
+}
+
+void htmSendAbortSignal(HtmFailureFaultCause cause) override
+{
+panic("htmSendAbortSignal() is for timing accesses, and should "
+  "never be called on AtomicSimpleCPU.\n");
+}
+
 Fault writeMem(uint8_t *data, unsigned size,
Addr addr, Request::Flags flags, uint64_t *res,
const std::vector& byte_enable =  
std::vector())

diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 323850a..b69765b 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2012,2015,2018 ARM Limited
+ * Copyright (c) 2011-2012,2015,2018-2019 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -168,6 +168,21 @@
 void serializeThread(CheckpointOut , ThreadID tid) const override;
 void unserializeThread(CheckpointIn , ThreadID tid) override;

+/** Hardware transactional memory commands (HtmCmds), e.g. start a
+ * transaction and commit a transaction, are memory operations but are
+ * neither really (true) loads nor stores. For this reason the  
interface
+ * is extended and initiateHtmCmd() is used to instigate the command.  
*/

+virtual Fault initiateHtmCmd(Request::Flags flags) = 0;
+
+/** This function is used to instruct the memory subsystem that a
+ * transaction should be aborted and the speculative state should be
+ * thrown away.  This is called in the transaction's very last breath  
in
+ * the core.  Afterwards, the core throws away its speculative state  
and
+ * resumes execution at the point the transaction started, i.e.  
reverses

+ * time.  When instruction execution resumes, the core expects the
+ * memory subsystem to be in a stable, i.e. pre-speculative, state as
+ * well. */
+virtual void htmSendAbortSignal(HtmFailureFaultCause cause) = 0;
 };

 #endif // __CPU_SIMPLE_BASE_HH__
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index c1c70cb..a509562 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -1,6 +1,6 @@
 /*
  * Copyright 2014 Google, Inc.
- * Copyright (c) 2010-2013,2015,2017-2018 ARM Limited
+ * Copyright (c) 2010-2013,2015,2017-2019 ARM Limited
  * All rights reserved
  *
  * The license 

[gem5-dev] Change in gem5/gem5[develop]: sim: Add some helpers to catch and reporting using unbound ports.

2020-06-15 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30295 )


Change subject: sim: Add some helpers to catch and reporting using unbound  
ports.

..

sim: Add some helpers to catch and reporting using unbound ports.

If a port is unbound, trying to call its peer will likely cause a
segfault. Rather than check if a port is bound every time you go to use
it, we can instead bind to a default peer which just throws an exception
back to the caller. The caller can catch the exception and report the
error.

This change adds a common new class to throw as the exception, and also
a small utility function which reports the error and dies.

Change-Id: Ia58a2030922c73e2fd7d139822bce38d9b0f2171
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30295
Reviewed-by: Nikos Nikoleris 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/sim/port.cc
M src/sim/port.hh
2 files changed, 13 insertions(+), 0 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/port.cc b/src/sim/port.cc
index 7ca8db6..9131f84 100644
--- a/src/sim/port.cc
+++ b/src/sim/port.cc
@@ -45,7 +45,16 @@

 #include "sim/port.hh"

+#include "base/logging.hh"
+
 Port::Port(const std::string& _name, PortID _id) :
 portName(_name), id(_id), _peer(nullptr), _connected(false)
 {}
 Port::~Port() {}
+
+
+void
+Port::reportUnbound() const
+{
+fatal("%s: Unconnected port!", name());
+}
diff --git a/src/sim/port.hh b/src/sim/port.hh
index 251624c..85472d0 100644
--- a/src/sim/port.hh
+++ b/src/sim/port.hh
@@ -63,6 +63,10 @@

   protected:

+class UnboundPortException {};
+
+[[noreturn]] void reportUnbound() const;
+
 /**
  * A numeric identifier to distinguish ports in a vector, and set
  * to InvalidPortID in case this port is not part of a vector.

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia58a2030922c73e2fd7d139822bce38d9b0f2171
Gerrit-Change-Number: 30295
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu: HTM Implementation for O3CPU

2020-06-15 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Hello Timothy Hayes,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/30328

to review the following change.


Change subject: cpu: HTM Implementation for O3CPU
..

cpu: HTM Implementation for O3CPU

JIRA: https://gem5.atlassian.net/browse/GEM5-587

Change-Id: I83787f4594963a15d856b81ad283b4f032d1c007
Signed-off-by: Giacomo Travaglini 
---
M src/cpu/base_dyn_inst.hh
M src/cpu/base_dyn_inst_impl.hh
M src/cpu/o3/commit.hh
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/iew.hh
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/o3/mem_dep_unit_impl.hh
M src/cpu/o3/thread_context_impl.hh
M src/cpu/o3/thread_state.hh
15 files changed, 676 insertions(+), 32 deletions(-)



diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 119b806..6d929ac 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -61,6 +61,7 @@
 #include "cpu/op_class.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/translation.hh"
+#include "debug/HtmCpu.hh"
 #include "mem/packet.hh"
 #include "mem/request.hh"
 #include "sim/byteswap.hh"
@@ -140,6 +141,7 @@
 IsStrictlyOrdered,
 ReqMade,
 MemOpDone,
+HtmFromTransaction,
 MaxFlags
 };

@@ -240,6 +242,11 @@
 // Need a copy of main request pointer to verify on writes.
 RequestPtr reqToVerify;

+  private:
+// hardware transactional memory
+uint64_t htmUid;
+uint64_t htmDepth;
+
   protected:
 /** Flattened register index of the destination registers of this
  *  instruction.
@@ -548,8 +555,8 @@

 uint64_t getHtmTransactionUid() const override
 {
-panic("Not yet implemented\n");
-return 0;
+assert(instFlags[HtmFromTransaction]);
+return this->htmUid;
 }

 uint64_t newHtmTransactionUid() const override
@@ -560,14 +567,35 @@

 bool inHtmTransactionalState() const override
 {
-panic("Not yet implemented\n");
-return false;
+return instFlags[HtmFromTransaction];
 }

 uint64_t getHtmTransactionalDepth() const override
 {
-panic("Not yet implemented\n");
-return 0;
+if (inHtmTransactionalState())
+return this->htmDepth;
+else
+return 0;
+}
+
+void setHtmTransactionalState(uint64_t htm_uid, uint64_t htm_depth)
+{
+instFlags.set(HtmFromTransaction);
+htmUid = htm_uid;
+htmDepth = htm_depth;
+}
+
+void clearHtmTransactionalState()
+{
+if (inHtmTransactionalState()) {
+DPRINTF(HtmCpu,
+"clearing instuction's transactional state htmUid=%u\n",
+getHtmTransactionUid());
+
+instFlags.reset(HtmFromTransaction);
+htmUid = -1;
+htmDepth = 0;
+}
 }

 /** Temporarily sets this instruction as a serialize before  
instruction. */

@@ -997,8 +1025,9 @@
 Fault
 BaseDynInst::initiateHtmCmd(Request::Flags flags)
 {
-panic("Not yet implemented\n");
-return NoFault;
+return cpu->pushRequest(
+dynamic_cast(this),
+/* ld */ true, nullptr, 8, 0x0ul, flags, nullptr, nullptr);
 }

 template
diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh
index 45b938d..bfe8ff5 100644
--- a/src/cpu/base_dyn_inst_impl.hh
+++ b/src/cpu/base_dyn_inst_impl.hh
@@ -95,6 +95,9 @@
 physEffAddr = 0;
 readyRegs = 0;
 memReqFlags = 0;
+// hardware transactional memory
+htmUid = -1;
+htmDepth = 0;

 status.reset();

diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index 69d1c86..85d00a9 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012, 2014 ARM Limited
+ * Copyright (c) 2010-2012, 2014, 2019 ARM Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -205,6 +205,12 @@
 /** Deschedules a thread from scheduling */
 void deactivateThread(ThreadID tid);

+/** Is the CPU currently processing a HTM transaction? */
+bool executingHtmTransaction(ThreadID) const;
+
+/* Reset HTM tracking, e.g. after an abort */
+void resetHtmStartsStops(ThreadID);
+
 /** Ticks the commit stage, which tries to commit instructions. */
 void tick();

@@ -473,6 +479,11 @@
 /** Updates commit stats based on this instruction. */
 void updateComInstStats(const DynInstPtr );

+
+// HTM
+int htmStarts[Impl::MaxThreads];
+int htmStops[Impl::MaxThreads];
+
 /** Stat for the total number of squashed instructions discarded by  
commit.

  */
 Stats::Scalar commitSquashedInsts;
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 667f42b..68823d6 100644
--- 

[gem5-dev] Change in gem5/gem5[develop]: cpu: Base dyn inst HTM flags getter

2020-06-15 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Hello Timothy Hayes,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/30326

to review the following change.


Change subject: cpu: Base dyn inst HTM flags getter
..

cpu: Base dyn inst HTM flags getter

JIRA: https://gem5.atlassian.net/browse/GEM5-587

Change-Id: Ie15d8849edcff34ee7d5c7dd5e6ee2e099f937fc
Signed-off-by: Giacomo Travaglini 
---
M src/cpu/base_dyn_inst.hh
1 file changed, 5 insertions(+), 0 deletions(-)



diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index e1580a5..119b806 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -540,6 +540,11 @@
 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
+// hardware transactional memory
+bool isHtmStart() const { return staticInst->isHtmStart(); }
+bool isHtmStop() const { return staticInst->isHtmStop(); }
+bool isHtmCancel() const { return staticInst->isHtmCancel(); }
+bool isHtmCmd() const { return staticInst->isHtmCmd(); }

 uint64_t getHtmTransactionUid() const override
 {

--
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Gerrit-Project: public/gem5
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Gerrit-Change-Id: Ie15d8849edcff34ee7d5c7dd5e6ee2e099f937fc
Gerrit-Change-Number: 30326
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Timothy Hayes 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: sim: Add HTM Generic Fault

2020-06-15 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Hello Timothy Hayes,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/30325

to review the following change.


Change subject: sim: Add HTM Generic Fault
..

sim: Add HTM Generic Fault

JIRA: https://gem5.atlassian.net/browse/GEM5-587

Change-Id: Iedbf06d25330a92790123805cff50d57b613a7a5
Signed-off-by: Giacomo Travaglini 
---
M src/sim/faults.cc
M src/sim/faults.hh
2 files changed, 71 insertions(+), 1 deletion(-)



diff --git a/src/sim/faults.cc b/src/sim/faults.cc
index c2ce978..a6cec37 100644
--- a/src/sim/faults.cc
+++ b/src/sim/faults.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -28,7 +40,9 @@

 #include "sim/faults.hh"

+#include "arch/decoder.hh"
 #include "arch/isa_traits.hh"
+#include "arch/locked_mem.hh"
 #include "base/logging.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
@@ -77,3 +91,24 @@
 {
 panic("Alignment fault when accessing virtual address %#x\n", vaddr);
 }
+
+void GenericHtmFailureFault::invoke(ThreadContext *tc,
+const StaticInstPtr )
+{
+// reset decoder
+TheISA::Decoder* dcdr = tc->getDecoderPtr();
+dcdr->reset();
+
+// restore transaction checkpoint
+TheISA::HTMCheckpoint* checkpoint = tc->getHTMCheckpointPtr();
+assert(checkpoint);
+assert(checkpoint->valid());
+
+checkpoint->restore(tc, getHtmFailureFaultCause());
+
+// reset the global monitor
+TheISA::globalClearExclusive(tc);
+
+// send abort packet to ruby (in final breath)
+tc->htmAbortTransaction(_uid, _cause);
+}
diff --git a/src/sim/faults.hh b/src/sim/faults.hh
index 646d24a..2faeeaa 100644
--- a/src/sim/faults.hh
+++ b/src/sim/faults.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -29,6 +41,7 @@
 #ifndef __FAULTS_HH__
 #define __FAULTS_HH__

+#include "arch/generic/htm.hh"
 #include "base/types.hh"
 #include "cpu/static_inst.hh"
 #include "sim/stats.hh"
@@ -44,7 +57,6 @@
 virtual FaultName name() const = 0;
 virtual void invoke(ThreadContext * tc, const StaticInstPtr  =
 StaticInst::nullStaticInstPtr);
-
 virtual ~FaultBase() {};
 };

@@ -111,4 +123,27 @@
 Addr getFaultVAddr() const { return vaddr; }
 };

+// Each ISA implementing HTM is expected
+// to inherit this as THEISA::HtmFailureFault.
+class GenericHtmFailureFault : public FaultBase
+{
+  protected:
+uint64_t _uid; // unique identifier used for debugging
+HtmFailureFaultCause _cause;
+  public:
+GenericHtmFailureFault(uint64_t htmUid, HtmFailureFaultCause cause)
+  : _uid(htmUid), _cause(cause)
+{}
+
+virtual FaultName name() const
+{
+return "Generic HTM transaction failure fault";
+}
+
+uint64_t getHtmUid() const { return _uid; }
+HtmFailureFaultCause getHtmFailureFaultCause() const { return _cause; }
+void invoke(ThreadContext *tc, const StaticInstPtr  =
+StaticInst::nullStaticInstPtr);
+};
+
 #endif // __FAULTS_HH__

--
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Gerrit-Branch: develop
Gerrit-Change-Id: Iedbf06d25330a92790123805cff50d57b613a7a5
Gerrit-Change-Number: 30325
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Timothy Hayes 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem: Add HTM fields to the Packet object

2020-06-15 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Hello Timothy Hayes,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/30318

to review the following change.


Change subject: mem: Add HTM fields to the Packet object
..

mem: Add HTM fields to the Packet object

JIRA: https://gem5.atlassian.net/browse/GEM5-587

Change-Id: I39268825327f2387ca7e622093fdb42c24a6c82c
---
M src/mem/SConscript
A src/mem/htm.cc
A src/mem/htm.hh
M src/mem/packet.cc
M src/mem/packet.hh
5 files changed, 243 insertions(+), 6 deletions(-)



diff --git a/src/mem/SConscript b/src/mem/SConscript
index b77dbb1..0187c09 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -1,6 +1,6 @@
 # -*- mode:python -*-
 #
-# Copyright (c) 2018 ARM Limited
+# Copyright (c) 2018-2019 ARM Limited
 # All rights reserved
 #
 # The license below extends only to copyright in the software and shall
@@ -77,6 +77,7 @@
 Source('tport.cc')
 Source('xbar.cc')
 Source('hmc_controller.cc')
+Source('htm.cc')
 Source('serial_link.cc')
 Source('mem_delay.cc')

@@ -108,6 +109,7 @@
 DebugFlag('DRAMPower')
 DebugFlag('DRAMState')
 DebugFlag('ExternalPort')
+DebugFlag('HtmMem', 'Hardware Transactional Memory (Mem side)')
 DebugFlag('LLSC')
 DebugFlag('MMU')
 DebugFlag('MemoryAccess')
diff --git a/src/mem/htm.cc b/src/mem/htm.cc
new file mode 100644
index 000..dc01e6d
--- /dev/null
+++ b/src/mem/htm.cc
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "mem/htm.hh"
+
+std::string
+htmFailureToStr(HtmCacheFailure rc)
+{
+static const std::map rc_to_string = {
+{ HtmCacheFailure::NO_FAIL, "NO_FAIL" },
+{ HtmCacheFailure::FAIL_SELF, "FAIL_SELF" },
+{ HtmCacheFailure::FAIL_REMOTE, "FAIL_REMOTE" },
+{ HtmCacheFailure::FAIL_OTHER, "FAIL_OTHER" }
+};
+
+auto it = rc_to_string.find(rc);
+return it == rc_to_string.end() ? "Unrecognized Failure" : it->second;
+}
diff --git a/src/mem/htm.hh b/src/mem/htm.hh
new file mode 100644
index 000..e60632b
--- /dev/null
+++ b/src/mem/htm.hh
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions 

[gem5-dev] Change in gem5/gem5[develop]: cpu: Add HTM Instruction Flags

2020-06-15 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Hello Timothy Hayes,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/30321

to review the following change.


Change subject: cpu: Add HTM Instruction Flags
..

cpu: Add HTM Instruction Flags

IsHtmStart: Starts a HTM transaction
IsHtmStop: Stops (commits) a HTM transaction
IsHtmCancel: Explicitely aborts a HTM transaction

JIRA: https://gem5.atlassian.net/browse/GEM5-587

Change-Id: I33144f97a2009e28b0c64777f0313cd6eadb7ff9
Signed-off-by: Giacomo Travaglini 
---
M src/cpu/StaticInstFlags.py
M src/cpu/static_inst.hh
2 files changed, 17 insertions(+), 2 deletions(-)



diff --git a/src/cpu/StaticInstFlags.py b/src/cpu/StaticInstFlags.py
index f756ba1..1c2b63a 100644
--- a/src/cpu/StaticInstFlags.py
+++ b/src/cpu/StaticInstFlags.py
@@ -1,3 +1,4 @@
+# Copyright (c) 2020 ARM Limited
 # Copyright (c) 2003-2005 The Regents of The University of Michigan
 # Copyright (c) 2013 Advanced Micro Devices, Inc.
 # All rights reserved.
@@ -109,5 +110,9 @@
 'IsMicroBranch',# This microop branches within the microcode  
for

 # a macroop
 'IsDspOp',
-'IsSquashAfter' # Squash all uncommitted state after executed
+'IsSquashAfter', # Squash all uncommitted state after executed
+# hardware transactional memory
+'IsHtmStart',   # Starts a HTM transaction
+'IsHtmStop',# Stops (commits) a HTM transaction
+'IsHtmCancel'   # Explicitely aborts a HTM transaction
 ]
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index b523ef9..a1ed299 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017 ARM Limited
+ * Copyright (c) 2017, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -202,6 +202,16 @@
 bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
 //This flag doesn't do anything yet
 bool isMicroBranch() const { return flags[IsMicroBranch]; }
+// hardware transactional memory
+// HtmCmds must be identified as such in order
+// to provide them with necessary memory ordering semantics.
+bool isHtmStart() const { return flags[IsHtmStart]; }
+bool isHtmStop() const { return flags[IsHtmStop]; }
+bool isHtmCancel() const { return flags[IsHtmCancel]; }
+bool isHtmCmd() const
+{
+return (isHtmStart()||isHtmStop()||isHtmCancel());
+}
 //@}

 void setFirstMicroop() { flags[IsFirstMicroop] = true; }

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Gerrit-Change-Id: I33144f97a2009e28b0c64777f0313cd6eadb7ff9
Gerrit-Change-Number: 30321
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Timothy Hayes 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arm: Add missing overrides to the ARM interrupt object.

2020-06-15 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30294 )


Change subject: arm: Add missing overrides to the ARM interrupt object.
..

arm: Add missing overrides to the ARM interrupt object.

Change-Id: Idddc5267d5eb287a0895a1a2e1631ca9a2e789f3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30294
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/interrupts.hh
1 file changed, 4 insertions(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/interrupts.hh b/src/arch/arm/interrupts.hh
index 814fd71..8e78f96 100644
--- a/src/arch/arm/interrupts.hh
+++ b/src/arch/arm/interrupts.hh
@@ -77,7 +77,7 @@


 void
-post(int int_num, int index)
+post(int int_num, int index) override
 {
 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);

@@ -92,7 +92,7 @@
 }

 void
-clear(int int_num, int index)
+clear(int int_num, int index) override
 {
 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);

@@ -107,7 +107,7 @@
 }

 void
-clearAll()
+clearAll() override
 {
 DPRINTF(Interrupt, "Interrupts all cleared\n");
 intStatus = 0;
@@ -123,7 +123,7 @@
 bool takeInt(InterruptTypes int_type) const;

 bool
-checkInterrupts() const
+checkInterrupts() const override
 {
 HCR  hcr  = tc->readMiscReg(MISCREG_HCR);


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idddc5267d5eb287a0895a1a2e1631ca9a2e789f3
Gerrit-Change-Number: 30294
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch: Add uReset helper to UPCState

2020-06-15 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Hello Timothy Hayes,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/30315

to review the following change.


Change subject: arch: Add uReset helper to UPCState
..

arch: Add uReset helper to UPCState

This allows to reset without advancing the pc

https://gem5.atlassian.net/browse/GEM5-587

Change-Id: Ied566f4cd5efed5eb500447d3f14388482435475
Signed-off-by: Giacomo Travaglini 
---
M src/arch/generic/types.hh
1 file changed, 20 insertions(+), 0 deletions(-)



diff --git a/src/arch/generic/types.hh b/src/arch/generic/types.hh
index f981e18..76df835 100644
--- a/src/arch/generic/types.hh
+++ b/src/arch/generic/types.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2010 Gabe Black
  * All rights reserved.
  *
@@ -247,6 +259,14 @@
 _nupc = 1;
 }

+// Reset the macroop's upc without advancing the regular pc.
+void
+uReset()
+{
+_upc = 0;
+_nupc = 1;
+}
+
 bool
 operator == (const UPCState ) const
 {

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ied566f4cd5efed5eb500447d3f14388482435475
Gerrit-Change-Number: 30315
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Timothy Hayes 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: base: Delete deletePointer helpers

2020-06-15 Thread Daniel Carvalho (Gerrit) via gem5-dev
Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/24251 )


Change subject: base: Delete deletePointer helpers
..

base: Delete deletePointer helpers

Now that the calls to deletePointer have been replaced by the use
of smart pointers, they can be safely removed.

Change-Id: I91d8b97f7ba3f64dd9948fd343cf0af969886598
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24251
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/base/stl_helpers.hh
1 file changed, 0 insertions(+), 17 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/stl_helpers.hh b/src/base/stl_helpers.hh
index 2030934..ef4f9ac 100644
--- a/src/base/stl_helpers.hh
+++ b/src/base/stl_helpers.hh
@@ -35,14 +35,6 @@
 namespace m5 {
 namespace stl_helpers {

-template 
-void
-deletePointer(T )
-{
-delete ptr;
-ptr = NULL;
-}
-
 template 
 class ContainerPrint
 {
@@ -68,15 +60,6 @@
 }
 };

-// Treat all objects in an stl container as pointers to heap objects,
-// calling delete on each one and zeroing the pointers along the way
-template  class C, typename T, typename  
A>

-void
-deletePointers(C )
-{
-std::for_each(container.begin(), container.end(), deletePointer);
-}
-
 // Write out all elements in an stl container as a space separated
 // list enclosed in square brackets
 template  class C, typename T, typename  
A>


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I91d8b97f7ba3f64dd9948fd343cf0af969886598
Gerrit-Change-Number: 24251
Gerrit-PatchSet: 7
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Add HTM ThreadContext API

2020-06-15 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Hello Timothy Hayes,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/30324

to review the following change.


Change subject: cpu: Add HTM ThreadContext API
..

cpu: Add HTM ThreadContext API

JIRA: https://gem5.atlassian.net/browse/GEM5-587

Change-Id: I9d60f69592c8072e70cef18787b5a4f2fc737a9d
Signed-off-by: Giacomo Travaglini 
---
M src/cpu/checker/thread_context.hh
M src/cpu/o3/thread_context.hh
M src/cpu/o3/thread_context_impl.hh
M src/cpu/simple_thread.cc
M src/cpu/simple_thread.hh
M src/cpu/thread_context.hh
6 files changed, 82 insertions(+), 8 deletions(-)



diff --git a/src/cpu/checker/thread_context.hh  
b/src/cpu/checker/thread_context.hh

index 52ea7d2..bb348cf 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2012, 2016-2018 ARM Limited
+ * Copyright (c) 2011-2012, 2016-2019 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -578,6 +578,17 @@
 {
 actualTC->setCCRegFlat(idx, val);
 }
+
+// hardware transactional memory
+void htmAbortTransaction(uint64_t htmUid, HtmFailureFaultCause cause)
+{
+panic("function not implemented");
+}
+
+TheISA::HTMCheckpoint *getHTMCheckpointPtr()
+{
+panic("function not implemented");
+}
 };

 #endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 3cb3e97..e9e3ff2 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2012, 2016-2018 ARM Limited
+ * Copyright (c) 2011-2012, 2016-2019 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -510,6 +510,10 @@

 RegVal readCCRegFlat(RegIndex idx) const override;
 void setCCRegFlat(RegIndex idx, RegVal val) override;
+
+// hardware transactional memory
+virtual void htmAbortTransaction(uint64_t, HtmFailureFaultCause);
+virtual TheISA::HTMCheckpoint *getHTMCheckpointPtr();
 };

 #endif
diff --git a/src/cpu/o3/thread_context_impl.hh  
b/src/cpu/o3/thread_context_impl.hh

index d02be71..e458983 100644
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012, 2016-2017 ARM Limited
+ * Copyright (c) 2010-2012, 2016-2017, 2019 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -359,4 +359,24 @@
 conditionalSquash();
 }

+// hardware transactional memory
+template 
+void
+O3ThreadContext::htmAbortTransaction(uint64_t htmUid,
+   HtmFailureFaultCause cause)
+{
+cpu->htmSendAbortSignal(thread->threadId(), htmUid, cause);
+
+conditionalSquash();
+}
+
+template 
+TheISA::HTMCheckpoint*
+O3ThreadContext::getHTMCheckpointPtr()
+{
+conditionalSquash();
+
+return >htmCheckpoint;
+}
+
 #endif //__CPU_O3_THREAD_CONTEXT_IMPL_HH__
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index d0c6bf4..f685883 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018 ARM Limited
+ * Copyright (c) 2018-2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -54,6 +54,7 @@
 #include "cpu/base.hh"
 #include "cpu/profile.hh"
 #include "cpu/quiesce_event.hh"
+#include "cpu/simple/base.hh"
 #include "cpu/thread_context.hh"
 #include "mem/se_translating_port_proxy.hh"
 #include "mem/translating_port_proxy.hh"
@@ -75,7 +76,8 @@
   isa(dynamic_cast(_isa)),
   predicate(true), memAccPredicate(true),
   comInstEventQueue("instruction-based event queue"),
-  system(_sys), itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(isa))
+  system(_sys), itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(isa)),
+  htmTransactionStarts(0), htmTransactionStops(0)
 {
 assert(isa);
 clearArchRegs();
@@ -89,7 +91,8 @@
   isa(dynamic_cast(_isa)),
   predicate(true), memAccPredicate(true),
   comInstEventQueue("instruction-based event queue"),
-  system(_sys), itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(isa))
+  system(_sys), itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(isa)),
+  htmTransactionStarts(0), htmTransactionStops(0)
 {
 assert(isa);

@@ -211,3 +214,23 @@
 {
 TheISA::copyRegs(src_tc, this);
 }
+
+// hardware transactional memory
+void
+SimpleThread::htmAbortTransaction(uint64_t htmUid, HtmFailureFaultCause  
cause)

+{
+BaseSimpleCPU *baseSimpleCpu = dynamic_cast(baseCpu);
+assert(baseSimpleCpu);
+
+baseSimpleCpu->htmSendAbortSignal(cause);
+
+// these must be reset after the abort signal has been sent
+htmTransactionStarts = 0;
+htmTransactionStops = 0;
+}
+
+TheISA::HTMCheckpoint*

[gem5-dev] Change in gem5/gem5[develop]: mem: Add HTM fields to Request

2020-06-15 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Hello Timothy Hayes,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/30316

to review the following change.


Change subject: mem: Add HTM fields to Request
..

mem: Add HTM fields to Request

This starts the support of Hardware Transactional Memory on the mem side

* The following flags have been added:

HTM_START: The request starts a HTM transaction
HTM_COMMIT: The request commits a HTM transaction
HTM_CANCEL: The request cancels a HTM transaction
HTM_ABORT: The request aborts a HTM transaction

* The following fields have been added:

_instCount: The instruction count at the time this request is created
_htmAbortCause: The cause for HTM transaction abort

https://gem5.atlassian.net/browse/GEM5-587

Change-Id: Ic582a6566fdd23f30eb92723e629d0c4d4ca10e5
Signed-off-by: Giacomo Travaglini 
---
M src/mem/request.hh
1 file changed, 96 insertions(+), 1 deletion(-)



diff --git a/src/mem/request.hh b/src/mem/request.hh
index 4e0ba97..a6fb10f 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2013,2017-2019 ARM Limited
+ * Copyright (c) 2012-2013,2017-2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -51,6 +51,7 @@
 #include 
 #include 

+#include "arch/generic/htm.hh"
 #include "base/amo.hh"
 #include "base/flags.hh"
 #include "base/logging.hh"
@@ -187,6 +188,42 @@
 /** Bits to define the destination of a request */
 DST_BITS= 0x0030,

+/** hardware transactional memory **/
+
+/** The request starts a HTM transaction */
+HTM_START   = 0x0100,
+
+/** The request commits a HTM transaction */
+HTM_COMMIT  = 0x0200,
+
+/** The request cancels a HTM transaction */
+HTM_CANCEL  = 0x0400,
+
+/** The request aborts a HTM transaction */
+HTM_ABORT   = 0x0800,
+
+// What is the different between HTM cancel and abort?
+//
+// HTM_CANCEL will originate from a user instruction, e.g.
+// Arm's TCANCEL or x86's XABORT. This is an explicit request
+// to end a transaction and restore from the last checkpoint.
+//
+// HTM_ABORT is an internally generated request used to synchronize
+// a transaction's failure between the core and memory subsystem.
+// If a transaction fails in the core, e.g. because an instruction
+// within the transaction generates an exception, the core will  
prepare

+// itself to stop fetching/executing more instructions and send an
+// HTM_ABORT to the memory subsystem before restoring the  
checkpoint.
+// Similarly, the transaction could fail in the memory subsystem  
and

+// this will be communicated to the core via the Packet object.
+// Once the core notices, it will do the same as the above and send
+// a HTM_ABORT to the memory subsystem.
+// A HTM_CANCEL sent to the memory subsystem will ultimately return
+// to the core which in turn will send a HTM_ABORT.
+//
+// This separation is necessary to ensure the disjoint components
+// of the system work correctly together.
+
 /**
  * These flags are *not* cleared when a Request object is
  * reused (assigned a new address).
@@ -196,6 +233,9 @@
 static const FlagsType STORE_NO_DATA = CACHE_BLOCK_ZERO |
 CLEAN | INVALIDATE;

+static const FlagsType HTM_CMD = HTM_START | HTM_COMMIT |
+HTM_CANCEL | HTM_ABORT;
+
 /** Master Ids that are statically allocated
  * @{*/
 enum : MasterID {
@@ -267,6 +307,11 @@
 /** Whether or not the stream ID and substream ID is valid. */
 VALID_STREAM_ID  = 0x0100,
 VALID_SUBSTREAM_ID   = 0x0200,
+// hardware transactional memory
+/** Whether or not the abort cause is valid. */
+VALID_HTM_ABORT_CAUSE = 0x0400,
+/** Whether or not the instruction count is valid. */
+VALID_INST_COUNT  = 0x0800,
 /**
  * These flags are *not* cleared when a Request object is reused
  * (assigned a new address).
@@ -355,6 +400,12 @@

 LocalAccessor _localAccessor;

+/** The instruction count at the time this request is created */
+Counter _instCount = 0;
+
+/** The cause for HTM transaction abort */
+HtmFailureFaultCause _htmAbortCause = HtmFailureFaultCause_INVALID;
+
   public:

 /**
@@ -510,6 +561,21 @@
 }

 /**
+ * Accessor for instruction count.
+ */
+Counter getInstCount() const
+{
+assert(privateFlags.isSet(VALID_INST_COUNT));
+return _instCount;
+}
+
+void 

[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: HTM mem implementation

2020-06-15 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Hello Timothy Hayes,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/30319

to review the following change.


Change subject: mem-ruby: HTM mem implementation
..

mem-ruby: HTM mem implementation

This patch augments the MESI_Three_Level Ruby protocol with hardware
transactional memory support.

The HTM implementation relies on buffering of speculative memory updates.
The core notifies the L0 cache controller that a new transaction has
started and the controller in turn places itself in transactional state
(htmTransactionalState := true).

When operating in transactional state, the usual MESI protocol changes
slightly. Lines loaded or stored are marked as part of a transaction's
read and write set respectively. If there is an invalidation request to
cache line in the read/write set, the transaction is marked as failed.
Similarly, if there is a read request by another core to a speculatively
written cache line, i.e. in the write set, the transaction is marked as
failed. If failed, all subsequent loads and stores from the core are
made benign, i.e. made into NOPS at the cache controller, and responses
are marked to indicate that the transactional state has failed. When the
core receives these marked responses, it generates a HtmFailureFault
with the reason for the transaction failure. Servicing this fault does
two things--

(a) Restores the architectural checkpoint
(b) Sends an HTM abort signal to the cache controller

The restoration includes all registers in the checkpoint as well as the
program counter of the instruction before the transaction started.

The abort signal is sent to the L0 cache controller and resets the
failed transactional state. It resets the transactional read and write
sets and invalidates any speculatively written cache lines.  It also
exits the transactional state so that the MESI protocol operates as
usual.

Alternatively, if the instructions within a transaction complete without
triggering a HtmFailureFault, the transaction can be committed. The core
is responsible for notifying the cache controller that the transaction
is complete and the cache controller makes all speculative writes
visible to the rest of the system and exits the transactional state.

Notifting the cache controller is done through HtmCmd Requests which are
a subtype of Load Requests.

KUDOS:
The code is based on a previous pull request by Pradip Vallathol who
developed HTM and TSX support in Gem5 as part of his master’s thesis:

http://reviews.gem5.org/r/2308/index.html

JIRA: https://gem5.atlassian.net/browse/GEM5-587

Change-Id: Icc328df93363486e923b8bd54f4d77741d8f5650
Signed-off-by: Giacomo Travaglini 
---
M src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
M src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
M src/mem/ruby/protocol/MESI_Three_Level-msg.sm
M src/mem/ruby/protocol/RubySlicc_Exports.sm
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
M src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
M src/mem/ruby/slicc_interface/RubyRequest.hh
M src/mem/ruby/slicc_interface/RubySlicc_Util.hh
M src/mem/ruby/structures/CacheMemory.cc
M src/mem/ruby/structures/CacheMemory.hh
M src/mem/ruby/system/RubyPort.cc
M src/mem/ruby/system/RubyPort.hh
M src/mem/ruby/system/Sequencer.cc
M src/mem/ruby/system/Sequencer.hh
15 files changed, 1,193 insertions(+), 65 deletions(-)



diff --git a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm  
b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm

index 4de4a29..4b8f71d 100644
--- a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
@@ -61,6 +61,12 @@
// Request Buffer for prefetches
MessageBuffer * prefetchQueue;
 {
+  // hardware transactional memory
+  bool htmTransactionalState, default="false";
+  bool htmFailed, default="false";
+  int htmUid, default=0;
+  HtmFailedInCacheReason htmFailedRc,  
default=HtmFailedInCacheReason_NO_FAIL;

+
   // STATES
   state_declaration(State, desc="Cache states", default="L0Cache_State_I")  
{

 // Base states
@@ -141,6 +147,15 @@
 PF_Ifetch,   desc="Instruction fetch request from prefetcher";
 PF_Store,desc="Exclusive load request from prefetcher";
 PF_Bad_Addr, desc="Throw away prefetch request due to bad address  
generation";

+
+// hardware transactional memory
+HTM_abort,desc="Abort HTM transaction and rollback cache to  
pre-transactional state";

+HTM_start,desc="Place cache in HTM transactional state";
+HTM_commit,   desc="Commit speculative loads/stores and place  
cache in normal state";
+HTM_cancel,   desc="Fail HTM transaction explicitely without  
aborting";
+HTM_notifyCMD,desc="Notify core via HTM CMD that HTM transaction  
has failed";
+HTM_notifyLD, desc="Notify core via LD that HTM transaction 

[gem5-dev] Change in gem5/gem5[develop]: arch: Initial Gem5 Hardware Transactional Memory implementation

2020-06-15 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Hello Timothy Hayes,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/30314

to review the following change.


Change subject: arch: Initial Gem5 Hardware Transactional Memory  
implementation

..

arch: Initial Gem5 Hardware Transactional Memory implementation

Gem5 Hardware Transactional Memory (HTM)

Here we provide a brief note describing HTM support in Gem5 at
a high level.

HTM is an architectural feature that enables speculative concurrency in
a shared-memory system; groups of instructions known as transactions are
executed as an atomic unit. The system allows that transactions be
executed concurrently but intervenes if a transaction's
atomicity/isolation is jeapordised and takes corrective action. In this
implementation, corrective active explicitely means rolling back a
thread's architectural state and reverting any memory updates to a point
just before the transaction began.

This HTM implementation relies on--
(1) A checkpointing mechanism for architectural register state.
(2) Buffering speculative memory updates.

This patch is focusing on the definition of the HTM checkpoint (1)

The checkpointing mechanism is architecture dependent. Each ISA
leveraging HTM support can define a class HTMCheckpoint inhereting from
the generic one (GenericISA::HTMCheckpoint).

Those will need to save/restore the architectural state by overriding
the virtual HTMCheckpoint::save (when starting a transaction) and
HTMCheckpoint::restore (when aborting a transaction).

Instances of this class live in O3's ThreadState and Atomic's
SimpleThread.  It is up to the ISA to populate this instance when
executing an instruction that begins a new transaction.

JIRA: https://gem5.atlassian.net/browse/GEM5-587

Change-Id: Icd8d1913d23652d78fe89e930ab1e302eb52363d
Signed-off-by: Giacomo Travaglini 
---
M src/arch/SConscript
A src/arch/arm/htm.hh
M src/arch/generic/SConscript
A src/arch/generic/htm.cc
A src/arch/generic/htm.hh
A src/arch/mips/htm.hh
A src/arch/null/htm.hh
A src/arch/power/htm.hh
A src/arch/riscv/htm.hh
A src/arch/sparc/htm.hh
A src/arch/x86/htm.hh
11 files changed, 633 insertions(+), 2 deletions(-)



diff --git a/src/arch/SConscript b/src/arch/SConscript
index 13ab8fb..6ebdb93 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -1,6 +1,6 @@
 # -*- mode:python -*-

-# Copyright (c) 2016-2017 ARM Limited
+# Copyright (c) 2016-2017,2020 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -58,6 +58,7 @@
 env.SwitchingHeaders(
 Split('''
 decoder.hh
+htm.hh
 isa.hh
 isa_traits.hh
 kernel_stats.hh
diff --git a/src/arch/arm/htm.hh b/src/arch/arm/htm.hh
new file mode 100644
index 000..a1ab7b4
--- /dev/null
+++ b/src/arch/arm/htm.hh
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ 

[gem5-dev] Change in gem5/gem5[develop]: cpu: Add HTM ExecContext API

2020-06-15 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Hello Timothy Hayes,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/30323

to review the following change.


Change subject: cpu: Add HTM ExecContext API
..

cpu: Add HTM ExecContext API

* initiateHtmCmd(Request::Flags flags)
* getHtmTransactionUid()
* newHtmTransactionUid()
* inHtmTransactionalState()
* getHtmTransactionalDepth()

JIRA: https://gem5.atlassian.net/browse/GEM5-587

Change-Id: I438832a3c47fff1d12d0123425985cfa2150ab40
Signed-off-by: Giacomo Travaglini 
---
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/exec_context.hh
M src/cpu/minor/exec_context.hh
M src/cpu/simple/exec_context.hh
5 files changed, 143 insertions(+), 0 deletions(-)



diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index b98cbaa..e1580a5 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -300,6 +300,8 @@
 Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags,
 const std::vector& byte_enable = std::vector());

+Fault initiateHtmCmd(Request::Flags flags);
+
 Fault writeMem(uint8_t *data, unsigned size, Addr addr,
Request::Flags flags, uint64_t *res,
const std::vector& byte_enable =  
std::vector());

@@ -539,6 +541,30 @@
 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
 bool isMicroBranch() const { return staticInst->isMicroBranch(); }

+uint64_t getHtmTransactionUid() const override
+{
+panic("Not yet implemented\n");
+return 0;
+}
+
+uint64_t newHtmTransactionUid() const override
+{
+panic("Not yet implemented\n");
+return 0;
+}
+
+bool inHtmTransactionalState() const override
+{
+panic("Not yet implemented\n");
+return false;
+}
+
+uint64_t getHtmTransactionalDepth() const override
+{
+panic("Not yet implemented\n");
+return 0;
+}
+
 /** Temporarily sets this instruction as a serialize before  
instruction. */

 void setSerializeBefore() { status.set(SerializeBefore); }

@@ -964,6 +990,14 @@

 template
 Fault
+BaseDynInst::initiateHtmCmd(Request::Flags flags)
+{
+panic("Not yet implemented\n");
+return NoFault;
+}
+
+template
+Fault
 BaseDynInst::writeMem(uint8_t *data, unsigned size, Addr addr,
 Request::Flags flags, uint64_t *res,
 const std::vector& byte_enable)
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 24fad1c..0e3ea2c 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -434,12 +434,36 @@
 thread->setMemAccPredicate(val);
 }

+uint64_t getHtmTransactionUid() const override
+{
+panic("not yet supported!");
+return 0;
+};
+
+uint64_t newHtmTransactionUid() const override
+{
+panic("not yet supported!");
+return 0;
+};
+
 Fault initiateHtmCmd(Request::Flags flags) override
 {
 panic("not yet supported!");
 return NoFault;
 }

+bool inHtmTransactionalState() const override
+{
+panic("not yet supported!");
+return false;
+}
+
+uint64_t getHtmTransactionalDepth() const override
+{
+panic("not yet supported!");
+return 0;
+}
+
 TheISA::PCState pcState() const override { return thread->pcState(); }
 void
 pcState(const TheISA::PCState ) override
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index 29daced..2492c4b 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -253,6 +253,11 @@
 }

 /**
+ * Initiate an HTM command,
+ * e.g. tell Ruby we're starting/stopping a transaction
+ */
+virtual Fault initiateHtmCmd(Request::Flags flags) = 0;
+/**
  * For atomic-mode contexts, perform an atomic memory write operation.
  * For timing-mode contexts, initiate a timing memory write operation.
  */
@@ -320,6 +325,12 @@
 virtual bool readMemAccPredicate() const = 0;
 virtual void setMemAccPredicate(bool val) = 0;

+// hardware transactional memory
+virtual uint64_t newHtmTransactionUid() const = 0;
+virtual uint64_t getHtmTransactionUid() const = 0;
+virtual bool inHtmTransactionalState() const = 0;
+virtual uint64_t getHtmTransactionalDepth() const = 0;
+
 /** @} */

 /**
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index a0b1d18..4ff046a 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -114,6 +114,13 @@
 }

 Fault
+initiateHtmCmd(Request::Flags flags) override
+{
+panic("ExecContext::initiateHtmCmd() not implemented on  
MinorCPU\n");

+return NoFault;
+}
+
+Fault
 writeMem(uint8_t *data, unsigned int size, Addr addr,
  Request::Flags flags, 

[gem5-dev] Change in gem5/gem5[develop]: cpu: HTM Implementation for TimingCPU

2020-06-15 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Hello Timothy Hayes,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/30327

to review the following change.


Change subject: cpu: HTM Implementation for TimingCPU
..

cpu: HTM Implementation for TimingCPU

JIRA: https://gem5.atlassian.net/browse/GEM5-587

Change-Id: I3e1de639560ea5492e914470e31bacb321425f0a
Signed-off-by: Giacomo Travaglini 
---
M src/cpu/simple/base.cc
M src/cpu/simple/exec_context.hh
M src/cpu/simple/timing.cc
3 files changed, 251 insertions(+), 16 deletions(-)



diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index c6d5761..fb0aa42 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012, 2015, 2017, 2018 ARM Limited
+ * Copyright (c) 2010-2012, 2015, 2017, 2018-2019 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -65,6 +65,7 @@
 #include "cpu/thread_context.hh"
 #include "debug/Decode.hh"
 #include "debug/Fetch.hh"
+#include "debug/HtmCpu.hh"
 #include "debug/Quiesce.hh"
 #include "mem/packet.hh"
 #include "mem/request.hh"
@@ -443,6 +444,17 @@
 Fault interrupt = interrupts[curThread]->getInterrupt();

 if (interrupt != NoFault) {
+// hardware transactional memory
+// Postpone taking interrupts while executing transactions.
+assert(!std::dynamic_pointer_cast(
+interrupt));
+if (t_info.inHtmTransactionalState()) {
+DPRINTF(HtmCpu, "Deferring pending interrupt - %s -"
+"due to transactional state\n",
+interrupt->name());
+return;
+}
+
 t_info.fetchOffset = 0;
 interrupts[curThread]->updateIntrInfo();
 interrupt->invoke(tc);
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index ade9b68..42b5d0e 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -475,8 +475,7 @@

 Fault initiateHtmCmd(Request::Flags flags) override
 {
-panic("Not yet supported\n");
-return NoFault;
+return cpu->initiateHtmCmd(flags);
 }

 /**
@@ -540,29 +539,26 @@
 uint64_t
 getHtmTransactionUid() const override
 {
-panic("Not yet supported\n");
-return 0;
+return tcBase()->getHTMCheckpointPtr()->getHtmUid();
 }

 uint64_t
 newHtmTransactionUid() const override
 {
-panic("Not yet supported\n");
-return 0;
+return tcBase()->getHTMCheckpointPtr()->newHtmUid();
 }

 bool
 inHtmTransactionalState() const override
 {
-panic("Not yet supported\n");
-return false;
+return (getHtmTransactionalDepth() > 0);
 }

 uint64_t
 getHtmTransactionalDepth() const override
 {
-panic("Not yet supported\n");
-return 0;
+assert(thread->htmTransactionStarts >=  
thread->htmTransactionStops);
+return (thread->htmTransactionStarts -  
thread->htmTransactionStops);

 }

 /**
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index a509562..3240792 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -48,6 +48,7 @@
 #include "debug/Config.hh"
 #include "debug/Drain.hh"
 #include "debug/ExecFaulting.hh"
+#include "debug/HtmCpu.hh"
 #include "debug/Mwait.hh"
 #include "debug/SimpleCPU.hh"
 #include "mem/packet.hh"
@@ -173,6 +174,10 @@
 SimpleExecContext& t_info = *threadInfo[curThread];
 M5_VAR_USED SimpleThread* thread = t_info.thread;

+// hardware transactional memory
+// Cannot switch out the CPU in the middle of a transaction
+assert(!t_info.inHtmTransactionalState());
+
 BaseSimpleCPU::switchOut();

 assert(!fetchEvent.scheduled());
@@ -234,6 +239,10 @@
 assert(thread_num < numThreads);
 activeThreads.remove(thread_num);

+// hardware transactional memory
+// Cannot suspend context in the middle of a transaction.
+assert(!threadInfo[curThread]->inHtmTransactionalState());
+
 if (_status == Idle)
 return;

@@ -260,6 +269,12 @@

 const RequestPtr  = pkt->req;

+// hardware transactional memory
+// sanity check
+if (req->isHTMCmd()) {
+assert(!req->isLocalAccess());
+}
+
 // We're about the issues a locked load, so tell the monitor
 // to start caring about this address
 if (pkt->isRead() && pkt->req->isLLSC()) {
@@ -291,6 +306,17 @@
 PacketPtr pkt = buildPacket(req, read);
 pkt->dataDynamic(data);

+// hardware transactional memory
+// If the core is in transactional mode or if the request is HtmCMD
+// to abort a transaction, the packet should reflect that it is
+// transactional and also contain a HtmUid for debugging.
+const bool is_htm_speculative = 

[gem5-dev] Change in gem5/gem5[develop]: cpu: Add HtmCpu DebugFlag

2020-06-15 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Hello Timothy Hayes,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/30320

to review the following change.


Change subject: cpu: Add HtmCpu DebugFlag
..

cpu: Add HtmCpu DebugFlag

JIRA: https://gem5.atlassian.net/browse/GEM5-587

Change-Id: Id4b86b8964bc64bce1d2e4af941217eb114f3cc4
---
M src/cpu/SConscript
1 file changed, 12 insertions(+), 0 deletions(-)



diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index f1dc6bd..48e305b 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -1,5 +1,16 @@
 # -*- mode:python -*-

+# Copyright (c) 2019 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
 # Copyright (c) 2006 The Regents of The University of Michigan
 # All rights reserved.
 #
@@ -51,6 +62,7 @@
 DebugFlag('ExecAsid', 'Format: Include ASID in trace')
 DebugFlag('ExecFlags', 'Format: Include instruction flags in trace')
 DebugFlag('Fetch')
+DebugFlag('HtmCpu', 'Hardware Transactional Memory (CPU side)')
 DebugFlag('IntrControl')
 DebugFlag('O3PipeView')
 DebugFlag('PCEvent')

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/30320
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id4b86b8964bc64bce1d2e4af941217eb114f3cc4
Gerrit-Change-Number: 30320
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Timothy Hayes 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem: Add a header latency parameter to the XBar

2020-06-15 Thread Nikos Nikoleris (Gerrit) via gem5-dev
Nikos Nikoleris has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30054 )


Change subject: mem: Add a header latency parameter to the XBar
..

mem: Add a header latency parameter to the XBar

The XBar uses the concept of Layers to model throughput and
instantiates one Layer per master. As it forwards a packet to and from
master, the corresponding Layer is marked as occupied for a number of
cycles. Requests/responses to/from a master are blocked while the
corresponding Layer is occupied. Previously the delay would be
calculated based on the formula 1 + size / width, which assumes that
the Layer is always occupied for 1 cycle while processing the packet
header. This changes makes the header latency a parameter which
defaults to 1.

Change-Id: I12752ab4415617a94fbd8379bcd2ae8982f91fd8
Signed-off-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30054
Reviewed-by: Daniel Carvalho 
Tested-by: kokoro 
---
M src/mem/XBar.py
M src/mem/coherent_xbar.cc
M src/mem/xbar.cc
M src/mem/xbar.hh
4 files changed, 15 insertions(+), 7 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Nikos Nikoleris: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/XBar.py b/src/mem/XBar.py
index deed98f..84aae99 100644
--- a/src/mem/XBar.py
+++ b/src/mem/XBar.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012, 2015, 2017, 2019 ARM Limited
+# Copyright (c) 2012, 2015, 2017, 2019-2020 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -68,6 +68,11 @@
 forward_latency = Param.Cycles("Forward latency")
 response_latency = Param.Cycles("Response latency")

+# The XBar uses one Layer per master. Each Layer forwards a packet
+# to its destination and is occupied for header_latency + size /
+# width cycles
+header_latency = Param.Cycles(1, "Header latency")
+
 # Width governing the throughput of the crossbar
 width = Param.Unsigned("Datapath width per port (bytes)")

diff --git a/src/mem/coherent_xbar.cc b/src/mem/coherent_xbar.cc
index 952bd41..7fb9c34 100644
--- a/src/mem/coherent_xbar.cc
+++ b/src/mem/coherent_xbar.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2019 ARM Limited
+ * Copyright (c) 2011-2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -180,7 +180,7 @@
 calcPacketTiming(pkt, xbar_delay);

 // determine how long to be crossbar layer is busy
-Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
+Tick packetFinishTime = clockEdge(headerLatency) + pkt->payloadDelay;

 // is this the destination point for this packet? (e.g. true if
 // this xbar is the PoC for a cache maintenance operation to the
@@ -471,7 +471,7 @@
 calcPacketTiming(pkt, xbar_delay);

 // determine how long to be crossbar layer is busy
-Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
+Tick packetFinishTime = clockEdge(headerLatency) + pkt->payloadDelay;

 if (snoopFilter && !system->bypassCaches()) {
 // let the snoop filter inspect the response and update its state
@@ -619,7 +619,7 @@
 calcPacketTiming(pkt, xbar_delay);

 // determine how long to be crossbar layer is busy
-Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
+Tick packetFinishTime = clockEdge(headerLatency) + pkt->payloadDelay;

 // forward it either as a snoop response or a normal response
 if (forwardAsSnoop) {
diff --git a/src/mem/xbar.cc b/src/mem/xbar.cc
index 9920216..f0b4ba3 100644
--- a/src/mem/xbar.cc
+++ b/src/mem/xbar.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2015, 2018-2019 ARM Limited
+ * Copyright (c) 2011-2015, 2018-2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -56,6 +56,7 @@
   frontendLatency(p->frontend_latency),
   forwardLatency(p->forward_latency),
   responseLatency(p->response_latency),
+  headerLatency(p->header_latency),
   width(p->width),
   gotAddrRanges(p->port_default_connection_count +
   p->port_master_connection_count, false),
diff --git a/src/mem/xbar.hh b/src/mem/xbar.hh
index 4488f74..086d7f4 100644
--- a/src/mem/xbar.hh
+++ b/src/mem/xbar.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2015, 2018-2019 ARM Limited
+ * Copyright (c) 2011-2015, 2018-2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -307,6 +307,8 @@
 const Cycles frontendLatency;
 const Cycles forwardLatency;
 const Cycles responseLatency;
+/** Cycles the layer is occupied processing the packet header */
+const Cycles headerLatency;
 /** the width of the xbar in bytes */
 const uint32_t width;


--
To view, visit