[gem5-dev] Change in gem5/gem5[develop]: arch, gpu-compute: Remove HSAIL related files

2020-06-16 Thread Anthony Gutierrez (Gerrit) via gem5-dev
Anthony Gutierrez has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28410 )


Change subject: arch, gpu-compute: Remove HSAIL related files
..

arch, gpu-compute: Remove HSAIL related files

Change-Id: Iefba0a38d62da7598bbfe3fe6ff46454d35144b1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28410
Reviewed-by: Anthony Gutierrez 
Maintainer: Anthony Gutierrez 
Tested-by: kokoro 
---
M MAINTAINERS
M SConstruct
D build_opts/HSAIL_X86
M src/arch/gcn3/SConscript
D src/arch/hsail/Brig.h
D src/arch/hsail/Brig_new.hpp
D src/arch/hsail/SConscript
D src/arch/hsail/SConsopts
D src/arch/hsail/gen.py
D src/arch/hsail/gpu_decoder.hh
D src/arch/hsail/gpu_isa.hh
D src/arch/hsail/gpu_types.hh
D src/arch/hsail/insts/branch.cc
D src/arch/hsail/insts/branch.hh
D src/arch/hsail/insts/decl.hh
D src/arch/hsail/insts/gpu_static_inst.cc
D src/arch/hsail/insts/gpu_static_inst.hh
D src/arch/hsail/insts/main.cc
D src/arch/hsail/insts/mem.cc
D src/arch/hsail/insts/mem.hh
D src/arch/hsail/insts/mem_impl.hh
D src/arch/hsail/insts/pseudo_inst.cc
D src/arch/hsail/operand.cc
D src/arch/hsail/operand.hh
D src/gpu-compute/brig_object.cc
D src/gpu-compute/brig_object.hh
D src/gpu-compute/cl_driver.cc
D src/gpu-compute/cl_driver.hh
D src/gpu-compute/cl_event.hh
D src/gpu-compute/condition_register_state.cc
D src/gpu-compute/condition_register_state.hh
D src/gpu-compute/hsa_code.hh
D src/gpu-compute/hsa_kernel_info.hh
D src/gpu-compute/hsa_object.cc
D src/gpu-compute/hsa_object.hh
D src/gpu-compute/hsail_code.cc
D src/gpu-compute/hsail_code.hh
D src/gpu-compute/kernel_cfg.cc
D src/gpu-compute/kernel_cfg.hh
D src/gpu-compute/ndrange.hh
D src/gpu-compute/qstruct.hh
D src/gpu-compute/vector_register_state.cc
D src/gpu-compute/vector_register_state.hh
M util/git-commit-msg.py
M util/regress
45 files changed, 6 insertions(+), 12,854 deletions(-)

Approvals:
  Anthony Gutierrez: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iefba0a38d62da7598bbfe3fe6ff46454d35144b1
Gerrit-Change-Number: 28410
Gerrit-PatchSet: 10
Gerrit-Owner: Anthony Gutierrez 
Gerrit-Reviewer: Alexandru Duțu 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Bradford Beckmann 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: Tony Gutierrez 
Gerrit-Reviewer: Tuan Ta 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem: Fix latency handling in MemDelay

2020-06-16 Thread Nikos Nikoleris (Gerrit) via gem5-dev
Nikos Nikoleris has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30055 )


Change subject: mem: Fix latency handling in MemDelay
..

mem: Fix latency handling in MemDelay

MemDelay wouldn't consume pre-existing delays in the packet and
therefore the latency it adds would overlap with them. This patch
fixes the MemDelay to properly account for them.

Change-Id: I7330fbf1c8161a21523a0b4aab31c72e34bce650
Signed-off-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30055
Reviewed-by: Daniel Carvalho 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/mem/mem_delay.cc
1 file changed, 14 insertions(+), 3 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Daniel Carvalho: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/mem_delay.cc b/src/mem/mem_delay.cc
index 83177fd..9adc072 100644
--- a/src/mem/mem_delay.cc
+++ b/src/mem/mem_delay.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018 ARM Limited
+ * Copyright (c) 2018, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -87,7 +87,12 @@
 bool
 MemDelay::MasterPort::recvTimingResp(PacketPtr pkt)
 {
-const Tick when = curTick() + parent.delayResp(pkt);
+// technically the packet only reaches us after the header delay,
+// and typically we also need to deserialise any payload
+const Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
+pkt->headerDelay = pkt->payloadDelay = 0;
+
+const Tick when = curTick() + parent.delayResp(pkt) + receive_delay;

 parent.slavePort.schedTimingResp(pkt, when);

@@ -136,7 +141,13 @@
 bool
 MemDelay::SlavePort::recvTimingReq(PacketPtr pkt)
 {
-const Tick when = curTick() + parent.delayReq(pkt);
+// technically the packet only reaches us after the header
+// delay, and typically we also need to deserialise any
+// payload
+Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
+pkt->headerDelay = pkt->payloadDelay = 0;
+
+const Tick when = curTick() + parent.delayReq(pkt) + receive_delay;

 parent.masterPort.schedTimingReq(pkt, when);


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7330fbf1c8161a21523a0b4aab31c72e34bce650
Gerrit-Change-Number: 30055
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris 
Gerrit-Assignee: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: python,util: Fixed string decoding in include verifier

2020-06-16 Thread Bobby R. Bruce (Gerrit) via gem5-dev
Bobby R. Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30336 )



Change subject: python,util: Fixed string decoding in include verifier
..

python,util: Fixed string decoding in include verifier

The Python2 <-> Python3 port included a decode on a string as part of
the include statement git-hook verifier. This results in a failure. To
fix this issue, the file to be checked is opened in binary mode.

This issue was highlighted by Gabe Black here:
https://gem5-review.googlesource.com/c/public/gem5/+/28588

Change-Id: I9a30ecc24d4741853ed1c2d0c03addf57c3e5b6c
---
M util/style/verifiers.py
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/util/style/verifiers.py b/util/style/verifiers.py
index 00cf070..85f31ce 100644
--- a/util/style/verifiers.py
+++ b/util/style/verifiers.py
@@ -347,7 +347,7 @@
 def check(self, filename, regions=all_regions, fobj=None,  
silent=False):

 close = False
 if fobj is None:
-fobj = self.open(filename, 'r')
+fobj = self.open(filename, 'rb')
 close = True
 norm_fname = self.normalize_filename(filename)


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9a30ecc24d4741853ed1c2d0c03addf57c3e5b6c
Gerrit-Change-Number: 30336
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem: Use the new unbound port reporting mechanism in the mem ports.

2020-06-16 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30296 )


Change subject: mem: Use the new unbound port reporting mechanism in the  
mem ports.

..

mem: Use the new unbound port reporting mechanism in the mem ports.

There was an add-hoc check added to getAddrRanges, but the other methods
would just segfault if they tried to talk to their peers. This change
wraps all the calls in try blocks and catches the exception which the
peer will throw if it's the default and the port is not actually
connected to anything.

Change-Id: Ie46be0230f33f74305c599b251ca319a65ba008d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30296
Reviewed-by: Nikos Nikoleris 
Maintainer: Nikos Nikoleris 
Tested-by: kokoro 
---
M src/mem/port.cc
M src/mem/port.hh
2 files changed, 137 insertions(+), 32 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/port.cc b/src/mem/port.cc
index 883b592..47e94f4 100644
--- a/src/mem/port.cc
+++ b/src/mem/port.cc
@@ -47,11 +47,72 @@
 #include "base/trace.hh"
 #include "sim/sim_object.hh"

+namespace
+{
+
+class DefaultMasterPort : public MasterPort
+{
+  protected:
+[[noreturn]] void
+blowUp() const
+{
+throw UnboundPortException();
+}
+
+  public:
+DefaultMasterPort() : MasterPort("default_master_port", nullptr) {}
+
+// Atomic protocol.
+Tick recvAtomicSnoop(PacketPtr) override { blowUp(); }
+
+// Timing protocol.
+bool recvTimingResp(PacketPtr) override { blowUp(); }
+void recvTimingSnoopReq(PacketPtr) override { blowUp(); }
+void recvReqRetry() override { blowUp(); }
+void recvRetrySnoopResp() override { blowUp(); }
+
+// Functional protocol.
+void recvFunctionalSnoop(PacketPtr) override { blowUp(); }
+};
+
+class DefaultSlavePort : public SlavePort
+{
+  protected:
+[[noreturn]] void
+blowUp() const
+{
+throw UnboundPortException();
+}
+
+  public:
+DefaultSlavePort() : SlavePort("default_slave_port", nullptr) {}
+
+// Atomic protocol.
+Tick recvAtomic(PacketPtr) override { blowUp(); }
+
+// Timing protocol.
+bool recvTimingReq(PacketPtr) override { blowUp(); }
+bool tryTiming(PacketPtr) override { blowUp(); }
+bool recvTimingSnoopResp(PacketPtr) override { blowUp(); }
+void recvRespRetry() override { blowUp(); }
+
+// Functional protocol.
+void recvFunctional(PacketPtr) override { blowUp(); }
+
+// General.
+AddrRangeList getAddrRanges() const override { return AddrRangeList();  
}

+};
+
+DefaultMasterPort defaultMasterPort;
+DefaultSlavePort defaultSlavePort;
+
+} // anonymous namespace
+
 /**
  * Master port
  */
 MasterPort::MasterPort(const std::string& name, SimObject* _owner, PortID  
_id)

-: Port(name, _id), _slavePort(NULL), owner(*_owner)
+: Port(name, _id), _slavePort(), owner(*_owner)
 {
 }

@@ -63,10 +124,8 @@
 MasterPort::bind(Port )
 {
 auto *slave_port = dynamic_cast();
-if (!slave_port) {
-fatal("Attempt to bind port %s to non-slave port %s.",
-name(), peer.name());
-}
+fatal_if(!slave_port, "Can't bind port %s to non-slave port %s.",
+ name(), peer.name());
 // master port keeps track of the slave port
 _slavePort = slave_port;
 Port::bind(peer);
@@ -77,11 +136,10 @@
 void
 MasterPort::unbind()
 {
-if (_slavePort == NULL)
-panic("Attempting to unbind master port %s that is not  
connected\n",

-  name());
+panic_if(!isConnected(), "Can't unbind master port %s which is not  
bound.",

+ name());
 _slavePort->slaveUnbind();
-_slavePort = nullptr;
+_slavePort = 
 Port::unbind();
 }

@@ -108,8 +166,8 @@
  * Slave port
  */
 SlavePort::SlavePort(const std::string& name, SimObject* _owner, PortID id)
-: Port(name, id), _masterPort(NULL), defaultBackdoorWarned(false),
-owner(*_owner)
+: Port(name, id), _masterPort(),
+defaultBackdoorWarned(false), owner(*_owner)
 {
 }

@@ -120,7 +178,7 @@
 void
 SlavePort::slaveUnbind()
 {
-_masterPort = NULL;
+_masterPort = 
 Port::unbind();
 }

diff --git a/src/mem/port.hh b/src/mem/port.hh
index d84e46f..eadf7f4 100644
--- a/src/mem/port.hh
+++ b/src/mem/port.hh
@@ -258,6 +258,7 @@

   private:
 MasterPort* _masterPort;
+
 bool defaultBackdoorWarned;

   protected:
@@ -278,13 +279,7 @@
 /**
  * Called by the owner to send a range change
  */
-void
-sendRangeChange() const
-{
-fatal_if(!_masterPort,
-"%s cannot sendRangeChange() without master port.",  
name());

-_masterPort->recvRangeChange();
-}
+void sendRangeChange() const { _masterPort->recvRangeChange(); }

 /**
  * Get a list of the non-overlapping address ranges the owner is
@@ -316,7 +311,11 

[gem5-dev] Change in gem5/gem5[develop]: cpu: Remove default argument values for the update() method in bpreds.

2020-06-16 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30375 )



Change subject: cpu: Remove default argument values for the update() method  
in bpreds.

..

cpu: Remove default argument values for the update() method in bpreds.

These defaults are never used. There was an assert in the predictors
until recently which was asserting that one of the arguments didn't
have the default value, I think to verify that the default wasn't used
by accident(?), but it could be used purposefully. That would cause
gem5 to crash and has been removed.

Beyond that, there's no reason to have default values for those
arguments in the first place, so this change removes them. That makes
the code slightly simpler, and avoids them being used by accident.

Additionally, the defalt values of the arguments made the function
signatures inconsistent, even though they were supposed to override
each other.

JIRA: https://gem5.atlassian.net/browse/GEM5-483

Change-Id: I28f8d2048985c12ec9cac018a868a32bfa20dc6c
---
M src/cpu/pred/bpred_unit.hh
M src/cpu/pred/ltage.hh
M src/cpu/pred/multiperspective_perceptron.hh
M src/cpu/pred/multiperspective_perceptron_tage.hh
M src/cpu/pred/tage.hh
M src/cpu/pred/tage_sc_l.hh
6 files changed, 6 insertions(+), 7 deletions(-)



diff --git a/src/cpu/pred/bpred_unit.hh b/src/cpu/pred/bpred_unit.hh
index c4dbad2..3ca6fa8 100644
--- a/src/cpu/pred/bpred_unit.hh
+++ b/src/cpu/pred/bpred_unit.hh
@@ -177,8 +177,7 @@
  */
 virtual void update(ThreadID tid, Addr instPC, bool taken,
void *bp_history, bool squashed,
-   const StaticInstPtr & inst =  
StaticInst::nullStaticInstPtr,

-   Addr corrTarget = MaxAddr) = 0;
+   const StaticInstPtr , Addr corrTarget) = 0;
 /**
  * Updates the BTB with the target of a branch.
  * @param inst_PC The branch's PC that will be updated.
diff --git a/src/cpu/pred/ltage.hh b/src/cpu/pred/ltage.hh
index 53081da..0bbac81 100644
--- a/src/cpu/pred/ltage.hh
+++ b/src/cpu/pred/ltage.hh
@@ -66,7 +66,7 @@
 void squash(ThreadID tid, void *bp_history) override;
 void update(ThreadID tid, Addr branch_addr, bool taken, void  
*bp_history,

 bool squashed, const StaticInstPtr & inst,
-Addr corrTarget = MaxAddr) override;
+Addr corrTarget) override;

 void init() override;
 virtual void regStats() override;
diff --git a/src/cpu/pred/multiperspective_perceptron.hh  
b/src/cpu/pred/multiperspective_perceptron.hh

index e680cce..fc37c58 100644
--- a/src/cpu/pred/multiperspective_perceptron.hh
+++ b/src/cpu/pred/multiperspective_perceptron.hh
@@ -1021,7 +1021,7 @@
 void update(ThreadID tid, Addr instPC, bool taken,
 void *bp_history, bool squashed,
 const StaticInstPtr & inst,
-Addr corrTarget = MaxAddr) override;
+Addr corrTarget) override;
 void btbUpdate(ThreadID tid, Addr branch_addr, void* _history)  
override;

 };
 #endif//__CPU_PRED_MULTIPERSPECTIVE_PERCEPTRON_HH__
diff --git a/src/cpu/pred/multiperspective_perceptron_tage.hh  
b/src/cpu/pred/multiperspective_perceptron_tage.hh

index bb92df6..d63be1e 100644
--- a/src/cpu/pred/multiperspective_perceptron_tage.hh
+++ b/src/cpu/pred/multiperspective_perceptron_tage.hh
@@ -224,7 +224,7 @@
 void update(ThreadID tid, Addr instPC, bool taken,
 void *bp_history, bool squashed,
 const StaticInstPtr & inst,
-Addr corrTarget = MaxAddr) override;
+Addr corrTarget) override;
 void uncondBranch(ThreadID tid, Addr pc, void * _history) override;
 void squash(ThreadID tid, void *bp_history) override;

diff --git a/src/cpu/pred/tage.hh b/src/cpu/pred/tage.hh
index a585717..b32ce67 100644
--- a/src/cpu/pred/tage.hh
+++ b/src/cpu/pred/tage.hh
@@ -85,7 +85,7 @@
 void btbUpdate(ThreadID tid, Addr branch_addr, void* _history)  
override;
 void update(ThreadID tid, Addr branch_addr, bool taken, void  
*bp_history,

 bool squashed, const StaticInstPtr & inst,
-Addr corrTarget = MaxAddr) override;
+Addr corrTarget) override;
 virtual void squash(ThreadID tid, void *bp_history) override;
 };

diff --git a/src/cpu/pred/tage_sc_l.hh b/src/cpu/pred/tage_sc_l.hh
index 8f7087b..a00f8ea 100644
--- a/src/cpu/pred/tage_sc_l.hh
+++ b/src/cpu/pred/tage_sc_l.hh
@@ -155,7 +155,7 @@

 void update(ThreadID tid, Addr branch_addr, bool taken, void  
*bp_history,

 bool squashed, const StaticInstPtr & inst,
-Addr corrTarget = MaxAddr) override;
+Addr corrTarget) override;

   protected:


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[gem5-dev] Change in gem5/gem5[develop]: cpu: Delete author information from the branch predictors.

2020-06-16 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30374 )



Change subject: cpu: Delete author information from the branch predictors.
..

cpu: Delete author information from the branch predictors.

Author information has been removed from most files, not to deny
authors credit, but because git already has a much more accurate
version of that information which doesn't become stale, etc.

Some branch predictor files had author information in them which this
change removes to be consistent with the rest of gem5.

Also from a practical perspective, unfortunately, one of the names in
these particular files contains a non-ascii character which can trip up
tools like our git precommit hook.

Change-Id: If7fa7751b1d15e93d865e568b769c7b317d73bc8
---
M src/cpu/pred/multiperspective_perceptron.cc
M src/cpu/pred/multiperspective_perceptron.hh
M src/cpu/pred/multiperspective_perceptron_64KB.cc
M src/cpu/pred/multiperspective_perceptron_64KB.hh
M src/cpu/pred/multiperspective_perceptron_8KB.cc
M src/cpu/pred/multiperspective_perceptron_8KB.hh
M src/cpu/pred/multiperspective_perceptron_tage.cc
M src/cpu/pred/multiperspective_perceptron_tage.hh
M src/cpu/pred/multiperspective_perceptron_tage_64KB.cc
M src/cpu/pred/multiperspective_perceptron_tage_64KB.hh
M src/cpu/pred/multiperspective_perceptron_tage_8KB.cc
M src/cpu/pred/multiperspective_perceptron_tage_8KB.hh
M src/cpu/pred/statistical_corrector.cc
M src/cpu/pred/statistical_corrector.hh
M src/cpu/pred/tage_sc_l.cc
M src/cpu/pred/tage_sc_l.hh
M src/cpu/pred/tage_sc_l_64KB.cc
M src/cpu/pred/tage_sc_l_64KB.hh
M src/cpu/pred/tage_sc_l_8KB.cc
M src/cpu/pred/tage_sc_l_8KB.hh
20 files changed, 16 insertions(+), 92 deletions(-)



diff --git a/src/cpu/pred/multiperspective_perceptron.cc  
b/src/cpu/pred/multiperspective_perceptron.cc

index 6582197..fc3b5fa 100644
--- a/src/cpu/pred/multiperspective_perceptron.cc
+++ b/src/cpu/pred/multiperspective_perceptron.cc
@@ -26,14 +26,10 @@
  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  Author: Daniel A. Jiménez
- *  Adapted to gem5 by: Javier Bueno Hedo
- *
  */

  /*
-  * Multiperspective Perceptron Predictor (by Daniel A. Jiménez)
+  * Multiperspective Perceptron Predictor
   */

 #include "cpu/pred/multiperspective_perceptron.hh"
diff --git a/src/cpu/pred/multiperspective_perceptron.hh  
b/src/cpu/pred/multiperspective_perceptron.hh

index 9d45032..e680cce 100644
--- a/src/cpu/pred/multiperspective_perceptron.hh
+++ b/src/cpu/pred/multiperspective_perceptron.hh
@@ -26,14 +26,6 @@
  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  Author: Daniel A. Jiménez
- *  Adapted to gem5 by: Javier Bueno Hedo
- *
- */
-
-/*
- * Multiperspective Perceptron Predictor (by Daniel A. Jiménez)
  */

 #ifndef __CPU_PRED_MULTIPERSPECTIVE_PERCEPTRON_HH__
diff --git a/src/cpu/pred/multiperspective_perceptron_64KB.cc  
b/src/cpu/pred/multiperspective_perceptron_64KB.cc

index a5d7241..ea23cb9 100644
--- a/src/cpu/pred/multiperspective_perceptron_64KB.cc
+++ b/src/cpu/pred/multiperspective_perceptron_64KB.cc
@@ -26,14 +26,10 @@
  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  Author: Daniel A. Jiménez
- *  Adapted to gem5 by: Javier Bueno Hedo
- *
  */

 /*
- * Multiperspective Perceptron Predictor (by Daniel A. Jiménez)
+ * Multiperspective Perceptron Predictor
  * - 64KB version
  */

diff --git a/src/cpu/pred/multiperspective_perceptron_64KB.hh  
b/src/cpu/pred/multiperspective_perceptron_64KB.hh

index a87020b..5eea8d5 100644
--- a/src/cpu/pred/multiperspective_perceptron_64KB.hh
+++ b/src/cpu/pred/multiperspective_perceptron_64KB.hh
@@ -26,14 +26,10 @@
  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  Author: Daniel A. Jiménez
- *  Adapted to gem5 by: Javier Bueno Hedo
- *
  */

 /*
- * Multiperspective Perceptron Predictor (by Daniel A. Jiménez)
+ * Multiperspective Perceptron Predictor
  * - 64KB version
  */

diff --git a/src/cpu/pred/multiperspective_perceptron_8KB.cc  
b/src/cpu/pred/multiperspective_perceptron_8KB.cc

index 832e172..ad8f114 100644
--- a/src/cpu/pred/multiperspective_perceptron_8KB.cc
+++ b/src/cpu/pred/multiperspective_perceptron_8KB.cc
@@ -26,14 +26,10 @@
  *  THEORY OF LIABILITY, WHETHER 

[gem5-dev] Change in gem5/gem5[develop]: mem: fixupAddr should not panic if it fails.

2020-06-16 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30376 )



Change subject: mem: fixupAddr should not panic if it fails.
..

mem: fixupAddr should not panic if it fails.

This function should just return false in that case, and its callers
should figure out what to do. Otherwise, when calling tryReadBlob in SE
mode, a failure to read the blob makes gem5 panic instead of just
returning false.

Change-Id: I74b9cb98f595c52300d683842ece68c6031d9b85
---
M src/mem/se_translating_port_proxy.cc
1 file changed, 1 insertion(+), 2 deletions(-)



diff --git a/src/mem/se_translating_port_proxy.cc  
b/src/mem/se_translating_port_proxy.cc

index bc1153e..a8a42d0 100644
--- a/src/mem/se_translating_port_proxy.cc
+++ b/src/mem/se_translating_port_proxy.cc
@@ -62,6 +62,5 @@
 return true;
 }
 }
-panic("Page table fault when accessing virtual address %#x "
-  "during functional write.", addr);
+return false;
 }

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I74b9cb98f595c52300d683842ece68c6031d9b85
Gerrit-Change-Number: 30376
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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