Re: [gem5-dev] Heterogeneous ISA Simulation Support

Hi Yasir, As Steve says gem5 has some way to go before supporting heterogeneous ISAs. I actually started out quite a while back to make as much as possible non-ISA specific. For example, the memory tree (src/mem) is pretty much completely ISA agnostic. I think the best way forward is to continue

[gem5-dev] changeset in gem5: stats: Update ref stats to match ARM TLB changes

changeset 7e0f869f8f7e in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=7e0f869f8f7e description: stats: Update ref stats to match ARM TLB changes diffstat: tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt | 2 +-

Re: [gem5-dev] Heterogeneous ISA Simulation Support

The situation hasn't changed. ISA is still a compile-time constant. That said, I don't know of any other systems that simulate both x86 and ARM even with a compile-time switch, so if you're bound and determined to do it, my guess is that gem5 is probably the best starting point you're going to

Re: [gem5-dev] Review Request 3477: misc: SystemC Elastic Trace Player Example

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3477/#review8394 --- Ship it! Ship It! - Paul Rosenfeld On May 28, 2016, 7:18 p.m.,

[gem5-dev] changeset in gem5: arm: refactor page table format determination

changeset 54230f1ebef2 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=54230f1ebef2 description: arm: refactor page table format determination In particular, when EL0 is in AArch32 but EL1 is AArch64, AArch64 memory translation must be used. This is

Re: [gem5-dev] Review Request 3465: dist, dev: Fixed the packet ordering in etherswitch

Hi all, Can somebody with commit access ship this path on behalf of me? http://reviews.gem5.org/r/3465/ Thanks, Mohammad On Thu, Jun 2, 2016 at 3:04 AM, Andreas Hansson wrote: > This is an automatically generated e-mail. To reply, visit: >

[gem5-dev] Heterogeneous ISA Simulation Support

Dear All, I am considering to use GEM5 for simulating heterogeneous ISA systems, eg. ARM-x86 systems in a single simulation. I have went through the archives and seen that this is wasn't supported 2 years ago. Is there any update regarding this or is this still not supported today ? Thank you

[gem5-dev] changeset in gem5: tests: Remove working dir assumption in tgen ...

changeset 12928a51616a in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=12928a51616a description: tests: Remove working dir assumption in tgen tests The traffic generator tests currently assume that they are run from the root of the source directory.

Re: [gem5-dev] LSQ Dynamic policy infinite loop

Hi Jyothish, Thanks for the contribution! Could you post this patch to the reviewboard site? http://reviews.gem5.org/ Take a look at http://gem5.org/Submitting_Contributions to see how to submit to reviewboard and the required commit message formatting. As a quick first pass review, it seems to

[gem5-dev] changeset in gem5: stats: Update to match ARM ISA changes

changeset c48c7cc5a522 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=c48c7cc5a522 description: stats: Update to match ARM ISA changes diffstat: tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini |26 +-

[gem5-dev] changeset in gem5: arm: Rewrite ERET to behave according to the ...

changeset eb53b59ea625 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=eb53b59ea625 description: arm: Rewrite ERET to behave according to the ARMv8 ARM The ERET instruction doesn't set PSTATE correctly in some cases (particularly when returning to

[gem5-dev] changeset in gem5: arm: Correctly check FP/SIMD access permissio...

changeset cb3a401c45d7 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=cb3a401c45d7 description: arm: Correctly check FP/SIMD access permission in aarch32 The current implementation of aarch32 FP/SIMD in gem5 assumes that EL1 and higher are all

[gem5-dev] changeset in gem5: style: remove extra newline from white space ...

changeset b539c1a6e597 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=b539c1a6e597 description: style: remove extra newline from white space verifier fix method Change-Id: I7bce7d1cb04efe20d31445eb67ea5ffd2a4a41f4 Reviewed-by: Andreas Sandberg

[gem5-dev] changeset in gem5: style: respect per verifier ignores for git c...

changeset d7e83588e5bc in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=d7e83588e5bc description: style: respect per verifier ignores for git commit Change-Id: Id00379bdb17594e627ee49c077fb75f499ea550e Reviewed-by: Andreas Sandberg

[gem5-dev] changeset in gem5: tests: add 'CHANGED' output to pickle viewer

changeset 060fc1591151 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=060fc1591151 description: tests: add 'CHANGED' output to pickle viewer Change-Id: I64c69fde8657c273adea69122877c5348a4f867a Reviewed-by: Andreas Sandberg

[gem5-dev] changeset in gem5: style: Move the last bits of file_types.py to...

changeset 46e5f3bf7f17 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=46e5f3bf7f17 description: style: Move the last bits of file_types.py to the style package The commit that refactored the style checkers into a new Python package (style: Refactor

Re: [gem5-dev] Review Request 3465: dist, dev: Fixed the packet ordering in etherswitch

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3465/#review8393 --- Ship it! Ship It! - Andreas Hansson On May 30, 2016, 1:32 p.m.,

[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

* build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp: CHANGED! *