[gem5-dev] Change in public/gem5[master]: mem-cache: Remove extra numSets zero check.

2018-02-06 Thread Daniel Carvalho (Gerrit) 
Daniel Carvalho merged this change by Daniel R. Carvalho. (  
https://gem5-review.googlesource.com/7901 )


Change subject: mem-cache: Remove extra numSets zero check.
..

mem-cache: Remove extra numSets zero check.

numSets is unsigned, so it cannot be lower than 0. Besides, isPowerOf2(0)
is false by definition (and implemmentation*), so there is no need for the
double check.

* As presented in base/intmath.hh

Change-Id: I3f6296694a937434feddc7ed21f11c2a6fdfc5a9
Reviewed-on: https://gem5-review.googlesource.com/7901
Reviewed-by: Andreas Sandberg 
Reviewed-by: Nikos Nikoleris 
Maintainer: Andreas Sandberg 
---
M src/mem/cache/tags/base_set_assoc.cc
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Nikos Nikoleris: Looks good to me, approved



diff --git a/src/mem/cache/tags/base_set_assoc.cc  
b/src/mem/cache/tags/base_set_assoc.cc

index ea74c97..ba94475 100644
--- a/src/mem/cache/tags/base_set_assoc.cc
+++ b/src/mem/cache/tags/base_set_assoc.cc
@@ -63,7 +63,7 @@
 if (blkSize < 4 || !isPowerOf2(blkSize)) {
 fatal("Block size must be at least 4 and a power of 2");
 }
-if (numSets <= 0 || !isPowerOf2(numSets)) {
+if (!isPowerOf2(numSets)) {
 fatal("# of sets must be non-zero and a power of 2");
 }
 if (assoc <= 0) {

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I3f6296694a937434feddc7ed21f11c2a6fdfc5a9
Gerrit-Change-Number: 7901
Gerrit-PatchSet: 2
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Nikos Nikoleris 
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[gem5-dev] Change in public/gem5[master]: arch-arm: IMPLEMENTATION DEFINED register

2018-02-06 Thread Giacomo Travaglini (Gerrit) 

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/7922

to review the following change.


Change subject: arch-arm: IMPLEMENTATION DEFINED register
..

arch-arm: IMPLEMENTATION DEFINED register

A new pseudo register has been added to the Misc pool. It is the
implementation defined register. This kinds of registers are covered by
the architecture and must be treated differently than UNIMPLEMENTED
registers: their access can be trapped to EL2 (See HCR.TIDCP bit in the
arm arm).
Some previously undecoded registers in c9,c10,c11 have now this register
type.

Change-Id: Ibfc35982470b9dea0ecf39aaa6b1012a21852f53
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/insts/pseudo.cc
M src/arch/arm/insts/pseudo.hh
M src/arch/arm/isa/formats/misc.isa
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
5 files changed, 88 insertions(+), 11 deletions(-)



diff --git a/src/arch/arm/insts/pseudo.cc b/src/arch/arm/insts/pseudo.cc
index 40e00ac..e2504d6 100644
--- a/src/arch/arm/insts/pseudo.cc
+++ b/src/arch/arm/insts/pseudo.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014,2016-2017 ARM Limited
+ * Copyright (c) 2014,2016-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -181,10 +181,8 @@
 fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
 }

-
-
 McrMrcMiscInst::McrMrcMiscInst(const char *_mnemonic, ExtMachInst  
_machInst,

- uint64_t _iss, MiscRegIndex _miscReg)
+   uint64_t _iss, MiscRegIndex _miscReg)
 : ArmStaticInst(_mnemonic, _machInst, No_OpClass)
 {
 flags[IsNonSpeculative] = true;
@@ -217,3 +215,37 @@
 {
 return csprintf("%-10s (pipe flush)", mnemonic);
 }
+
+McrMrcImplDefined::McrMrcImplDefined(const char *_mnemonic,
+ ExtMachInst _machInst, uint64_t _iss,
+ MiscRegIndex _miscReg)
+: McrMrcMiscInst(_mnemonic, _machInst, _iss, _miscReg)
+{}
+
+Fault
+McrMrcImplDefined::execute(ExecContext *xc, Trace::InstRecord *traceData)  
const

+{
+uint32_t cpsr = xc->readMiscReg(MISCREG_CPSR);
+uint32_t hcr = xc->readMiscReg(MISCREG_HCR);
+uint32_t scr = xc->readMiscReg(MISCREG_SCR);
+uint32_t hdcr = xc->readMiscReg(MISCREG_HDCR);
+uint32_t hstr = xc->readMiscReg(MISCREG_HSTR);
+uint32_t hcptr = xc->readMiscReg(MISCREG_HCPTR);
+
+bool hypTrap  = mcrMrc15TrapToHyp(miscReg, hcr, cpsr, scr, hdcr, hstr,
+  hcptr, iss);
+if (hypTrap) {
+return std::make_shared(machInst, iss,
+EC_TRAPPED_CP15_MCR_MRC);
+} else {
+return std::make_shared(machInst, false,
+  mnemonic);
+}
+}
+
+std::string
+McrMrcImplDefined::generateDisassembly(Addr pc,
+   const SymbolTable *symtab) const
+{
+return csprintf("%-10s (implementation defined)", mnemonic);
+}
diff --git a/src/arch/arm/insts/pseudo.hh b/src/arch/arm/insts/pseudo.hh
index fe28789..5fb7499 100644
--- a/src/arch/arm/insts/pseudo.hh
+++ b/src/arch/arm/insts/pseudo.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014,2016 ARM Limited
+ * Copyright (c) 2014,2016,2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -123,7 +123,7 @@
  */
 class McrMrcMiscInst : public ArmStaticInst
 {
-  private:
+  protected:
 uint64_t iss;
 MiscRegIndex miscReg;

@@ -138,4 +138,21 @@

 };

+/**
+ * This class is also used for IMPLEMENTATION DEFINED registers, whose  
mcr/mrc

+ * behaviour is trappable even for unimplemented registers.
+ */
+class McrMrcImplDefined : public McrMrcMiscInst
+{
+  public:
+McrMrcImplDefined(const char *_mnemonic, ExtMachInst _machInst,
+  uint64_t _iss, MiscRegIndex _miscReg);
+
+Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
+
+std::string
+generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+
+};
+
 #endif
diff --git a/src/arch/arm/isa/formats/misc.isa  
b/src/arch/arm/isa/formats/misc.isa

index 4f834b8..a9acc21 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2010-2013,2016-2017 ARM Limited
+// Copyright (c) 2010-2013,2016-2018 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -219,6 +219,11 @@
 machInst,
 csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s  
unknown",

 crn, opc1, crm, opc2, isRead ? "read" : "write"));
+  case

[gem5-dev] Change in public/gem5[master]: arch-arm: Arch regs and pseudo regs distinction

2018-02-06 Thread Giacomo Travaglini (Gerrit) 

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/7921

to review the following change.


Change subject: arch-arm: Arch regs and pseudo regs distinction
..

arch-arm: Arch regs and pseudo regs distinction

A new identifier has been introduced: NUM_PHYS_MISCREGS, which is used
as a boundary for the number of physical (real) Misc registers in the
system.  Pseudo registers (like CP15_UNIMPL) have been moved after the
NUM_PHYS_MISCREGS identifier, so that their enum number is
(NUM_PHYS_MISCREGS < number < NUM_MISCREGS).  Moving away those
registers has created some free slots that can be used for future Misc
register implementation.
SERIALIZE and UNSERIALIZE now only save/restore PHYSICAL Misc Registers.
This allows us to define as many pseudo registers as we want without
being concerned about checkpoint compatibility.

Change-Id: I7e297b814eeaa4bee640e81bee625fb66710af45
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/isa.hh
M src/arch/arm/miscregs.hh
2 files changed, 38 insertions(+), 12 deletions(-)



diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 1711ee0..aa905e5 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2017 ARM Limited
+ * Copyright (c) 2010, 2012-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -629,7 +629,7 @@
 void serialize(CheckpointOut ) const
 {
 DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
-SERIALIZE_ARRAY(miscRegs, NumMiscRegs);
+SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);

 SERIALIZE_SCALAR(highestELIs64);
 SERIALIZE_SCALAR(haveSecurity);
@@ -641,7 +641,7 @@
 void unserialize(CheckpointIn )
 {
 DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
-UNSERIALIZE_ARRAY(miscRegs, NumMiscRegs);
+UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
 CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
 updateRegMap(tmp_cpsr);

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 779ead7..12f6f3f 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2017 ARM Limited
+ * Copyright (c) 2010-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -666,15 +666,32 @@
 MISCREG_CBAR_EL1,   // 598
 MISCREG_CONTEXTIDR_EL2, // 599

-// Dummy registers
-MISCREG_NOP,// 600
-MISCREG_RAZ,// 601
-MISCREG_CP14_UNIMPL,// 602
-MISCREG_CP15_UNIMPL,// 603
-MISCREG_A64_UNIMPL, // 604
-MISCREG_UNKNOWN,// 605
+// These MISCREG_FREESLOT are available Misc Register
+// slots for future registers to be implemented.
+MISCREG_FREESLOT_1, // 600
+MISCREG_FREESLOT_2, // 601
+MISCREG_FREESLOT_3, // 602
+MISCREG_FREESLOT_4, // 603
+MISCREG_FREESLOT_5, // 604
+MISCREG_FREESLOT_6, // 605

-NUM_MISCREGS// 606
+// NUM_PHYS_MISCREGS specifies the number of actual physical
+// registers, not considering the following pseudo-registers
+// (dummy registers), like UNKNOWN, CP15_UNIMPL...
+// Checkpointing should use this physical index when
+// saving/restoring register values.
+NUM_PHYS_MISCREGS = 606,// 606
+
+// Dummy registers
+MISCREG_NOP,
+MISCREG_RAZ,
+MISCREG_CP14_UNIMPL,
+MISCREG_CP15_UNIMPL,
+MISCREG_A64_UNIMPL,
+MISCREG_UNKNOWN,
+
+// Total number of Misc Registers: Physical + Dummy
+NUM_MISCREGS
 };

 enum MiscRegInfo {
@@ -1348,6 +1365,15 @@
 "cbar_el1",
 "contextidr_el2",

+"freeslot1",
+"freeslot2",
+"freeslot3",
+"freeslot4",
+"freeslot5",
+"freeslot6",
+
+"num_phys_regs",
+
 // Dummy registers
 "nop",
 "raz",

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I7e297b814eeaa4bee640e81bee625fb66710af45
Gerrit-Change-Number: 7921
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg

[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

2018-02-06 Thread Cron Daemon 
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby:
 FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/o3-timing: 
FAILED!
* build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO: 
FAILED!
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple:
 CHANGED!
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level:
 CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: CHANGED!
* build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: 
CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: 
CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual:
 CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: 
CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual:
 CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: CHANGED!
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple:
 CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: 
CHANGED!
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level:
 CHANGED!
* 
build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer:
 CHANGED!
* 
build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level:
 CHANGED!
* 
build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory:
 CHANGED!
* 
build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token:
 CHANGED!
* build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing: CHANGED!
* 
build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple:
 CHANGED!
* 
build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level:
 CHANGED!
* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp:
 CHANGED!
* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: CHANGED!
* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp:
 CHANGED!
* 
build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple:
 CHANGED!
* 
build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level:
 CHANGED!
* build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing: CHANGED!
* build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker: 
CHANGED!
* build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing: CHANGED!
* 
build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple:
 CHANGED!
* build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomic: CHANGED!
* build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing: CHANGED!
* build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic: CHANGED!
* 
build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker: 
CHANGED!
* build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timing: CHANGED!
* build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing: CHANGED!
* build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic: CHANGED!
* build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic: CHANGED!
* build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing: CHANGED!
* 
build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level:
 CHANGED!
* build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing: CHANGED!
* 
build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual:
 CHANGED!
* 
build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual:
 CHANGED!
* 
build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic: 
CHANGED!
* 
build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing: 
CHANGED!
* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing-ruby: 
CHANGED!
* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing: 
CHANGED!
*

[gem5-dev] Change in public/gem5[master]: mem: Standardize mem folder header guards

2018-02-06 Thread Daniel Carvalho (Gerrit) 
Daniel Carvalho merged this change by Daniel R. Carvalho. (  
https://gem5-review.googlesource.com/7881 )


Change subject: mem: Standardize mem folder header guards
..

mem: Standardize mem folder header guards

Standardize all header guards in the mem directory according to the most
frequent patterns. In general they have the form:
  mem:  __FOLDER_TREE_FILE_NAME_HH__
  ruby: __FOLDER_TREE_FILENAME_HH__

Change-Id: I983853e292deb302becf151bf0e970057dc24774
Reviewed-on: https://gem5-review.googlesource.com/7881
Reviewed-by: Nikos Nikoleris 
Maintainer: Nikos Nikoleris 
---
M src/mem/abstract_mem.hh
M src/mem/cache/tags/base.hh
M src/mem/cache/tags/base_set_assoc.hh
M src/mem/external_master.hh
M src/mem/external_slave.hh
M src/mem/fs_translating_port_proxy.hh
M src/mem/hmc_controller.hh
M src/mem/ruby/common/BoolVec.hh
M src/mem/ruby/common/IntVec.hh
M src/mem/ruby/common/MachineID.hh
M src/mem/ruby/common/TypeDefines.hh
M src/mem/ruby/filters/LSB_CountingBloomFilter.hh
M src/mem/ruby/network/BasicLink.hh
M src/mem/ruby/network/BasicRouter.hh
M src/mem/ruby/network/MessageBuffer.hh
M src/mem/ruby/network/fault_model/FaultModel.hh
M src/mem/ruby/network/garnet2.0/CommonTypes.hh
M src/mem/ruby/network/garnet2.0/Credit.hh
M src/mem/ruby/network/garnet2.0/CreditLink.hh
M src/mem/ruby/network/garnet2.0/CrossbarSwitch.hh
M src/mem/ruby/network/garnet2.0/GarnetLink.hh
M src/mem/ruby/network/garnet2.0/GarnetNetwork.hh
M src/mem/ruby/network/garnet2.0/InputUnit.hh
M src/mem/ruby/network/garnet2.0/NetworkInterface.hh
M src/mem/ruby/network/garnet2.0/NetworkLink.hh
M src/mem/ruby/network/garnet2.0/OutVcState.hh
M src/mem/ruby/network/garnet2.0/OutputUnit.hh
M src/mem/ruby/network/garnet2.0/Router.hh
M src/mem/ruby/network/garnet2.0/RoutingUnit.hh
M src/mem/ruby/network/garnet2.0/SwitchAllocator.hh
M src/mem/ruby/network/garnet2.0/VirtualChannel.hh
M src/mem/ruby/network/garnet2.0/flit.hh
M src/mem/ruby/network/garnet2.0/flitBuffer.hh
M src/mem/ruby/network/simple/SimpleLink.hh
M src/mem/ruby/slicc_interface/RubyRequest.hh
M src/mem/ruby/slicc_interface/RubySlicc_Util.hh
M src/mem/ruby/system/CacheRecorder.hh
M src/mem/ruby/system/RubySystem.hh
M src/mem/ruby/system/VIPERCoalescer.hh
M src/mem/simple_mem.hh
40 files changed, 124 insertions(+), 115 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved



diff --git a/src/mem/abstract_mem.hh b/src/mem/abstract_mem.hh
index 31d34f0..b57f73b 100644
--- a/src/mem/abstract_mem.hh
+++ b/src/mem/abstract_mem.hh
@@ -46,8 +46,8 @@
  * AbstractMemory declaration
  */

-#ifndef __ABSTRACT_MEMORY_HH__
-#define __ABSTRACT_MEMORY_HH__
+#ifndef __MEM_ABSTRACT_MEMORY_HH__
+#define __MEM_ABSTRACT_MEMORY_HH__

 #include "mem/mem_object.hh"
 #include "params/AbstractMemory.hh"
@@ -319,4 +319,4 @@

 };

-#endif //__ABSTRACT_MEMORY_HH__
+#endif //__MEM_ABSTRACT_MEMORY_HH__
diff --git a/src/mem/cache/tags/base.hh b/src/mem/cache/tags/base.hh
index 4caf6de..5c9f46a 100644
--- a/src/mem/cache/tags/base.hh
+++ b/src/mem/cache/tags/base.hh
@@ -46,8 +46,8 @@
  * Declaration of a common base class for cache tagstore objects.
  */

-#ifndef __BASE_TAGS_HH__
-#define __BASE_TAGS_HH__
+#ifndef __MEM_CACHE_TAGS_BASE_HH__
+#define __MEM_CACHE_TAGS_BASE_HH__

 #include 

@@ -268,4 +268,4 @@
 virtual void process() { tags->computeStats(); };
 };

-#endif //__BASE_TAGS_HH__
+#endif //__MEM_CACHE_TAGS_BASE_HH__
diff --git a/src/mem/cache/tags/base_set_assoc.hh  
b/src/mem/cache/tags/base_set_assoc.hh

index 4049b84..ef4c68b 100644
--- a/src/mem/cache/tags/base_set_assoc.hh
+++ b/src/mem/cache/tags/base_set_assoc.hh
@@ -45,8 +45,8 @@
  * Declaration of a base set associative tag store.
  */

-#ifndef __MEM_CACHE_TAGS_BASESETASSOC_HH__
-#define __MEM_CACHE_TAGS_BASESETASSOC_HH__
+#ifndef __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
+#define __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__

 #include 
 #include 
@@ -365,4 +365,4 @@
 }
 };

-#endif // __MEM_CACHE_TAGS_BASESETASSOC_HH__
+#endif //__MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
diff --git a/src/mem/external_master.hh b/src/mem/external_master.hh
index 7303de0..d27cb4d 100644
--- a/src/mem/external_master.hh
+++ b/src/mem/external_master.hh
@@ -57,8 +57,8 @@
  * The external port must provide a gem5 MasterPort interface.
  */

-#ifndef __MEM_EXTERNAL_MASTER__
-#define __MEM_EXTERNAL_MASTER__
+#ifndef __MEM_EXTERNAL_MASTER_HH__
+#define __MEM_EXTERNAL_MASTER_HH__

 #include "mem/mem_object.hh"
 #include "params/ExternalMaster.hh"
@@ -135,4 +135,4 @@
 };


-#endif // __MEM_EXTERNAL_MASTER__
+#endif //__MEM_EXTERNAL_MASTER_HH__
diff --git a/src/mem/external_slave.hh b/src/mem/external_slave.hh
index d178223..2bb0be8 100644
--- a/src/mem/external_slave.hh
+++ b/src/mem/external_slave.hh
@@ -57,8 +57,8 @@
  * object).
  */

-#ifndef __MEM_EXTERNAL_SLAVE__
-#define __MEM_EXTERNAL_SLAVE__
+#ifndef

[gem5-dev] Change in public/gem5[master]: mem-cache: Remove extra numSets zero check.

2018-02-06 Thread Daniel Carvalho (Gerrit) 
Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/7901



Change subject: mem-cache: Remove extra numSets zero check.
..

mem-cache: Remove extra numSets zero check.

numSets is unsigned, so it cannot be lower than 0. Besides, isPowerOf2(0)
is false by definition (and implemmentation*), so there is no need for the
double check.

* As presented in base/intmath.hh

Change-Id: I3f6296694a937434feddc7ed21f11c2a6fdfc5a9
---
M src/mem/cache/tags/base_set_assoc.cc
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/mem/cache/tags/base_set_assoc.cc  
b/src/mem/cache/tags/base_set_assoc.cc

index ea74c97..ba94475 100644
--- a/src/mem/cache/tags/base_set_assoc.cc
+++ b/src/mem/cache/tags/base_set_assoc.cc
@@ -63,7 +63,7 @@
 if (blkSize < 4 || !isPowerOf2(blkSize)) {
 fatal("Block size must be at least 4 and a power of 2");
 }
-if (numSets <= 0 || !isPowerOf2(numSets)) {
+if (!isPowerOf2(numSets)) {
 fatal("# of sets must be non-zero and a power of 2");
 }
 if (assoc <= 0) {

--
To view, visit https://gem5-review.googlesource.com/7901
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I3f6296694a937434feddc7ed21f11c2a6fdfc5a9
Gerrit-Change-Number: 7901
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Daniel Carvalho 
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[gem5-dev] Change in public/gem5[master]: mem: Standardize mem folder header guards

2018-02-06 Thread Daniel Carvalho (Gerrit) 
Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/7881



Change subject: mem: Standardize mem folder header guards
..

mem: Standardize mem folder header guards

Standardize all header guards in the mem directory according to the most
frequent patterns. In general they have the form:
  mem:  __FOLDER_TREE_FILE_NAME_HH__
  ruby: __FOLDER_TREE_FILENAME_HH__

Change-Id: I983853e292deb302becf151bf0e970057dc24774
---
M src/mem/abstract_mem.hh
M src/mem/cache/tags/base.hh
M src/mem/cache/tags/base_set_assoc.hh
M src/mem/external_master.hh
M src/mem/external_slave.hh
M src/mem/fs_translating_port_proxy.hh
M src/mem/hmc_controller.hh
M src/mem/ruby/common/BoolVec.hh
M src/mem/ruby/common/IntVec.hh
M src/mem/ruby/common/MachineID.hh
M src/mem/ruby/common/TypeDefines.hh
M src/mem/ruby/filters/LSB_CountingBloomFilter.hh
M src/mem/ruby/network/BasicLink.hh
M src/mem/ruby/network/BasicRouter.hh
M src/mem/ruby/network/MessageBuffer.hh
M src/mem/ruby/network/fault_model/FaultModel.hh
M src/mem/ruby/network/garnet2.0/CommonTypes.hh
M src/mem/ruby/network/garnet2.0/Credit.hh
M src/mem/ruby/network/garnet2.0/CreditLink.hh
M src/mem/ruby/network/garnet2.0/CrossbarSwitch.hh
M src/mem/ruby/network/garnet2.0/GarnetLink.hh
M src/mem/ruby/network/garnet2.0/GarnetNetwork.hh
M src/mem/ruby/network/garnet2.0/InputUnit.hh
M src/mem/ruby/network/garnet2.0/NetworkInterface.hh
M src/mem/ruby/network/garnet2.0/NetworkLink.hh
M src/mem/ruby/network/garnet2.0/OutVcState.hh
M src/mem/ruby/network/garnet2.0/OutputUnit.hh
M src/mem/ruby/network/garnet2.0/Router.hh
M src/mem/ruby/network/garnet2.0/RoutingUnit.hh
M src/mem/ruby/network/garnet2.0/SwitchAllocator.hh
M src/mem/ruby/network/garnet2.0/VirtualChannel.hh
M src/mem/ruby/network/garnet2.0/flit.hh
M src/mem/ruby/network/garnet2.0/flitBuffer.hh
M src/mem/ruby/network/simple/SimpleLink.hh
M src/mem/ruby/slicc_interface/RubyRequest.hh
M src/mem/ruby/slicc_interface/RubySlicc_Util.hh
M src/mem/ruby/system/CacheRecorder.hh
M src/mem/ruby/system/RubySystem.hh
M src/mem/ruby/system/VIPERCoalescer.hh
M src/mem/simple_mem.hh
40 files changed, 124 insertions(+), 115 deletions(-)



diff --git a/src/mem/abstract_mem.hh b/src/mem/abstract_mem.hh
index 31d34f0..b57f73b 100644
--- a/src/mem/abstract_mem.hh
+++ b/src/mem/abstract_mem.hh
@@ -46,8 +46,8 @@
  * AbstractMemory declaration
  */

-#ifndef __ABSTRACT_MEMORY_HH__
-#define __ABSTRACT_MEMORY_HH__
+#ifndef __MEM_ABSTRACT_MEMORY_HH__
+#define __MEM_ABSTRACT_MEMORY_HH__

 #include "mem/mem_object.hh"
 #include "params/AbstractMemory.hh"
@@ -319,4 +319,4 @@

 };

-#endif //__ABSTRACT_MEMORY_HH__
+#endif //__MEM_ABSTRACT_MEMORY_HH__
diff --git a/src/mem/cache/tags/base.hh b/src/mem/cache/tags/base.hh
index 4caf6de..5c9f46a 100644
--- a/src/mem/cache/tags/base.hh
+++ b/src/mem/cache/tags/base.hh
@@ -46,8 +46,8 @@
  * Declaration of a common base class for cache tagstore objects.
  */

-#ifndef __BASE_TAGS_HH__
-#define __BASE_TAGS_HH__
+#ifndef __MEM_CACHE_TAGS_BASE_HH__
+#define __MEM_CACHE_TAGS_BASE_HH__

 #include 

@@ -268,4 +268,4 @@
 virtual void process() { tags->computeStats(); };
 };

-#endif //__BASE_TAGS_HH__
+#endif //__MEM_CACHE_TAGS_BASE_HH__
diff --git a/src/mem/cache/tags/base_set_assoc.hh  
b/src/mem/cache/tags/base_set_assoc.hh

index 4049b84..ef4c68b 100644
--- a/src/mem/cache/tags/base_set_assoc.hh
+++ b/src/mem/cache/tags/base_set_assoc.hh
@@ -45,8 +45,8 @@
  * Declaration of a base set associative tag store.
  */

-#ifndef __MEM_CACHE_TAGS_BASESETASSOC_HH__
-#define __MEM_CACHE_TAGS_BASESETASSOC_HH__
+#ifndef __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
+#define __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__

 #include 
 #include 
@@ -365,4 +365,4 @@
 }
 };

-#endif // __MEM_CACHE_TAGS_BASESETASSOC_HH__
+#endif //__MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
diff --git a/src/mem/external_master.hh b/src/mem/external_master.hh
index 7303de0..d27cb4d 100644
--- a/src/mem/external_master.hh
+++ b/src/mem/external_master.hh
@@ -57,8 +57,8 @@
  * The external port must provide a gem5 MasterPort interface.
  */

-#ifndef __MEM_EXTERNAL_MASTER__
-#define __MEM_EXTERNAL_MASTER__
+#ifndef __MEM_EXTERNAL_MASTER_HH__
+#define __MEM_EXTERNAL_MASTER_HH__

 #include "mem/mem_object.hh"
 #include "params/ExternalMaster.hh"
@@ -135,4 +135,4 @@
 };


-#endif // __MEM_EXTERNAL_MASTER__
+#endif //__MEM_EXTERNAL_MASTER_HH__
diff --git a/src/mem/external_slave.hh b/src/mem/external_slave.hh
index d178223..2bb0be8 100644
--- a/src/mem/external_slave.hh
+++ b/src/mem/external_slave.hh
@@ -57,8 +57,8 @@
  * object).
  */

-#ifndef __MEM_EXTERNAL_SLAVE__
-#define __MEM_EXTERNAL_SLAVE__
+#ifndef __MEM_EXTERNAL_SLAVE_HH__
+#define __MEM_EXTERNAL_SLAVE_HH__

 #include "mem/mem_object.hh"
 #include "params/ExternalSlave.hh"
@@ -139,4 +139,4 @@
 };


-#endif // __MEM_EXTERNAL_SLAVE__
+#endif //__MEM_EXTERNAL_SLAVE_HH__
diff --git