date:20180305

[gem5-dev] Change in public/gem5[master]: sparc: Passify a new g++ warning.

2018-03-05 Thread Gabe Black (Gerrit)

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/8763



Change subject: sparc: Passify a new g++ warning.
..

sparc: Passify a new g++ warning.

g++ seems to think there are some missing brackets when initializing
the sparc fault information. Passify it by adding extra brackets.

Change-Id: I826995f88b8ac8a21721c949a244dec480831b80
---
M src/arch/sparc/faults.cc
1 file changed, 55 insertions(+), 55 deletions(-)



diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index c5263cf..6375fa5 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -52,226 +52,226 @@

 template<> SparcFaultBase::FaultVals
 SparcFault::vals
-("power_on_reset", 0x001, 0, {H, H, H});
+("power_on_reset", 0x001, 0, {{H, H, H}});

 template<> SparcFaultBase::FaultVals
 SparcFault::vals
-("watch_dog_reset", 0x002, 120, {H, H, H});
+("watch_dog_reset", 0x002, 120, {{H, H, H}});

 template<> SparcFaultBase::FaultVals
 SparcFault::vals
-("externally_initiated_reset", 0x003, 110, {H, H, H});
+("externally_initiated_reset", 0x003, 110, {{H, H, H}});

 template<> SparcFaultBase::FaultVals
 SparcFault::vals
-("software_initiated_reset", 0x004, 130, {SH, SH, H});
+("software_initiated_reset", 0x004, 130, {{SH, SH, H}});

 template<> SparcFaultBase::FaultVals
 SparcFault::vals
-("RED_state_exception", 0x005, 1, {H, H, H});
+("RED_state_exception", 0x005, 1, {{H, H, H}});

 template<> SparcFaultBase::FaultVals
 SparcFault::vals
-("store_error", 0x007, 201, {H, H, H});
+("store_error", 0x007, 201, {{H, H, H}});

 template<> SparcFaultBase::FaultVals
 SparcFault::vals
-("instruction_access_exception", 0x008, 300, {H, H, H});
+("instruction_access_exception", 0x008, 300, {{H, H, H}});

 //XXX This trap is apparently dropped from ua2005
 /*template<> SparcFaultBase::FaultVals
 SparcFault::vals
-{"inst_mmu", 0x009, 2, {H, H, H}};*/
+("inst_mmu", 0x009, 2, {{H, H, H}});*/

 template<> SparcFaultBase::FaultVals
 SparcFault::vals
-("instruction_access_error", 0x00A, 400, {H, H, H});
+("instruction_access_error", 0x00A, 400, {{H, H, H}});

 template<> SparcFaultBase::FaultVals
 SparcFault::vals
-("illegal_instruction", 0x010, 620, {H, H, H});
+("illegal_instruction", 0x010, 620, {{H, H, H}});

 template<> SparcFaultBase::FaultVals
 SparcFault::vals
-("privileged_opcode", 0x011, 700, {P, SH, SH});
+("privileged_opcode", 0x011, 700, {{P, SH, SH}});

 //XXX This trap is apparently dropped from ua2005
 /*template<> SparcFaultBase::FaultVals
 SparcFault::vals
-{"unimp_ldd", 0x012, 6, {H, H, H}};*/
+("unimp_ldd", 0x012, 6, {{H, H, H}});*/

 //XXX This trap is apparently dropped from ua2005
 /*template<> SparcFaultBase::FaultVals
 SparcFault::vals
-{"unimp_std", 0x013, 6, {H, H, H}};*/
+("unimp_std", 0x013, 6, {{H, H, H}});*/

 template<> SparcFaultBase::FaultVals
 SparcFault::vals
-("fp_disabled", 0x020, 800, {P, P, H});
+("fp_disabled", 0x020, 800, {{P, P, H}});

 /* SPARCv8 and SPARCv9 define just fp_disabled trap. SIMD is not  
contemplated

  * as a separate part. Therefore, we use the same code and TT */
 template<> SparcFaultBase::FaultVals
-SparcFault::vals =
-{"fp_disabled", 0x020, 800, {P, P, H}};
+SparcFault::vals
+("fp_disabled", 0x020, 800, {{P, P, H}});

 template<> SparcFaultBase::FaultVals
 SparcFault::vals
-("fp_exception_ieee_754", 0x021, 1110, {P, P, H});
+("fp_exception_ieee_754", 0x021, 1110, {{P, P, H}});

 template<> SparcFaultBase::FaultVals
 SparcFault::vals
-("fp_exception_other", 0x022, 1110, {P, P, H});
+("fp_exception_other", 0x022, 1110, {{P, P, H}});

 template<> SparcFaultBase::FaultVals
 SparcFault::vals
-("tag_overflow", 0x023, 1400, {P, P, H});
+("tag_overflow", 0x023, 1400, {{P, P, H}});

 template<> SparcFaultBase::FaultVals
 SparcFault::vals
-("clean_window", 0x024, 1010, {P, P, H});
+("clean_window", 0x024, 1010, {{P, P, H}});

 template<> SparcFaultBase::FaultVals
 SparcFault::vals
-("division_by_zero", 0x028, 1500, {P, P, H});
+("division_by_zero", 0x028, 1500, {{P, P, H}});

 template<> SparcFaultBase::FaultVals
 SparcFault::vals
-("internal_processor_error", 0x029, 4, {H, H, H});
+("internal_processor_error", 0x029, 4, {{H, H, H}});

 template<> SparcFaultBase::FaultVals
 SparcFault::vals
-("instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH});
+("instruction_invalid_tsb_entry", 0x02A, 210, {{H, H, SH}});

 template<> SparcFaultBase::FaultVals
 SparcFault::vals
-("data_invalid_tsb_entry", 0x02B, 1203, {H, H, H});
+("data_invalid_tsb_entry", 0x02B, 1203, {{H, H, H}});

 template<> SparcFaultBase::FaultVals
 SparcFault::vals
-("data_access_exception", 0x030, 1201, {H, H, H});
+("data_access_exception", 0x030, 1201, {{H, H, H}});

 //XXX This trap is apparently dropped from ua2005
 /*template<> SparcFaultBase::FaultVals
 SparcFault::vals
-{"data_mmu",

[gem5-dev] Change in public/gem5[master]: config: Switch from the print statement to the print function.

2018-03-05 Thread Gabe Black (Gerrit)

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/8762



Change subject: config: Switch from the print statement to the print  
function.

..

config: Switch from the print statement to the print function.

Change-Id: I701fa58cfcfa2767ce9ad24da314a053889878d0
---
M configs/common/Benchmarks.py
M configs/common/CacheConfig.py
M configs/common/CpuConfig.py
M configs/common/FSConfig.py
M configs/common/GPUTLBConfig.py
M configs/common/MemConfig.py
M configs/common/PlatformConfig.py
M configs/common/Simulation.py
M configs/common/cores/arm/HPI.py
M configs/common/cpu2000.py
M configs/dram/lat_mem_rd.py
M configs/dram/low_power_sweep.py
M configs/dram/sweep.py
M configs/example/apu_se.py
M configs/example/arm/fs_bigLITTLE.py
M configs/example/arm/fs_power.py
M configs/example/arm/starter_fs.py
M configs/example/arm/starter_se.py
M configs/example/etrace_replay.py
M configs/example/fs.py
M configs/example/garnet_synth_traffic.py
M configs/example/hmctest.py
M configs/example/memcheck.py
M configs/example/memtest.py
M configs/example/read_config.py
M configs/example/ruby_direct_test.py
M configs/example/ruby_gpu_random_test.py
M configs/example/ruby_mem_test.py
M configs/example/ruby_random_test.py
M configs/example/se.py
M configs/learning_gem5/part1/simple.py
M configs/learning_gem5/part1/two_level.py
M configs/learning_gem5/part2/hello_goodbye.py
M configs/learning_gem5/part2/run_simple.py
M configs/learning_gem5/part2/simple_cache.py
M configs/learning_gem5/part2/simple_memobj.py
M configs/ruby/Ruby.py
M configs/splash2/cluster.py
M configs/splash2/run.py
39 files changed, 273 insertions(+), 194 deletions(-)



diff --git a/configs/common/Benchmarks.py b/configs/common/Benchmarks.py
index dec1e3e..b7d10b5 100644
--- a/configs/common/Benchmarks.py
+++ b/configs/common/Benchmarks.py
@@ -26,6 +26,8 @@
 #
 # Authors: Ali Saidi

+from __future__ import print_function
+
 from SysPaths import script, disk, binary
 from os import environ as env
 from m5.defines import buildEnv
@@ -63,8 +65,8 @@
 elif buildEnv['TARGET_ISA'] == 'sparc':
 return env.get('LINUX_IMAGE', disk('disk.s10hw2'))
 else:
-print "Don't know what default disk image to use for %s ISA" %  
\

-buildEnv['TARGET_ISA']
+print("Don't know what default disk image to use for %s ISA" %
+buildEnv['TARGET_ISA'])
 exit(1)

 def rootdev(self):
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index a0a18a3..3fa3676 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -41,13 +41,15 @@
 # Configure the M5 cache hierarchy config in one place
 #

+from __future__ import print_function
+
 import m5
 from m5.objects import *
 from Caches import *

 def config_cache(options, system):
 if options.external_memory_system and (options.caches or  
options.l2cache):
-print "External caches and internal caches are exclusive  
options.\n"
+print("External caches and internal caches are exclusive  
options.\n")

 sys.exit(1)

 if options.external_memory_system:
@@ -57,7 +59,7 @@
 try:
 from cores.arm.O3_ARM_v7a import *
 except:
-print "O3_ARM_v7a_3 is unavailable. Did you compile the O3  
model?"
+print("O3_ARM_v7a_3 is unavailable. Did you compile the O3  
model?")

 sys.exit(1)

 dcache_class, icache_class, l2_cache_class, walk_cache_class = \
diff --git a/configs/common/CpuConfig.py b/configs/common/CpuConfig.py
index 327c431..3f193ae 100644
--- a/configs/common/CpuConfig.py
+++ b/configs/common/CpuConfig.py
@@ -35,6 +35,8 @@
 #
 # Authors: Andreas Sandberg

+from __future__ import print_function
+
 from m5 import fatal
 import m5.objects
 import inspect
@@ -64,23 +66,23 @@
 cpu_class = _cpu_classes[name]
 return cpu_class
 except KeyError:
-print "%s is not a valid CPU model." % (name,)
+print("%s is not a valid CPU model." % (name,))
 sys.exit(1)

 def print_cpu_list():
 """Print a list of available CPU classes including their aliases."""

-print "Available CPU classes:"
+print("Available CPU classes:")
 doc_wrapper = TextWrapper(initial_indent="\t\t",  
subsequent_indent="\t\t")

 for name, cls in _cpu_classes.items():
-print "\t%s" % name
+print("\t%s" % name)

 # Try to extract the class documentation from the class help
 # string.
 doc = inspect.getdoc(cls)
 if doc:
 for line in doc_wrapper.wrap(doc):
-print line
+print(line)

 def cpu_names():
 """Return a list of valid CPU names."""
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index fc8765b..42cfafe 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@

[gem5-dev] Change in public/gem5[master]: scons: Switch from the print statement to the print function.

2018-03-05 Thread Gabe Black (Gerrit)

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/8761



Change subject: scons: Switch from the print statement to the print  
function.

..

scons: Switch from the print statement to the print function.

Starting with version 3, scons imposes using the print function instead
of the print statement in code it processes. To get things building
again, this change moves all python code within gem5 to use the
function version. Another change by another author separately made this
same change to the site_tools and site_init.py files.

Change-Id: I2de7dc3b1be756baad6f60574c47c8b7e80ea3b0
---
M SConstruct
M ext/libelf/SConscript
M ext/systemc/SConscript
M ext/systemc/src/sysc/kernel/SConscript.sc
M ext/systemc/src/sysc/qt/SConscript.sc
M src/SConscript
M src/arch/hsail/gen.py
M src/arch/isa_parser.py
M src/arch/micro_asm.py
M src/arch/micro_asm_test.py
M src/cpu/BaseCPU.py
M src/cpu/minor/MinorCPU.py
M src/cpu/o3/O3CPU.py
M src/cpu/simple/BaseSimpleCPU.py
M src/mem/ruby/SConscript
M src/mem/slicc/main.py
M src/mem/slicc/util.py
M src/python/m5/SimObject.py
M src/python/m5/debug.py
M src/python/m5/event.py
M src/python/m5/main.py
M src/python/m5/params.py
M src/python/m5/simulate.py
M src/python/m5/ticks.py
M src/python/m5/util/__init__.py
M src/python/m5/util/attrdict.py
M src/python/m5/util/code_formatter.py
M src/python/m5/util/jobfile.py
M src/python/m5/util/multidict.py
M src/python/m5/util/sorteddict.py
M src/python/m5/util/terminal.py
M src/unittest/genini.py
M tests/SConscript
33 files changed, 386 insertions(+), 318 deletions(-)



diff --git a/SConstruct b/SConstruct
index df647e7..0bb0f69 100755
--- a/SConstruct
+++ b/SConstruct
@@ -78,6 +78,8 @@
 #
 ###

+from __future__ import print_function
+
 # Global Python includes
 import itertools
 import os
@@ -164,7 +166,7 @@
help='Build with Address Sanitizer if available')

 if GetOption('no_lto') and GetOption('force_lto'):
-print '--no-lto and --force-lto are mutually exclusive'
+print('--no-lto and --force-lto are mutually exclusive')
 Exit(1)

 
@@ -183,7 +185,7 @@

 # Check that we have a C/C++ compiler
 if not ('CC' in main_dict_keys and 'CXX' in main_dict_keys):
-print "No C++ compiler installed (package g++ on Ubuntu and RedHat)"
+print("No C++ compiler installed (package g++ on Ubuntu and RedHat)")
 Exit(1)

 ###
@@ -230,15 +232,15 @@
 try:
 build_top = rfind(path_dirs, 'build', -2)
 except:
-print "Error: no non-leaf 'build' dir found on target path", t
+print("Error: no non-leaf 'build' dir found on target path", t)
 Exit(1)
 this_build_root = joinpath('/',*path_dirs[:build_top+1])
 if not build_root:
 build_root = this_build_root
 else:
 if this_build_root != build_root:
-print "Error: build targets not under same build root\n"\
-  "  %s\n  %s" % (build_root, this_build_root)
+print("Error: build targets not under same build root\n"
+  "  %s\n  %s" % (build_root, this_build_root))
 Exit(1)
 variant_path = joinpath('/',*path_dirs[:build_top+2])
 if variant_path not in variant_paths:
@@ -335,7 +337,7 @@
 main['GCC'] = CXX_version and CXX_version.find('g++') >= 0
 main['CLANG'] = CXX_version and CXX_version.find('clang') >= 0
 if main['GCC'] + main['CLANG'] > 1:
-print 'Error: How can we have two at the same time?'
+print('Error: How can we have two at the same time?')
 Exit(1)

 # Set up default C++ compiler flags
@@ -367,22 +369,22 @@
  '-Wno-error=deprecated',
 ])
 else:
-print termcap.Yellow + termcap.Bold + 'Error' + termcap.Normal,
-print "Don't know what compiler options to use for your compiler."
-print termcap.Yellow + '   compiler:' + termcap.Normal, main['CXX']
-print termcap.Yellow + '   version:' + termcap.Normal,
+print(termcap.Yellow + termcap.Bold + 'Error' + termcap.Normal,  
end=' ')

+print("Don't know what compiler options to use for your compiler.")
+print(termcap.Yellow + '   compiler:' + termcap.Normal,  
main['CXX'])

+print(termcap.Yellow + '   version:' + termcap.Normal, end = ' ')
 if not CXX_version:
-print termcap.Yellow + termcap.Bold + "COMMAND NOT FOUND!" +\
-   termcap.Normal
+print(termcap.Yellow + termcap.Bold + "COMMAND NOT FOUND!" +
+  termcap.Normal)
 else:
-print CXX_version.replace('\n', '')
-print "   If you're trying to use a compiler other than GCC"
-print "   or clang, there appears to be something wrong with your"
-print "   environment."
-print "   "
-

[gem5-dev] Change in public/gem5[master]: mem-cache: Remove redundant block initialization on allocation

2018-03-05 Thread Nikos Nikoleris (Gerrit)

Nikos Nikoleris has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/8282 )


Change subject: mem-cache: Remove redundant block initialization on  
allocation

..

mem-cache: Remove redundant block initialization on allocation

Change-Id: I7496e12e6a517529316c480d5f6e2ade601f0e2d
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/8282
Reviewed-by: Daniel Carvalho 
Maintainer: Nikos Nikoleris 
---
M src/mem/cache/tags/base_set_assoc.hh
1 file changed, 1 insertion(+), 5 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Nikos Nikoleris: Looks good to me, approved



diff --git a/src/mem/cache/tags/base_set_assoc.hh  
b/src/mem/cache/tags/base_set_assoc.hh

index cbd4809..fc15b02 100644
--- a/src/mem/cache/tags/base_set_assoc.hh
+++ b/src/mem/cache/tags/base_set_assoc.hh
@@ -257,12 +257,8 @@
  replacements[0]++;
  totalRefs += blk->refCount;
  ++sampledRefs;
- blk->refCount = 0;

- // deal with evicted block
- assert(blk->srcMasterId < cache->system->maxMasters());
- occupancies[blk->srcMasterId]--;
-
+ invalidate(blk);
  blk->invalidate();
  }


--
To view, visit https://gem5-review.googlesource.com/8282
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I7496e12e6a517529316c480d5f6e2ade601f0e2d
Gerrit-Change-Number: 8282
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-MessageType: merged
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[gem5-dev] Change in public/gem5[master]: arch-arm, configs: Treat the bootloader rom as cacheable memory

2018-03-05 Thread Nikos Nikoleris (Gerrit)


Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/8741

to review the following change.


Change subject: arch-arm, configs: Treat the bootloader rom as cacheable  
memory

..

arch-arm, configs: Treat the bootloader rom as cacheable memory

Prior to this changeset the bootloader rom (instantiated as a
SimpleMemory) in ruby Arm systems was treated as an IO device and it
was fronted by a DMA controller. This changeset moves the bootloader
rom and adds it to the system as another memory with a dedicated
directory controller.

Change-Id: I094fed031cdef7f77a939d94f948d967b349b7e0
Reviewed-by: Andreas Sandberg 
---
M configs/common/FSConfig.py
M configs/example/fs.py
M configs/ruby/GPU_RfO.py
M configs/ruby/GPU_VIPER.py
M configs/ruby/GPU_VIPER_Baseline.py
M configs/ruby/GPU_VIPER_Region.py
M configs/ruby/Garnet_standalone.py
M configs/ruby/MESI_Three_Level.py
M configs/ruby/MESI_Two_Level.py
M configs/ruby/MI_example.py
M configs/ruby/MOESI_AMD_Base.py
M configs/ruby/MOESI_CMP_directory.py
M configs/ruby/MOESI_CMP_token.py
M configs/ruby/MOESI_hammer.py
M configs/ruby/Ruby.py
M src/dev/arm/RealView.py
M tests/configs/base_config.py
17 files changed, 109 insertions(+), 59 deletions(-)



diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index fc8765b..dd9f894 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2010-2012, 2015-2017 ARM Limited
+# Copyright (c) 2010-2012, 2015-2018 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -323,8 +323,10 @@
 # iobus, as gem5's membus is only used for initialization and
 # SST doesn't use it.  Attaching nvmem to iobus solves this issue.
 # During initialization, system_port -> membus -> iobus -> nvmem.
-if external_memory or ruby:
+if external_memory:
 self.realview.setupBootLoader(self.iobus,  self, binary)
+elif ruby:
+self.realview.setupBootLoader(None, self, binary)
 else:
 self.realview.setupBootLoader(self.membus, self, binary)
 self.gic_cpu_addr = self.realview.gic.cpu_addr
@@ -383,8 +385,6 @@
 elif ruby:
 self._dma_ports = [ ]
 self.realview.attachOnChipIO(self.iobus, dma_ports=self._dma_ports)
-# Force Ruby to treat the boot ROM as an IO device.
-self.realview.nvmem.in_addr_map = False
 self.realview.attachIO(self.iobus, dma_ports=self._dma_ports)
 else:
 self.realview.attachOnChipIO(self.membus, self.bridge)
diff --git a/configs/example/fs.py b/configs/example/fs.py
index f7115eb..c6d7bfa 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -150,8 +150,9 @@
 test_sys.kvm_vm = KvmVM()

 if options.ruby:
+bootmem = getattr(test_sys 'bootmem', None)
 Ruby.create_system(options, True, test_sys, test_sys.iobus,
-   test_sys._dma_ports)
+   test_sys._dma_ports, bootmem)

 # Create a seperate clock domain for Ruby
 test_sys.ruby.clk_domain = SrcClockDomain(clock =  
options.ruby_clock,

diff --git a/configs/ruby/GPU_RfO.py b/configs/ruby/GPU_RfO.py
index 832ea44..3331ab2 100644
--- a/configs/ruby/GPU_RfO.py
+++ b/configs/ruby/GPU_RfO.py
@@ -427,7 +427,8 @@
 parser.add_option("--tcc-dir-factor", type='int', default=4,
   help="TCCdir size = factor *(TCPs + TCC)")

-def create_system(options, full_system, system, dma_devices, ruby_system):
+def create_system(options, full_system, system, dma_devices, bootmem,
+  ruby_system):
 if buildEnv['PROTOCOL'] != 'GPU_RfO':
 panic("This script requires the GPU_RfO protocol to be built.")

diff --git a/configs/ruby/GPU_VIPER.py b/configs/ruby/GPU_VIPER.py
index e4ba180..37136af 100644
--- a/configs/ruby/GPU_VIPER.py
+++ b/configs/ruby/GPU_VIPER.py
@@ -390,7 +390,8 @@
 parser.add_option("--noL1", action = "store_true", default = False,
   help = "bypassL1")

-def create_system(options, full_system, system, dma_devices, ruby_system):
+def create_system(options, full_system, system, dma_devices, bootmem,
+  ruby_system):
 if buildEnv['PROTOCOL'] != 'GPU_VIPER':
 panic("This script requires the GPU_VIPER protocol to be built.")

diff --git a/configs/ruby/GPU_VIPER_Baseline.py  
b/configs/ruby/GPU_VIPER_Baseline.py

index 978d4cc..ec56925 100644
--- a/configs/ruby/GPU_VIPER_Baseline.py
+++ b/configs/ruby/GPU_VIPER_Baseline.py
@@ -373,7 +373,8 @@
 parser.add_option("--noL2", action = "store_true", default = False,
   help = "bypassL2")

-def create_system(options, full_system, system, dma_devices, ruby_system):
+def create_system(options, full_system, system,

[gem5-dev] Change in public/gem5[master]: mem-cache: Use findBlock() in accessBlock()

2018-03-05 Thread Daniel Carvalho (Gerrit)

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/8721



Change subject: mem-cache: Use findBlock() in accessBlock()
..

mem-cache: Use findBlock() in accessBlock()

Use placement policy specific block search within generic access.

Change-Id: I6070035e6e00595bcf073d4011f78a55ba7e7a8a
---
M src/mem/cache/tags/base_set_assoc.hh
1 file changed, 1 insertion(+), 3 deletions(-)



diff --git a/src/mem/cache/tags/base_set_assoc.hh  
b/src/mem/cache/tags/base_set_assoc.hh

index cbd4809..6a0ead1 100644
--- a/src/mem/cache/tags/base_set_assoc.hh
+++ b/src/mem/cache/tags/base_set_assoc.hh
@@ -161,9 +161,7 @@
  */
 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles ) override
 {
-Addr tag = extractTag(addr);
-int set = extractSet(addr);
-BlkType *blk = sets[set].findBlk(tag, is_secure);
+BlkType *blk = findBlock(addr, is_secure);

 // Access all tags in parallel, hence one in each way.  The data  
side
 // either accesses all blocks in parallel, or one block  
sequentially on


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I6070035e6e00595bcf073d4011f78a55ba7e7a8a
Gerrit-Change-Number: 8721
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho 
Gerrit-MessageType: newchange
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[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

2018-03-05 Thread Cron Daemon

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[gem5-dev] Change in public/gem5[master]: sparc: Passify a new g++ warning.

[gem5-dev] Change in public/gem5[master]: config: Switch from the print statement to the print function.

[gem5-dev] Change in public/gem5[master]: scons: Switch from the print statement to the print function.

[gem5-dev] Change in public/gem5[master]: mem-cache: Remove redundant block initialization on allocation

[gem5-dev] Change in public/gem5[master]: arch-arm, configs: Treat the bootloader rom as cacheable memory

[gem5-dev] Change in public/gem5[master]: mem-cache: Use findBlock() in accessBlock()

[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

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