date:20180326

Re: [gem5-dev] Multicore ARM v8 KVM based simulation

2018-03-26 Thread Gabe Black

I looked into this a little further, and I see the same problem happen with
one CPU but with the CPU and the devices in different event queues. I
haven't figured out exactly where things go wrong, but it looks like a
write DMA is set up but doesn't happen for some reason. I'm not sure if the
DMA starts but then gets stuck, or if it never starts at all. It could also
be that the DMA happens, but the completion event (which is what doesn't
seem to happen) is mishandled because of the additional event queue.

I turned on the DMA debug flag, but that produced so much debug output that
my tools are crashing. I'll have to see what I can do to narrow things down
a bit.

Gabe

On Thu, Mar 22, 2018 at 11:28 AM, Gabe Black  wrote:

> Ok, thanks. We're deciding internally what approach to use to tackle this.
>
> Gabe
>
> On Wed, Mar 21, 2018 at 3:01 AM, Andreas Sandberg <
> andreas.sandb...@arm.com> wrote:
>
>> Hi Gabe,
>>
>> There are issues with the IDE model that prevent it from working with
>> in-kernel GIC emulation. I believe the model doesn't clear interrupts
>> correctly, which confuses the host kernel. I tried to debug this at some
>> point, but wasn't able to do much immaediate progress and decided it wasn't
>> worth the effort. The VirtIO block devices doesn't suffer from this problem.
>>
>> Using the VirtIO device by default seems like a good idea to me. It
>> doesn't simulate any timing, but that might not be a huge deal since the
>> IDE device doesn't provide realistic timing anyway. It would be really
>> awesome if we had a modern storage controller (e.g., NVMe or AHCI) and
>> proper storage timing models.
>>
>> Cheers,
>> Andreas
>>
>> On 20/03/2018 23:38, Gabe Black wrote:
>>
>> My next question is about disks. I see that the fs_bigLITTLE.py script
>> uses PciVirtIO to set up its disks, where I'm using IDE which I inherited
>> from the fs.py scripts I used as reference. The problem I'm seeing is that
>> the IDE controllers seem to be mangling commands and dropping interrupts,
>> so this difference looks particularly suspicious. Is there a KVM related
>> reason you're using PciVirtIO? Is this something that *should* work with
>> IDE bug doesn't, or do I have to use PciVirtIO for things to work properly?
>> I'm not familiar with PciVirtIO beyond briefly skimming the source for it
>> in gem5. Is this something we should consider using globally as a
>> replacement for IDE, even in simulations where we're trying to be really
>> realistic?
>>
>> Thanks again for all the help.
>>
>> Gabe
>>
>> On Tue, Mar 20, 2018 at 3:14 PM, Gabe Black  wrote:
>>
>>> Ok, that (multiple event queues) made things way better. There are still
>>> some glitches to figure out, but at least it makes good forward progress at
>>> a reasonable speed. Thanks!
>>>
>>> Gabe
>>>
>>> On Mon, Mar 19, 2018 at 5:12 PM, Gabe Black 
>>> wrote:
>>>
 This is on an chromebook based on the RK3399 with only ~4GB of RAM
 which is not ideal, although we have a bigger machine in the works for the
 future. I agree with your reasoning and don't think option 1 is a problem.
 We're using static DTBs so I don't think that's an issue either. In my
 script, I'm not doing anything smart with the event queues, so that's
 likely at least part of the problem. When I tried using fs_bigLITTLE.py I
 ran into what looked like a similar issue so that might not be the whole
 story, but it's definitely something I should fix up. I'll let you know how
 that goes!

 Gabe

 On Mon, Mar 19, 2018 at 4:30 AM, Andreas Sandberg <
 andreas.sandb...@arm.com> wrote:

> Hmm, OK, this is very strange.
>
> What type of hardware are you running on? Is it an A57-based chip or
> something else? Also, what's your simulation quantum? I have been able to
> run with a 0.5ms quantum  (5e8 ticks).
> I think the following trace of two CPUs running in KVM should be
> roughly equivalent to the trace you shared earlier. It was generated on a
> commercially available 8xA57 (16GiB ram) using the following command (gem5
> rev 9dc44b417):
>
> gem5.opt -r --debug-flags Kvm,KvmIO,KvmRun 
> configs/example/arm/fs_bigLITTLE.py \
> --sim-quantum '0.5ms' \
> --cpu-type kvm --big-cpus 0 --little-cpus 2 \
> --dtb system/arm/dt/armv8_gem5_v1_2cpu.dtb --kernel 
> vmlinux.aarch64.4.4-d318f95d0c
>
> Note that the tick counts are a bit weird since we have three
> different event queues at play (1 for devices and one per CPU).
>
>   0: system.littleCluster.cpus0: KVM: Executing for 5 ticks
>   0: system.littleCluster.cpus1: KVM: Executing for 5 ticks
>   0: system.littleCluster.cpus0: KVM: Executed 79170 instructions in 
> 176363 cycles (88181504 ticks, sim cycles: 176363).
> 88182000: system.littleCluster.cpus0: handleKvmExit (exit_reason: 6)
>

[gem5-dev] Change in public/gem5[master]: cpu: Proposed fix for backwards compatibility in proto/inst.proto.

2018-03-26 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/9361 )


Change subject: cpu: Proposed fix for backwards compatibility in  
proto/inst.proto.

..

cpu: Proposed fix for backwards compatibility in proto/inst.proto.

I haven't tested this at all, but this may fix backwards compatibility
in inst.proto by removing the oneof construct.

Change-Id: Iba19744791c2c577c3b442402f8cc6dcef8550bd
Reviewed-on: https://gem5-review.googlesource.com/9361
Reviewed-by: Andreas Sandberg 
Reviewed-by: Jason Lowe-Power 
Maintainer: Gabe Black 
---
M src/proto/inst.proto
1 file changed, 7 insertions(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved
  Gabe Black: Looks good to me, approved



diff --git a/src/proto/inst.proto b/src/proto/inst.proto
index d561661..2a5dd95 100644
--- a/src/proto/inst.proto
+++ b/src/proto/inst.proto
@@ -52,10 +52,13 @@

 message Inst {
   required uint64 pc = 1;
-  oneof inst_oneof {
-fixed32 inst = 2;
-bytes inst_bytes = 9;
-  }
+
+  // Either inst or inst_bytes must be used, but never both. That should be
+  // enforced by the oneof keyword, but that's not supported in all  
versions

+  // of protobuf syntax we need to work with for now.
+  optional fixed32 inst = 2;
+  optional bytes inst_bytes = 9;
+
   optional uint32 nodeid = 3;
   optional uint32 cpuid = 4;
   optional fixed64 tick = 5;

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Gerrit-Change-Id: Iba19744791c2c577c3b442402f8cc6dcef8550bd
Gerrit-Change-Number: 9361
Gerrit-PatchSet: 2
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[gem5-dev] Change in public/gem5[master]: scons: Re-enable override based warnings on gcc.

2018-03-26 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/9344 )


Change subject: scons: Re-enable override based warnings on gcc.
..

scons: Re-enable override based warnings on gcc.

These warnings have been fixed.

Change-Id: I28ee5f4ae21412121849fcb9d273939d8e462842
Reviewed-on: https://gem5-review.googlesource.com/9344
Reviewed-by: Andreas Sandberg 
Maintainer: Gabe Black 
---
M SConstruct
1 file changed, 0 insertions(+), 4 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Gabe Black: Looks good to me, approved



diff --git a/SConstruct b/SConstruct
index 0bb0f69..8fde133 100755
--- a/SConstruct
+++ b/SConstruct
@@ -478,10 +478,6 @@
  
main.Append(TCMALLOC_CCFLAGS=['-fno-builtin-malloc', '-fno-builtin-calloc',

   '-fno-builtin-realloc', '-fno-builtin-free'])

-# add option to check for undeclared overrides
-if compareVersions(gcc_version, "5.0") > 0:
-main.Append(CCFLAGS=['-Wno-error=suggest-override'])
-
 # The address sanitizer is available for gcc >= 4.8
 if GetOption('with_asan'):
 if GetOption('with_ubsan') and \

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Gerrit-PatchSet: 2
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[gem5-dev] Change in public/gem5[master]: cpu: Use the new asBytes function in the protobuf inst tracer.

2018-03-26 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/7563 )


Change subject: cpu: Use the new asBytes function in the protobuf inst  
tracer.

..

cpu: Use the new asBytes function in the protobuf inst tracer.

Use this function to get the binary representation of the instruction
rather than referencing the ExtMachInst typed machInst member of the
StaticInst directly. ExtMachInst is an ISA specific type and can't
always be straightforwardly squished into a 32 bit integer.

Change-Id: Ic1f74d6d86eb779016677ae45c022939ce3e2b9f
Reviewed-on: https://gem5-review.googlesource.com/7563
Reviewed-by: Andreas Sandberg 
Maintainer: Gabe Black 
---
M src/cpu/inst_pb_trace.cc
M src/cpu/inst_pb_trace.hh
2 files changed, 17 insertions(+), 2 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Gabe Black: Looks good to me, approved



diff --git a/src/cpu/inst_pb_trace.cc b/src/cpu/inst_pb_trace.cc
index 4003600..138ef53 100644
--- a/src/cpu/inst_pb_trace.cc
+++ b/src/cpu/inst_pb_trace.cc
@@ -69,7 +69,7 @@
 }

 InstPBTrace::InstPBTrace(const InstPBTraceParams *p)
-: InstTracer(p), curMsg(nullptr)
+: InstTracer(p), buf(nullptr), bufSize(0), curMsg(nullptr)
 {
 // Create our output file
 createTraceFile(p->file_name);
@@ -141,10 +141,22 @@
 curMsg = NULL;
 }

+size_t instSize = si->asBytes(buf.get(), bufSize);
+if (instSize > bufSize) {
+bufSize = instSize;
+buf.reset(new uint8_t[bufSize]);
+instSize = si->asBytes(buf.get(), bufSize);
+}
+
 // Create a new instruction message and fill out the fields
 curMsg = new ProtoMessage::Inst;
 curMsg->set_pc(pc.pc());
-curMsg->set_inst(static_cast(bits(si->machInst, 31, 0)));
+if (instSize == sizeof(uint32_t)) {
+curMsg->set_inst(letoh(*reinterpret_cast(buf.get(;
+} else if (instSize) {
+curMsg->set_inst_bytes(
+std::string(reinterpret_cast(buf.get()),  
bufSize));

+}
 curMsg->set_cpuid(tc->cpuId());
 curMsg->set_tick(curTick());
  
curMsg->set_type(static_cast(si->opClass()));

diff --git a/src/cpu/inst_pb_trace.hh b/src/cpu/inst_pb_trace.hh
index 57b3c2c..e9e0147 100644
--- a/src/cpu/inst_pb_trace.hh
+++ b/src/cpu/inst_pb_trace.hh
@@ -93,6 +93,9 @@
 StaticInstPtr mi = NULL) override;

   protected:
+std::unique_ptr buf;
+size_t bufSize;
+
 /** One output stream for the entire simulation.
  * We encode the CPU & system ID so all we need is a single file
  */

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Gerrit-Change-Number: 7563
Gerrit-PatchSet: 3
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Gerrit-Reviewer: Brandon Potter 
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[gem5-dev] Change in public/gem5[master]: arch: Add a virtual asBytes function to the StaticInst class.

2018-03-26 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/7562 )


Change subject: arch: Add a virtual asBytes function to the StaticInst  
class.

..

arch: Add a virtual asBytes function to the StaticInst class.

This function takes a pointer to a buffer and the current size of the
buffer as a pass by reference argument. If the size of the buffer is
sufficient, the function stores a binary representation of itself
(generally the ISA defined instruction encoding) in the buffer, and
sets the size argument to how much space it used. This could be used
by ISAs which have two instruction sizes (ARM and thumb, for example).
If the buffer size isn't sufficient, then the size parameter should be
set to what size is required, and then the function should return
without modifying the buffer.

The buffer itself should be aligned to the same standard as memory
returned by new, specifically "The pointer returned shall be suitably
aligned so that it can be converted to a pointer of any complete object
type and then used to access the object or array in the storage
allocated...". This will avoid having to memcpy buffers to avoid
unaligned accesses.

To standardize the representation of the data, it should be stored in
the buffer as little endian. Since most hosts (including ARM and x86
hosts) will be little endian, this will almost always be a no-op.

Change-Id: I2f31aa0b4f9c0126b44f47a881c2901243279bd6
Reviewed-on: https://gem5-review.googlesource.com/7562
Reviewed-by: Andreas Sandberg 
Maintainer: Gabe Black 
---
M src/arch/alpha/isa/main.isa
M src/arch/arm/insts/static_inst.hh
M src/arch/mips/isa/base.isa
M src/arch/power/insts/static_inst.hh
M src/arch/riscv/insts/static_inst.hh
M src/arch/sparc/insts/static_inst.hh
M src/cpu/static_inst.hh
7 files changed, 67 insertions(+), 2 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Gabe Black: Looks good to me, approved



diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index a23710a..4f269b3 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -51,6 +51,8 @@
 #include "cpu/static_inst.hh"
 #include "mem/packet.hh"
 #include "mem/request.hh"  // some constructors use MemReq flags
+#include "sim/byteswap.hh"
+
 }};

 output decoder {{
@@ -59,9 +61,9 @@
 #include "arch/alpha/decoder.hh"
 #include "arch/alpha/registers.hh"
 #include "arch/alpha/regredir.hh"
-#include "base/loader/symtab.hh"
 #include "base/cprintf.hh"
 #include "base/fenv.hh"
+#include "base/loader/symtab.hh"
 #include "config/ss_compatible_fp.hh"
 #include "cpu/thread_context.hh"  // for Jump::branchTarget()
 #include "mem/packet.hh"
@@ -219,7 +221,6 @@
 class AlphaStaticInst : public StaticInst
 {
   protected:
-
 /// Constructor.
 AlphaStaticInst(const char *mnem, ExtMachInst _machInst,
 OpClass __opClass)
@@ -239,6 +240,13 @@
 {
 pcState.advance();
 }
+
+  public:
+size_t
+asBytes(void *buf, size_t max_size) override
+{
+return simpleAsBytes(buf, max_size, machInst);
+}
 };
 }};

diff --git a/src/arch/arm/insts/static_inst.hh  
b/src/arch/arm/insts/static_inst.hh

index c68880c..3ed374a 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -505,6 +505,12 @@
 {
 return static_cast(machInst & (mask(instSize() * 8)));
 }
+
+size_t
+asBytes(void *buf, size_t max_size) override
+{
+return simpleAsBytes(buf, max_size, machInst);
+}
 };
 }

diff --git a/src/arch/mips/isa/base.isa b/src/arch/mips/isa/base.isa
index 946dce6..3759390 100644
--- a/src/arch/mips/isa/base.isa
+++ b/src/arch/mips/isa/base.isa
@@ -63,6 +63,12 @@
 {
 pc.advance();
 }
+
+size_t
+asBytes(void *buf, size_t max_size) override
+{
+return simpleAsBytes(buf, max_size, machInst);
+}
 };

 }};
diff --git a/src/arch/power/insts/static_inst.hh  
b/src/arch/power/insts/static_inst.hh

index b7a818a..f4f1bec 100644
--- a/src/arch/power/insts/static_inst.hh
+++ b/src/arch/power/insts/static_inst.hh
@@ -69,6 +69,12 @@
 {
 pcState.advance();
 }
+
+size_t
+asBytes(void *buf, size_t max_size) override
+{
+return simpleAsBytes(buf, max_size, machInst);
+}
 };

 } // namespace PowerISA
diff --git a/src/arch/riscv/insts/static_inst.hh  
b/src/arch/riscv/insts/static_inst.hh

index 073b60c..3f6d586 100644
--- a/src/arch/riscv/insts/static_inst.hh
+++ b/src/arch/riscv/insts/static_inst.hh
@@ -56,6 +56,12 @@

   public:
 void advancePC(PCState ) const { pc.advance(); }
+
+size_t
+asBytes(void *buf, size_t size) override
+{
+return simpleAsBytes(buf, size, machInst);
+}
 };

 /**
diff --git

Re: [gem5-dev] Gem5 support for RISC-V 32-bit binaries

2018-03-26 Thread Raul Garcia

Hello Robert,


Thanks for your reply, some of of us would appreciate the riscv32 support.


Regards,
Raul.



From: gem5-dev [gem5-dev-boun...@gem5.org] on behalf of Robert Scheffel 
[robert.scheff...@tu-dresden.de]
Sent: Monday, March 26, 2018 7:31 PM
To: gem5-dev@gem5.org
Subject: Re: [gem5-dev] Gem5 support for RISC-V 32-bit binaries

Hello Raul,

I wanted to start implementing support for rv32 binaries in a couple of
weeks, but currently I can't estimate the effort. So unfortunately I
can't tell, when it will be available.

Regards,
Robert

Am 26.03.2018 um 15:28 schrieb Raul Garcia:
> Hello All,
>
>
> I would like to simulate a RISCV32 binary generated with the 
> riscv32-unknown-elf-gcc compiler.
> I tried to run this binary on Gem5 but I got an error. According to the 
> thread below there is support for 64-bit binaries. I would like to know if is 
> there a GEM5 version that supports RISC-V 32-bit binaries, a workaround that 
> can be used, or if are there plans in the future to support it.
>
>
> https://www.mail-archive.com/gem5-users@gem5.org/msg13556.html
>
>
> Regards,
> Raul.
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Re: [gem5-dev] Gem5 support for RISC-V 32-bit binaries

2018-03-26 Thread Robert Scheffel

Hello Raul,

I wanted to start implementing support for rv32 binaries in a couple of
weeks, but currently I can't estimate the effort. So unfortunately I
can't tell, when it will be available.

Regards,
Robert

Am 26.03.2018 um 15:28 schrieb Raul Garcia:
> Hello All,
> 
> 
> I would like to simulate a RISCV32 binary generated with the 
> riscv32-unknown-elf-gcc compiler.
> I tried to run this binary on Gem5 but I got an error. According to the 
> thread below there is support for 64-bit binaries. I would like to know if is 
> there a GEM5 version that supports RISC-V 32-bit binaries, a workaround that 
> can be used, or if are there plans in the future to support it.
> 
> 
> https://www.mail-archive.com/gem5-users@gem5.org/msg13556.html
> 
> 
> Regards,
> Raul.
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[gem5-dev] Gem5 support for RISC-V 32-bit binaries

2018-03-26 Thread Raul Garcia

Hello All,


I would like to simulate a RISCV32 binary generated with the 
riscv32-unknown-elf-gcc compiler.
I tried to run this binary on Gem5 but I got an error. According to the thread 
below there is support for 64-bit binaries. I would like to know if is there a 
GEM5 version that supports RISC-V 32-bit binaries, a workaround that can be 
used, or if are there plans in the future to support it.


https://www.mail-archive.com/gem5-users@gem5.org/msg13556.html


Regards,
Raul.
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[gem5-dev] Change in public/gem5[master]: arch-arm: Add support for Tarmac trace generation

2018-03-26 Thread Giacomo Travaglini (Gerrit)

Giacomo Travaglini has uploaded a new patch set (#2). (  
https://gem5-review.googlesource.com/9382 )


Change subject: arch-arm: Add support for Tarmac trace generation
..

arch-arm: Add support for Tarmac trace generation

This patch introduces the TarmacTracer: an instruction tracer which
allows to dump a gem5 execution trace in Tarmac format [1]. The new
tracer is supporting either Tarmac and TarmacV8 format specifications.
Not every traceable information has been implemented:

Implemented Trace Type:
Instruction Trace
Register Trace
Processor Memory Access Trace

Unimplemented Trace Type:
Program Flow Trace
Event Trace
Memory Bus Trace

[1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format

Change-Id: I8799d8e5852e868673f728971db3fe8c63961f5e
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/tracers/SConscript
M src/arch/arm/tracers/TarmacTrace.py
A src/arch/arm/tracers/tarmac_record.cc
A src/arch/arm/tracers/tarmac_record.hh
A src/arch/arm/tracers/tarmac_record_v8.cc
A src/arch/arm/tracers/tarmac_record_v8.hh
A src/arch/arm/tracers/tarmac_tracer.cc
A src/arch/arm/tracers/tarmac_tracer.hh
8 files changed, 1,372 insertions(+), 0 deletions(-)


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[gem5-dev] Change in public/gem5[master]: arch-arm: Add support for Tarmac trace-based simulation

2018-03-26 Thread Giacomo Travaglini (Gerrit)

Giacomo Travaglini has uploaded a new patch set (#2). (  
https://gem5-review.googlesource.com/9381 )


Change subject: arch-arm: Add support for Tarmac trace-based simulation
..

arch-arm: Add support for Tarmac trace-based simulation

A new InstTracer (TarmacParser) has been implemented. This tracer is
parsing a pre-existing Tarmac trace file [1] while gem5 is running; it
is comparing execution data together with trace data and it is dumping
differences.
This allows to use Tarmac format as a glue between heterogeneous
simuators speaking the same Tarmac language.

Kudos to Giacomo Gabrielli for writing the original tracer.

[1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format

Change-Id: I9b92204a149813166166adba4a7c61a248bdcac3
Signed-off-by: Giacomo Travaglini 
---
A src/arch/arm/tracers/SConscript
A src/arch/arm/tracers/TarmacTrace.py
A src/arch/arm/tracers/tarmac_base.cc
A src/arch/arm/tracers/tarmac_base.hh
A src/arch/arm/tracers/tarmac_parser.cc
A src/arch/arm/tracers/tarmac_parser.hh
6 files changed, 1,805 insertions(+), 0 deletions(-)


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I9b92204a149813166166adba4a7c61a248bdcac3
Gerrit-Change-Number: 9381
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newpatchset
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[gem5-dev] Change in public/gem5[master]: arch-arm: Add support for Tarmac trace-based simulation

2018-03-26 Thread Giacomo Travaglini (Gerrit)

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/9381



Change subject: arch-arm: Add support for Tarmac trace-based simulation
..

arch-arm: Add support for Tarmac trace-based simulation

A new InstTracer (TarmacParser) has been implemented. This tracer is
parsing a pre-existing Tarmac trace file [1] while gem5 is running; it
is comparing execution data together with trace data and it is dumping
differences.
This allows to use Tarmac format as a glue between heterogeneous
simuators speaking the same Tarmac language.

Kudos to Giacomo Gabrielli for writing the original tracer.

[1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format

Change-Id: I9b92204a149813166166adba4a7c61a248bdcac3
Signed-off-by: Giacomo Travaglini 
---
A src/arch/arm/tracers/SConscript
A src/arch/arm/tracers/TarmacTrace.py
A src/arch/arm/tracers/tarmac_base.cc
A src/arch/arm/tracers/tarmac_base.hh
A src/arch/arm/tracers/tarmac_parser.cc
A src/arch/arm/tracers/tarmac_parser.hh
6 files changed, 1,806 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/tracers/SConscript  
b/src/arch/arm/tracers/SConscript

new file mode 100644
index 000..1491e1a
--- /dev/null
+++ b/src/arch/arm/tracers/SConscript
@@ -0,0 +1,44 @@
+# Copyright (c) 2018 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Giacomo Gabrielli
+#  Giacomo Travaglini
+
+Import('*')
+
+if env['TARGET_ISA'] == 'arm':
+SimObject('TarmacTrace.py')
+Source('tarmac_base.cc')
+Source('tarmac_parser.cc')
diff --git a/src/arch/arm/tracers/TarmacTrace.py  
b/src/arch/arm/tracers/TarmacTrace.py

new file mode 100644
index 000..c2bcbb3
--- /dev/null
+++ b/src/arch/arm/tracers/TarmacTrace.py
@@ -0,0 +1,66 @@
+# Copyright (c) 2018 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the

[gem5-dev] Change in public/gem5[master]: arch-arm: Add support for Tarmac trace generation

2018-03-26 Thread Giacomo Travaglini (Gerrit)

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/9382



Change subject: arch-arm: Add support for Tarmac trace generation
..

arch-arm: Add support for Tarmac trace generation

This patch introduces the TarmacTracer: an instruction tracer which
allows to dump a gem5 execution trace in Tarmac format [1]. The new
tracer is supporting either Tarmac and TarmacV8 format specifications.
Not every traceable information has been implemented:

Implemented Trace Type:
Instruction Trace
Register Trace
Processor Memory Access Trace

Unimplemented Trace Type:
Program Flow Trace
Event Trace
Memory Bus Trace

[1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format

Change-Id: I8799d8e5852e868673f728971db3fe8c63961f5e
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/tracers/SConscript
M src/arch/arm/tracers/TarmacTrace.py
A src/arch/arm/tracers/tarmac_record.cc
A src/arch/arm/tracers/tarmac_record.hh
A src/arch/arm/tracers/tarmac_record_v8.cc
A src/arch/arm/tracers/tarmac_record_v8.hh
A src/arch/arm/tracers/tarmac_tracer.cc
A src/arch/arm/tracers/tarmac_tracer.hh
8 files changed, 1,373 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/tracers/SConscript  
b/src/arch/arm/tracers/SConscript

index 1491e1a..ad11b0a 100644
--- a/src/arch/arm/tracers/SConscript
+++ b/src/arch/arm/tracers/SConscript
@@ -42,3 +42,6 @@
 SimObject('TarmacTrace.py')
 Source('tarmac_base.cc')
 Source('tarmac_parser.cc')
+Source('tarmac_tracer.cc')
+Source('tarmac_record.cc')
+Source('tarmac_record_v8.cc')
diff --git a/src/arch/arm/tracers/TarmacTrace.py  
b/src/arch/arm/tracers/TarmacTrace.py

index c2bcbb3..8955fad 100644
--- a/src/arch/arm/tracers/TarmacTrace.py
+++ b/src/arch/arm/tracers/TarmacTrace.py
@@ -64,3 +64,14 @@

 ignore_mem_addr = Param.AddrRange(AddrRange(0, size=0),
 "Range of unverifiable memory addresses")
+
+class TarmacTracer(InstTracer):
+type = 'TarmacTracer'
+cxx_class = 'Trace::TarmacTracer'
+cxx_header = "arch/arm/tracers/tarmac_tracer.hh"
+
+start_tick = Param.Tick(0,
+"tracing starts when the tick time gets this value")
+
+end_tick = Param.Tick(MaxTick,
+"tracing ends when the tick time gets this value")
diff --git a/src/arch/arm/tracers/tarmac_record.cc  
b/src/arch/arm/tracers/tarmac_record.cc

new file mode 100644
index 000..30ee2a3
--- /dev/null
+++ b/src/arch/arm/tracers/tarmac_record.cc
@@ -0,0 +1,458 @@
+/*
+ * Copyright (c) 2017-2018 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Giacomo Travaglini
+ */
+
+#include "arch/arm/tracers/tarmac_record.hh"
+
+#include "arch/arm/insts/static_inst.hh"
+#include "tarmac_tracer.hh"
+
+namespace Trace {
+
+// TARMAC Instruction Record static variables
+uint64_t

[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

2018-03-26 Thread Cron Daemon

scons: *** [build/ALPHA/proto/inst.pb.cc] Error 1
scons: *** [build/MIPS/proto/inst.pb.cc] Error 1
scons: *** [build/NULL/proto/inst.pb.cc] Error 1
scons: *** [build/NULL_MOESI_hammer/proto/inst.pb.cc] Error 1
scons: *** [build/NULL_MESI_Two_Level/proto/inst.pb.cc] Error 1
scons: *** [build/NULL_MOESI_CMP_directory/proto/inst.pb.cc] Error 1
scons: *** [build/NULL_MOESI_CMP_token/proto/inst.pb.cc] Error 1
scons: *** [build/POWER/proto/inst.pb.cc] Error 1
scons: *** [build/SPARC/proto/inst.pb.cc] Error 1
scons: *** [build/X86/proto/inst.pb.cc] Error 1
scons: *** [build/X86_MESI_Two_Level/proto/inst.pb.cc] Error 1
scons: *** [build/ARM/proto/inst.pb.cc] Error 1
scons: `build/MIPS/tests/opt/quick/fs' is up to date.
scons: `build/NULL/tests/opt/quick/fs' is up to date.
scons: `build/NULL_MOESI_hammer/tests/opt/quick/fs' is up to date.
scons: `build/NULL_MESI_Two_Level/tests/opt/quick/fs' is up to date.
scons: `build/NULL_MOESI_CMP_directory/tests/opt/quick/fs' is up to date.
scons: `build/NULL_MOESI_CMP_token/tests/opt/quick/fs' is up to date.
scons: `build/POWER/tests/opt/quick/fs' is up to date.
scons: `build/X86/tests/opt/quick/fs' is up to date.
scons: `build/X86_MESI_Two_Level/tests/opt/quick/se' is up to date.
scons: `build/X86_MESI_Two_Level/tests/opt/quick/fs' is up to date.
scons: `build/RISCV/tests/opt/quick/fs' is up to date.
scons: `build/HSAIL_X86/tests/opt/quick/fs' is up to date.
scons: *** [build/RISCV/proto/inst.pb.cc] Error 1
scons: *** [build/HSAIL_X86/proto/inst.pb.cc] Error 1
scons: *** Found dependency cycle(s):

See /z/m5/regression/regress-2018-03-26-03:00:01 for details.

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Re: [gem5-dev] Multicore ARM v8 KVM based simulation

[gem5-dev] Change in public/gem5[master]: cpu: Proposed fix for backwards compatibility in proto/inst.proto.

[gem5-dev] Change in public/gem5[master]: scons: Re-enable override based warnings on gcc.

[gem5-dev] Change in public/gem5[master]: cpu: Use the new asBytes function in the protobuf inst tracer.

[gem5-dev] Change in public/gem5[master]: arch: Add a virtual asBytes function to the StaticInst class.

Re: [gem5-dev] Gem5 support for RISC-V 32-bit binaries

Re: [gem5-dev] Gem5 support for RISC-V 32-bit binaries

[gem5-dev] Gem5 support for RISC-V 32-bit binaries

[gem5-dev] Change in public/gem5[master]: arch-arm: Add support for Tarmac trace generation

[gem5-dev] Change in public/gem5[master]: arch-arm: Add support for Tarmac trace-based simulation

[gem5-dev] Change in public/gem5[master]: arch-arm: Add support for Tarmac trace-based simulation

[gem5-dev] Change in public/gem5[master]: arch-arm: Add support for Tarmac trace generation

[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

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