[gem5-dev] Change in public/gem5[master]: mem-cache: Adopt a more sensible cache class hierarchy

2018-03-30 Thread Nikos Nikoleris (Gerrit) 

Hello Gabe Black, Daniel Carvalho, Jason Lowe-Power,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/8290

to look at the new patch set (#3).

Change subject: mem-cache: Adopt a more sensible cache class hierarchy
..

mem-cache: Adopt a more sensible cache class hierarchy

This patch changes what goes into the BaseCache and what goes into the
Cache, to make it easier to add a NoncoherentCache with as much re-use
as possible. A number of redundant members and definitions are also
removed in the process.

This is a modified version of a changeset put together by Andreas
Hansson 

Change-Id: I56cef203728e500f74e9e7599fe307f366dfb753
---
M src/mem/cache/base.cc
M src/mem/cache/base.hh
M src/mem/cache/cache.cc
M src/mem/cache/cache.hh
M src/mem/cache/mshr.cc
M src/mem/cache/mshr.hh
M src/mem/cache/queue_entry.hh
M src/mem/cache/replacement_policies/base.hh
M src/mem/cache/write_queue_entry.cc
M src/mem/cache/write_queue_entry.hh
10 files changed, 446 insertions(+), 454 deletions(-)


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I56cef203728e500f74e9e7599fe307f366dfb753
Gerrit-Change-Number: 8290
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: mem-cache: Add a non-coherent cache

2018-03-30 Thread Nikos Nikoleris (Gerrit) 

Hello Gabe Black, Jason Lowe-Power, Daniel Carvalho,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/8291

to look at the new patch set (#4).

Change subject: mem-cache: Add a non-coherent cache
..

mem-cache: Add a non-coherent cache

The class re-uses the existing MSHR and write queue. At the moment
every single access is handled by the cache, even uncacheable
accesses, and nothing is forwarded.

This is a modified version of a changeset put together by Andreas
Hansson 

Change-Id: I41f7f9c2b8c7fa5ec23712a4446e8adb1c9a336a
---
M configs/example/memtest.py
M src/mem/cache/Cache.py
M src/mem/cache/SConscript
A src/mem/cache/noncoherent_cache.cc
A src/mem/cache/noncoherent_cache.hh
M src/mem/cache/queue.hh
M tests/configs/base_config.py
7 files changed, 1,522 insertions(+), 12 deletions(-)


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Gerrit-Change-Number: 8291
Gerrit-PatchSet: 4
Gerrit-Owner: Nikos Nikoleris 
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[gem5-dev] Change in public/gem5[master]: mem-cache: ReplacementPolicy specific replacement data

2018-03-30 Thread Daniel Carvalho (Gerrit) 

Hello Jason Lowe-Power, Nikos Nikoleris,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/9421

to look at the new patch set (#6).

Change subject: mem-cache: ReplacementPolicy specific replacement data
..

mem-cache: ReplacementPolicy specific replacement data

Replacement data is specific for each replacement policy, and thus
should be instantiated differently by each policy.

Touch and reset do not need to be aware of CacheBlk, as they only
update its ReplacementData.

Change-Id: I998917d800fa48504ed95abffa2f1b7bfd68522b
---
M src/mem/cache/blk.hh
M src/mem/cache/replacement_policies/base.cc
M src/mem/cache/replacement_policies/base.hh
M src/mem/cache/replacement_policies/brrip_rp.cc
M src/mem/cache/replacement_policies/brrip_rp.hh
M src/mem/cache/replacement_policies/fifo_rp.cc
M src/mem/cache/replacement_policies/lru_rp.cc
M src/mem/cache/replacement_policies/lru_rp.hh
M src/mem/cache/replacement_policies/mru_rp.cc
M src/mem/cache/replacement_policies/mru_rp.hh
M src/mem/cache/replacement_policies/random_rp.cc
M src/mem/cache/tags/base_set_assoc.cc
M src/mem/cache/tags/base_set_assoc.hh
13 files changed, 293 insertions(+), 127 deletions(-)


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Gerrit-Change-Number: 9421
Gerrit-PatchSet: 6
Gerrit-Owner: Daniel Carvalho 
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[gem5-dev] Change in public/gem5[master]: mem-cache: ReplacementPolicy specific replacement data

2018-03-30 Thread Daniel Carvalho (Gerrit) 

Hello Jason Lowe-Power, Nikos Nikoleris,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/9421

to look at the new patch set (#7).

Change subject: mem-cache: ReplacementPolicy specific replacement data
..

mem-cache: ReplacementPolicy specific replacement data

Replacement data is specific for each replacement policy, and thus
should be instantiated differently by each policy.

Touch and reset do not need to be aware of CacheBlk, as they only
update its ReplacementData.

Change-Id: I998917d800fa48504ed95abffa2f1b7bfd68522b
---
M src/mem/cache/blk.hh
M src/mem/cache/replacement_policies/base.cc
M src/mem/cache/replacement_policies/base.hh
M src/mem/cache/replacement_policies/brrip_rp.cc
M src/mem/cache/replacement_policies/brrip_rp.hh
M src/mem/cache/replacement_policies/fifo_rp.cc
M src/mem/cache/replacement_policies/lfu_rp.cc
M src/mem/cache/replacement_policies/lru_rp.cc
M src/mem/cache/replacement_policies/lru_rp.hh
M src/mem/cache/replacement_policies/mru_rp.cc
M src/mem/cache/replacement_policies/mru_rp.hh
M src/mem/cache/replacement_policies/random_rp.cc
M src/mem/cache/tags/base_set_assoc.cc
M src/mem/cache/tags/base_set_assoc.hh
14 files changed, 296 insertions(+), 131 deletions(-)


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Gerrit-Change-Number: 9421
Gerrit-PatchSet: 7
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[gem5-dev] Change in public/gem5[master]: mem-cache: Move insertBlock functionality in FALRU

2018-03-30 Thread Daniel Carvalho (Gerrit) 

Hello Jason Lowe-Power, Nikos Nikoleris,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/8882

to look at the new patch set (#5).

Change subject: mem-cache: Move insertBlock functionality in FALRU
..

mem-cache: Move insertBlock functionality in FALRU

Block insertion is being done in the getCandidates function, while the
insertBlock function does not do anything.

Besides, BaseTags' stats weren't being updated.

Change-Id: Iadab9c1ea61519214f66fa24c4b91c4fc95604c0
---
M src/mem/cache/tags/base.cc
M src/mem/cache/tags/base.hh
M src/mem/cache/tags/base_set_assoc.hh
M src/mem/cache/tags/fa_lru.cc
M src/mem/cache/tags/fa_lru.hh
5 files changed, 91 insertions(+), 67 deletions(-)


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Gerrit-Change-Number: 8882
Gerrit-PatchSet: 5
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[gem5-dev] Change in public/gem5[master]: base: Make bitunion output functions static/inline.

2018-03-30 Thread Gabe Black (Gerrit) 
Gabe Black has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/9581 )


Change subject: base: Make bitunion output functions static/inline.
..

base: Make bitunion output functions static/inline.

The specializations need to be online only and not static, but the
template itself is static and inline.

Originally they were in an anonymous namespace, but that causes
warnings when building on clang or with certain versions of gcc because
the functions may not be used in every .cc.

Change-Id: Iff127337f7bf0c18755de07a49d6e7a9ce6f2f0a
Reviewed-on: https://gem5-review.googlesource.com/9581
Reviewed-by: Anthony Gutierrez 
Reviewed-by: Jason Lowe-Power 
Maintainer: Anthony Gutierrez 
Maintainer: Jason Lowe-Power 
---
M src/base/bitunion.hh
1 file changed, 4 insertions(+), 6 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Anthony Gutierrez: Looks good to me, approved; Looks good to me, approved



diff --git a/src/base/bitunion.hh b/src/base/bitunion.hh
index b2a2ba8..49a956e 100644
--- a/src/base/bitunion.hh
+++ b/src/base/bitunion.hh
@@ -419,10 +419,9 @@

 namespace BitfieldBackend
 {
-namespace
-{
+
 template
-std::ostream &
+static inline std::ostream &
 bitfieldBackendPrinter(std::ostream , const T )
 {
 os << t;
@@ -433,7 +432,7 @@
 //these specializations attempt to ensure that they get cast to  
integers

 //of the appropriate type before printing.
 template <>
-std::ostream &
+inline std::ostream &
 bitfieldBackendPrinter(std::ostream , const char )
 {
 os << (const int)t;
@@ -441,14 +440,13 @@
 }

 template <>
-std::ostream &
+inline std::ostream &
 bitfieldBackendPrinter(std::ostream , const unsigned char )
 {
 os << (const unsigned int)t;
 return os;
 }
 }
-}

 //A default << operator which casts a bitunion to its underlying type and
 //passes it to BitfieldBackend::bitfieldBackendPrinter.

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Gerrit-Change-Number: 9581
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Alexandru Duțu 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Gabe Black 
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Gerrit-MessageType: merged
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[gem5-dev] Change in public/gem5[master]: mem-cache: Remove unused return value from the recvTimingReq func

2018-03-30 Thread Nikos Nikoleris (Gerrit) 
Nikos Nikoleris has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/8289 )


Change subject: mem-cache: Remove unused return value from the  
recvTimingReq func

..

mem-cache: Remove unused return value from the recvTimingReq func

The recvTimingReq function in the cache always returns true. This
changeset removes the return value.

Change-Id: I00dddca65ee7224ecfa579ea5195c841dac02972
Reviewed-on: https://gem5-review.googlesource.com/8289
Maintainer: Nikos Nikoleris 
Reviewed-by: Daniel Carvalho 
---
M src/mem/cache/cache.cc
M src/mem/cache/cache.hh
2 files changed, 7 insertions(+), 12 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Nikos Nikoleris: Looks good to me, approved



diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index cbc0ed9..c03b5b2 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -648,7 +648,7 @@
 }
 }

-bool
+void
 Cache::recvTimingReq(PacketPtr pkt)
 {
 DPRINTF(CacheTags, "%s tags:\n%s\n", __func__, tags->print());
@@ -660,7 +660,7 @@
 // @todo This should really enqueue the packet rather
 bool M5_VAR_USED success = memSidePort->sendTimingReq(pkt);
 assert(success);
-return true;
+return;
 }

 promoteWholeLineWrites(pkt);
@@ -730,7 +730,7 @@
 // and we have already sent out any express snoops in the
 // section above to ensure all other copies in the system are
 // invalidated
-return true;
+return;
 }

 // anything that is merely forwarded pays for the forward latency and
@@ -976,8 +976,6 @@

 if (next_pf_time != MaxTick)
 schedMemSideSendEvent(next_pf_time);
-
-return true;
 }

 PacketPtr
@@ -2770,13 +2768,11 @@
 assert(!cache->system->bypassCaches());

 // always let express snoop packets through if even if blocked
-if (pkt->isExpressSnoop()) {
-bool M5_VAR_USED bypass_success = cache->recvTimingReq(pkt);
-assert(bypass_success);
+if (pkt->isExpressSnoop() || tryTiming(pkt)) {
+cache->recvTimingReq(pkt);
 return true;
 }
-
-return tryTiming(pkt) && cache->recvTimingReq(pkt);
+return false;
 }

 Tick
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 4d840be..7d28279 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -350,9 +350,8 @@
 /**
  * Performs the access specified by the request.
  * @param pkt The request to perform.
- * @return The result of the access.
  */
-bool recvTimingReq(PacketPtr pkt);
+void recvTimingReq(PacketPtr pkt);

 /**
  * Insert writebacks into the write buffer

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Gerrit-Change-Number: 8289
Gerrit-PatchSet: 4
Gerrit-Owner: Nikos Nikoleris 
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[gem5-dev] Change in public/gem5[master]: mem-cache: Create LIP Replacement Policy

2018-03-30 Thread Daniel Carvalho (Gerrit) 

Hello Jason Lowe-Power, Nikos Nikoleris,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/9002

to look at the new patch set (#3).

Change subject: mem-cache: Create LIP Replacement Policy
..

mem-cache: Create LIP Replacement Policy

Implementation of a LRU Insertion Policy replacement policy.

Change-Id: I1a9aa0091ff2cdc1b1652c1d5ec7a3b33fba5b44
---
M src/mem/cache/replacement_policies/ReplacementPolicies.py
1 file changed, 3 insertions(+), 0 deletions(-)


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Gerrit-Change-Id: I1a9aa0091ff2cdc1b1652c1d5ec7a3b33fba5b44
Gerrit-Change-Number: 9002
Gerrit-PatchSet: 3
Gerrit-Owner: Daniel Carvalho 
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[gem5-dev] Change in public/gem5[master]: mem-cache: Create BIP Replacement Policy

2018-03-30 Thread Daniel Carvalho (Gerrit) 

Hello Jason Lowe-Power,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/9003

to look at the new patch set (#3).

Change subject: mem-cache: Create BIP Replacement Policy
..

mem-cache: Create BIP Replacement Policy

Implementation of a Bimodal Insertion Policy replacement policy.

Change-Id: Ife058d0d4310dbcb35858348006189f0b2bf7c37
---
M src/mem/cache/replacement_policies/ReplacementPolicies.py
M src/mem/cache/replacement_policies/SConscript
A src/mem/cache/replacement_policies/bip_rp.cc
A src/mem/cache/replacement_policies/bip_rp.hh
4 files changed, 150 insertions(+), 0 deletions(-)


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[gem5-dev] Change in public/gem5[master]: mem-cache: Fix FALRU data block seg fault

2018-03-30 Thread Daniel Carvalho (Gerrit) 
Daniel Carvalho has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/9302 )


Change subject: mem-cache: Fix FALRU data block seg fault
..

mem-cache: Fix FALRU data block seg fault

FALRU didn't initialize the blocks' data, causing seg faults.
This patch does not make FALRU functional yet.

Change-Id: I10cbcf5afc3f8bc357eeb8b7cb46789dec47ba8b
Reviewed-on: https://gem5-review.googlesource.com/9302
Reviewed-by: Nikos Nikoleris 
Maintainer: Nikos Nikoleris 
---
M src/mem/cache/tags/base.cc
M src/mem/cache/tags/base.hh
M src/mem/cache/tags/base_set_assoc.cc
M src/mem/cache/tags/base_set_assoc.hh
M src/mem/cache/tags/fa_lru.cc
5 files changed, 10 insertions(+), 5 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved



diff --git a/src/mem/cache/tags/base.cc b/src/mem/cache/tags/base.cc
index 8b52b74..d2d6e8e 100644
--- a/src/mem/cache/tags/base.cc
+++ b/src/mem/cache/tags/base.cc
@@ -63,7 +63,8 @@
 std::max(p->tag_latency, p->data_latency)),
   cache(nullptr),
   warmupBound((p->warmup_percentage/100.0) * (p->size /  
p->block_size)),

-  warmedUp(false), numBlocks(p->size / p->block_size)
+  warmedUp(false), numBlocks(p->size / p->block_size),
+  dataBlks(new uint8_t[p->size]) // Allocate data storage in one big  
chunk

 {
 }

diff --git a/src/mem/cache/tags/base.hh b/src/mem/cache/tags/base.hh
index 74fc7e0..3370de2 100644
--- a/src/mem/cache/tags/base.hh
+++ b/src/mem/cache/tags/base.hh
@@ -94,6 +94,9 @@
 /** the number of blocks in the cache */
 const unsigned numBlocks;

+/** The data blocks, 1 per cache block. */
+std::unique_ptr dataBlks;
+
 // Statistics
 /**
  * TODO: It would be good if these stats were acquired after warmup.
diff --git a/src/mem/cache/tags/base_set_assoc.cc  
b/src/mem/cache/tags/base_set_assoc.cc

index 2475e6f..0ab806e 100644
--- a/src/mem/cache/tags/base_set_assoc.cc
+++ b/src/mem/cache/tags/base_set_assoc.cc
@@ -57,7 +57,6 @@
 BaseSetAssoc::BaseSetAssoc(const Params *p)
 :BaseTags(p), assoc(p->assoc), allocAssoc(p->assoc),
  blks(p->size / p->block_size),
- dataBlks(new uint8_t[p->size]), // Allocate data storage in one big  
chunk

  numSets(p->size / (p->block_size * p->assoc)),
  sequentialAccess(p->sequential_access),
  sets(p->size / (p->block_size * p->assoc)),
diff --git a/src/mem/cache/tags/base_set_assoc.hh  
b/src/mem/cache/tags/base_set_assoc.hh

index f7b386a..3bc275b 100644
--- a/src/mem/cache/tags/base_set_assoc.hh
+++ b/src/mem/cache/tags/base_set_assoc.hh
@@ -76,7 +76,6 @@
 /** Typedef the set type used in this tag store. */
 typedef CacheSet SetType;

-
   protected:
 /** The associativity of the cache. */
 const unsigned assoc;
@@ -85,8 +84,6 @@

 /** The cache blocks. */
 std::vector blks;
-/** The data blocks, 1 per cache block. */
-std::unique_ptr dataBlks;

 /** The number of sets in the cache. */
 const unsigned numSets;
diff --git a/src/mem/cache/tags/fa_lru.cc b/src/mem/cache/tags/fa_lru.cc
index a38d0bf..1f2909e 100644
--- a/src/mem/cache/tags/fa_lru.cc
+++ b/src/mem/cache/tags/fa_lru.cc
@@ -80,10 +80,12 @@
 head->prev = nullptr;
 head->next = &(blks[1]);
 head->inCache = cacheMask;
+head->data = [0];

 tail->prev = &(blks[numBlocks-2]);
 tail->next = nullptr;
 tail->inCache = 0;
+tail->data = [(numBlocks-1)*blkSize];

 unsigned index = (1 << 17) / blkSize;
 unsigned j = 0;
@@ -100,6 +102,9 @@
 blks[i].next = &(blks[i+1]);
 blks[i].set = 0;
 blks[i].way = i;
+
+// Associate a data chunk to the block
+blks[i].data = [blkSize*i];
 }
 assert(j == numCaches);
 assert(index == numBlocks);

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Gerrit-Change-Number: 9302
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Gerrit-Owner: Daniel Carvalho 
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[gem5-dev] Change in public/gem5[master]: mem-cache: Create LFU replacement policy

2018-03-30 Thread Daniel Carvalho (Gerrit) 
Daniel Carvalho has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/8890 )


Change subject: mem-cache: Create LFU replacement policy
..

mem-cache: Create LFU replacement policy

Implementation of a Least Frequently Used replacement policy.

Change-Id: I772afccd3a7955777e53d59341e922718db44e5c
Reviewed-on: https://gem5-review.googlesource.com/8890
Reviewed-by: Nikos Nikoleris 
Maintainer: Nikos Nikoleris 
---
M src/mem/cache/replacement_policies/ReplacementPolicies.py
M src/mem/cache/replacement_policies/SConscript
A src/mem/cache/replacement_policies/lfu_rp.cc
A src/mem/cache/replacement_policies/lfu_rp.hh
4 files changed, 145 insertions(+), 0 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved



diff --git a/src/mem/cache/replacement_policies/ReplacementPolicies.py  
b/src/mem/cache/replacement_policies/ReplacementPolicies.py

index 5f7ecfc..0beb3e6 100644
--- a/src/mem/cache/replacement_policies/ReplacementPolicies.py
+++ b/src/mem/cache/replacement_policies/ReplacementPolicies.py
@@ -40,6 +40,11 @@
 cxx_class = 'FIFORP'
 cxx_header = "mem/cache/replacement_policies/fifo_rp.hh"

+class LFURP(BaseReplacementPolicy):
+type = 'LFURP'
+cxx_class = 'LFURP'
+cxx_header = "mem/cache/replacement_policies/lfu_rp.hh"
+
 class LRURP(BaseReplacementPolicy):
 type = 'LRURP'
 cxx_class = 'LRURP'
diff --git a/src/mem/cache/replacement_policies/SConscript  
b/src/mem/cache/replacement_policies/SConscript

index 4ac8fe8..26c450a 100644
--- a/src/mem/cache/replacement_policies/SConscript
+++ b/src/mem/cache/replacement_policies/SConscript
@@ -35,6 +35,7 @@
 Source('base.cc')
 Source('brrip_rp.cc')
 Source('fifo_rp.cc')
+Source('lfu_rp.cc')
 Source('lru_rp.cc')
 Source('mru_rp.cc')
 Source('random_rp.cc')
diff --git a/src/mem/cache/replacement_policies/lfu_rp.cc  
b/src/mem/cache/replacement_policies/lfu_rp.cc

new file mode 100644
index 000..90a5ee2
--- /dev/null
+++ b/src/mem/cache/replacement_policies/lfu_rp.cc
@@ -0,0 +1,69 @@
+/**
+ * Copyright (c) 2018 Inria
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Daniel Carvalho
+ */
+
+#include "mem/cache/replacement_policies/lfu_rp.hh"
+
+#include "debug/CacheRepl.hh"
+
+LFURP::LFURP(const Params *p)
+: BaseReplacementPolicy(p)
+{
+}
+
+CacheBlk*
+LFURP::getVictim(const ReplacementCandidates& candidates)
+{
+// There must be at least one replacement candidate
+assert(candidates.size() > 0);
+
+// Visit all candidates to find victim
+CacheBlk* blk = candidates[0];
+for (const auto& candidate : candidates) {
+// Stop iteration if found an invalid block
+if (!candidate->isValid()) {
+blk = candidate;
+break;
+// Update victim block if necessary
+} else if (candidate->refCount < blk->refCount) {
+blk = candidate;
+}
+}
+
+DPRINTF(CacheRepl, "set %x, way %x: selecting blk for replacement\n",
+blk->set, blk->way);
+
+return blk;
+}
+
+LFURP*
+LFURPParams::create()
+{
+return new LFURP(this);
+}
diff --git a/src/mem/cache/replacement_policies/lfu_rp.hh  
b/src/mem/cache/replacement_policies/lfu_rp.hh

new file mode 100644
index 000..affc849
--- /dev/null
+++ b/src/mem/cache/replacement_policies/lfu_rp.hh
@@ -0,0 +1,70 @@
+/**
+ * Copyright (c) 2018

[gem5-dev] Change in public/gem5[master]: mem-cache: Create RRIP Replacement Policy

2018-03-30 Thread Daniel Carvalho (Gerrit) 
Daniel Carvalho has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/8981 )


Change subject: mem-cache: Create RRIP Replacement Policy
..

mem-cache: Create RRIP Replacement Policy

Implementation of a Re-Reference Interval Prediction replacement
policy.

Change-Id: Iba716eb5df2bf2be156e765f889d94f6ad00c91b
Reviewed-on: https://gem5-review.googlesource.com/8981
Maintainer: Nikos Nikoleris 
Reviewed-by: Nikos Nikoleris 
Reviewed-by: Jason Lowe-Power 
---
M src/mem/cache/replacement_policies/ReplacementPolicies.py
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved



diff --git a/src/mem/cache/replacement_policies/ReplacementPolicies.py  
b/src/mem/cache/replacement_policies/ReplacementPolicies.py

index 9176d2b..5f7ecfc 100644
--- a/src/mem/cache/replacement_policies/ReplacementPolicies.py
+++ b/src/mem/cache/replacement_policies/ReplacementPolicies.py
@@ -64,3 +64,6 @@
 "Prioritize evicting blocks that havent had a hit recently")
 btp = Param.Percent(3,
 "Percentage of blocks to be inserted with long RRPV")
+
+class RRIPRP(BRRIPRP):
+btp = 0

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Iba716eb5df2bf2be156e765f889d94f6ad00c91b
Gerrit-Change-Number: 8981
Gerrit-PatchSet: 12
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-MessageType: merged
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[gem5-dev] Change in public/gem5[master]: mem-cache: Create BRRIP replacement policy

2018-03-30 Thread Daniel Carvalho (Gerrit) 
Daniel Carvalho has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/8891 )


Change subject: mem-cache: Create BRRIP replacement policy
..

mem-cache: Create BRRIP replacement policy

Implementation of a Bimodal Re-Reference Interval Prediction
replacement policy.

Change-Id: I25d4a59a60ef7ac496c66852e394fd6cbaf50912
Reviewed-on: https://gem5-review.googlesource.com/8891
Reviewed-by: Nikos Nikoleris 
Maintainer: Nikos Nikoleris 
---
M src/mem/cache/blk.hh
M src/mem/cache/replacement_policies/ReplacementPolicies.py
M src/mem/cache/replacement_policies/SConscript
A src/mem/cache/replacement_policies/brrip_rp.cc
A src/mem/cache/replacement_policies/brrip_rp.hh
5 files changed, 261 insertions(+), 0 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved



diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh
index a1e4502..65f32ff 100644
--- a/src/mem/cache/blk.hh
+++ b/src/mem/cache/blk.hh
@@ -129,6 +129,11 @@
  */
 Tick lastTouchTick;

+/**
+ * Re-Reference Interval Prediction Value. Used with RRIP repl policy.
+ */
+unsigned rrpv;
+
   protected:
 /**
  * Represents that the indicated thread context has a "lock" on
diff --git a/src/mem/cache/replacement_policies/ReplacementPolicies.py  
b/src/mem/cache/replacement_policies/ReplacementPolicies.py

index be9f2de..9176d2b 100644
--- a/src/mem/cache/replacement_policies/ReplacementPolicies.py
+++ b/src/mem/cache/replacement_policies/ReplacementPolicies.py
@@ -54,3 +54,13 @@
 type = 'RandomRP'
 cxx_class = 'RandomRP'
 cxx_header = "mem/cache/replacement_policies/random_rp.hh"
+
+class BRRIPRP(BaseReplacementPolicy):
+type = 'BRRIPRP'
+cxx_class = 'BRRIPRP'
+cxx_header = "mem/cache/replacement_policies/brrip_rp.hh"
+max_RRPV = Param.Unsigned(3, "Maximum RRPV possible")
+hit_priority = Param.Bool(False,
+"Prioritize evicting blocks that havent had a hit recently")
+btp = Param.Percent(3,
+"Percentage of blocks to be inserted with long RRPV")
diff --git a/src/mem/cache/replacement_policies/SConscript  
b/src/mem/cache/replacement_policies/SConscript

index 45a7b4f..4ac8fe8 100644
--- a/src/mem/cache/replacement_policies/SConscript
+++ b/src/mem/cache/replacement_policies/SConscript
@@ -33,6 +33,7 @@
 SimObject('ReplacementPolicies.py')

 Source('base.cc')
+Source('brrip_rp.cc')
 Source('fifo_rp.cc')
 Source('lru_rp.cc')
 Source('mru_rp.cc')
diff --git a/src/mem/cache/replacement_policies/brrip_rp.cc  
b/src/mem/cache/replacement_policies/brrip_rp.cc

new file mode 100644
index 000..9185638
--- /dev/null
+++ b/src/mem/cache/replacement_policies/brrip_rp.cc
@@ -0,0 +1,121 @@
+/**
+ * Copyright (c) 2018 Inria
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Daniel Carvalho
+ */
+
+#include "mem/cache/replacement_policies/brrip_rp.hh"
+
+#include "base/random.hh"
+#include "debug/CacheRepl.hh"
+
+BRRIPRP::BRRIPRP(const Params *p)
+: BaseReplacementPolicy(p),
+  maxRRPV(p->max_RRPV), hitPriority(p->hit_priority), btp(p->btp)
+{
+if (maxRRPV == 0){
+fatal("max_RRPV should be greater than zero.\n");
+}
+}
+
+void
+BRRIPRP::touch(CacheBlk *blk)
+{
+BaseReplacementPolicy::touch(blk);
+
+// Update RRPV if not 0 yet
+// Every hit in HP mode makes the block the last to be evicted, while
+

[gem5-dev] Change in public/gem5[master]: mem-cache: Create BRRIP replacement policy

2018-03-30 Thread Daniel Carvalho (Gerrit) 

Hello Jason Lowe-Power, Nikos Nikoleris,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/8891

to look at the new patch set (#10).

Change subject: mem-cache: Create BRRIP replacement policy
..

mem-cache: Create BRRIP replacement policy

Implementation of a Bimodal Re-Reference Interval Prediction
replacement policy.

Change-Id: I25d4a59a60ef7ac496c66852e394fd6cbaf50912
---
M src/mem/cache/blk.hh
M src/mem/cache/replacement_policies/ReplacementPolicies.py
M src/mem/cache/replacement_policies/SConscript
A src/mem/cache/replacement_policies/brrip_rp.cc
A src/mem/cache/replacement_policies/brrip_rp.hh
5 files changed, 261 insertions(+), 0 deletions(-)


--
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To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I25d4a59a60ef7ac496c66852e394fd6cbaf50912
Gerrit-Change-Number: 8891
Gerrit-PatchSet: 10
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-MessageType: newpatchset
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Re: [gem5-dev] Multicore ARM v8 KVM based simulation

2018-03-30 Thread Gabe Black 
Now out of the blue I'm hitting errors having to do with setting GIC
"attributes" of some sort with code that was working a few hours earlier.
Any idea what it's upset about?



gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 compiled Mar 30 2018 03:08:57
gem5 started Mar 30 2018 03:13:05
gem5 executing on localhost, pid 9033
command line: build/ARM/gem5.debug gem5/google/configs/kvm.py

INFO:root:Disk 0: /home/gabeblack/dist/m5/system/disks/disk.img
INFO:root:Add GPU: NoMali GPU model...
INFO:root:Kernel: /home/gabeblack/dist/m5/system/binaries/vmlinux
INFO:root:Device tree:
/home/gabeblack/dist/m5/system/binaries/armv8_1440x2560_google_v1_2cpu.dtb
Global frequency set at 1 ticks per second
warn: system.pci_ide adopting orphan SimObject param 'disks'
info: kernel located at: /home/gabeblack/dist/m5/system/binaries/vmlinux
warn: Highest ARM exception-level set to AArch32 but bootloader is for
AArch64. Assuming you wanted these to match.
Listening for system connection on port 5900
Listening for system connection on port 3456
Listening for uart1 connection on port 3457
0: system.remote_gdb: listening for remote gdb on port 7000
0: system.remote_gdb: listening for remote gdb on port 7001
warn: CoherentXBar system.membus has no snooping ports attached!
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x8008
info: Loading DTB file:
/home/gabeblack/dist/m5/system/binaries/armv8_1440x2560_google_v1_2cpu.dtb
at address 0x8800
info: KVM: Coalesced MMIO disabled by config.
info: KVM: Coalesced MMIO disabled by config.
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
panic: Failed to set attribute (group: 2, attr: 9, errno: 6)
Memory Usage: 3516676 KBytes
Program aborted at tick 0
--- BEGIN LIBC BACKTRACE ---
build/ARM/gem5.debug(_Z15print_backtracev+0x2c)[0x1a3e750]
build/ARM/gem5.debug(_Z12abortHandleri+0x7c)[0x1a47070]
[0x7988061510]
/lib/aarch64-linux-gnu/libc.so.6(gsignal+0x38)[0x798771b528]
--- END LIBC BACKTRACE ---
Aborted (core dumped)


On Wed, Mar 28, 2018 at 5:14 PM, Gabe Black  wrote:

> Ok, I think I figured it out, and it all has to do with the simulation
> quantum. If the quantum is too big, the kernel might poke hardware and
> expect to get an interrupt within a certain period of time. It could be
> that the CPU gets to the end of its timeout before the simulated hardware
> has had a chance to trigger an interrupt, even though the interrupt would
> happen first if the event queues were held in tighter sync. If I decrease
> the size of the quantum from 500ms (per your suggestion) to 1ms, then I see
> the errors from the keyboard/mouse drivers and the ATA driver go away, at
> least in the one CPU/multiple event queue configuration.
>
> I'm going to do some more testing to make sure there isn't some other
> problem that pops up, and also to characterize the performance impact which
> I'm hopeful won't be too bad.
>
> Also, I was thinking it would be nice if KVM CPUs could set up their event
> queues in some more automatic, less error prone way. Before I knew that
> they needed their own event queue (which I think is just institutional
> knowledge that isn't documented/warned about/etc.?), I had no idea what was
> going wrong when just dropping in some KVM CPUs in place of regular CPUs. I
> don't have a fully fleshed out plan for how to do that, but it doesn't
> *seem* like something that should be that hard to do.
>
> Gabe
>
> On Mon, Mar 26, 2018 at 7:06 PM, Gabe Black  wrote:
>
>> I looked into this a little further, and I see the same problem happen
>> with one CPU but with the CPU and the devices in different event queues. I
>> haven't figured out exactly where things go wrong, but it looks like a
>> write DMA is set up but doesn't happen for some reason. I'm not sure if the
>> DMA starts but then gets stuck, or if it never starts at all. It could also
>> be that the DMA happens, but the completion event (which is what doesn't
>> seem to happen) is mishandled because of the additional event queue.
>>
>> I turned on the DMA debug flag, but that produced so much debug output
>> that my tools are crashing. I'll have to see what I can do to narrow things
>> down a bit.
>>
>> Gabe
>>
>> On Thu, Mar 22, 2018 at 11:28 AM, Gabe Black 
>> wrote:
>>
>>> Ok, thanks. We're deciding internally what approach to use to tackle
>>> this.
>>>
>>> Gabe
>>>
>>> On Wed, Mar 21, 2018 at 3:01 AM, Andreas Sandberg <
>>> andreas.sandb...@arm.com> wrote:
>>>
 Hi Gabe,

 There are issues with the IDE model that prevent it from working with
 in-kernel GIC emulation. I believe the model doesn't clear interrupts
 correctly, which confuses the host kernel. I tried to debug this at some
 point, but wasn't able to do much immaediate progress and decided it wasn't
 worth the effort. The VirtIO block

[gem5-dev] Change in public/gem5[master]: mem: Remove unused 'using namespace'

2018-03-30 Thread Daniel Carvalho (Gerrit) 
Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/9601



Change subject: mem: Remove unused 'using namespace'
..

mem: Remove unused 'using namespace'

Removal of unused/barely used 'using namespace' from C++ files.

Change-Id: I66dc548c04506db2e41180b9ea7ab5abd7d5375a
---
M src/mem/cache/mshr.cc
M src/mem/cache/mshr_queue.cc
M src/mem/cache/tags/base.cc
M src/mem/cache/tags/base_set_assoc.cc
M src/mem/cache/tags/fa_lru.cc
M src/mem/cache/write_queue.cc
M src/mem/cache/write_queue_entry.cc
M src/mem/dram_ctrl.cc
M src/mem/drampower.cc
M src/mem/fs_translating_port_proxy.cc
M src/mem/mem_checker_monitor.cc
M src/mem/packet_queue.cc
M src/mem/page_table.cc
M src/mem/simple_mem.cc
14 files changed, 6 insertions(+), 35 deletions(-)



diff --git a/src/mem/cache/mshr.cc b/src/mem/cache/mshr.cc
index 493b7f0..cc26b56 100644
--- a/src/mem/cache/mshr.cc
+++ b/src/mem/cache/mshr.cc
@@ -60,8 +60,6 @@
 #include "mem/cache/cache.hh"
 #include "sim/core.hh"

-using namespace std;
-
 MSHR::MSHR() : downstreamPending(false),
pendingModified(false),
postInvalidate(false), postDowngrade(false),
@@ -617,7 +615,7 @@
 std::string
 MSHR::print() const
 {
-ostringstream str;
+std::ostringstream str;
 print(str);
 return str.str();
 }
diff --git a/src/mem/cache/mshr_queue.cc b/src/mem/cache/mshr_queue.cc
index f4992e1..29358d7 100644
--- a/src/mem/cache/mshr_queue.cc
+++ b/src/mem/cache/mshr_queue.cc
@@ -47,8 +47,6 @@

 #include "mem/cache/mshr_queue.hh"

-using namespace std;
-
 MSHRQueue::MSHRQueue(const std::string &_label,
  int num_entries, int reserve, int demand_reserve)
 : Queue(_label, num_entries, reserve),
diff --git a/src/mem/cache/tags/base.cc b/src/mem/cache/tags/base.cc
index 8b52b74..b647787 100644
--- a/src/mem/cache/tags/base.cc
+++ b/src/mem/cache/tags/base.cc
@@ -52,8 +52,6 @@
 #include "mem/cache/base.hh"
 #include "sim/sim_exit.hh"

-using namespace std;
-
 BaseTags::BaseTags(const Params *p)
 : ClockedObject(p), blkSize(p->block_size), blkMask(blkSize - 1),
   size(p->size),
diff --git a/src/mem/cache/tags/base_set_assoc.cc  
b/src/mem/cache/tags/base_set_assoc.cc

index 2475e6f..01836b7 100644
--- a/src/mem/cache/tags/base_set_assoc.cc
+++ b/src/mem/cache/tags/base_set_assoc.cc
@@ -52,8 +52,6 @@
 #include "base/intmath.hh"
 #include "sim/core.hh"

-using namespace std;
-
 BaseSetAssoc::BaseSetAssoc(const Params *p)
 :BaseTags(p), assoc(p->assoc), allocAssoc(p->assoc),
  blks(p->size / p->block_size),
diff --git a/src/mem/cache/tags/fa_lru.cc b/src/mem/cache/tags/fa_lru.cc
index a38d0bf..3fa14da 100644
--- a/src/mem/cache/tags/fa_lru.cc
+++ b/src/mem/cache/tags/fa_lru.cc
@@ -53,8 +53,6 @@
 #include "base/intmath.hh"
 #include "base/logging.hh"

-using namespace std;
-
 FALRU::FALRU(const Params *p)
 : BaseTags(p), cacheBoundaries(nullptr)
 {
@@ -117,7 +115,6 @@
 void
 FALRU::regStats()
 {
-using namespace Stats;
 BaseTags::regStats();
 hits
 .init(numCaches+1)
@@ -135,7 +132,7 @@
 ;

 for (unsigned i = 0; i <= numCaches; ++i) {
-stringstream size_str;
+std::stringstream size_str;
 if (i < 3){
 size_str << (1<<(i+7)) <<"K";
 } else {
diff --git a/src/mem/cache/write_queue.cc b/src/mem/cache/write_queue.cc
index 7a876b3..13e0fc5 100644
--- a/src/mem/cache/write_queue.cc
+++ b/src/mem/cache/write_queue.cc
@@ -48,8 +48,6 @@

 #include "mem/cache/write_queue.hh"

-using namespace std;
-
 WriteQueue::WriteQueue(const std::string &_label,
int num_entries, int reserve)
 : Queue(_label, num_entries, reserve)
diff --git a/src/mem/cache/write_queue_entry.cc  
b/src/mem/cache/write_queue_entry.cc

index 663c231..b8275e1 100644
--- a/src/mem/cache/write_queue_entry.cc
+++ b/src/mem/cache/write_queue_entry.cc
@@ -61,8 +61,6 @@
 #include "mem/cache/cache.hh"
 #include "sim/core.hh"

-using namespace std;
-
 inline void
 WriteQueueEntry::TargetList::add(PacketPtr pkt, Tick readyTime,
  Counter order)
@@ -163,7 +161,7 @@
 std::string
 WriteQueueEntry::print() const
 {
-ostringstream str;
+std::ostringstream str;
 print(str);
 return str.str();
 }
diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc
index 62de18d..fed519d 100644
--- a/src/mem/dram_ctrl.cc
+++ b/src/mem/dram_ctrl.cc
@@ -2302,8 +2302,6 @@
 void
 DRAMCtrl::Rank::regStats()
 {
-using namespace Stats;
-
 pwrStateTime
 .init(6)
 .name(name() + ".memoryStateTime")
@@ -2367,8 +2365,8 @@
 .name(name() + ".totalIdleTime")
 .desc("Total Idle time Per DRAM Rank");

-registerDumpCallback(new RankDumpCallback(this));
-registerResetCallback(new RankResetCallback(this));
+Stats::registerDumpCallback(new RankDumpCallback(this));
+Stats::registerResetCallback(new

[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

2018-03-30 Thread Cron Daemon 
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby:
 FAILED!--- quick/se/02.insttest/riscv/linux-rv64d/minor-timing ---
* build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO: 
FAILED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: 
CHANGED!
* build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: 
CHANGED!
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple:
 CHANGED!
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build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level:
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* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: 
CHANGED!
*** stat_diff: FAILURE: Statistics mismatch* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual:
 CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: 
CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual:
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* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: 
CHANGED!*** diff[simerr]: SKIPPED
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple:
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build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level:
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build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer:
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build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level:
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build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory:
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build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token:
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* build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing: CHANGED!
* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing: 
CHANGED!
* 
build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple:
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* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: CHANGED!
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build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp:
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* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp:
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* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp:
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* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing: 
CHANGED!
* 
build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level:
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* build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing: 
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* build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing: 
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* build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing: CHANGED!
* build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic: CHANGED!
* build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing: CHANGED!
* build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby: 
CHANGED!
* 
build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple:
 CHANGED!
* 
build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level:
 CHANGED!
* build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic: CHANGED!
* build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic: CHANGED!
* build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing: CHANGED!
* 
build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple:
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* build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing: CHANGED!
* build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic: CHANGED!
* build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing: CHANGED!
*** diff[simout]: SKIPPED* 
build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker: CHANGED!
* 
build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker: 
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* build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing: CHANGED!
* 
build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level:
 CHANGED!
*