[gem5-dev] Change in gem5/gem5[master]: Pl011: Added registers UART_RSR/UART_ECR

MadMaurice has uploaded a new patch set (#2). ( https://gem5-review.googlesource.com/c/public/gem5/+/12686 ) Change subject: Pl011: Added registers UART_RSR/UART_ECR .. Pl011: Added registers UART_RSR/UART_ECR UART_RSR shows

[gem5-dev] Change in gem5/gem5[master]: Pl011: Added registers UART_RSR/UART_ECR

MadMaurice has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/12686 Change subject: Pl011: Added registers UART_RSR/UART_ECR .. Pl011: Added registers UART_RSR/UART_ECR UART_RSR

[gem5-dev] Change in gem5/gem5[master]: Fix error class-memaccess with GCC >= 8.1

MadMaurice has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/12685 Change subject: Fix error class-memaccess with GCC >= 8.1 .. Fix error class-memaccess with GCC >= 8.1 From GCC

[gem5-dev] Cron /z/m5/regression/do-regression quick

* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: FAILED! *