[gem5-dev] Change in gem5/gem5[master]: cpu: Made the Loop Predictor a SimObject

Pau Cabre has uploaded a new patch set (#10) to the change originally created by Javier Bueno Hedo. ( https://gem5-review.googlesource.com/c/public/gem5/+/15775 ) Change subject: cpu: Made the Loop Predictor a SimObject ..

[gem5-dev] Change in gem5/gem5[master]: arch, cpu: Add vector predicate registers

Giacomo Gabrielli has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/13715 ) Change subject: arch,cpu: Add vector predicate registers .. arch,cpu: Add vector predicate

[gem5-dev] Change in gem5/gem5[master]: cpu: Made the Loop Predictor part of LTAGE a SimObject

Pau Cabre has uploaded a new patch set (#9) to the change originally created by Javier Bueno Hedo. ( https://gem5-review.googlesource.com/c/public/gem5/+/15775 ) Change subject: cpu: Made the Loop Predictor part of LTAGE a SimObject

[gem5-dev] Change in gem5/gem5[master]: cpu: Made TAGE a SimObject that can be used by other predictors

Pau Cabre has uploaded a new patch set (#4) to the change originally created by Jairo Balart. ( https://gem5-review.googlesource.com/c/public/gem5/+/15317 ) Change subject: cpu: Made TAGE a SimObject that can be used by other predictors

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Add compression and decompression calls

Hello Daniel Carvalho, Jason Lowe-Power, Nikos Nikoleris, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/11410 to look at the new patch set (#10). Change subject: mem-cache: Add compression and decompression calls

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Create BDI Compressor

Hello Daniel Carvalho, Jason Lowe-Power, Nikos Nikoleris, Gennady Pekhimenko, Mohammad Seyedzadeh, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/11412 to look at the new patch set (#10). Change subject: mem-cache: Create BDI

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Allow tag-only accesses on latency calculation

Hello Jason Lowe-Power, Nikos Nikoleris, max bomb, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/14878 to look at the new patch set (#5). Change subject: mem-cache: Allow tag-only accesses on latency calculation

[gem5-dev] Change in gem5/gem5[master]: configs: Enable DTB autogeneration in starter_fs.py

Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/15959 ) Change subject: configs: Enable DTB autogeneration in starter_fs.py .. configs: Enable DTB

[gem5-dev] Change in gem5/gem5[master]: arch-arm, configs: Create single instance of DTB autogeneration

Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/15958 ) Change subject: arch-arm, configs: Create single instance of DTB autogeneration .. arch-arm,

[gem5-dev] Change in gem5/gem5[master]: arch, cpu: Add vector predicate registers

Hello Gabe Black, Anthony Gutierrez, Jason Lowe-Power, Nikos Nikoleris, Alec Roelke, Giacomo Travaglini, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/13715 to look at the new patch set (#14). Change subject:

[gem5-dev] Change in gem5/gem5[master]: cpu: Move the Loop Predictor from LTAGE to an external class

Hello Giacomo Travaglini, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15775 to look at the new patch set (#7). Change subject: cpu: Move the Loop Predictor from LTAGE to an external class

[gem5-dev] Cron /z/m5/regression/do-regression quick

* build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-checkpoint: FAILED! * build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic: FAILED! * build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing: FAILED! *