date:20190509

[gem5-dev] Change in gem5/gem5[master]: sim-se: remove /sys from special paths

2019-05-09 Thread Brandon Potter (Gerrit)


Hello kokoro, Alexandru Duțu, John Alsop, Jason Lowe-Power,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/12127

to look at the new patch set (#24).

Change subject: sim-se: remove /sys from special paths
..

sim-se: remove /sys from special paths

Currently, the open system call implementation in SE mode
treats /sys/ as a special path that is opened using a
special open handler. The ROC runtime, however, reads
several files in /sys/ that are supported via path
redirection. Here we remove /sys/ from the special files
so that the necessary files may be read via path
redirection.

Change-Id: Ifdab38ea1e6cc486ad43aec96b6e032fe63f137d
---
M configs/learning_gem5/part3/simple_ruby.py
M src/kern/linux/linux.cc
M src/sim/syscall_emul.hh
3 files changed, 28 insertions(+), 13 deletions(-)


--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ifdab38ea1e6cc486ad43aec96b6e032fe63f137d
Gerrit-Change-Number: 12127
Gerrit-PatchSet: 24
Gerrit-Owner: Brandon Potter 
Gerrit-Reviewer: Alexandru Duțu 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: John Alsop 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: newpatchset
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[gem5-dev] AMD GCN - Trace Generation and Replay

2019-05-09 Thread Sampad Mohapatra

Hello Everyone,

Can we use the TraceCPU to generate and replay traces for both the CPU
and GPU ?


In another scenario, can we run the cpu host code on O3 cpu (gpu code
on gpu) and cpu benchmark(s) on separate TraceCPUs ?


Thanks and regards,
Sampad Mohapatra



Virus-free.
www.avg.com

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[gem5-dev] Change in gem5/gem5[master]: config, sim-se: bugfix for 54c77aa0

2019-05-09 Thread Brandon Potter (Gerrit)

Brandon Potter has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18748



Change subject: config, sim-se: bugfix for 54c77aa0
..

config, sim-se: bugfix for 54c77aa0

The NULL ISA does not have some members for the options
class which are referenced by the FileSystemConfig
code.

Create default values for the members so that the
simulation does not fail during the configuration phase.

Change-Id: Ie65bf0e5550c964eae42d1df4c36c2c5bc4ea703
---
M configs/common/FileSystemConfig.py
1 file changed, 17 insertions(+), 3 deletions(-)



diff --git a/configs/common/FileSystemConfig.py  
b/configs/common/FileSystemConfig.py

index 8a6da52..e37fbd3 100644
--- a/configs/common/FileSystemConfig.py
+++ b/configs/common/FileSystemConfig.py
@@ -60,6 +60,20 @@
 procdir = joinpath(fsdir, 'proc')
 mkdir(procdir)

+cpu_clock = '0'
+if hasattr(options, 'cpu_clock'):
+cpu_clock = options.cpu_clock
+cpu_clock = toFrequency(cpu_clock)/mega
+
+l2_size = '0'
+if hasattr(options, 'l2_size'):
+l2_size = options.l2_size
+l2_size = toMemorySize(l2_size)/kibi
+
+cacheline_size = '0'
+if hasattr(options, 'cacheline_size'):
+cacheline_size = options.cacheline_size
+
 for i in xrange(options.num_cpus):
 one_cpu = 'processor   : %d\n' % (i)  + \
   'vendor_id   : Generic\n'   + \
@@ -68,9 +82,9 @@
   'model name  : Generic\n'   + \
   'stepping: 0\n' + \
   'cpu MHz : %0.3d\n'   \
-% (toFrequency(options.cpu_clock)/mega)   + \
+% cpu_clock   + \
   'cache size: : %dK\n' \
-% (toMemorySize(options.l2_size)/kibi)+ \
+% l2_size + \
   'physical id : 0\n' + \
   'siblings: %s\n'  \
 % options.num_cpus+ \
@@ -84,7 +98,7 @@
   'wp  : yes\n'   + \
   'flags   : fpu\n'   + \
   'cache alignment : %d\n'  \
-% options.cacheline_size  + \
+% cacheline_size  + \
   '\n'
 file_append((procdir, 'cpuinfo'), one_cpu)


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ie65bf0e5550c964eae42d1df4c36c2c5bc4ea703
Gerrit-Change-Number: 18748
Gerrit-PatchSet: 1
Gerrit-Owner: Brandon Potter 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: configs: Fix FileSystemConfig import

2019-05-09 Thread Brandon Potter (Gerrit)

Brandon Potter has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18709 )


Change subject: configs: Fix FileSystemConfig import
..

configs: Fix FileSystemConfig import

Add source to FileSystemConfig import

Change-Id: I2cd70a332244cbdc58b1b7c06d589b4339f6e19a
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18709
Tested-by: kokoro 
Maintainer: Brandon Potter 
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
---
M configs/ruby/MESI_Three_Level.py
M configs/ruby/MOESI_AMD_Base.py
M configs/ruby/MOESI_hammer.py
3 files changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Brandon Potter: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/ruby/MESI_Three_Level.py  
b/configs/ruby/MESI_Three_Level.py

index 6d6bc89..90e9190 100644
--- a/configs/ruby/MESI_Three_Level.py
+++ b/configs/ruby/MESI_Three_Level.py
@@ -35,7 +35,7 @@
 from m5.defines import buildEnv
 from Ruby import create_topology, create_directories
 from Ruby import send_evicts
-import FileSystemConfig
+from common import FileSystemConfig

 #
 # Declare caches used by the protocol
diff --git a/configs/ruby/MOESI_AMD_Base.py b/configs/ruby/MOESI_AMD_Base.py
index d465083..5c4bbe0 100644
--- a/configs/ruby/MOESI_AMD_Base.py
+++ b/configs/ruby/MOESI_AMD_Base.py
@@ -38,7 +38,7 @@
 from m5.util import addToPath
 from Ruby import create_topology
 from Ruby import send_evicts
-import FileSystemConfig
+from common import FileSystemConfig

 addToPath('../')

diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py
index ecac17e..0b04980 100644
--- a/configs/ruby/MOESI_hammer.py
+++ b/configs/ruby/MOESI_hammer.py
@@ -33,7 +33,7 @@
 from m5.defines import buildEnv
 from Ruby import create_topology, create_directories
 from Ruby import send_evicts
-import FileSystemConfig
+from common import FileSystemConfig

 #
 # Declare caches used by the protocol

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I2cd70a332244cbdc58b1b7c06d589b4339f6e19a
Gerrit-Change-Number: 18709
Gerrit-PatchSet: 3
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: tests: Fix import scope of test

2019-05-09 Thread Daniel Carvalho (Gerrit)

Daniel Carvalho has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18708 )


Change subject: tests: Fix import scope of test
..

tests: Fix import scope of test

Add missing scope delimiters to Alpha tester

Change-Id: Ib6796864c0dc8fc3108d9d2a7c2f770d2122889a
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18708
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M tests/configs/twosys-tsunami-simple-atomic.py
1 file changed, 5 insertions(+), 5 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/configs/twosys-tsunami-simple-atomic.py  
b/tests/configs/twosys-tsunami-simple-atomic.py

index 3892745..0ba92f4 100644
--- a/tests/configs/twosys-tsunami-simple-atomic.py
+++ b/tests/configs/twosys-tsunami-simple-atomic.py
@@ -31,8 +31,8 @@
 m5.util.addToPath('../configs/')
 from common import Benchmarks, FSConfig, SysPaths

-test_sys = makeLinuxAlphaSystem('atomic',
-SysConfig('netperf-stream-client.rcS'))
+test_sys = FSConfig.makeLinuxAlphaSystem('atomic',
+Benchmarks.SysConfig('netperf-stream-client.rcS'))
 test_sys.kernel = SysPaths.binary('vmlinux')

 # Dummy voltage domain for all test_sys clock domains
@@ -68,8 +68,8 @@
 test_sys.physmem = SimpleMemory(range = test_sys.mem_ranges[0])
 test_sys.physmem.port = test_sys.membus.master

-drive_sys = makeLinuxAlphaSystem('atomic',
- SysConfig('netperf-server.rcS'))
+drive_sys = FSConfig.makeLinuxAlphaSystem('atomic',
+Benchmarks.SysConfig('netperf-server.rcS'))
 drive_sys.kernel = SysPaths.binary('vmlinux')
 # Dummy voltage domain for all drive_sys clock domains
 drive_sys.voltage_domain = VoltageDomain()
@@ -100,6 +100,6 @@
 drive_sys.physmem = SimpleMemory(range = drive_sys.mem_ranges[0])
 drive_sys.physmem.port = drive_sys.membus.master

-root = makeDualRoot(True, test_sys, drive_sys, "ethertrace")
+root = FSConfig.makeDualRoot(True, test_sys, drive_sys, "ethertrace")

 maxtick = 1

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ib6796864c0dc8fc3108d9d2a7c2f770d2122889a
Gerrit-Change-Number: 18708
Gerrit-PatchSet: 4
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Fix MOESI_CMP_directory blocked line handling

2019-05-09 Thread Tiago Mück (Gerrit)

Tiago Mück has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/17568 )


Change subject: mem-ruby: Fix MOESI_CMP_directory blocked line handling
..

mem-ruby: Fix MOESI_CMP_directory blocked line handling

Using recycle in the L2 controllers to put messages back into the buffer
may lead to starvation when there are many L1 requests for the same line.
This can easily trigger the deadlock detection mechanism in configurations
with many cores (16+). Replacing recycle by stall_and_wait for L1
requests avoids this issue. wakeUpBuffers calls were added to all
transitions from transient to stable states.

Change-Id: I28b8aeacc48919ccf38e69653cd9205a4153514b
Signed-off-by: Tiago Muck 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17568
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Matthew Poremba 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/mem/protocol/MOESI_CMP_directory-L2cache.sm
1 file changed, 67 insertions(+), 10 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Matthew Poremba: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm  
b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm

index 0c00bd9..6252219 100644
--- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
@@ -234,6 +234,7 @@
   void set_tbe(TBE b);
   void unset_tbe();
   MachineID mapAddressToMachine(Addr addr, MachineType mtype);
+  void wakeUpAllBuffers(Addr a);

   Entry getCacheEntry(Addr address), return_by_pointer="yes" {
 return static_cast(Entry, "pointer", L2cache[address]);
@@ -1537,13 +1538,6 @@
 localDirectory.deallocate(address);
   }

-  action(zz_recycleL1RequestQueue, "zz", desc="Send the head of the  
mandatory queue to the back of the queue.") {

-peek(L1requestNetwork_in, RequestMsg) {
-  APPEND_TRANSITION_COMMENT(in_msg.Requestor);
-}
-L1requestNetwork_in.recycle(clockEdge(),  
cyclesToTicks(recycle_latency));

-  }
-
   action(zz_recycleRequestQueue, "\zz", desc="Send the head of the  
mandatory queue to the back of the queue.") {

 peek(requestNetwork_in, RequestMsg) {
   APPEND_TRANSITION_COMMENT(in_msg.Requestor);
@@ -1558,6 +1552,14 @@
 responseNetwork_in.recycle(clockEdge(),  
cyclesToTicks(recycle_latency));

   }

+  action(st_stallAndWaitL1RequestQueue, "st", desc="Stall and wait on the  
address") {

+stall_and_wait(L1requestNetwork_in, address);
+  }
+
+  action(wa_wakeUpDependents, "wa", desc="Wake up any requests waiting for  
this address") {

+wakeUpAllBuffers(address);
+  }
+
   action(da_sendDmaAckUnblock, "da", desc="Send dma ack to global  
directory") {

 enqueue(responseNetwork_out, ResponseMsg, response_latency) {
   out_msg.addr := address;
@@ -1576,11 +1578,11 @@
   //*

   transition({II, IFGX, IFGS, ISFGS, IFGXX, IFLXO, OFGX, ILOW, ILOXW,  
ILOSW, ILOSXW, SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO,  
IFLOX, IFLOXX, IFLOSX, OLSXS, IGS, IGM, IGMLS, IGMO, IGMIO, OGMIO, IGMIOF,  
OGMIOF, MM, SS, OO, OI, MI, MII, OLSI, ILSI, SLSS, OLSS, OLSF, IGMIOFS,  
ILOSD, ILOSXD, ILOD, ILXD, ILOXD}, {L1_PUTO, L1_PUTS, L1_PUTS_only,  
L1_PUTX}) {

-zz_recycleL1RequestQueue;
+st_stallAndWaitL1RequestQueue;
   }

   transition({II, IFGX, IFGS, ISFGS, IFGXX, IFLXO, OFGX, ILOW, ILOXW,  
ILOSW, ILOSXW, SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO,  
IFLOX, IFLOXX, IFLOSX, OLSXS, IGS, IGM, IGMLS, IGMO, IGMIO, OGMIO, IGMIOF,  
OGMIOF, MM, SS, OO, OI, MI, MII, OLSI, ILSI, SLSS, OLSS, OLSF, IGMIOFS,  
ILOSD, ILOSXD, ILOD, ILXD, ILOXD}, {L1_GETX, L1_GETS}) {

-zz_recycleL1RequestQueue;
+st_stallAndWaitL1RequestQueue;
   }

   transition({IFGX, IFGS, ISFGS, IFGXX, IFLXO, OFGX, ILOW, ILOXW, ILOSW,  
ILOSXW, SLSW, OLSW, ILSW, IW, ILXW, OW, SW, OXW, OLSXW, IFLS, IFLO, IFLOX,  
IFLOXX, IFLOSX,OLSXS,  IGS, IGM, IGMLS, IGMO, MM, SS, OO, OI, MI, MII,  
OLSI, ILSI, SLSS, OLSS, OLSF, IGMIOFS, ILOSD, ILOSXD, ILOD, ILXD, ILOXD},  
L2_Replacement) {

@@ -1674,6 +1676,7 @@
 s_deallocateTBE;
 da_sendDmaAckUnblock;
 n_popResponseQueue;
+wa_wakeUpDependents;
   }

   transition(ILOSX, Fwd_DMA, ILOSXD) {
@@ -1687,6 +1690,7 @@
 s_deallocateTBE;
 da_sendDmaAckUnblock;
 n_popResponseQueue;
+wa_wakeUpDependents;
   }

   transition(ILO, Fwd_DMA, ILOD) {
@@ -1700,6 +1704,7 @@
 s_deallocateTBE;
 da_sendDmaAckUnblock;
 n_popResponseQueue;
+wa_wakeUpDependents;
   }

   transition(ILX, Fwd_DMA, ILXD) {
@@ -1713,6 +1718,7 @@
 s_deallocateTBE;
 da_sendDmaAckUnblock;
 n_popResponseQueue;
+wa_wakeUpDependents;
   }

   transition(ILOX, Fwd_DMA, ILOXD) {
@@ -1726,6 +1732,7 @@
 s_deallocateTBE;

[gem5-dev] Cron /z/m5/regression/do-regression quick

2019-05-09 Thread Cron Daemon

* 
build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic:
 FAILED!
* build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: FAILED!
* 
build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer:
 FAILED!
* 
build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level:
 FAILED!
* 
build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory:
 FAILED!
* 
build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token:
 FAILED!
* 
build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual:
 FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby:
 FAILED!
* build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO: 
FAILED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: 
CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic: 
CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: CHANGED!
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple:
 CHANGED!
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level:
 CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: 
CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic: CHANGED!
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple:
 CHANGED!
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level:
 CHANGED!
* build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: 
CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: 
CHANGED!
* build/NULL/tests/opt/quick/se/80.dram-openpage/null/none/dram-lowp: 
CHANGED!
* build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem: CHANGED!
* build/NULL/tests/opt/quick/se/80.dram-closepage/null/none/dram-lowp: 
CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: 
CHANGED!
* build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual:
 CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: 
CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual:
 CHANGED!
* build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing: CHANGED!
* build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic: 
CHANGED!
* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing: 
CHANGED!
* 
build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple:
 CHANGED!
* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp:
 CHANGED!
* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby: 
CHANGED!
* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp:
 CHANGED!
* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing: 
CHANGED!
* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic: 
CHANGED!
* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp:
 CHANGED!
* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: CHANGED!
* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic: 
CHANGED!
* 
build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level:
 CHANGED!
* 
build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level:
 CHANGED!
* 
build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple:
 CHANGED!
* build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic: 
CHANGED!
* build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic: 
CHANGED!
* build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing: 
CHANGED!
*

[gem5-dev] Change in gem5/gem5[master]: sim-se: remove /sys from special paths

[gem5-dev] AMD GCN - Trace Generation and Replay

[gem5-dev] Change in gem5/gem5[master]: config, sim-se: bugfix for 54c77aa0

[gem5-dev] Change in gem5/gem5[master]: configs: Fix FileSystemConfig import

[gem5-dev] Change in gem5/gem5[master]: tests: Fix import scope of test

[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Fix MOESI_CMP_directory blocked line handling

[gem5-dev] Cron /z/m5/regression/do-regression quick

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