[gem5-dev] Change in gem5/gem5[master]: arch, base, dev, sim: Remove now unnecessary casts from PortProxy met...
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18572 )
Change subject: arch, base, dev, sim: Remove now unnecessary casts from
PortProxy methods.
..
arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods.
Change-Id: Ia73b2d86a10d02fa09c924a4571477bb5f200eb7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18572
Tested-by: kokoro
Reviewed-by: Andreas Sandberg
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
---
M src/arch/alpha/linux/system.cc
M src/arch/alpha/process.cc
M src/arch/alpha/system.cc
M src/arch/arm/linux/process.cc
M src/arch/arm/process.cc
M src/arch/arm/semihosting.cc
M src/arch/generic/linux/threadinfo.hh
M src/arch/mips/process.cc
M src/arch/power/process.cc
M src/arch/sparc/process.cc
M src/arch/x86/bios/e820.cc
M src/arch/x86/bios/intelmp.cc
M src/arch/x86/bios/smbios.cc
M src/arch/x86/linux/system.cc
M src/arch/x86/process.cc
M src/arch/x86/pseudo_inst.cc
M src/arch/x86/system.cc
M src/base/loader/hex_file.cc
M src/base/remote_gdb.cc
M src/dev/alpha/tsunami_pchip.cc
M src/dev/arm/gic_v3_redistributor.cc
M src/dev/virtio/base.cc
M src/dev/virtio/base.hh
M src/sim/process_impl.hh
M src/sim/syscall_emul.hh
25 files changed, 111 insertions(+), 132 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/alpha/linux/system.cc b/src/arch/alpha/linux/system.cc
index 950b773..d963d29 100644
--- a/src/arch/alpha/linux/system.cc
+++ b/src/arch/alpha/linux/system.cc
@@ -90,8 +90,8 @@
* kernel arguments directly into the kernel's memory.
*/
virtProxy.writeBlob(CommandLine(),
-(uint8_t*)params()->boot_osflags.c_str(),
-params()->boot_osflags.length()+1);
+params()->boot_osflags.c_str(),
+params()->boot_osflags.length() + 1);
/**
* find the address of the est_cycle_freq variable and insert it
diff --git a/src/arch/alpha/process.cc b/src/arch/alpha/process.cc
index a7822a3..83c4c26 100644
--- a/src/arch/alpha/process.cc
+++ b/src/arch/alpha/process.cc
@@ -162,7 +162,7 @@
else
panic("Unknown int size");
-initVirtMem.writeBlob(memState->getStackMin(), (uint8_t*),
intSize);
+initVirtMem.writeBlob(memState->getStackMin(), , intSize);
copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
diff --git a/src/arch/alpha/system.cc b/src/arch/alpha/system.cc
index 3029429..b72821e 100644
--- a/src/arch/alpha/system.cc
+++ b/src/arch/alpha/system.cc
@@ -119,7 +119,7 @@
* others do.)
*/
if (consoleSymtab->findAddress("env_booted_osflags", addr)) {
-virtProxy.writeBlob(addr, (uint8_t*)params()->boot_osflags.c_str(),
+virtProxy.writeBlob(addr, params()->boot_osflags.c_str(),
strlen(params()->boot_osflags.c_str()));
}
diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc
index 1bb7548..25bccb6 100644
--- a/src/arch/arm/linux/process.cc
+++ b/src/arch/arm/linux/process.cc
@@ -148,7 +148,7 @@
uint32_t tlsPtr = process->getSyscallArg(tc, index);
tc->getMemProxy().writeBlob(ArmLinuxProcess32::commPage + 0x0ff0,
- (uint8_t *), sizeof(tlsPtr));
+, sizeof(tlsPtr));
tc->setMiscReg(MISCREG_TPIDRURO,tlsPtr);
return 0;
}
diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index baa861f..8e3cfd9 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -415,8 +415,7 @@
//Write out the sentry void *
IntType sentry_NULL = 0;
-initVirtMem.writeBlob(sentry_base,
-(uint8_t*)_NULL, sentry_size);
+initVirtMem.writeBlob(sentry_base, _NULL, sentry_size);
//Fix up the aux vectors which point to other data
for (int i = auxv.size() - 1; i >= 0; i--) {
@@ -446,7 +445,7 @@
copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
-initVirtMem.writeBlob(argc_base, (uint8_t*), intSize);
+initVirtMem.writeBlob(argc_base, , intSize);
ThreadContext *tc = system->getThreadContext(contextIds[0]);
//Set the stack pointer register
diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index 2b769ef..e04f419 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -272,7 +272,7 @@
std::vector buf(len + 1);
buf[len] = '\0';
-physProxy(tc).readBlob(ptr, (uint8_t *)buf.data(), len);
+physProxy(tc).readBlob(ptr, buf.data(), len);
return std::string(buf.data());
}
@@ -479,8 +479,7 @@
[gem5-dev] Change in gem5/gem5[master]: mem: Use a const T & in write<> to avoid an unnecessary copy.
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18573 )
Change subject: mem: Use a const T & in write<> to avoid an unnecessary
copy.
..
mem: Use a const T & in write<> to avoid an unnecessary copy.
If the type T is complex/large, the it makes sense to access it in place
and not copy it and then not modify it.
Change-Id: Idd24be4fbba636375637ff72b1ba5ee32eb76215
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18573
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
---
M src/mem/port_proxy.hh
1 file changed, 2 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/port_proxy.hh b/src/mem/port_proxy.hh
index 096f826..469273f 100644
--- a/src/mem/port_proxy.hh
+++ b/src/mem/port_proxy.hh
@@ -195,7 +195,7 @@
* Write object T to address. Writes sizeof(T) bytes.
*/
template
-void write(Addr address, T data) const;
+void write(Addr address, const T ) const;
/**
* Read sizeof(T) bytes from address and return as object T.
@@ -256,7 +256,7 @@
template
void
-PortProxy::write(Addr address, T data) const
+PortProxy::write(Addr address, const T ) const
{
writeBlob(address, , sizeof(T));
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Idd24be4fbba636375637ff72b1ba5ee32eb76215
Gerrit-Change-Number: 18573
Gerrit-PatchSet: 5
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: mem: Add a readString method to the PortProxy which takes a char *.
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18574 )
Change subject: mem: Add a readString method to the PortProxy which takes a
char *.
..
mem: Add a readString method to the PortProxy which takes a char *.
This version takes a char * instead of an std::string &, and a maximum
length to fill in like strncpy. This is intended to be a replacement
for the CopyStringOut function.
Change-Id: Ib661924a3fa7e05761d572ffecbe2c0cc8659d48
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18574
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
Reviewed-by: Brandon Potter
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
---
M src/mem/port_proxy.cc
M src/mem/port_proxy.hh
2 files changed, 34 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Brandon Potter: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/port_proxy.cc b/src/mem/port_proxy.cc
index f56bfeb..60f79e3 100644
--- a/src/mem/port_proxy.cc
+++ b/src/mem/port_proxy.cc
@@ -110,3 +110,18 @@
str += c;
}
}
+
+bool
+PortProxy::tryReadString(char *str, Addr addr, size_t maxlen) const
+{
+assert(maxlen);
+while (maxlen--) {
+if (!tryReadBlob(addr++, str, 1))
+return false;
+if (!*str++)
+return true;
+}
+// We ran out of room, so back up and add a terminator.
+*--str = '\0';
+return true;
+}
diff --git a/src/mem/port_proxy.hh b/src/mem/port_proxy.hh
index 469273f..61a2071 100644
--- a/src/mem/port_proxy.hh
+++ b/src/mem/port_proxy.hh
@@ -59,6 +59,8 @@
#ifndef __MEM_PORT_PROXY_HH__
#define __MEM_PORT_PROXY_HH__
+#include
+
#include "mem/port.hh"
#include "sim/byteswap.hh"
@@ -242,6 +244,23 @@
if (!tryReadString(str, addr))
fatal("readString(%#x, ...) failed", addr);
}
+
+/**
+ * Reads the string at guest address addr into the char * str, reading
up
+ * to maxlen characters. The last character read is always a nul
+ * terminator. Returns true on success and false on failure.
+ */
+bool tryReadString(char *str, Addr addr, size_t maxlen) const;
+
+/**
+ * Same as tryReadString, but insists on success.
+ */
+void
+readString(char *str, Addr addr, size_t maxlen) const
+{
+if (!tryReadString(str, addr, maxlen))
+fatal("readString(%#x, ...) failed", addr);
+}
};
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ib661924a3fa7e05761d572ffecbe2c0cc8659d48
Gerrit-Change-Number: 18574
Gerrit-PatchSet: 6
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Brandon Potter
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: mem, arm: Replace the pointer type in PortProxy with void *.
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18571 )
Change subject: mem, arm: Replace the pointer type in PortProxy with void *.
..
mem, arm: Replace the pointer type in PortProxy with void *.
The void * type is for pointers which point to an unknown type. We
should use that when handling anonymous buffers in the PortProxy
functions, instead of uint8_t * which points to bytes.
Importantly, C/C++ doesn't require you to do any casting to turn an
arbitrary pointer type into a void *. This will get rid of lots of
tedious, verbose casting throughout the code base.
Change-Id: Id1adecc283c866d8e24524efd64f37b079088bd9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18571
Tested-by: kokoro
Reviewed-by: Andreas Sandberg
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
---
M src/mem/fs_translating_port_proxy.cc
M src/mem/fs_translating_port_proxy.hh
M src/mem/port_proxy.cc
M src/mem/port_proxy.hh
M src/mem/se_translating_port_proxy.cc
M src/mem/se_translating_port_proxy.hh
M src/mem/secure_port_proxy.cc
M src/mem/secure_port_proxy.hh
8 files changed, 35 insertions(+), 34 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/fs_translating_port_proxy.cc
b/src/mem/fs_translating_port_proxy.cc
index a21d328..2e17cbf 100644
--- a/src/mem/fs_translating_port_proxy.cc
+++ b/src/mem/fs_translating_port_proxy.cc
@@ -67,7 +67,7 @@
}
bool
-FSTranslatingPortProxy::tryReadBlob(Addr addr, uint8_t *p, int size) const
+FSTranslatingPortProxy::tryReadBlob(Addr addr, void *p, int size) const
{
Addr paddr;
for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done();
@@ -79,14 +79,14 @@
paddr = TheISA::vtophys(gen.addr());
PortProxy::readBlobPhys(paddr, 0, p, gen.size());
-p += gen.size();
+p = static_cast(p) + gen.size();
}
return true;
}
bool
FSTranslatingPortProxy::tryWriteBlob(
-Addr addr, const uint8_t *p, int size) const
+Addr addr, const void *p, int size) const
{
Addr paddr;
for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done();
@@ -98,7 +98,7 @@
paddr = TheISA::vtophys(gen.addr());
PortProxy::writeBlobPhys(paddr, 0, p, gen.size());
-p += gen.size();
+p = static_cast(p) + gen.size();
}
return true;
}
diff --git a/src/mem/fs_translating_port_proxy.hh
b/src/mem/fs_translating_port_proxy.hh
index 5ae8700..78adf1a 100644
--- a/src/mem/fs_translating_port_proxy.hh
+++ b/src/mem/fs_translating_port_proxy.hh
@@ -85,11 +85,11 @@
/** Version of tryReadblob that translates virt->phys and deals
* with page boundries. */
-bool tryReadBlob(Addr addr, uint8_t *p, int size) const override;
+bool tryReadBlob(Addr addr, void *p, int size) const override;
/** Version of tryWriteBlob that translates virt->phys and deals
* with page boundries. */
-bool tryWriteBlob(Addr addr, const uint8_t *p, int size) const
override;
+bool tryWriteBlob(Addr addr, const void *p, int size) const override;
/**
* Fill size bytes starting at addr with byte value val.
diff --git a/src/mem/port_proxy.cc b/src/mem/port_proxy.cc
index 97eb67e..f56bfeb 100644
--- a/src/mem/port_proxy.cc
+++ b/src/mem/port_proxy.cc
@@ -43,7 +43,7 @@
void
PortProxy::readBlobPhys(Addr addr, Request::Flags flags,
-uint8_t *p, int size) const
+void *p, int size) const
{
for (ChunkGenerator gen(addr, size, _cacheLineSize); !gen.done();
gen.next()) {
@@ -52,15 +52,15 @@
gen.addr(), gen.size(), flags, Request::funcMasterId);
Packet pkt(req, MemCmd::ReadReq);
-pkt.dataStatic(p);
+pkt.dataStatic(static_cast(p));
_port.sendFunctional();
-p += gen.size();
+p = static_cast(p) + gen.size();
}
}
void
PortProxy::writeBlobPhys(Addr addr, Request::Flags flags,
- const uint8_t *p, int size) const
+ const void *p, int size) const
{
for (ChunkGenerator gen(addr, size, _cacheLineSize); !gen.done();
gen.next()) {
@@ -69,9 +69,9 @@
gen.addr(), gen.size(), flags, Request::funcMasterId);
Packet pkt(req, MemCmd::WriteReq);
-pkt.dataStaticConst(p);
+pkt.dataStaticConst(static_cast(p));
_port.sendFunctional();
-p += gen.size();
+p = static_cast(p) + gen.size();
}
}
@@ -92,7 +92,7 @@
PortProxy::tryWriteString(Addr addr, const char *str) const
{
do {
-if (!tryWriteBlob(addr++, (uint8_t *)str, 1))
+if (!tryWriteBlob(addr++, str, 1))
return false;
} while (*str++);
[gem5-dev] Change in gem5/gem5[master]: mem, arm: Move some helper methods into the base PortProxy class.
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18570 )
Change subject: mem, arm: Move some helper methods into the base PortProxy
class.
..
mem, arm: Move some helper methods into the base PortProxy class.
These were originally in the SETranslatingPortProxy class, but they're
not specific to SE mode in any way and are an unnecessary divergence
between the SE and FS mode translating port proxies.
Change-Id: I8cb77531cc287bd15b2386410ffa7b43cdfa67d0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18570
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
---
M src/mem/fs_translating_port_proxy.cc
M src/mem/fs_translating_port_proxy.hh
M src/mem/port_proxy.cc
M src/mem/port_proxy.hh
M src/mem/se_translating_port_proxy.cc
M src/mem/se_translating_port_proxy.hh
M src/mem/secure_port_proxy.cc
M src/mem/secure_port_proxy.hh
8 files changed, 159 insertions(+), 145 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/fs_translating_port_proxy.cc
b/src/mem/fs_translating_port_proxy.cc
index 15ad823..a21d328 100644
--- a/src/mem/fs_translating_port_proxy.cc
+++ b/src/mem/fs_translating_port_proxy.cc
@@ -66,12 +66,8 @@
{
}
-FSTranslatingPortProxy::~FSTranslatingPortProxy()
-{
-}
-
-void
-FSTranslatingPortProxy::readBlob(Addr addr, uint8_t *p, int size) const
+bool
+FSTranslatingPortProxy::tryReadBlob(Addr addr, uint8_t *p, int size) const
{
Addr paddr;
for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done();
@@ -85,10 +81,12 @@
PortProxy::readBlobPhys(paddr, 0, p, gen.size());
p += gen.size();
}
+return true;
}
-void
-FSTranslatingPortProxy::writeBlob(Addr addr, const uint8_t *p, int size)
const
+bool
+FSTranslatingPortProxy::tryWriteBlob(
+Addr addr, const uint8_t *p, int size) const
{
Addr paddr;
for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done();
@@ -102,10 +100,11 @@
PortProxy::writeBlobPhys(paddr, 0, p, gen.size());
p += gen.size();
}
+return true;
}
-void
-FSTranslatingPortProxy::memsetBlob(Addr address, uint8_t v, int size) const
+bool
+FSTranslatingPortProxy::tryMemsetBlob(Addr address, uint8_t v, int size)
const
{
Addr paddr;
for (ChunkGenerator gen(address, size, TheISA::PageBytes); !gen.done();
@@ -118,6 +117,7 @@
PortProxy::memsetBlobPhys(paddr, 0, v, gen.size());
}
+return true;
}
void
diff --git a/src/mem/fs_translating_port_proxy.hh
b/src/mem/fs_translating_port_proxy.hh
index d4b4eb5..5ae8700 100644
--- a/src/mem/fs_translating_port_proxy.hh
+++ b/src/mem/fs_translating_port_proxy.hh
@@ -81,20 +81,20 @@
FSTranslatingPortProxy(MasterPort , unsigned int cacheLineSize);
-~FSTranslatingPortProxy();
+~FSTranslatingPortProxy() {}
-/** Version of readblob that translates virt->phys and deals
+/** Version of tryReadblob that translates virt->phys and deals
* with page boundries. */
-void readBlob(Addr addr, uint8_t *p, int size) const override;
+bool tryReadBlob(Addr addr, uint8_t *p, int size) const override;
-/** Version of writeBlob that translates virt->phys and deals
+/** Version of tryWriteBlob that translates virt->phys and deals
* with page boundries. */
-void writeBlob(Addr addr, const uint8_t *p, int size) const override;
+bool tryWriteBlob(Addr addr, const uint8_t *p, int size) const
override;
/**
* Fill size bytes starting at addr with byte value val.
*/
-void memsetBlob(Addr address, uint8_t v, int size) const override;
+bool tryMemsetBlob(Addr address, uint8_t v, int size) const override;
};
void CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen);
diff --git a/src/mem/port_proxy.cc b/src/mem/port_proxy.cc
index f13bcbe..97eb67e 100644
--- a/src/mem/port_proxy.cc
+++ b/src/mem/port_proxy.cc
@@ -87,3 +87,26 @@
delete [] buf;
}
+
+bool
+PortProxy::tryWriteString(Addr addr, const char *str) const
+{
+do {
+if (!tryWriteBlob(addr++, (uint8_t *)str, 1))
+return false;
+} while (*str++);
+return true;
+}
+
+bool
+PortProxy::tryReadString(std::string , Addr addr) const
+{
+while (true) {
+uint8_t c;
+if (!tryReadBlob(addr++, , 1))
+return false;
+if (!c)
+return true;
+str += c;
+}
+}
diff --git a/src/mem/port_proxy.hh b/src/mem/port_proxy.hh
index bed448d..dcc1905 100644
--- a/src/mem/port_proxy.hh
+++ b/src/mem/port_proxy.hh
@@ -92,32 +92,9 @@
{}
virtual ~PortProxy() { }
-/**
- * Read size bytes memory at address and store in p.
- */
-virtual void
-readBlob(Addr addr, uint8_t* p, int size) const
-{
-
[gem5-dev] Change in gem5/gem5[master]: arm, mem: Move the SecurePortProxy subclass into it's own file.
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18569 )
Change subject: arm, mem: Move the SecurePortProxy subclass into it's own
file.
..
arm, mem: Move the SecurePortProxy subclass into it's own file.
The idea of a "secure" memory area/access is specific to ARM and
shouldn't be in the common mem directory, although it's built in to the
generic memory protocol at this point.
Regardless, it should minimially be in its own file like the virtual
and physical port proxy classes are.
Change-Id: I140d4566ee2deded784adb04bcf6f11755a85c0c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18569
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/arm/semihosting.cc
M src/mem/SConscript
M src/mem/port_proxy.cc
M src/mem/port_proxy.hh
A src/mem/secure_port_proxy.cc
A src/mem/secure_port_proxy.hh
6 files changed, 141 insertions(+), 37 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index 3f9c095..2b769ef 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -47,7 +47,7 @@
#include "debug/Semihosting.hh"
#include "dev/serial/serial.hh"
#include "mem/physical.hh"
-#include "mem/port_proxy.hh"
+#include "mem/secure_port_proxy.hh"
#include "params/ArmSemihosting.hh"
#include "sim/byteswap.hh"
#include "sim/sim_exit.hh"
diff --git a/src/mem/SConscript b/src/mem/SConscript
index b9d5672..95d8654 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -74,6 +74,7 @@
Source('packet_queue.cc')
Source('port_proxy.cc')
Source('physical.cc')
+Source('secure_port_proxy.cc')
Source('simple_mem.cc')
Source('snoop_filter.cc')
Source('stack_dist_calc.cc')
diff --git a/src/mem/port_proxy.cc b/src/mem/port_proxy.cc
index a36e66a..f13bcbe 100644
--- a/src/mem/port_proxy.cc
+++ b/src/mem/port_proxy.cc
@@ -87,22 +87,3 @@
delete [] buf;
}
-
-
-void
-SecurePortProxy::readBlob(Addr addr, uint8_t *p, int size) const
-{
-readBlobPhys(addr, Request::SECURE, p, size);
-}
-
-void
-SecurePortProxy::writeBlob(Addr addr, const uint8_t *p, int size) const
-{
-writeBlobPhys(addr, Request::SECURE, p, size);
-}
-
-void
-SecurePortProxy::memsetBlob(Addr addr, uint8_t v, int size) const
-{
-memsetBlobPhys(addr, Request::SECURE, v, size);
-}
diff --git a/src/mem/port_proxy.hh b/src/mem/port_proxy.hh
index e48942e..bed448d 100644
--- a/src/mem/port_proxy.hh
+++ b/src/mem/port_proxy.hh
@@ -165,23 +165,6 @@
};
-/**
- * This object is a proxy for a structural port, to be used for debug
- * accesses to secure memory.
- *
- * The addresses are interpreted as physical addresses to secure memory.
- */
-class SecurePortProxy : public PortProxy
-{
- public:
-SecurePortProxy(MasterPort , unsigned int cache_line_size)
-: PortProxy(port, cache_line_size) {}
-
-void readBlob(Addr addr, uint8_t *p, int size) const override;
-void writeBlob(Addr addr, const uint8_t *p, int size) const override;
-void memsetBlob(Addr addr, uint8_t val, int size) const override;
-};
-
template
T
PortProxy::read(Addr address) const
diff --git a/src/mem/secure_port_proxy.cc b/src/mem/secure_port_proxy.cc
new file mode 100644
index 000..7bf23d7
--- /dev/null
+++ b/src/mem/secure_port_proxy.cc
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2012, 2018 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+
[gem5-dev] Change in gem5/gem5[master]: arch, base, sim: Replace Copy(String)?(In|Out) with equivalent code.
Hello Andreas Sandberg, Brandon Potter, Jason Lowe-Power, Nikos Nikoleris, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/18575 to look at the new patch set (#4). Change subject: arch, base, sim: Replace Copy(String)?(In|Out) with equivalent code. .. arch, base, sim: Replace Copy(String)?(In|Out) with equivalent code. This expands those functions into code which extracts the virt proxy and then uses the appropriate method on it. This has two benefits. First, the Copy* functions where mostly redundant wrappers around the methods the proxy port already had. Second, using them forced a particular port which might not actually be what the user wanted. Change-Id: I62084631dd080061e3c74997125164f40da2d77c --- M src/arch/alpha/stacktrace.cc M src/arch/arm/stacktrace.cc M src/arch/generic/linux/threadinfo.hh M src/arch/mips/stacktrace.cc M src/arch/x86/stacktrace.cc M src/base/cp_annotate.cc M src/sim/arguments.hh M src/sim/pseudo_inst.cc 8 files changed, 48 insertions(+), 72 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18575 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I62084631dd080061e3c74997125164f40da2d77c Gerrit-Change-Number: 18575 Gerrit-PatchSet: 4 Gerrit-Owner: Gabe Black Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Brandon Potter Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arm, mem: Move the SecurePortProxy subclass into it's own file.
Hello Andreas Sandberg, Brandon Potter, kokoro, Jason Lowe-Power, Nikos Nikoleris, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/18569 to look at the new patch set (#4). Change subject: arm, mem: Move the SecurePortProxy subclass into it's own file. .. arm, mem: Move the SecurePortProxy subclass into it's own file. The idea of a "secure" memory area/access is specific to ARM and shouldn't be in the common mem directory, although it's built in to the generic memory protocol at this point. Regardless, it should minimially be in its own file like the virtual and physical port proxy classes are. Change-Id: I140d4566ee2deded784adb04bcf6f11755a85c0c --- M src/arch/arm/semihosting.cc M src/mem/SConscript M src/mem/port_proxy.cc M src/mem/port_proxy.hh A src/mem/secure_port_proxy.cc A src/mem/secure_port_proxy.hh 6 files changed, 141 insertions(+), 37 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18569 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I140d4566ee2deded784adb04bcf6f11755a85c0c Gerrit-Change-Number: 18569 Gerrit-PatchSet: 4 Gerrit-Owner: Gabe Black Gerrit-Assignee: Nikos Nikoleris Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Brandon Potter Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Enable set size increase
John Alsop has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/18968
Change subject: mem-ruby: Enable set size increase
..
mem-ruby: Enable set size increase
When SETSIZE_128 or SETSIZE_256 environment variable is set,
use size 128 or 256 bitset for Set class, respectively.
Necessary for configs which require >64 instances of a given
machine type. This can be set in the build_opts file, e.g.
by adding the following line:
SETSIZE_128 = True
Change-Id: I314a3cadca8ce975fcf4a60d9022494751688e88
---
M SConstruct
M src/mem/ruby/common/SConscript
M src/mem/ruby/common/Set.hh
3 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/SConstruct b/SConstruct
index 53b8c9d..2d0556b 100755
--- a/SConstruct
+++ b/SConstruct
@@ -1013,14 +1013,19 @@
EnumVariable('PROTOCOL', 'Coherence protocol for Ruby', 'None',
all_protocols),
EnumVariable('BACKTRACE_IMPL', 'Post-mortem dump implementation',
- backtrace_impls[-1], backtrace_impls)
+ backtrace_impls[-1], backtrace_impls),
+BoolVariable('SETSIZE_128', 'Use a larger set size (128 instead of
64)',
+ False),
+BoolVariable('SETSIZE_256', 'Use a larger set size (256 instead of
64)',
+ False),
)
# These variables get exported to #defines in config/*.hh (see
src/SConscript).
export_vars +=
['USE_FENV', 'SS_COMPATIBLE_FP', 'TARGET_ISA', 'TARGET_GPU_ISA',
'CP_ANNOTATE', 'USE_POSIX_CLOCK', 'USE_KVM', 'USE_TUNTAP',
'PROTOCOL', 'HAVE_PROTOBUF', 'HAVE_VALGRIND',
-'HAVE_PERF_ATTR_EXCLUDE_HOST', 'USE_PNG']
+'HAVE_PERF_ATTR_EXCLUDE_HOST', 'USE_PNG', 'SETSIZE_128',
+'SETSIZE_256']
###
#
diff --git a/src/mem/ruby/common/SConscript b/src/mem/ruby/common/SConscript
index a19268c..95c5f51 100644
--- a/src/mem/ruby/common/SConscript
+++ b/src/mem/ruby/common/SConscript
@@ -33,6 +33,11 @@
if env['PROTOCOL'] == 'None':
Return()
+if env['SETSIZE_128'] == True:
+env.Append(CPPDEFINES=['SETSIZE_128'])
+elif env['SETSIZE_256'] == True:
+env.Append(CPPDEFINES=['SETSIZE_256'])
+
Source('Address.cc')
Source('BoolVec.cc')
Source('Consumer.cc')
diff --git a/src/mem/ruby/common/Set.hh b/src/mem/ruby/common/Set.hh
index cb01c96..5f93b9b 100644
--- a/src/mem/ruby/common/Set.hh
+++ b/src/mem/ruby/common/Set.hh
@@ -39,8 +39,15 @@
#include "base/logging.hh"
#include "mem/ruby/common/TypeDefines.hh"
-// Change for systems with more than 64 controllers of a particular type.
+// Make sure SETSIZE_128 is defined if more than 64 controllers of any
+// type are needed
+#ifdef SETSIZE_128
+const int NUMBER_BITS_PER_SET = 128;
+#elif defined SETSIZE_256
+const int NUMBER_BITS_PER_SET = 256;
+#else
const int NUMBER_BITS_PER_SET = 64;
+#endif
class Set
{
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18968
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I314a3cadca8ce975fcf4a60d9022494751688e88
Gerrit-Change-Number: 18968
Gerrit-PatchSet: 1
Gerrit-Owner: John Alsop
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: mem: Parameterize coherent xbar sanity checks
Tiago Mück has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18789 )
Change subject: mem: Parameterize coherent xbar sanity checks
..
mem: Parameterize coherent xbar sanity checks
Parameters can be used to change coherent xbar limits for the routing
table and outstanding snoops. We need the ability to tweak these values
as the current defaults may be violated in simulations with large core
counts.
Change-Id: Idb64b8c105683d02d8beba5bce13b815181ba824
Signed-off-by: Tiago Muck
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18789
Reviewed-by: Daniel Carvalho
Reviewed-by: Nikos Nikoleris
Maintainer: Nikos Nikoleris
Tested-by: kokoro
---
M src/mem/XBar.py
M src/mem/coherent_xbar.cc
M src/mem/coherent_xbar.hh
3 files changed, 31 insertions(+), 9 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/XBar.py b/src/mem/XBar.py
index 976a290..dab961f 100644
--- a/src/mem/XBar.py
+++ b/src/mem/XBar.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012, 2015, 2017 ARM Limited
+# Copyright (c) 2012, 2015, 2017, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -101,6 +101,12 @@
# An optional snoop filter
snoop_filter = Param.SnoopFilter(NULL, "Selected snoop filter")
+# Maximum number of outstanding snoop requests for sanity checks
+max_outstanding_snoops = Param.Int(512, "Max. outstanding snoops
allowed")
+
+# Maximum routing table size for sanity checks
+max_routing_table_size = Param.Int(512, "Max. routing table size")
+
# Determine how this crossbar handles packets where caches have
# already committed to responding, by establishing if the crossbar
# is the point of coherency or not.
diff --git a/src/mem/coherent_xbar.cc b/src/mem/coherent_xbar.cc
index 839d95b..74c93be 100644
--- a/src/mem/coherent_xbar.cc
+++ b/src/mem/coherent_xbar.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2018 ARM Limited
+ * Copyright (c) 2011-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -59,6 +59,8 @@
CoherentXBar::CoherentXBar(const CoherentXBarParams *p)
: BaseXBar(p), system(p->system), snoopFilter(p->snoop_filter),
snoopResponseLatency(p->snoop_response_latency),
+ maxOutstandingSnoopCheck(p->max_outstanding_snoops),
+ maxRoutingTableSizeCheck(p->max_routing_table_size),
pointOfCoherency(p->point_of_coherency),
pointOfUnification(p->point_of_unification)
{
@@ -325,8 +327,9 @@
outstandingSnoop.insert(pkt->req);
// basic sanity check on the outstanding snoops
-panic_if(outstandingSnoop.size() > 512,
- "Outstanding snoop requests exceeded 512\n");
+panic_if(outstandingSnoop.size() >
maxOutstandingSnoopCheck,
+ "%s: Outstanding snoop requests exceeded %d\n",
+ name(), maxOutstandingSnoopCheck);
}
// remember where to route the normal response to
@@ -334,8 +337,9 @@
assert(routeTo.find(pkt->req) == routeTo.end());
routeTo[pkt->req] = slave_port_id;
-panic_if(routeTo.size() > 512,
- "Routing table exceeds 512 packets\n");
+panic_if(routeTo.size() > maxRoutingTableSizeCheck,
+ "%s: Routing table exceeds %d packets\n",
+ name(), maxRoutingTableSizeCheck);
}
// update the layer state and schedule an idle event
@@ -401,8 +405,9 @@
assert(routeTo.find(pkt->req) == routeTo.end());
routeTo[pkt->req] = slave_port_id;
-panic_if(routeTo.size() > 512,
- "Routing table exceeds 512 packets\n");
+panic_if(routeTo.size() > maxRoutingTableSizeCheck,
+ "%s: Routing table exceeds %d packets\n",
+ name(), maxRoutingTableSizeCheck);
}
}
}
diff --git a/src/mem/coherent_xbar.hh b/src/mem/coherent_xbar.hh
index ff28cb7..386b479 100644
--- a/src/mem/coherent_xbar.hh
+++ b/src/mem/coherent_xbar.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2015, 2017 ARM Limited
+ * Copyright (c) 2011-2015, 2017, 2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -278,8 +278,19 @@
* broadcast needed for probes. NULL denotes an absent filter. */
SnoopFilter *snoopFilter;
+/** Cycles of snoop response latency.*/
const Cycles snoopResponseLatency;
+
+/** Maximum number of outstading snoops sanity
[gem5-dev] Change in gem5/gem5[master]: mem: Snoop filter support for large systems
Tiago Mück has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18791 )
Change subject: mem: Snoop filter support for large systems
..
mem: Snoop filter support for large systems
Changed SnoopMask to use std::bitset instead of uint64 so we can simulate
larger systems without having to workaround limitations on the number of
ports. No noticeable performance drop was observed after this change.
The size of the bitset is currently set to 256 which should fit most
needs.
Change-Id: I216882300500e2dcb789889756e73a1033271621
Signed-off-by: Tiago Muck
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18791
Reviewed-by: Daniel Carvalho
Reviewed-by: Nikos Nikoleris
Maintainer: Nikos Nikoleris
Tested-by: kokoro
---
M src/mem/snoop_filter.cc
M src/mem/snoop_filter.hh
2 files changed, 34 insertions(+), 28 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/snoop_filter.cc b/src/mem/snoop_filter.cc
index 3e1dae6..8168c3d 100644
--- a/src/mem/snoop_filter.cc
+++ b/src/mem/snoop_filter.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2017 ARM Limited
+ * Copyright (c) 2013-2017,2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -49,11 +49,13 @@
#include "debug/SnoopFilter.hh"
#include "sim/system.hh"
+const int SnoopFilter::SNOOP_MASK_SIZE;
+
void
SnoopFilter::eraseIfNullEntry(SnoopFilterCache::iterator& sf_it)
{
SnoopItem& sf_item = sf_it->second;
-if (!(sf_item.requested | sf_item.holder)) {
+if ((sf_item.requested | sf_item.holder).none()) {
cachedLocations.erase(sf_it);
DPRINTF(SnoopFilter, "%s: Removed SF entry.\n",
__func__);
@@ -96,8 +98,7 @@
totRequests++;
if (is_hit) {
-// Single bit set -> value is a power of two
-if (isPow2(interested))
+if (interested.count() == 1)
hitSingleRequests++;
else
hitMultiRequests++;
@@ -114,8 +115,9 @@
if (cpkt->needsResponse()) {
if (!cpkt->cacheResponding()) {
// Max one request per address per port
-panic_if(sf_item.requested & req_port, "double request :( " \
- "SF value %x.%x\n", sf_item.requested,
sf_item.holder);
+panic_if((sf_item.requested & req_port).any(),
+ "double request :( SF value %x.%x\n",
+ sf_item.requested, sf_item.holder);
// Mark in-flight requests to distinguish later on
sf_item.requested |= req_port;
@@ -126,7 +128,8 @@
// to the CPU, already -> the response will not be seen by this
// filter -> we do not need to keep the in-flight request, but
make
// sure that we know that that cluster has a copy
-panic_if(!(sf_item.holder & req_port), "Need to hold the
value!");
+panic_if((sf_item.holder & req_port).none(),
+ "Need to hold the value!");
DPRINTF(SnoopFilter,
"%s: not marking request. SF value %x.%x\n",
__func__, sf_item.requested, sf_item.holder);
@@ -134,7 +137,7 @@
} else { // if (!cpkt->needsResponse())
assert(cpkt->isEviction());
// make sure that the sender actually had the line
-panic_if(!(sf_item.holder & req_port), "requester %x is not a " \
+panic_if((sf_item.holder & req_port).none(), "requester %x is not
a " \
"holder :( SF value %x.%x\n", req_port,
sf_item.requested, sf_item.holder);
// CleanEvicts and Writebacks -> the sender and all caches above
@@ -206,8 +209,8 @@
SnoopMask interested = (sf_item.holder | sf_item.requested);
totSnoops++;
-// Single bit set -> value is a power of two
-if (isPow2(interested))
+
+if (interested.count() == 1)
hitSingleSnoops++;
else
hitMultiSnoops++;
@@ -222,7 +225,7 @@
assert(cpkt->isWriteback() || cpkt->req->isUncacheable() ||
(cpkt->isInvalidate() == cpkt->needsWritable()) ||
cpkt->req->isCacheMaintenance());
-if (cpkt->isInvalidate() && !sf_item.requested) {
+if (cpkt->isInvalidate() && sf_item.requested.none()) {
// Early clear of the holder, if no other request is currently
going on
// @todo: This should possibly be updated even though we do not
filter
// upward snoops
@@ -266,11 +269,12 @@
__func__, sf_item.requested, sf_item.holder);
// The source should have the line
-panic_if(!(sf_item.holder & rsp_mask), "SF value %x.%x does not have "\
- "the line\n", sf_item.requested, sf_item.holder);
+
[gem5-dev] Change in gem5/gem5[master]: base: Add warn_if_once macro
Tiago Mück has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18420 )
Change subject: base: Add warn_if_once macro
..
base: Add warn_if_once macro
Change-Id: Ie68f3b07a35ed2e6b0eee20b3b34050542fcdc6c
Signed-off-by: Tiago Muck
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18420
Reviewed-by: Brandon Potter
Reviewed-by: Daniel Carvalho
Reviewed-by: Nikos Nikoleris
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/base/logging.hh
1 file changed, 7 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Brandon Potter: Looks good to me, approved
Nikos Nikoleris: Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/logging.hh b/src/base/logging.hh
index 1c504d2..7040037 100644
--- a/src/base/logging.hh
+++ b/src/base/logging.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, 2017 ARM Limited
+ * Copyright (c) 2014, 2017, 2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -231,6 +231,12 @@
warn(__VA_ARGS__); \
} while (0)
+#define warn_if_once(cond, ...) \
+do { \
+if ((cond)) \
+warn_once(__VA_ARGS__); \
+} while (0)
+
/**
* The chatty assert macro will function like a normal assert, but will
allow
* the specification of additional, helpful material to aid debugging why
the
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18420
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ie68f3b07a35ed2e6b0eee20b3b34050542fcdc6c
Gerrit-Change-Number: 18420
Gerrit-PatchSet: 2
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Brandon Potter
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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Re: [gem5-dev] Cron /z/m5/regression/do-regression --scratch all
Hi Bjoern, These tests are wildly out of date. I've been considering shutting them down since we started running CI tests on the review site. Now, every changeset must pass the CI tests before it can be merged. The only downside to killing these tests is that not all of them have been migrated to the CI service. We need help doing this :). Cheers, Jason On Mon, May 27, 2019 at 2:40 PM Bjoern A. Zeeb < bzeeb-li...@lists.zabbadoz.net> wrote: > On 27 May 2019, at 21:28, Cron Daemon wrote: > > > * > > build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3: > > FAILED! > > * > > build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual: > > FAILED! > > * > > > build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full: > > > FAILED! > > * > > build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: > > FAILED! > > * > > > build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer: > > > FAILED! > > * > > > build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level: > > > FAILED! > > * > > > build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory: > > > FAILED! > > * > > > build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token: > > > FAILED! > > * > > build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing: > > FAILED! > > * > > build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full: > > FAILED! > > * > > > build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: > > FAILED! > > * > > build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: > > FAILED! > > * > > build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: > > FAILED! > > * > > > build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: > > FAILED! > > * > > > build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby: > > > FAILED! > > * > > build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/o3-timing: > > FAILED! > > * > > > build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: > > FAILED! > > * > > > build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple: > > > CHANGED! > .. > .. > .. > .. is there any interest in actually getting things to pass again or > ..? > > I am mostly wondering, having watched this for a while now, in what > state the current repo is in, and if anything is supposed to work or if > the tests are out of date or ..? > > It doesn’t leave people with a lot of confidence and given there is no > updated stable branch anymore, you simply cannot afford keeping such a > state for long. > > > /bz > ___ > gem5-dev mailing list > gem5-dev@gem5.org > http://m5sim.org/mailman/listinfo/gem5-dev ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Cron /z/m5/regression/do-regression quick
* build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: FAILED! * build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer: FAILED! * build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level: FAILED! * build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory: FAILED! * build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token: FAILED! * build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/o3-timing: FAILED! * build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: CHANGED! * build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level: CHANGED! * build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-closepage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-openpage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing: CHANGED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp: CHANGED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp: CHANGED! * build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing: CHANGED! *
[gem5-dev] Cron /z/m5/regression/do-regression quick
* build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: FAILED! * build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer: FAILED! * build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level: FAILED! * build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory: FAILED! * build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token: FAILED! * build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: FAILED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: CHANGED! * build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-closepage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-openpage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic: CHANGED! * build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic: CHANGED! * build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic: CHANGED! * build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple: CHANGED! * build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing: CHANGED! * build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby: CHANGED! * build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level: CHANGED! * build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp: CHANGED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp: CHANGED! *
[gem5-dev] Change in gem5/gem5[master]: cpu: Remove assert causing issues with x86 Linux boot
Giacomo Gabrielli has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18910 )
Change subject: cpu: Remove assert causing issues with x86 Linux boot
..
cpu: Remove assert causing issues with x86 Linux boot
Change-Id: I5e0b189ced0dd59ac6dbbb2c498c068e132b9b93
Signed-off-by: Giacomo Gabrielli
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18910
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/cpu/simple/atomic.cc
1 file changed, 0 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index c5b0245..5fc1d69 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -541,7 +541,6 @@
{
if (req->isLockedRMW() && fault == NoFault) {
assert(byteEnable.empty());
-assert(locked && curr_frag_id == 0);
locked = false;
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18910
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I5e0b189ced0dd59ac6dbbb2c498c068e132b9b93
Gerrit-Change-Number: 18910
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Gabrielli
Gerrit-Reviewer: Anthony Gutierrez
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Gabrielli
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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