[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Remove assertion with incorrect assumption
Hello Tiago Mück, Nikos Nikoleris, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19708 to look at the new patch set (#2). Change subject: mem-ruby: Remove assertion with incorrect assumption .. mem-ruby: Remove assertion with incorrect assumption Current code assumes that only one cacheline would either be in RW. This is not true for GPU protocols, and may not be true for some CPU-only protocols with state violations. Change-Id: I70db4fbb4e80663551e8635307bb937a4db8dc63 --- M src/mem/ruby/system/RubySystem.cc 1 file changed, 4 insertions(+), 2 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19708 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I70db4fbb4e80663551e8635307bb937a4db8dc63 Gerrit-Change-Number: 19708 Gerrit-PatchSet: 2 Gerrit-Owner: Pouya Fotouhi Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: Tiago Mück Gerrit-CC: Jason Lowe-Power Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Cron /z/m5/regression/do-regression --scratch all
* build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full: FAILED! * build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3: FAILED! * build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual: FAILED! * build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: FAILED! * build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer: FAILED! * build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level: FAILED! * build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory: FAILED! * build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic: FAILED! * build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomic: FAILED! * build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3: FAILED! * build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full: FAILED! * build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing: FAILED! * build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor: FAILED! * build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual-ruby-MOESI_CMP_directory: FAILED! * build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-checkpoint: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-simple-timing-ruby-MOESI_CMP_directory: FAILED! * build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic: FAILED! * build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual: FAILED! * build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timing: FAILED! * build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing: FAILED! * build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual: FAILED! * build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing: FAILED! * build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3: FAILED! * build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker: FAILED! * build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic: FAILED! * build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing: FAILED! * build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual: FAILED! * build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing: FAILED! * build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing: FAILED! * build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3: FAILED! * build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic: FAILED! * build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual: FAILED! * build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual: FAILED! * build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual: FAILED! * build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-timing: FAILED! * build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-ruby-MOESI_CMP_directory: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic: FAILED! * build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-simple-timing-dual-ruby-MOESI_CMP_directory: FAILED! * build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-swit
[gem5-dev] Change in gem5/gem5[master]: mem-cache: mark block as dirty when handling SW prefetch
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/19688 )
Change subject: mem-cache: mark block as dirty when handling SW prefetch
..
mem-cache: mark block as dirty when handling SW prefetch
This addresses the issue described in
64687ee mem-cache: Mark block as dirty after a SWPrefetchEXResp.
Previous patch misses cases when the prefetch response is ReadExResp or
UpgradeResp. Also, marking the block as dirty in serviceMSHRTargets
instead of in handleFill covers cases when the prefetch is coalesced with
other requests.
Change-Id: I2b377fdd240eb0f09e720b6bb284dee6545925ce
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19688
Reviewed-by: Nikos Nikoleris
Reviewed-by: Daniel Carvalho
Maintainer: Nikos Nikoleris
Tested-by: kokoro
---
M src/mem/cache/base.cc
M src/mem/cache/cache.cc
2 files changed, 26 insertions(+), 24 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 082650c..0de7f21 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -1409,30 +1409,6 @@
chatty_assert(!isReadOnly, "Should never see dirty snoop
response "
"in read-only cache %s\n", name());
-} else if (pkt->cmd.isSWPrefetch() && pkt->needsWritable()) {
-// All other copies of the block were invalidated and we
-// have an exclusive copy.
-
-// The coherence protocol assumes that if we fetched an
-// exclusive copy of the block, we have the intention to
-// modify it. Therefore the MSHR for the PrefetchExReq has
-// been the point of ordering and this cache has commited
-// to respond to snoops for the block.
-//
-// In most cases this is true anyway - a PrefetchExReq
-// will be followed by a WriteReq. However, if that
-// doesn't happen, the block is not marked as dirty and
-// the cache doesn't respond to snoops that has committed
-// to do so.
-//
-// To avoid deadlocks in cases where there is a snoop
-// between the PrefetchExReq and the expected WriteReq, we
-// proactively mark the block as Dirty.
-
-blk->status |= BlkDirty;
-
-panic_if(!isReadOnly, "Prefetch exclusive requests from
read-only "
- "cache %s\n", name());
}
}
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index bded746..b054cd4 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -710,6 +710,32 @@
// Software prefetch handling for cache closest to core
if (tgt_pkt->cmd.isSWPrefetch()) {
+if (tgt_pkt->needsWritable()) {
+// All other copies of the block were invalidated and
we
+// have an exclusive copy.
+
+// The coherence protocol assumes that if we fetched an
+// exclusive copy of the block, we have the intention
to
+// modify it. Therefore the MSHR for the PrefetchExReq
has
+// been the point of ordering and this cache has
commited
+// to respond to snoops for the block.
+//
+// In most cases this is true anyway - a PrefetchExReq
+// will be followed by a WriteReq. However, if that
+// doesn't happen, the block is not marked as dirty and
+// the cache doesn't respond to snoops that has
committed
+// to do so.
+//
+// To avoid deadlocks in cases where there is a snoop
+// between the PrefetchExReq and the expected
WriteReq, we
+// proactively mark the block as Dirty.
+assert(blk);
+blk->status |= BlkDirty;
+
+panic_if(isReadOnly, "Prefetch exclusive requests
from "
+"read-only cache %s\n", name());
+}
+
// a software prefetch would have already been ack'd
// immediately with dummy data so the core would be able to
// retire it. This request completes right here, so we
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19688
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I2b377fdd240eb0f09e720b6bb284dee6545925ce
Gerrit-Change-Number: 19688
Gerrit-PatchSet: 2
Gerrit-Owner: Tiago
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Rewrite MSR immediate instruction class
Hello Andreas Sandberg,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19728
to review the following change.
Change subject: arch-arm: Rewrite MSR immediate instruction class
..
arch-arm: Rewrite MSR immediate instruction class
MSR , #imm is used for setting a PSTATE field using an
immediate. Current implementation has the following flaws:
* There is no base MSR immediate definition: all the existing
PSTATE fields have a different class definition
* Those implementation make use of a generic data64 base class
which results in a wrong disassembly (pstate register is printed as an
integer register).
This patch is fixing this by defining a new base class (MiscRegImmOp64)
and new related templates. In this way, we aim to ease addition of new
PSTATE fields (in ARMv8.x)
Change-Id: I71b630ff32abe1b105bbb3ab5781c6589b67d419
Signed-off-by: Giacomo Travaglini
Reviewed-by: Andreas Sandberg
---
M src/arch/arm/insts/misc64.cc
M src/arch/arm/insts/misc64.hh
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/insts/data64.isa
M src/arch/arm/isa/templates/misc64.isa
5 files changed, 110 insertions(+), 49 deletions(-)
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 423aaca..cf625eb 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -35,6 +35,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
+ * Giacomo Travaglini
*/
#include "arch/arm/insts/misc64.hh"
@@ -321,6 +322,27 @@
return trap_to_mon;
}
+RegVal
+MiscRegImmOp64::miscRegImm() const
+{
+if (dest == MISCREG_SPSEL) {
+return imm & 0x1;
+} else {
+panic("Not a valid PSTATE field register\n");
+}
+}
+
+std::string
+MiscRegImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab)
const
+{
+std::stringstream ss;
+printMnemonic(ss);
+printMiscReg(ss, dest);
+ss << ", ";
+ccprintf(ss, "#0x%x", imm);
+return ss.str();
+}
+
std::string
MiscRegRegImmOp64::generateDisassembly(
Addr pc, const SymbolTable *symtab) const
diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh
index f70344b..741b7b5 100644
--- a/src/arch/arm/insts/misc64.hh
+++ b/src/arch/arm/insts/misc64.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2013,2017-2018 ARM Limited
+ * Copyright (c) 2011-2013,2017-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -35,6 +35,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
+ * Giacomo Travaglini
*/
#ifndef __ARCH_ARM_INSTS_MISC64_HH__
@@ -142,6 +143,30 @@
};
+class MiscRegImmOp64 : public MiscRegOp64
+{
+ protected:
+MiscRegIndex dest;
+uint32_t imm;
+
+MiscRegImmOp64(const char *mnem, ExtMachInst _machInst,
+ OpClass __opClass, MiscRegIndex _dest,
+ uint32_t _imm) :
+MiscRegOp64(mnem, _machInst, __opClass, false),
+dest(_dest), imm(_imm)
+{}
+
+/** Returns the "register view" of the immediate field.
+ * as if it was a MSR PSTATE REG instruction.
+ * This means basically shifting and masking depending on
+ * which PSTATE field is being set/cleared.
+ */
+RegVal miscRegImm() const;
+
+std::string generateDisassembly(
+Addr pc, const SymbolTable *symtab) const override;
+};
+
class MiscRegRegImmOp64 : public MiscRegOp64
{
protected:
diff --git a/src/arch/arm/isa/formats/aarch64.isa
b/src/arch/arm/isa/formats/aarch64.isa
index 15cbe90..144ff88 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -1,4 +1,4 @@
-// Copyright (c) 2011-2018 ARM Limited
+// Copyright (c) 2011-2019 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -389,28 +389,21 @@
return new Unknown64(machInst);
}
} else if (crn == 0x4) {
-// MSR immediate
+// MSR immediate: moving immediate value to
selected
+// bits of the PSTATE
switch (op1 << 3 | op2) {
case 0x5:
// SP
-return new MsrSP64(machInst,
- (IntRegIndex) MISCREG_SPSEL,
- INTREG_ZERO,
- crm & 0x1);
+return new MsrImm64(
+machInst, MISCREG_SPSEL, crm);
case 0x1e:
// DAIFSet
-return new MsrDAIFSet6
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Implement ARMv8.1-PAN, Privileged access never
Hello Andreas Sandberg,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19729
to review the following change.
Change subject: arch-arm: Implement ARMv8.1-PAN, Privileged access never
..
arch-arm: Implement ARMv8.1-PAN, Privileged access never
ARMv8.1-PAN adds a new bit to PSTATE. When the value of this PAN state
bit is 1, any privileged data access from EL1 or EL2 to a virtual memory
address that is accessible at EL0 generates a Permission fault.
This feature is mandatory in ARMv8.1 implementations.
This feature is supported in AArch64 and AArch32 states.
The ID_AA64MMFR1_EL1.PAN, ID_MMFR3_EL1.PAN, and ID_MMFR3.PAN fields
identify the support for ARMv8.1-PAN.
Signed-off-by: Giacomo Travaglini
Change-Id: I94a76311711739dd2394c72944d88ba9321fd159
Reviewed-by: Andreas Sandberg
---
M src/arch/arm/ArmISA.py
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
M src/arch/arm/insts/misc64.cc
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/isa.cc
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/miscregs_types.hh
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
12 files changed, 92 insertions(+), 15 deletions(-)
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 3d30e5f..3c1f7dd 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -105,8 +105,8 @@
# 4K | 64K | !16K | !BigEndEL0 | !SNSMem | !BigEnd | 8b ASID | 40b PA
id_aa64mmfr0_el1 = Param.UInt64(0x00f2,
"AArch64 Memory Model Feature Register 0")
-# HPDS
-id_aa64mmfr1_el1 = Param.UInt64(0x1000,
+# PAN | HPDS
+id_aa64mmfr1_el1 = Param.UInt64(0x00101000,
"AArch64 Memory Model Feature Register 1")
id_aa64mmfr2_el1 = Param.UInt64(0x,
"AArch64 Memory Model Feature Register 2")
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index a03c917..25d1393 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited
+ * Copyright (c) 2010, 2012-2014, 2016-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -448,6 +448,18 @@
if (fromEL > toEL)
toEL = fromEL;
+// Check for Set Priviledge Access Never
+if (toEL == EL1) {
+const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
+span = !sctlr.span;
+}
+
+const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
+if (toEL == EL2 && hcr.e2h && hcr.tge) {
+const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL2);
+span = !sctlr.span;
+}
+
to64 = ELIs64(tc, toEL);
// The fault specific informations have been updated; it is
@@ -536,6 +548,7 @@
}
cpsr.it1 = cpsr.it2 = 0;
cpsr.j = 0;
+cpsr.pan = span ? 1 : saved_cpsr.pan;
tc->setMiscReg(MISCREG_CPSR, cpsr);
// Make sure mailbox sets to one always
@@ -635,7 +648,6 @@
spsr.q = 0;
spsr.it1 = 0;
spsr.j = 0;
-spsr.res0_23_22 = 0;
spsr.ge = 0;
spsr.it2 = 0;
spsr.t = 0;
@@ -645,7 +657,6 @@
spsr.it2 = it.top6;
spsr.it1 = it.bottom2;
// Force some bitfields to 0
-spsr.res0_23_22 = 0;
spsr.ss = 0;
}
tc->setMiscReg(spsr_idx, spsr);
@@ -670,6 +681,7 @@
cpsr.daif = 0xf;
cpsr.il = 0;
cpsr.ss = 0;
+cpsr.pan = span ? 1 : spsr.pan;
tc->setMiscReg(MISCREG_CPSR, cpsr);
// If we have a valid instruction then use it to annotate this fault
with
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index d14983d..5e68875 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2012-2013, 2016-2018 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2016-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -82,6 +82,7 @@
bool faultUpdated;
bool hypRouted; // True if the fault has been routed to Hypervisor
+bool span; // True if the fault is setting the PSTATE.PAN bit
virtual Addr getVector(ThreadContext *tc);
Addr getVector64(ThreadContext *tc);
@@ -200,7 +201,7 @@
ArmFault(ExtMachInst _machInst = 0, uint32_t _iss = 0) :
machInst(_machInst), issRaw(_iss), from64(false), to64(false),
fromEL(EL0), toEL(EL0), fromMode(MODE_UNDEFINED),
-faultUpdated(false), hypRouted(false) {}
+faultUpdated(false), hypRouted(false), span(false) {}
// Returns the actual syndrome register to use based on the target
// exception level
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index cf625eb..2d0422f 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
[gem5-dev] Change in gem5/gem5[master]: stats: Add support for listing available formats
Hello Daniel Carvalho, Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19670 to look at the new patch set (#2). Change subject: stats: Add support for listing available formats .. stats: Add support for listing available formats Add a command line option to list available stat formats and their documentation. Change-Id: I7f5f2272d9b0176639f59f2efedb9cab2f7da5b9 Signed-off-by: Andreas Sandberg --- M src/python/m5/main.py M src/python/m5/stats/__init__.py 2 files changed, 94 insertions(+), 48 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19670 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I7f5f2272d9b0176639f59f2efedb9cab2f7da5b9 Gerrit-Change-Number: 19670 Gerrit-PatchSet: 2 Gerrit-Owner: Andreas Sandberg Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Jason Lowe-Power Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Fix set and way of sub-entries
Daniel Carvalho has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/19669 )
Change subject: mem-cache: Fix set and way of sub-entries
..
mem-cache: Fix set and way of sub-entries
Set and way of sub-entries were not being set previously.
They must be set after the sub-blocks have been assigned
to the main block.
Change-Id: I7b6921b8437b29c472d691cd78cf20f2bb6c7e07
Signed-off-by: Daniel R. Carvalho
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19669
Reviewed-by: Nikos Nikoleris
Maintainer: Nikos Nikoleris
Tested-by: kokoro
---
M src/mem/cache/replacement_policies/replaceable_entry.hh
M src/mem/cache/tags/compressed_tags.cc
M src/mem/cache/tags/sector_blk.cc
M src/mem/cache/tags/sector_blk.hh
M src/mem/cache/tags/sector_tags.cc
5 files changed, 26 insertions(+), 7 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/cache/replacement_policies/replaceable_entry.hh
b/src/mem/cache/replacement_policies/replaceable_entry.hh
index bf54e22..dffa4cf 100644
--- a/src/mem/cache/replacement_policies/replaceable_entry.hh
+++ b/src/mem/cache/replacement_policies/replaceable_entry.hh
@@ -76,7 +76,9 @@
* @param set The set of this entry.
* @param way The way of this entry.
*/
-void setPosition(const uint32_t set, const uint32_t way) {
+virtual void
+setPosition(const uint32_t set, const uint32_t way)
+{
_set = set;
_way = way;
}
diff --git a/src/mem/cache/tags/compressed_tags.cc
b/src/mem/cache/tags/compressed_tags.cc
index 0896a1b..1394be8 100644
--- a/src/mem/cache/tags/compressed_tags.cc
+++ b/src/mem/cache/tags/compressed_tags.cc
@@ -67,9 +67,6 @@
// allocation conditions
superblock->setBlkSize(blkSize);
-// Link block to indexing policy
-indexingPolicy->setEntry(superblock, superblock_index);
-
// Associate a replacement data entry to the block
superblock->replacementData =
replacementPolicy->instantiateEntry();
@@ -97,6 +94,9 @@
// Update block index
++blk_index;
}
+
+// Link block to indexing policy
+indexingPolicy->setEntry(superblock, superblock_index);
}
}
diff --git a/src/mem/cache/tags/sector_blk.cc
b/src/mem/cache/tags/sector_blk.cc
index 93b1961..7e4468d 100644
--- a/src/mem/cache/tags/sector_blk.cc
+++ b/src/mem/cache/tags/sector_blk.cc
@@ -167,3 +167,12 @@
{
_secureBit = true;
}
+
+void
+SectorBlk::setPosition(const uint32_t set, const uint32_t way)
+{
+ReplaceableEntry::setPosition(set, way);
+for (auto& blk : blks) {
+blk->setPosition(set, way);
+}
+}
diff --git a/src/mem/cache/tags/sector_blk.hh
b/src/mem/cache/tags/sector_blk.hh
index ca0d9a8..a30fb81 100644
--- a/src/mem/cache/tags/sector_blk.hh
+++ b/src/mem/cache/tags/sector_blk.hh
@@ -214,6 +214,14 @@
* Set secure bit.
*/
void setSecure();
+
+/**
+ * Sets the position of the sub-entries, besides its own.
+ *
+ * @param set The set of this entry and sub-entries.
+ * @param way The way of this entry and sub-entries.
+ */
+void setPosition(const uint32_t set, const uint32_t way) override;
};
#endif //__MEM_CACHE_TAGS_SECTOR_BLK_HH__
diff --git a/src/mem/cache/tags/sector_tags.cc
b/src/mem/cache/tags/sector_tags.cc
index 535badb..1098885 100644
--- a/src/mem/cache/tags/sector_tags.cc
+++ b/src/mem/cache/tags/sector_tags.cc
@@ -77,9 +77,6 @@
// Locate next cache sector
SectorBlk* sec_blk = &secBlks[sec_blk_index];
-// Link block to indexing policy
-indexingPolicy->setEntry(sec_blk, sec_blk_index);
-
// Associate a replacement data entry to the sector
sec_blk->replacementData = replacementPolicy->instantiateEntry();
@@ -107,6 +104,9 @@
// Update block index
++blk_index;
}
+
+// Link block to indexing policy
+indexingPolicy->setEntry(sec_blk, sec_blk_index);
}
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19669
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I7b6921b8437b29c472d691cd78cf20f2bb6c7e07
Gerrit-Change-Number: 19669
Gerrit-PatchSet: 2
Gerrit-Owner: Daniel Carvalho
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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