[gem5-dev] Change in gem5/gem5[master]: cpu, arm: Push the stage 2 MMUs out of the CPU into the TLBs.
Gabe Black has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/21842 ) Change subject: cpu,arm: Push the stage 2 MMUs out of the CPU into the TLBs. .. cpu,arm: Push the stage 2 MMUs out of the CPU into the TLBs. This regularizes the TLB setup in the CPU so that ARM is no longer a special case with extra objects. Change-Id: I739b82578ff74f8f9777cd7e34cd5227b47b186c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21842 Tested-by: kokoro Reviewed-by: Jason Lowe-Power Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- M src/arch/arm/ArmTLB.py M src/cpu/BaseCPU.py 2 files changed, 10 insertions(+), 8 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved Andreas Sandberg: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py index 4a6b3e7..d233463 100644 --- a/src/arch/arm/ArmTLB.py +++ b/src/arch/arm/ArmTLB.py @@ -90,11 +90,17 @@ class ArmStage2IMMU(ArmStage2MMU): # We rely on the itb being a parameter of the CPU, and get the # appropriate object that way -tlb = Parent.itb +tlb = Parent.any stage2_tlb = ArmStage2TLB() class ArmStage2DMMU(ArmStage2MMU): # We rely on the dtb being a parameter of the CPU, and get the # appropriate object that way -tlb = Parent.dtb +tlb = Parent.any stage2_tlb = ArmStage2TLB() + +class ArmITB(ArmTLB): +stage2_mmu = ArmStage2IMMU() + +class ArmDTB(ArmTLB): +stage2_mmu = ArmStage2DMMU() diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index e17e26a..57f0f2f 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -83,8 +83,7 @@ from m5.objects.MipsISA import MipsISA as ArchISA ArchISAsParam = VectorParam.MipsISA elif buildEnv['TARGET_ISA'] == 'arm': -from m5.objects.ArmTLB import ArmTLB as ArchDTB, ArmTLB as ArchITB -from m5.objects.ArmTLB import ArmStage2IMMU, ArmStage2DMMU +from m5.objects.ArmTLB import ArmDTB as ArchDTB, ArmITB as ArchITB from m5.objects.ArmInterrupts import ArmInterrupts as ArchInterrupts from m5.objects.ArmISA import ArmISA as ArchISA ArchISAsParam = VectorParam.ArmISA @@ -174,10 +173,7 @@ dtb = Param.BaseTLB(ArchDTB(), "Data TLB") itb = Param.BaseTLB(ArchITB(), "Instruction TLB") -if buildEnv['TARGET_ISA'] == 'arm': -istage2_mmu = ArmStage2IMMU() -dstage2_mmu = ArmStage2DMMU() -elif buildEnv['TARGET_ISA'] == 'power': +if buildEnv['TARGET_ISA'] == 'power': UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") interrupts = VectorParam.BaseInterrupts([], "Interrupt Controller") isa = ArchISAsParam([], "ISA instance") -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/21842 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I739b82578ff74f8f9777cd7e34cd5227b47b186c Gerrit-Change-Number: 21842 Gerrit-PatchSet: 3 Gerrit-Owner: Gabe Black Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch: Make a base class for Interrupts.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/20831 )
Change subject: arch: Make a base class for Interrupts.
..
arch: Make a base class for Interrupts.
That abstracts the ISA further from the CPU, getting us a small step
closer to being able to build in more than one ISA at a time.
Change-Id: Ibf7e26a3df411ffe994ac1e11d2a53b656863223
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20831
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
---
M src/arch/alpha/AlphaInterrupts.py
M src/arch/alpha/interrupts.hh
M src/arch/alpha/isa/decoder.isa
M src/arch/arm/ArmInterrupts.py
M src/arch/arm/interrupts.hh
M src/arch/arm/isa.cc
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa/insts/misc.isa
A src/arch/generic/BaseInterrupts.py
M src/arch/generic/SConscript
A src/arch/generic/interrupts.hh
M src/arch/mips/MipsInterrupts.py
M src/arch/mips/interrupts.cc
M src/arch/mips/interrupts.hh
M src/arch/power/PowerInterrupts.py
M src/arch/power/interrupts.hh
M src/arch/riscv/RiscvInterrupts.py
M src/arch/riscv/interrupts.hh
M src/arch/riscv/isa.cc
M src/arch/sparc/SparcInterrupts.py
M src/arch/sparc/interrupts.hh
M src/arch/sparc/isa.cc
M src/arch/x86/X86LocalApic.py
M src/arch/x86/interrupts.cc
M src/arch/x86/interrupts.hh
M src/arch/x86/pagetable_walker.cc
M src/cpu/BaseCPU.py
M src/cpu/base.hh
M src/cpu/kvm/base.hh
M src/cpu/kvm/x86_cpu.cc
M src/dev/x86/i82094aa.cc
31 files changed, 236 insertions(+), 70 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/alpha/AlphaInterrupts.py
b/src/arch/alpha/AlphaInterrupts.py
index a75b11f..7bab9b0 100644
--- a/src/arch/alpha/AlphaInterrupts.py
+++ b/src/arch/alpha/AlphaInterrupts.py
@@ -26,9 +26,9 @@
#
# Authors: Gabe Black
-from m5.SimObject import SimObject
+from m5.objects.BaseInterrupts import BaseInterrupts
-class AlphaInterrupts(SimObject):
+class AlphaInterrupts(BaseInterrupts):
type = 'AlphaInterrupts'
cxx_class = 'AlphaISA::Interrupts'
cxx_header = "arch/alpha/interrupts.hh"
diff --git a/src/arch/alpha/interrupts.hh b/src/arch/alpha/interrupts.hh
index 61ac6c9..e054b43 100644
--- a/src/arch/alpha/interrupts.hh
+++ b/src/arch/alpha/interrupts.hh
@@ -36,17 +36,17 @@
#include "arch/alpha/faults.hh"
#include "arch/alpha/isa_traits.hh"
+#include "arch/generic/interrupts.hh"
#include "base/compiler.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "debug/Flow.hh"
#include "debug/Interrupt.hh"
#include "params/AlphaInterrupts.hh"
-#include "sim/sim_object.hh"
namespace AlphaISA {
-class Interrupts : public SimObject
+class Interrupts : public BaseInterrupts
{
private:
bool newInfoSet;
@@ -67,7 +67,7 @@
return dynamic_cast(_params);
}
-Interrupts(Params * p) : SimObject(p), cpu(NULL)
+Interrupts(Params * p) : BaseInterrupts(p), cpu(NULL)
{
memset(interrupts, 0, sizeof(interrupts));
intstatus = 0;
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 8732d70..020e433 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -982,7 +982,7 @@
}}, IsNonSpeculative);
0x01: quiesce({{
// Don't sleep if (unmasked) interrupts are pending
-Interrupts* interrupts =
+BaseInterrupts* interrupts =
xc->tcBase()->getCpuPtr()->getInterruptController(0);
if (interrupts->checkInterrupts(xc->tcBase())) {
PseudoInst::quiesceSkip(xc->tcBase());
diff --git a/src/arch/arm/ArmInterrupts.py b/src/arch/arm/ArmInterrupts.py
index 68a5895..9a6b546 100644
--- a/src/arch/arm/ArmInterrupts.py
+++ b/src/arch/arm/ArmInterrupts.py
@@ -26,9 +26,9 @@
#
# Authors: Ali Saidi
-from m5.SimObject import SimObject
+from m5.objects.BaseInterrupts import BaseInterrupts
-class ArmInterrupts(SimObject):
+class ArmInterrupts(BaseInterrupts):
type = 'ArmInterrupts'
cxx_class = 'ArmISA::Interrupts'
cxx_header = "arch/arm/interrupts.hh"
diff --git a/src/arch/arm/interrupts.hh b/src/arch/arm/interrupts.hh
index 8d0cb49..1f8e321 100644
--- a/src/arch/arm/interrupts.hh
+++ b/src/arch/arm/interrupts.hh
@@ -48,15 +48,15 @@
#include "arch/arm/miscregs.hh"
#include "arch/arm/registers.hh"
#include "arch/arm/utility.hh"
+#include "arch/generic/interrupts.hh"
#include "cpu/thread_context.hh"
#include "debug/Interrupt.hh"
#include "params/ArmInterrupts.hh"
-#include "sim/sim_object.hh"
namespace ArmISA
{
-class Interrupts : public SimObject
+class Interrupts : public BaseInterrupts
{
private:
BaseCPU * cpu;
@@ -80,7 +80,7 @@
return dynamic_cast(_params);
[gem5-dev] Change in gem5/gem5[master]: arch: Remove the "interrupts.hh" switching header file.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/20832 )
Change subject: arch: Remove the "interrupts.hh" switching header file.
..
arch: Remove the "interrupts.hh" switching header file.
That switching header is no longer necessary since everything outside
of the ISA can use the BaseInterrupts class.
Change-Id: Ie3ed45c38fec24234ff51fb05ba94f6f3cd02afd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20832
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
---
M src/arch/SConscript
1 file changed, 0 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/SConscript b/src/arch/SConscript
index f59b026..0661db7 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -60,7 +60,6 @@
env.SwitchingHeaders(
Split('''
decoder.hh
-interrupts.hh
isa.hh
isa_traits.hh
kernel_stats.hh
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/20832
To unsubscribe, or for help writing mail filters, visit
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ie3ed45c38fec24234ff51fb05ba94f6f3cd02afd
Gerrit-Change-Number: 20832
Gerrit-PatchSet: 10
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Brandon Potter
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: NetDest static allocation of bitmasks
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/21900 )
Change subject: mem-ruby: NetDest static allocation of bitmasks
..
mem-ruby: NetDest static allocation of bitmasks
Replacing std::vector by std::array since the number of machine types
is fixed at compile time.
Some tests with a 32-core simulation using
configs/example/ruby_mem_test.py show about 20% performance improvement
(mostly due to the removal of the "resize()" calls from NetDest's
constructor)
Change-Id: I78ec1fb0bc87df2f8ca65b9eb5f9050396b9083c
Signed-off-by: Tiago Mück
---
M src/mem/ruby/common/NetDest.cc
M src/mem/ruby/common/NetDest.hh
2 files changed, 63 insertions(+), 31 deletions(-)
diff --git a/src/mem/ruby/common/NetDest.cc b/src/mem/ruby/common/NetDest.cc
index 3a28646..40078c2 100644
--- a/src/mem/ruby/common/NetDest.cc
+++ b/src/mem/ruby/common/NetDest.cc
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
* All rights reserved.
*
@@ -32,14 +44,16 @@
NetDest::NetDest()
{
- resize();
}
void
-NetDest::add(MachineID newElement)
+NetDest::add(const MachineID &newElement)
{
-assert(bitIndex(newElement.num) <
m_bits[vecIndex(newElement)].getSize());
-m_bits[vecIndex(newElement)].add(bitIndex(newElement.num));
+Set &bits = m_bits[vecIndex(newElement)];
+if (bits.getSize() == 0)
+bits.setSize(MachineType_base_count(newElement.getType()));
+assert(bitIndex(newElement.num) < bits.getSize());
+bits.add(bitIndex(newElement.num));
}
void
@@ -47,7 +61,10 @@
{
assert(m_bits.size() == netDest.getSize());
for (int i = 0; i < m_bits.size(); i++) {
-m_bits[i].addSet(netDest.m_bits[i]);
+if (netDest.m_bits[i].getSize() > 0){
+m_bits[i].setSize(netDest.m_bits[i].getSize());
+m_bits[i].addSet(netDest.m_bits[i]);
+}
}
}
@@ -61,7 +78,7 @@
}
void
-NetDest::remove(MachineID oldElement)
+NetDest::remove(const MachineID &oldElement)
{
m_bits[vecIndex(oldElement)].remove(bitIndex(oldElement.num));
}
@@ -71,7 +88,8 @@
{
assert(m_bits.size() == netDest.getSize());
for (int i = 0; i < m_bits.size(); i++) {
-m_bits[i].removeSet(netDest.m_bits[i]);
+if ((m_bits[i].getSize() != 0) && (netDest.m_bits[i].getSize() !=
0))
+m_bits[i].removeSet(netDest.m_bits[i]);
}
}
@@ -129,7 +147,7 @@
}
NodeID
-NetDest::elementAt(MachineID index)
+NetDest::elementAt(const MachineID &index)
{
return m_bits[vecIndex(index)].elementAt(bitIndex(index.num));
}
@@ -194,7 +212,12 @@
assert(m_bits.size() == orNetDest.getSize());
NetDest result;
for (int i = 0; i < m_bits.size(); i++) {
-result.m_bits[i] = m_bits[i].OR(orNetDest.m_bits[i]);
+if (orNetDest.m_bits[i].getSize() == 0)
+result.m_bits[i] = m_bits[i];
+else if (m_bits[i].getSize() == 0)
+result.m_bits[i] = orNetDest.m_bits[i];
+else
+result.m_bits[i] = m_bits[i].OR(orNetDest.m_bits[i]);
}
return result;
}
@@ -206,7 +229,11 @@
assert(m_bits.size() == andNetDest.getSize());
NetDest result;
for (int i = 0; i < m_bits.size(); i++) {
-result.m_bits[i] = m_bits[i].AND(andNetDest.m_bits[i]);
+if ((andNetDest.m_bits[i].getSize() == 0) ||
+(m_bits[i].getSize() == 0))
+result.m_bits[i].clear();
+else
+result.m_bits[i] = m_bits[i].AND(andNetDest.m_bits[i]);
}
return result;
}
@@ -238,20 +265,13 @@
}
bool
-NetDest::isElement(MachineID element) const
+NetDest::isElement(const MachineID &element) const
{
-return ((m_bits[vecIndex(element)])).isElement(bitIndex(element.num));
-}
-
-void
-NetDest::resize()
-{
-m_bits.resize(MachineType_base_level(MachineType_NUM));
-assert(m_bits.size() == MachineType_NUM);
-
-for (int i = 0; i < m_bits.size(); i++) {
-m_bits[i].setSize(MachineType_base_count((MachineType)i));
-}
+int vi = vecIndex(element);
+if (m_bits[vi].getSize() == 0)
+return false;
+else
+return m_bits[vi].isElement(bitIndex(element.num));
}
void
diff --git a/src/mem/ruby/common/NetDest.hh b/src/mem/ruby/common/NetDest.hh
index 69bfa8a..8437
[gem5-dev] Change in gem5/gem5[master]: dev-arm: Check for gem5 extensions in GicV2
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/19288 )
Change subject: dev-arm: Check for gem5 extensions in GicV2
..
dev-arm: Check for gem5 extensions in GicV2
Using GicV2 without setting the gem5_extensions parameter in a
config with more than 8 is not allowed to prevent overflow of
the 8-bit mask.
Change-Id: I780c6985e8f44ed780b4f74f9a27805124e23a7b
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19288
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/dev/arm/gic_v2.hh
1 file changed, 6 insertions(+), 3 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh
index f9b66b8..4104140 100644
--- a/src/dev/arm/gic_v2.hh
+++ b/src/dev/arm/gic_v2.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
+ * Copyright (c) 2010, 2013, 2015-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -309,8 +309,11 @@
if (gem5ExtensionsEnabled) {
ctx_mask = ctx;
} else {
-// convert the CPU id number into a bit mask
-ctx_mask = power(2, ctx);
+fatal_if(ctx >= 8,
+"%s requires the gem5_extensions parameter to support "
+"more than 8 cores\n", name());
+// convert the CPU id number into a bit mask
+ctx_mask = 1 << ctx;
}
return ctx_mask;
} else {
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19288
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I780c6985e8f44ed780b4f74f9a27805124e23a7b
Gerrit-Change-Number: 19288
Gerrit-PatchSet: 2
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: removed unused checkCoherence
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/21924 )
Change subject: mem-ruby: removed unused checkCoherence
..
mem-ruby: removed unused checkCoherence
Change-Id: I108b95513f2828470fe70bad5f136b0721598582
Signed-off-by: Tiago Mück
---
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/system/GPUCoalescer.cc
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/ruby/system/Sequencer.cc
M src/mem/ruby/system/Sequencer.hh
5 files changed, 0 insertions(+), 20 deletions(-)
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index 99931bc..2c0404d 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -124,7 +124,6 @@
void writeCallback(Addr, DataBlock, bool, MachineType,
Cycles, Cycles, Cycles);
- void checkCoherence(Addr);
void evictionCallback(Addr);
void recordRequestType(SequencerRequestType);
bool checkResourceAvailable(CacheResourceType, Addr);
@@ -144,7 +143,6 @@
Cycles, Cycles, Cycles);
void writeCallback(Addr, MachineType, DataBlock,
Cycles, Cycles, Cycles, bool);
- void checkCoherence(Addr);
void evictionCallback(Addr);
void recordCPReadCallBack(MachineID, MachineID);
void recordCPWriteCallBack(MachineID, MachineID);
@@ -165,7 +163,6 @@
Cycles, Cycles, Cycles, bool);
void invCallback(Addr);
void wbCallback(Addr);
- void checkCoherence(Addr);
void evictionCallback(Addr);
}
diff --git a/src/mem/ruby/system/GPUCoalescer.cc
b/src/mem/ruby/system/GPUCoalescer.cc
index 61ee2ae..e7d2cb6 100644
--- a/src/mem/ruby/system/GPUCoalescer.cc
+++ b/src/mem/ruby/system/GPUCoalescer.cc
@@ -978,13 +978,6 @@
<< "]";
}
-// this can be called from setState whenever coherence permissions are
-// upgraded when invoked, coherence violations will be checked for the
-// given block
-void
-GPUCoalescer::checkCoherence(Addr addr)
-{
-}
void
GPUCoalescer::recordRequestType(SequencerRequestType requestType) {
diff --git a/src/mem/ruby/system/GPUCoalescer.hh
b/src/mem/ruby/system/GPUCoalescer.hh
index 56f81c6..2d5604f 100644
--- a/src/mem/ruby/system/GPUCoalescer.hh
+++ b/src/mem/ruby/system/GPUCoalescer.hh
@@ -178,7 +178,6 @@
bool empty() const;
void print(std::ostream& out) const;
-void checkCoherence(Addr address);
void markRemoved();
void removeRequest(GPUCoalescerRequest* request);
diff --git a/src/mem/ruby/system/Sequencer.cc
b/src/mem/ruby/system/Sequencer.cc
index 9d317aa..5604356 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -679,14 +679,6 @@
<< "]";
}
-// this can be called from setState whenever coherence permissions are
-// upgraded when invoked, coherence violations will be checked for the
-// given block
-void
-Sequencer::checkCoherence(Addr addr)
-{
-}
-
void
Sequencer::recordRequestType(SequencerRequestType requestType) {
DPRINTF(RubyStats, "Recorded statistic: %s\n",
diff --git a/src/mem/ruby/system/Sequencer.hh
b/src/mem/ruby/system/Sequencer.hh
index 33fd530..8b48ae1 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -94,7 +94,6 @@
{ deschedule(deadlockCheckEvent); }
void print(std::ostream& out) const;
-void checkCoherence(Addr address);
void markRemoved();
void evictionCallback(Addr address);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I108b95513f2828470fe70bad5f136b0721598582
Gerrit-Change-Number: 21924
Gerrit-PatchSet: 1
Gerrit-Owner: Tiago Mück
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: fix possible MOESI_CMP deadlock
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/21929 )
Change subject: mem-ruby: fix possible MOESI_CMP deadlock
..
mem-ruby: fix possible MOESI_CMP deadlock
Freeing the L2 block only after local invalidates are acked in the OLSF
state may lead to a deadlock.
Change-Id: Ia4b60e5bc9e2d3315b874a8c6616478db6eb38c1
Signed-off-by: Tiago Mück
---
M src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
index 8b6643e..ed91821 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
@@ -1912,6 +1912,9 @@
i_allocateTBE;
t_recordFwdXID;
ee_sendLocalInv;
+gg_clearLocalSharers;
+checkCacheNoSharersNoOwner;
+rr_deallocateL2CacheBlock;
m_popRequestQueue;
}
@@ -1923,10 +1926,7 @@
transition(OLSF, All_Acks, I) {
c_sendDataFromTBEToFwdGETX;
-gg_clearLocalSharers;
s_deallocateTBE;
-checkCacheNoSharersNoOwner;
-rr_deallocateL2CacheBlock;
n_popTriggerQueue;
wa_wakeUpDependents;
}
--
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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Missing transition in MOESI_CMP_directory
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/21925 )
Change subject: mem-ruby: Missing transition in MOESI_CMP_directory
..
mem-ruby: Missing transition in MOESI_CMP_directory
Change-Id: I3aa9cd0230c141128ef5bddc728775b1ea6bbe14
Signed-off-by: Tiago Mück
---
M src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
index 85e7946..39de654 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
@@ -663,7 +663,7 @@
i_popIncomingRequestQueue;
}
- transition({I, S}, PUTO) {
+ transition({I, S}, {PUTO, PUTO_SHARERS}) {
b_sendWriteBackNack;
i_popIncomingRequestQueue;
}
--
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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Add deallocate to DirectoryMemory
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/21920 )
Change subject: mem-ruby: Add deallocate to DirectoryMemory
..
mem-ruby: Add deallocate to DirectoryMemory
Change-Id: Ib261ec8b302b55e539d8e13064957170412b752c
Signed-off-by: Tiago Mück
---
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/structures/DirectoryMemory.cc
M src/mem/ruby/structures/DirectoryMemory.hh
3 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index fd76289..99931bc 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved.
@@ -181,6 +193,7 @@
structure (DirectoryMemory, external = "yes") {
AbstractCacheEntry allocate(Addr, AbstractCacheEntry);
AbstractCacheEntry lookup(Addr);
+ void deallocate(Addr);
bool isPresent(Addr);
void invalidateBlock(Addr);
void recordRequestType(DirectoryRequestType);
diff --git a/src/mem/ruby/structures/DirectoryMemory.cc
b/src/mem/ruby/structures/DirectoryMemory.cc
index d9da058..c878ee8 100644
--- a/src/mem/ruby/structures/DirectoryMemory.cc
+++ b/src/mem/ruby/structures/DirectoryMemory.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 ARM Limited
+ * Copyright (c) 2017,2019 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -129,6 +129,7 @@
idx = mapAddressToLocalIdx(address);
assert(idx < m_num_entries);
+assert(m_entries[idx] == NULL);
entry->changePermission(AccessPermission_Read_Only);
m_entries[idx] = entry;
@@ -136,6 +137,20 @@
}
void
+DirectoryMemory::deallocate(Addr address)
+{
+assert(isPresent(address));
+uint64_t idx;
+DPRINTF(RubyCache, "Removing entry for address: %#x\n", address);
+
+idx = mapAddressToLocalIdx(address);
+assert(idx < m_num_entries);
+assert(m_entries[idx] != NULL);
+delete m_entries[idx];
+m_entries[idx] = NULL;
+}
+
+void
DirectoryMemory::print(ostream& out) const
{
}
diff --git a/src/mem/ruby/structures/DirectoryMemory.hh
b/src/mem/ruby/structures/DirectoryMemory.hh
index f879b29..3dd0e95 100644
--- a/src/mem/ruby/structures/DirectoryMemory.hh
+++ b/src/mem/ruby/structures/DirectoryMemory.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 ARM Limited
+ * Copyright (c) 2017,2019 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -79,6 +79,9 @@
AbstractCacheEntry *lookup(Addr address);
AbstractCacheEntry *allocate(Addr address, AbstractCacheEntry*
new_entry);
+// Explicitly free up this address
+void deallocate(Addr address);
+
void print(std::ostream& out) const;
void recordRequestType(DirectoryRequestType requestType);
--
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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: fix MOESI_CMP_directory functional reads
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/21927 )
Change subject: mem-ruby: fix MOESI_CMP_directory functional reads
..
mem-ruby: fix MOESI_CMP_directory functional reads
This patch properly sets the access permissions in all controllers.
'Busy' was used for all transient states, which is incorrect in lots of
cases when we still hold a valid copy of the line and are able to handle
a functional read.
In the L2 controller these states were split to differentiate the access
permissions:
IFGXX -> IFGXX, IFGXXD
IGMO -> IGMO, IGMOU
IGMIOF -> IGMIOF, IGMIOFD
Same for the dir. controller:
IS -> IS, IS_M
MM -> MM, MM_M
The dir. controllers also has the states WBI/WBS for lines that have
been queued for a writeback. In these states we hold the data in the TBE
for replying to functional reads until the memory acks the write and we
move to I or S.
Other minor changes includes updated debug messages and asserts.
Change-Id: Ie4f6eac3b4d2641ec91ac6b168a0a017f61c0d6f
Signed-off-by: Tiago Mück
---
M configs/ruby/MOESI_CMP_directory.py
M src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
M src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
M src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
M src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm
M src/mem/ruby/protocol/MOESI_CMP_directory-msg.sm
6 files changed, 225 insertions(+), 95 deletions(-)
diff --git a/configs/ruby/MOESI_CMP_directory.py
b/configs/ruby/MOESI_CMP_directory.py
index 18e9ef6..234141b 100644
--- a/configs/ruby/MOESI_CMP_directory.py
+++ b/configs/ruby/MOESI_CMP_directory.py
@@ -212,6 +212,7 @@
dir_cntrl.forwardFromDir = MessageBuffer()
dir_cntrl.forwardFromDir.master = ruby_system.network.slave
dir_cntrl.responseFromMemory = MessageBuffer()
+dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
for i, dma_port in enumerate(dma_ports):
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
index d7b175c..a29fb5c 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
@@ -74,19 +74,20 @@
I, AccessPermission:Invalid, desc="Idle";
S, AccessPermission:Read_Only, desc="Shared";
O, AccessPermission:Read_Only, desc="Owned";
-M, AccessPermission:Read_Only, desc="Modified (dirty)";
-M_W, AccessPermission:Read_Only, desc="Modified (dirty)";
+M, AccessPermission:Read_Write, desc="Modified (dirty)";
+M_W, AccessPermission:Read_Write, desc="Modified (dirty)";
MM, AccessPermission:Read_Write, desc="Modified (dirty and locally
modified)";
MM_W, AccessPermission:Read_Write, desc="Modified (dirty and locally
modified)";
// Transient States
+// Notice we still have a valid copy of the block in most states
IM, AccessPermission:Busy, "IM", desc="Issued GetX";
+IS, AccessPermission:Busy, "IS", desc="Issued GetS";
SM, AccessPermission:Read_Only, "SM", desc="Issued GetX, we still have
an old copy of the line";
OM, AccessPermission:Read_Only, "SM", desc="Issued GetX, received
data";
-IS, AccessPermission:Busy, "IS", desc="Issued GetS";
-SI, AccessPermission:Busy, "OI", desc="Issued PutS, waiting for ack";
-OI, AccessPermission:Busy, "OI", desc="Issued PutO, waiting for ack";
-MI, AccessPermission:Busy, "MI", desc="Issued PutX, waiting for ack";
+SI, AccessPermission:Read_Only, "OI", desc="Issued PutS, waiting for
ack";
+OI, AccessPermission:Read_Only, "OI", desc="Issued PutO, waiting for
ack";
+MI, AccessPermission:Read_Write, "MI", desc="Issued PutX, waiting for
ack";
II, AccessPermission:Busy, "II", desc="Issued PutX/O, saw Fwd_GETS or
Fwd_GETX, waiting for ack";
}
@@ -225,13 +226,13 @@
AccessPermission getAccessPermission(Addr addr) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
- DPRINTF(RubySlicc, "%s\n",
L1Cache_State_to_permission(tbe.TBEState));
+ DPRINTF(RubySlicc, "%s,%s\n", tbe.TBEState,
L1Cache_State_to_permission(tbe.TBEState));
return L1Cache_State_to_permission(tbe.TBEState);
}
Entry cache_entry := getCacheEntry(addr);
if(is_valid(cache_entry)) {
- DPRINTF(RubySlicc, "%s\n",
L1Cache_State_to_permission(cache_entry.CacheState));
+ DPRINTF(RubySlicc, "%s,%s\n", cache_entry.CacheState,
L1Cache_State_to_permission(cache_entry.CacheState));
return L1Cache_State_to_permission(cache_entry.CacheState);
}
@@ -270,8 +271,10 @@
}
TBE tbe := TBEs[addr];
-num_functional_writes := num_functional_writes +
-testAndWrite(addr, tbe.DataBlk, pkt);
+if (is_valid(tbe)){
+ num_functional_writes := num_functional_writes +
+ testAndWrite(addr, tbe.DataBlk, pkt);
+}
return num_functional_writes;
}
diff --git a/src/m
[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Fixed MOESI_CMP_directory resource tracking
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/21928 )
Change subject: mem-ruby: Fixed MOESI_CMP_directory resource tracking
..
mem-ruby: Fixed MOESI_CMP_directory resource tracking
Fixes a few resource allocation issues in the directory controller:
- Added TBE resource checks on allocation.
- Now also allocating a TBE when issuing read requests to the controller
to allow for a better response to backpressure. Without the TBE as a
limiting factor, the directory can have an unbounded amount of
outstanding memory requests.
- Also allocating a TBE for forwarded requests.
Change-Id: I17016668bd64a50a4354baad5d181e6d3802ac46
Signed-off-by: Tiago Mück
---
M src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
M src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm
2 files changed, 31 insertions(+), 5 deletions(-)
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
index 7e64271..25738a1 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
@@ -456,6 +456,9 @@
action(d_sendDataMsg, "d", desc="Send data to requestor") {
peek(memQueue_in, MemoryMsg) {
+ // Not using tbe here, but we must have allocated on a memory
+ // request
+ assert(is_valid(tbe));
enqueue(responseNetwork_out, ResponseMsg, 1) {
out_msg.addr := address;
out_msg.Sender := machineID;
@@ -593,6 +596,7 @@
action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch
request") {
peek(requestQueue_in, RequestMsg) {
+ assert(is_valid(tbe));
queueMemoryRead(in_msg.Requestor, address,
to_memory_controller_latency);
}
}
@@ -680,6 +684,7 @@
}
action(v_allocateTBE, "v", desc="Allocate TBE entry") {
+check_allocate(TBEs);
peek (requestQueue_in, RequestMsg) {
assert(is_valid(tbe) == false);
TBEs.allocate(address);
@@ -705,12 +710,14 @@
// TRANSITIONS
transition(I, GETX, MM_M) {
allocDirEntry;
+v_allocateTBE;
qf_queueMemoryFetchRequest;
i_popIncomingRequestQueue;
}
transition(I, DMA_READ, XI_M) {
allocDirEntry;
+v_allocateTBE;
qf_queueMemoryFetchRequest;
i_popIncomingRequestQueue;
}
@@ -739,6 +746,7 @@
transition(XI_M, Memory_Data_DMA, I) {
d_sendDataMsg; // ack count may be zero
deallocDirEntry;
+w_deallocateTBE;
q_popMemQueue;
}
@@ -763,6 +771,7 @@
}
transition(S, GETX, MM_M) {
+v_allocateTBE;
qf_queueMemoryFetchRequest;
g_sendInvalidations;
i_popIncomingRequestQueue;
@@ -785,11 +794,19 @@
transition(I, GETS, IS_M) {
allocDirEntry;
+v_allocateTBE;
qf_queueMemoryFetchRequest;
i_popIncomingRequestQueue;
}
- transition({S, SS}, {GETS, DMA_READ}, SS) {
+ transition(S, {GETS, DMA_READ}, SS) {
+v_allocateTBE;
+qf_queueMemoryFetchRequest;
+n_incrementOutstanding;
+i_popIncomingRequestQueue;
+ }
+
+ transition(SS, {GETS, DMA_READ}) {
qf_queueMemoryFetchRequest;
n_incrementOutstanding;
i_popIncomingRequestQueue;
@@ -855,22 +872,26 @@
}
transition(M, GETS, MO) {
+v_allocateTBE;
f_forwardRequest;
i_popIncomingRequestQueue;
}
transition(M, PUTX, MI) {
+v_allocateTBE;
a_sendWriteBackAck;
i_popIncomingRequestQueue;
}
// happens if M->O transition happens on-chip
transition(M, PUTO, MI) {
+v_allocateTBE;
a_sendWriteBackAck;
i_popIncomingRequestQueue;
}
transition(M, PUTO_SHARERS, MIS) {
+v_allocateTBE;
a_sendWriteBackAck;
i_popIncomingRequestQueue;
}
@@ -891,12 +912,14 @@
}
transition({MM, MO}, Exclusive_Unblock, M) {
+w_deallocateTBE;
cc_clearSharers;
e_ownerIsUnblocker;
j_popIncomingUnblockQueue;
}
transition(MO, Unblock, O) {
+w_deallocateTBE;
m_addUnlockerToSharers;
j_popIncomingUnblockQueue;
}
@@ -910,11 +933,13 @@
}
transition(IS, Unblock, S) {
+w_deallocateTBE;
m_addUnlockerToSharers;
j_popIncomingUnblockQueue;
}
transition(IS, Exclusive_Unblock, M) {
+w_deallocateTBE;
cc_clearSharers;
e_ownerIsUnblocker;
j_popIncomingUnblockQueue;
@@ -927,6 +952,7 @@
}
transition(SS, Last_Unblock, S) {
+w_deallocateTBE;
m_addUnlockerToSharers;
o_decrementOutstanding;
j_popIncomingUnblockQueue;
@@ -947,7 +973,6 @@
transition(MI, Dirty_Writeback, WBI) {
c_clearOwner;
cc_clearSharers;
-v_allocateTBE;
qw_queueMemoryWBFromCacheRequest;
i_popIncomingRequestQueue;
}
@@ -961,13 +986,13 @@
transition(MIS, Dirty_Writeback, WBS) {
c_moveOwnerToSharer;
-v_allocateTBE;
qw_queueMemoryWBFromCacheRequest;
i_popIncomingRequestQueue;
}
transition(MIS, Clean_Writeback, S) {
c_moveOwnerToSh
[gem5-dev] Change in gem5/gem5[master]: mem-ruby: removed checkCoherence from MOESI_CMP_directory
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/21923 )
Change subject: mem-ruby: removed checkCoherence from MOESI_CMP_directory
..
mem-ruby: removed checkCoherence from MOESI_CMP_directory
The implementation is empty and this is not used by other protocols
Change-Id: Iaed7d6d4b7ef1eb4cd47bdc0710dc9dbb7a86a0c
Signed-off-by: Tiago Mück
---
M src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
M src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
M src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
3 files changed, 0 insertions(+), 11 deletions(-)
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
index b8d8ab4..d7b175c 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
@@ -215,7 +215,6 @@
((cache_entry.CacheState != State:O) && (state == State:O)) ) {
cache_entry.CacheState := state;
-sequencer.checkCoherence(addr);
}
else {
cache_entry.CacheState := state;
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
index b3a170e..a04f167 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
@@ -523,13 +523,6 @@
(state == State:SLS)) {
assert(is_valid(cache_entry));
assert(L2cache.isTagPresent(addr));
-
- if ( ((cache_entry.CacheState != State:M) && (state == State:M)) ||
- ((cache_entry.CacheState != State:S) && (state == State:S)) ||
- ((cache_entry.CacheState != State:O) && (state == State:O)) ) {
-// disable Coherence Checker for now
-// sequencer.checkCoherence(addr);
- }
} else if ( (state == State:ILS) ||
(state == State:ILX) ||
(state == State:ILO) ||
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
index e1c287e..85e7946 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
@@ -155,9 +155,6 @@
assert(getDirectoryEntry(addr).Sharers.count() == 0);
directory.deallocate(addr);
-
-// disable coherence checker
-// sequencer.checkCoherence(addr);
}
State getState(TBE tbe, Addr addr) {
--
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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Deallocating unused entries in MOESI_CMP_dir
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/21922 )
Change subject: mem-ruby: Deallocating unused entries in MOESI_CMP_dir
..
mem-ruby: Deallocating unused entries in MOESI_CMP_dir
Invalid entries are never removed from the directories in both the L2 and
Directory controllers. This patch fixes this by deallocating the entries
when they become invalid. The NP (not present) state was removed from
the L2 controller since it's now equivalent to Invalid.
Change-Id: Id807b341a2aadb06008491545aca614d5a09b8df
Signed-off-by: Tiago Mück
---
M src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
M src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
2 files changed, 161 insertions(+), 103 deletions(-)
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
index 18e3b89..b3a170e 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
@@ -66,14 +66,13 @@
state_declaration(State, desc="L2 Cache states",
default="L2Cache_State_I") {
// Stable states
-NP, AccessPermission:Invalid, desc="Not Present";
I, AccessPermission:Invalid, desc="Invalid";
-ILS, AccessPermission:Invalid, desc="Idle/NP, but local sharers exist";
-ILX, AccessPermission:Invalid, desc="Idle/NP, but local exclusive
exists";
-ILO, AccessPermission:Invalid, desc="Idle/NP, but local owner exists";
-ILOX, AccessPermission:Invalid, desc="Idle/NP, but local owner exists
and chip is exclusive";
-ILOS, AccessPermission:Invalid, desc="Idle/NP, but local owner exists
and local sharers as well";
-ILOSX, AccessPermission:Invalid, desc="Idle/NP, but local owner
exists, local sharers exist, chip is exclusive ";
+ILS, AccessPermission:Invalid, desc="Not present, but local sharers
exist";
+ILX, AccessPermission:Invalid, desc="Not present, but local exclusive
exists";
+ILO, AccessPermission:Invalid, desc="Not present, but local owner
exists";
+ILOX, AccessPermission:Invalid, desc="Not present, but local owner
exists and chip is exclusive";
+ILOS, AccessPermission:Invalid, desc="Not present, but local owner
exists and local sharers as well";
+ILOSX, AccessPermission:Invalid, desc="Not present, but local owner
exists, local sharers exist, chip is exclusive ";
S, AccessPermission:Read_Only, desc="Shared, no local sharers";
O, AccessPermission:Read_Only, desc="Owned, no local sharers";
OLS, AccessPermission:Read_Only, desc="Owned with local sharers";
@@ -324,11 +323,22 @@
void copyDirToCache(Entry cache_entry, Addr addr) {
assert(is_valid(cache_entry));
DirEntry dir_entry := getDirEntry(addr);
+assert(is_valid(dir_entry));
cache_entry.Sharers := dir_entry.Sharers;
cache_entry.Owner := dir_entry.Owner;
cache_entry.OwnerValid := dir_entry.OwnerValid;
}
+ bool isDirEntryClean(DirEntry dir_entry) {
+assert(is_valid(dir_entry));
+return (dir_entry.Sharers.count() == 0) &&
+ (dir_entry.OwnerValid == false);
+ }
+
+ bool isCacheEntryClean(Entry cache_entry) {
+return (cache_entry.Sharers.count() == 0) &&
+ (cache_entry.OwnerValid == false);
+ }
void recordLocalSharerInDir(Entry cache_entry, Addr addr, MachineID
shar_id) {
if (is_valid(cache_entry)) {
@@ -478,7 +488,6 @@
}
State getState(TBE tbe, Entry cache_entry, Addr addr) {
-
if (is_valid(tbe)) {
return tbe.TBEState;
} else if (is_valid(cache_entry)) {
@@ -487,7 +496,7 @@
DirEntry dir_entry := getDirEntry(addr);
return dir_entry.DirState;
} else {
- return State:NP;
+ return State:I;
}
}
@@ -496,50 +505,53 @@
}
void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
+// Consistency checks
+
+// Either on the the cache, directory, or invalid
assert((localDirectory.isTagPresent(addr) &&
L2cache.isTagPresent(addr)) == false);
+if (state == State:I) {
+ assert(L2cache.isTagPresent(addr) == false);
+ assert(is_valid(cache_entry) == false);
+ assert(localDirectory.isTagPresent(addr) == false);
+} else if ( (state == State:M) ||
+(state == State:O) ||
+(state == State:S) ||
+(state == State:OLS) ||
+(state == State:SLS) ||
+(state == State:OLSX) ||
+(state == State:SLS)) {
+ assert(is_valid(cache_entry));
+ assert(L2cache.isTagPresent(addr));
+
+ if ( ((cache_entry.CacheState != State:M) && (state == State:M)) ||
+ ((cache_entry.CacheState != State:S) && (state == State:S)) ||
+ ((cache_entry.CacheState != State:O) && (state == State:O)) ) {
+// disable Coherence Checker for now
+// sequencer.checkCoherence(addr);
+
[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Fix MOESI_CMP_directory DMA handling
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/21926 )
Change subject: mem-ruby: Fix MOESI_CMP_directory DMA handling
..
mem-ruby: Fix MOESI_CMP_directory DMA handling
This patch fixes some issues in the directory controller regarding DMA
handling:
1) Junk data messages were being sent immediately in response to DMA reads
for a line in the S state (one or more sharers, clean). Now, data is
fetched from memory directly and forwarded to the device. Some existing
transitions for handling GETS requests are reused, since it's essentially
the same behavior (except we don't update the list of sharers for DMAs)
2) DMA writes for lines in the I or S states would always overwrite the
whole line. We now check if it's only a partial line write, in which case
we fetch the line from memory, update it, and writeback.
3) Fixed incorrect DMA msg size
Some existing functions were renamed for clarity.
Change-Id: I759344ea4136cd11c3a52f9eaab2e8ce678edd04
Signed-off-by: Tiago Mück
---
M src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
M src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm
M src/mem/ruby/protocol/RubySlicc_Types.sm
3 files changed, 107 insertions(+), 59 deletions(-)
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
index 39de654..63a6bc0 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
@@ -75,8 +75,9 @@
OS, AccessPermission:Busy, desc="Blocked on a writeback";
OSS, AccessPermission:Busy, desc="Blocked on a writeback, but don't
remove from sharers when received";
-XI_M, AccessPermission:Busy, desc="In a stable state, going to I,
waiting for the memory controller";
-XI_U, AccessPermission:Busy, desc="In a stable state, going to I,
waiting for an unblock";
+XI_M, AccessPermission:Busy, desc="Blocked, going to I, waiting for
the memory controller";
+XI_M_U, AccessPermission:Busy, desc="Blocked, going to XI_U, waiting
for the memory controller";
+XI_U, AccessPermission:Busy, desc="Blocked, going to I, waiting for an
unblock";
OI_D, AccessPermission:Busy, desc="In O, going to I, waiting for data";
OD, AccessPermission:Busy, desc="In O, waiting for dma ack from L2";
@@ -95,10 +96,12 @@
Exclusive_Unblock, desc="The processor become the exclusive owner (E
or M) of the line";
Clean_Writeback, desc="The final message as part of a PutX/PutS, no
data";
Dirty_Writeback, desc="The final message as part of a PutX/PutS,
contains data";
-Memory_Data, desc="Fetched data from memory arrives";
+Memory_Data_DMA, desc="Fetched data from memory arrives; original
requestor is DMA";
+Memory_Data_Cache, desc="Fetched data from memory arrives; original
requestor is Cache";
Memory_Ack,desc="Writeback Ack from memory arrives";
DMA_READ, desc="DMA Read";
-DMA_WRITE, desc="DMA Write";
+DMA_WRITE_LINE,desc="DMA Write full line";
+DMA_WRITE_PARTIAL, desc="DMA Write partial line";
DMA_ACK, desc="DMA Ack";
Data, desc="Data to directory";
}
@@ -127,6 +130,8 @@
bool isPresent(Addr);
}
+ int blockSize, default="RubySystem::getBlockSizeBytes()";
+
// ** OBJECTS **
TBETable TBEs, template="",
constructor="m_number_of_TBEs";
@@ -262,6 +267,9 @@
out_port(forwardNetwork_out, RequestMsg, forwardFromDir);
out_port(responseNetwork_out, ResponseMsg, responseFromDir);
+ // For inserting internal unblocks only
+ out_port(unblockNetwork_out_internal, ResponseMsg, responseToDir);
+
// ** IN_PORTS **
in_port(unblockNetwork_in, ResponseMsg, responseToDir, rank=2) {
@@ -314,8 +322,13 @@
trigger(Event:DMA_READ, makeLineAddress(in_msg.addr),
TBEs[makeLineAddress(in_msg.addr)]);
} else if (in_msg.Type == CoherenceRequestType:DMA_WRITE) {
- trigger(Event:DMA_WRITE, makeLineAddress(in_msg.addr),
+ if (in_msg.Len == blockSize) {
+assert(makeLineAddress(in_msg.addr) == in_msg.addr);
+trigger(Event:DMA_WRITE_LINE, in_msg.addr, TBEs[in_msg.addr]);
+ } else {
+trigger(Event:DMA_WRITE_PARTIAL, makeLineAddress(in_msg.addr),
TBEs[makeLineAddress(in_msg.addr)]);
+ }
} else {
error("Invalid message");
}
@@ -328,7 +341,11 @@
if (memQueue_in.isReady(clockEdge())) {
peek(memQueue_in, MemoryMsg) {
if (in_msg.Type == MemoryRequestType:MEMORY_READ) {
- trigger(Event:Memory_Data, in_msg.addr, TBEs[in_msg.addr]);
+ if (in_msg.OriginalRequestorMachId.getType() ==
MachineType:L2Cache){
+trigger(Event:Memory_Data_Cache, in_msg.addr,
TBEs[in_msg.addr]);
+ } else {
+trigger(Event:Memory_Data_DMA, i
[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Check on PerfectCacheMemory deallocate
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/21921 )
Change subject: mem-ruby: Check on PerfectCacheMemory deallocate
..
mem-ruby: Check on PerfectCacheMemory deallocate
Allowing deallocate to be called for non-existing blocks may hide
potential bugs.
Change-Id: Ida77e2db1da59d7cdb21d58968e1f17e75eaa6e0
Signed-off-by: Tiago Mück
---
M src/mem/ruby/structures/PerfectCacheMemory.hh
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/src/mem/ruby/structures/PerfectCacheMemory.hh
b/src/mem/ruby/structures/PerfectCacheMemory.hh
index 363e3e8..9898995 100644
--- a/src/mem/ruby/structures/PerfectCacheMemory.hh
+++ b/src/mem/ruby/structures/PerfectCacheMemory.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
* All rights reserved.
*
@@ -138,7 +150,8 @@
inline void
PerfectCacheMemory::deallocate(Addr address)
{
-m_map.erase(makeLineAddress(address));
+auto num_erased M5_VAR_USED = m_map.erase(makeLineAddress(address));
+assert(num_erased == 1);
}
// Returns with the physical address of the conflicting cache line
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/21921
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ida77e2db1da59d7cdb21d58968e1f17e75eaa6e0
Gerrit-Change-Number: 21921
Gerrit-PatchSet: 1
Gerrit-Owner: Tiago Mück
Gerrit-MessageType: newchange
___
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[gem5-dev] Change in gem5/gem5[master]: tests: Added GTests for base/bitfield.hh
Bobby R. Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/21700 )
Change subject: tests: Added GTests for base/bitfield.hh
..
tests: Added GTests for base/bitfield.hh
In addition to the tests, a more detailed explanation of how
"insertBits(..)" functions has been included in its doxygen
documentation. The previous explanation was ambigious and led to
confusion.
Change-Id: I2ae8608733ebaa8f8f726cbb3a2cd8639b69c6b7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21700
Tested-by: kokoro
Reviewed-by: Gabe Black
Reviewed-by: Daniel Carvalho
Maintainer: Jason Lowe-Power
---
M src/base/SConscript
M src/base/bitfield.hh
A src/base/bitfield.test.cc
3 files changed, 418 insertions(+), 1 deletion(-)
Approvals:
Gabe Black: Looks good to me, but someone else must approve
Daniel Carvalho: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/SConscript b/src/base/SConscript
index 89a8dce..ca81822 100644
--- a/src/base/SConscript
+++ b/src/base/SConscript
@@ -37,6 +37,7 @@
Source('atomicio.cc')
GTest('atomicio.test', 'atomicio.test.cc', 'atomicio.cc')
Source('bitfield.cc')
+GTest('bitfield.test', 'bitfield.test.cc', 'bitfield.cc')
Source('imgwriter.cc')
Source('bmpwriter.cc')
Source('callback.cc')
diff --git a/src/base/bitfield.hh b/src/base/bitfield.hh
index f289396..08e3d2c 100644
--- a/src/base/bitfield.hh
+++ b/src/base/bitfield.hh
@@ -117,7 +117,14 @@
}
/**
- * Return val with bits first to last set to bit_val
+ * Returns val with bits first to last set to the LSBs of bit_val
+ *
+ * E.g.:
+ * first: 7
+ * last: 4
+ * val: 0x
+ * bit_val: 0x
+ * returned: 0xFF0F
*/
template
inline
diff --git a/src/base/bitfield.test.cc b/src/base/bitfield.test.cc
new file mode 100644
index 000..0ee2a51
--- /dev/null
+++ b/src/base/bitfield.test.cc
@@ -0,0 +1,409 @@
+/*
+ * Copyright (c) 2019 The Regents of the University of California
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Bobby R. Bruce
+ */
+
+#include
+
+#include "base/bitfield.hh"
+
+/*
+ * The following tests the "mask(N)" function. It is assumed that the mask
+ * returned is a 64 bit value with the N LSBs set to one.
+ */
+TEST(BitfieldTest, Mask0Bits)
+{
+EXPECT_EQ(0x0, mask(0));
+}
+
+TEST(BitfieldTest, Mask1Bit)
+{
+EXPECT_EQ(0x1, mask(1));
+}
+
+TEST(BitfieldTest, Mask8Bits)
+{
+EXPECT_EQ(0xFF, mask(8));
+}
+
+TEST(BitfieldTest, Mask16Bits)
+{
+EXPECT_EQ(0x, mask(16));
+}
+
+TEST(BitfieldTest, Mask32Bits)
+{
+EXPECT_EQ(0x, mask(32));
+}
+
+TEST(BitfieldTest, MaskAllBits)
+{
+EXPECT_EQ(0x, mask(64));
+}
+
+TEST(BitfieldTest, MaskAllBitsGreaterThan64)
+{
+/* We cannot create a mask greater than 64 bits. It should default to
64
+ * b
[gem5-dev] Change in gem5/gem5[master]: arch: Get rid of the unused GenericTLB.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/21841 )
Change subject: arch: Get rid of the unused GenericTLB.
..
arch: Get rid of the unused GenericTLB.
Nothing is using it, and it's actually not use*able* at the moment
because it doesn't have implementations for all the pure virtual
methods that exist in the BaseTLB class.
Change-Id: I03d47c2e116f354c7247a2fa19a9f33dfe4c5eec
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21841
Reviewed-by: Jason Lowe-Power
Reviewed-by: Andreas Sandberg
Maintainer: Jason Lowe-Power
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/arch/generic/SConscript
D src/arch/generic/tlb.cc
M src/arch/generic/tlb.hh
3 files changed, 0 insertions(+), 94 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/generic/SConscript b/src/arch/generic/SConscript
index 7123eaf..0fc5e74 100644
--- a/src/arch/generic/SConscript
+++ b/src/arch/generic/SConscript
@@ -45,7 +45,6 @@
Source('decode_cache.cc')
Source('mmapped_ipr.cc')
-Source('tlb.cc')
SimObject('BaseTLB.py')
SimObject('ISACommon.py')
diff --git a/src/arch/generic/tlb.cc b/src/arch/generic/tlb.cc
deleted file mode 100644
index aebdd4b..000
--- a/src/arch/generic/tlb.cc
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright (c) 2001-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#include "arch/generic/tlb.hh"
-
-#include "cpu/thread_context.hh"
-#include "mem/page_table.hh"
-#include "sim/faults.hh"
-#include "sim/full_system.hh"
-#include "sim/process.hh"
-
-Fault
-GenericTLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode)
-{
-if (FullSystem)
-panic("Generic translation shouldn't be used in full system
mode.\n");
-
-Process * p = tc->getProcessPtr();
-
-Fault fault = p->pTable->translate(req);
-if (fault != NoFault)
-return fault;
-
-return NoFault;
-}
-
-void
-GenericTLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
-Translation *translation, Mode mode)
-{
-assert(translation);
-translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
-}
-
-Fault
-GenericTLB::finalizePhysical(const RequestPtr &req, ThreadContext *tc,
- Mode mode) const
-{
-return NoFault;
-}
-
-void
-GenericTLB::demapPage(Addr vaddr, uint64_t asn)
-{
-warn("Demapping pages in the generic TLB is unnecessary.\n");
-}
diff --git a/src/arch/generic/tlb.hh b/src/arch/generic/tlb.hh
index 8aab513..09438a7 100644
--- a/src/arch/generic/tlb.hh
+++ b/src/arch/generic/tlb.hh
@@ -141,24 +141,4 @@
void memInvalidate() { flushAll(); }
};
-class GenericTLB : public BaseTLB
-{
- protected:
-GenericTLB(const Params *p)
-: BaseTLB(p)
-{}
-
- public:
-void demapPage(Addr vaddr, uint64_t asn) override;
-
-Fault translateAtomic(
-const RequestPtr &req, ThreadContext *tc, Mode mode) override;
-void translateTiming(
-const RequestPtr &req, ThreadContext *tc,
-Translation *translation, Mode mode) override;
-
-Fault finalizePhysical(
-const RequestPtr &req, ThreadContext *tc, Mode mode) const
override;
[gem5-dev] Change in gem5/gem5[master]: cpu: Turn the stage 2 ARM MMUs from params to children.
Gabe Black has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/21839 ) Change subject: cpu: Turn the stage 2 ARM MMUs from params to children. .. cpu: Turn the stage 2 ARM MMUs from params to children. These aren't referred to in the C++, so there's no reason for them to be parameters. By making them children, they can still be modified, replaced wholesale, or even replaced by an entirely different object to, for instance, mask them when they're not needed. Change-Id: Ic7f144a3cd3d1fca12fec220918aa72af885f61c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21839 Reviewed-by: Jason Lowe-Power Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg Tested-by: kokoro --- M src/cpu/BaseCPU.py 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved Andreas Sandberg: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 85e3777..143ee92 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -182,8 +182,8 @@ dtb = Param.BaseTLB(ArchDTB(), "Data TLB") itb = Param.BaseTLB(ArchITB(), "Instruction TLB") if buildEnv['TARGET_ISA'] == 'arm': -istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans") -dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans") +istage2_mmu = ArmStage2IMMU() +dstage2_mmu = ArmStage2DMMU() elif buildEnv['TARGET_ISA'] == 'power': UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") interrupts = ArchInterruptsParam([], "Interrupt Controller") -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/21839 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ic7f144a3cd3d1fca12fec220918aa72af885f61c Gerrit-Change-Number: 21839 Gerrit-PatchSet: 2 Gerrit-Owner: Gabe Black Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: x86: Turn the local APIC Interrupts class into a SimObject.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/20829 )
Change subject: x86: Turn the local APIC Interrupts class into a SimObject.
..
x86: Turn the local APIC Interrupts class into a SimObject.
It will no longer be a PioDevice or a ClockedObject, but will carry
forward the little bits and pieces of those classes that it was using.
Those are a PIO port for memory mapped register accesses, and a clock
domain parameter for setting the apic tick frequency.
This brings the x86 Interrupts class in line with the Interrupts of the
other ISAs so that they can inherit from a standard base class.
Change-Id: I6b25fa21911b39a756e0cf9408c5489a81d6ca56
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20829
Reviewed-by: Jason Lowe-Power
Reviewed-by: Brandon Potter
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/x86/X86LocalApic.py
M src/arch/x86/interrupts.cc
M src/arch/x86/interrupts.hh
3 files changed, 29 insertions(+), 19 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Brandon Potter: Looks good to me, but someone else must approve
kokoro: Regressions pass
diff --git a/src/arch/x86/X86LocalApic.py b/src/arch/x86/X86LocalApic.py
index 456409a..914f297 100644
--- a/src/arch/x86/X86LocalApic.py
+++ b/src/arch/x86/X86LocalApic.py
@@ -42,10 +42,10 @@
from m5.params import *
from m5.proxy import *
-from m5.objects.Device import PioDevice
from m5.objects.ClockDomain import DerivedClockDomain
+from m5.SimObject import SimObject
-class X86LocalApic(PioDevice):
+class X86LocalApic(SimObject):
type = 'X86LocalApic'
cxx_class = 'X86ISA::Interrupts'
cxx_header = 'arch/x86/interrupts.hh'
@@ -53,6 +53,8 @@
int_slave = SlavePort("Port for receiving interrupt messages")
int_latency = Param.Latency('1ns', \
"Latency for an interrupt to propagate through this device.")
+pio = SlavePort("Programmed I/O port")
+system = Param.System(Parent.any, "System this device is part of")
pio_latency = Param.Latency('100ns', 'Programmed IO latency')
@@ -60,5 +62,6 @@
# which we assume is 1/16th the rate of the CPU clock. I don't think
this
# is a hard rule, but seems to be true in practice. This can be
overriden
# in configs that use it.
-clk_domain = DerivedClockDomain(
-clk_domain=Parent.clk_domain, clk_divider=16)
+clk_domain = Param.DerivedClockDomain(
+DerivedClockDomain(clk_domain=Parent.clk_domain,
clk_divider=16),
+"The clock for the local APIC. Should not be modified.")
diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc
index 14bdc0f..d237366 100644
--- a/src/arch/x86/interrupts.cc
+++ b/src/arch/x86/interrupts.cc
@@ -290,16 +290,13 @@
void
X86ISA::Interrupts::init()
{
-//
-// The local apic must register its address ranges on its pio
-// port via the basicpiodevice(piodevice) init() function.
-PioDevice::init();
-
-// The slave port has a range, so inform the connected master.
-intSlavePort.sendRangeChange();
-// If the master port isn't connected, we can't send interrupts
anywhere.
panic_if(!intMasterPort.isConnected(),
"Int port not connected to anything!");
+panic_if(!pioPort.isConnected(),
+"Pio port of %s not connected to anything!", name());
+
+intSlavePort.sendRangeChange();
+pioPort.sendRangeChange();
}
@@ -599,7 +596,7 @@
X86ISA::Interrupts::Interrupts(Params * p)
-: PioDevice(p),
+: SimObject(p), sys(p->system), clockDomain(*p->clk_domain),
apicTimerEvent([this]{ processApicTimerEvent(); }, name()),
pendingSmi(false), smiVector(0),
pendingNmi(false), nmiVector(0),
@@ -610,7 +607,7 @@
pendingIPIs(0), cpu(NULL),
intSlavePort(name() + ".int_slave", this, this),
intMasterPort(name() + ".int_master", this, this, p->int_latency),
- pioDelay(p->pio_latency)
+ pioPort(this), pioDelay(p->pio_latency)
{
memset(regs, 0, sizeof(regs));
//Set the local apic DFR to the flat model.
diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh
index 3d6ef1f..519d9f1 100644
--- a/src/arch/x86/interrupts.hh
+++ b/src/arch/x86/interrupts.hh
@@ -72,9 +72,12 @@
ApicRegIndex decodeAddr(Addr paddr);
-class Interrupts : public PioDevice
+class Interrupts : public SimObject
{
protected:
+System *sys;
+ClockDomain &clockDomain;
+
// Storage for the APIC registers
uint32_t regs[NUM_APIC_REGS];
@@ -165,6 +168,8 @@
return bits(regs[base + (vector / 32)], vector % 32);
}
+Tick clockPeriod() const { return clockDomain.clockPeriod(); }
+
void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool
level);
BaseCPU *cpu;
@@ -175,6 +180,9 @@
IntSlavePort intSlavePort;
IntMasterPort int
[gem5-dev] Change in gem5/gem5[master]: base, tests: Change assumption about AddrRange size
Brandon Potter has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/21939 )
Change subject: base,tests: Change assumption about AddrRange size
..
base,tests: Change assumption about AddrRange size
This changeset fixes an off-by-one error in the size method. An
empty AddrRange (i.e. start and end are equal) would return a
size of 1 even though the end is non-inclusive (according to
doxygen comments).
The changeset also adds two unit tests.
Change-Id: I4bed6e633a4693bd6eaea7624f7f83d1b1165b10
---
M src/base/addr_range.hh
M src/base/addr_range.test.cc
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/src/base/addr_range.hh b/src/base/addr_range.hh
index cda6ccf..63647c6 100644
--- a/src/base/addr_range.hh
+++ b/src/base/addr_range.hh
@@ -281,7 +281,7 @@
*/
Addr size() const
{
-return (_end - _start + 1) >> masks.size();
+return (_end - _start) >> masks.size();
}
/**
diff --git a/src/base/addr_range.test.cc b/src/base/addr_range.test.cc
index 54eb198..3bef430 100644
--- a/src/base/addr_range.test.cc
+++ b/src/base/addr_range.test.cc
@@ -42,6 +42,18 @@
#include "base/addr_range.hh"
#include "base/bitfield.hh"
+TEST(AddrRange, ValidRange)
+{
+AddrRange r;
+EXPECT_FALSE(r.valid());
+}
+
+TEST(AddrRange, EmptyRange)
+{
+AddrRange r(0x0, 0x0);
+EXPECT_EQ(0, r.size());
+}
+
TEST(AddrRangeComp, AddrRangeIsSubset)
{
AddrRange r, r1, r2;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/21939
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I4bed6e633a4693bd6eaea7624f7f83d1b1165b10
Gerrit-Change-Number: 21939
Gerrit-PatchSet: 1
Gerrit-Owner: Brandon Potter
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: tests: Added GTests for base/atomicio.cc
Bobby R. Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/21699 )
Change subject: tests: Added GTests for base/atomicio.cc
..
tests: Added GTests for base/atomicio.cc
Change-Id: I586a06c70f4e7331b4a31208ef7831e8473509c5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21699
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/base/SConscript
A src/base/atomicio.test.cc
2 files changed, 127 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/SConscript b/src/base/SConscript
index 129110f..89a8dce 100644
--- a/src/base/SConscript
+++ b/src/base/SConscript
@@ -35,6 +35,7 @@
Source('cp_annotate.cc')
SimObject('Graphics.py')
Source('atomicio.cc')
+GTest('atomicio.test', 'atomicio.test.cc', 'atomicio.cc')
Source('bitfield.cc')
Source('imgwriter.cc')
Source('bmpwriter.cc')
diff --git a/src/base/atomicio.test.cc b/src/base/atomicio.test.cc
new file mode 100644
index 000..d192ab5
--- /dev/null
+++ b/src/base/atomicio.test.cc
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2019 The Regents of the University of California
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Bobby R. Bruce
+ */
+
+#include
+#include
+
+#include
+
+#include "base/atomicio.hh"
+
+/*
+ * This will test reading from a file with a buffer capable of storing the
+ * entirity of the file.
+ */
+TEST(AtomicioTest, AtomicReadBigBuffer)
+{
+FILE* file;
+file = tmpfile();
+
+std::string file_contents = "This is just some test data to ensure
that we"
+" can read correctly from a file.";
+
+fputs(file_contents.c_str(), file);
+fflush(file);
+rewind(file);
+
+char s[1000];
+
+ssize_t size = atomic_read(fileno(file), s, 1000);
+fclose(file);
+
+EXPECT_EQ(file_contents.size(), size);
+for (unsigned int i = 0; i < size; i++) {
+EXPECT_EQ(file_contents[i], s[i]);
+}
+}
+
+/*
+ * This will test reading from a file using a buffer smaller than the file
+ * contents. The buffer should be filled and the remainder left unread.
+ */
+TEST(AtomicioTest, AtomicReadSmallBuffer)
+{
+FILE* file;
+file = tmpfile();
+
+std::string file_contents = "This is just some test data to ensure
that we"
+" can read correctly from a file.";
+
+fputs(file_contents.c_str(), file);
+fflush(file);
+rewind(file);
+
+char s[10];
+
+ssize_t size = atomic_read(fileno(file), s, 10);
+fclose(file);
+
+EXPECT_EQ(10, size);
+for (unsigned int i = 0; i < size; i++) {
+EXPECT_EQ(file_contents[i], s[i]);
+}
+}
+
+/*
+ * This tests writing a string to a file via the atomic_write function.
+ */
+TEST(Ato
[gem5-dev] Change in gem5/gem5[master]: misc: Add Giacomo Travaglini as an Arm maintainer
Andreas Sandberg has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/21899 ) Change subject: misc: Add Giacomo Travaglini as an Arm maintainer .. misc: Add Giacomo Travaglini as an Arm maintainer I have been delegating a lot of changes to Giacomo T for a long time, making him a de facto Arm co-maintainer. Make this official by adding him to the list of maintainers. Change-Id: I69c53316e2fc6ca162d07ac2d167ac2ae2b6bbee Signed-off-by: Andreas Sandberg --- M MAINTAINERS 1 file changed, 6 insertions(+), 0 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index a99a49b..4461f61 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -27,6 +27,7 @@ arch-alpha: arch-arm: Andreas Sandberg + Giacomo Travaglini arch-hsail: Tony Gutierrez arch-mips: @@ -54,6 +55,10 @@ dev-virtio: Andreas Sandberg +dev-arm: + Andreas Sandberg + Giacomo Travaglini + ext: Components external to gem5 gpu-compute: @@ -93,6 +98,7 @@ system-alpha: system-arm: Andreas Sandberg + Giacomo Travaglini tests: testing changes (not stats updates for tests. See stats:) Andreas Sandberg -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/21899 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I69c53316e2fc6ca162d07ac2d167ac2ae2b6bbee Gerrit-Change-Number: 21899 Gerrit-PatchSet: 1 Gerrit-Owner: Andreas Sandberg Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: base: Add classes that encapsulate a channel address
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/21600 )
Change subject: base: Add classes that encapsulate a channel address
..
base: Add classes that encapsulate a channel address
There are cases where the memory system needs to reason about
channel-local addresses. These are currently represented using the
Addr and AddrRange classes. This is not ideal since it doesn't provide
any type safety when working with global addresses and channel-local
addresses. This is particularly problematic when porting existing
components to work in multi-channel configurations.
This changeset introduces the new ChannelAddr and ChannelAddrRange
classes. These classes encapsulate channel-local addresses in a
contiguous address space. These can, for example, be used in a memory
controller to represent a flat address space when calculating timings
or in a sectored cache.
Change-Id: I45d4061ebc8507a10d0a4577b28796dc5ec7a469
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21600
Reviewed-by: Bobby R. Bruce
Reviewed-by: Daniel Carvalho
Reviewed-by: Nikos Nikoleris
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/base/SConscript
A src/base/channel_addr.cc
A src/base/channel_addr.hh
A src/base/channel_addr.test.cc
4 files changed, 324 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Nikos Nikoleris: Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/SConscript b/src/base/SConscript
index b4b381b..129110f 100644
--- a/src/base/SConscript
+++ b/src/base/SConscript
@@ -40,6 +40,7 @@
Source('bmpwriter.cc')
Source('callback.cc')
GTest('callback.test', 'callback.test.cc', 'callback.cc')
+Source('channel_addr.cc')
Source('cprintf.cc', add_tags='gtest lib')
GTest('cprintf.test', 'cprintf.test.cc')
Source('debug.cc')
@@ -90,6 +91,7 @@
GTest('addr_range.test', 'addr_range.test.cc')
GTest('addr_range_map.test', 'addr_range_map.test.cc')
GTest('bitunion.test', 'bitunion.test.cc')
+GTest('channel_addr.test', 'channel_addr.test.cc')
GTest('circlebuf.test', 'circlebuf.test.cc')
GTest('circular_queue.test', 'circular_queue.test.cc')
GTest('sat_counter.test', 'sat_counter.test.cc')
diff --git a/src/base/channel_addr.cc b/src/base/channel_addr.cc
new file mode 100644
index 000..c50f94c
--- /dev/null
+++ b/src/base/channel_addr.cc
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Sandberg
+ */
+
+#include "base/channel_addr.hh"
+
+#include "base/logging.hh"
+
+ChannelAddrRange::ChannelAddrRange(AddrRange ch_range, Addr start, Addr
end)
+
