[gem5-dev] Change in gem5/gem5[develop]: arm: Return whether a semihosting call was recognized/handled.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/25949 )
Change subject: arm: Return whether a semihosting call was
recognized/handled.
..
arm: Return whether a semihosting call was recognized/handled.
Change-Id: Ie2da812172fe2f9c1e2b5be95561863bd12920b1
---
M src/arch/arm/semihosting.cc
M src/arch/arm/semihosting.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
4 files changed, 18 insertions(+), 14 deletions(-)
diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index 08728ed..6e58556 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -153,21 +153,21 @@
tickShift);
}
-void
+bool
ArmSemihosting::call64(ThreadContext *tc, bool gem5_ops)
{
RegVal op = tc->readIntReg(ArmISA::INTREG_X0 & mask(32));
if (op > MaxStandardOp && !gem5_ops) {
unrecognizedCall(
tc, "Gem5 semihosting op (0x%x) disabled from here.", op);
-return;
+return false;
}
auto it = calls.find(op);
if (it == calls.end()) {
unrecognizedCall(
tc, "Unknown aarch64 semihosting call: op = 0x%x", op);
-return;
+return false;
}
const SemiCall = it->second;
@@ -175,23 +175,25 @@
auto err = call.call64(this, tc);
semiErrno = err.second;
DPRINTF(Semihosting, "\t ->: 0x%x, %i\n", err.first, err.second);
+
+return true;
}
-void
+bool
ArmSemihosting::call32(ThreadContext *tc, bool gem5_ops)
{
RegVal op = tc->readIntReg(ArmISA::INTREG_R0);
if (op > MaxStandardOp && !gem5_ops) {
unrecognizedCall(
tc, "Gem5 semihosting op (0x%x) disabled from here.", op);
-return;
+return false;
}
auto it = calls.find(op);
if (it == calls.end()) {
unrecognizedCall(
tc, "Unknown aarch32 semihosting call: op = 0x%x", op);
-return;
+return false;
}
const SemiCall = it->second;
@@ -199,6 +201,8 @@
auto err = call.call32(this, tc);
semiErrno = err.second;
DPRINTF(Semihosting, "\t ->: 0x%x, %i\n", err.first, err.second);
+
+return true;
}
void
diff --git a/src/arch/arm/semihosting.hh b/src/arch/arm/semihosting.hh
index 7b575c0..d45aa74 100644
--- a/src/arch/arm/semihosting.hh
+++ b/src/arch/arm/semihosting.hh
@@ -214,9 +214,9 @@
ArmSemihosting(const ArmSemihostingParams *p);
/** Perform an Arm Semihosting call from aarch64 code. */
-void call64(ThreadContext *tc, bool gem5_ops=false);
+bool call64(ThreadContext *tc, bool gem5_ops=false);
/** Perform an Arm Semihosting call from aarch32 code. */
-void call32(ThreadContext *tc, bool gem5_ops=false);
+bool call32(ThreadContext *tc, bool gem5_ops=false);
public: // SimObject and related interfaces
void serialize(CheckpointOut ) const override;
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 3cd8858..950caee 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -291,16 +291,16 @@
return FullSystem && getArmSystem(tc)->haveSemihosting();
}
-void
+bool
ArmSystem::callSemihosting64(ThreadContext *tc, bool gem5_ops)
{
-getArmSystem(tc)->semihosting->call64(tc, gem5_ops);
+return getArmSystem(tc)->semihosting->call64(tc, gem5_ops);
}
-void
+bool
ArmSystem::callSemihosting32(ThreadContext *tc, bool gem5_ops)
{
-getArmSystem(tc)->semihosting->call32(tc, gem5_ops);
+return getArmSystem(tc)->semihosting->call32(tc, gem5_ops);
}
ArmSystem *
diff --git a/src/arch/arm/system.hh b/src/arch/arm/system.hh
index b598977..e890d10 100644
--- a/src/arch/arm/system.hh
+++ b/src/arch/arm/system.hh
@@ -334,10 +334,10 @@
static bool haveSemihosting(ThreadContext *tc);
/** Make a Semihosting call from aarch64 */
-static void callSemihosting64(ThreadContext *tc, bool gem5_ops=false);
+static bool callSemihosting64(ThreadContext *tc, bool gem5_ops=false);
/** Make a Semihosting call from aarch32 */
-static void callSemihosting32(ThreadContext *tc, bool gem5_ops=false);
+static bool callSemihosting32(ThreadContext *tc, bool gem5_ops=false);
};
class GenericArmSystem : public ArmSystem
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie2da812172fe2f9c1e2b5be95561863bd12920b1
Gerrit-Change-Number: 25949
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arm: Make the semihosting implementation use GuestABI.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/25946 )
Change subject: arm: Make the semihosting implementation use GuestABI.
..
arm: Make the semihosting implementation use GuestABI.
Change-Id: Ie99e7d79c08c039384250fab0c98117554c93128
---
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/isa/insts/misc64.isa
M src/arch/arm/semihosting.cc
M src/arch/arm/semihosting.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
6 files changed, 532 insertions(+), 326 deletions(-)
diff --git a/src/arch/arm/isa/insts/misc.isa
b/src/arch/arm/isa/insts/misc.isa
index f0394be..197a9cd 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -43,7 +43,7 @@
const auto semihost_imm = Thumb? 0xAB : 0x123456;
if (ArmSystem::haveSemihosting(tc) && imm == semihost_imm) {
-R0 = ArmSystem::callSemihosting32(tc, R0, R1);
+ArmSystem::callSemihosting32(tc);
} else {
fault = std::make_shared(machInst, imm);
}
@@ -66,7 +66,7 @@
const auto semihost_imm = Thumb? 0x3C : 0xF000;
if (ArmSystem::haveSemihosting(tc) && imm == semihost_imm) {
-R0 = ArmSystem::callSemihosting32(tc, R0, R1);
+ArmSystem::callSemihosting32(tc);
} else {
// HLT instructions aren't implemented, so treat them as undefined
// instructions.
@@ -80,7 +80,7 @@
"predicate_test": predicateTest,
"thumb_semihost": '0x3C',
"arm_semihost": '0xF000' },
- ["IsNonSpeculative"])
+ ["IsNonSpeculative", "IsSerializeAfter"])
header_output += ImmOpDeclare.subst(hltIop)
decoder_output += SemihostConstructor.subst(hltIop)
exec_output += PredOpExecute.subst(hltIop)
diff --git a/src/arch/arm/isa/insts/misc64.isa
b/src/arch/arm/isa/insts/misc64.isa
index 88c68e6..e2cfb41 100644
--- a/src/arch/arm/isa/insts/misc64.isa
+++ b/src/arch/arm/isa/insts/misc64.isa
@@ -186,7 +186,7 @@
hltCode = '''
ThreadContext *tc = xc->tcBase();
if (ArmSystem::haveSemihosting(tc) && imm == 0xF000) {
-X0 = ArmSystem::callSemihosting64(tc, X0 & mask(32), X1);
+ArmSystem::callSemihosting64(tc);
} else {
// HLT instructions aren't implemented, so treat them as undefined
// instructions.
@@ -197,7 +197,7 @@
'''
hltIop = InstObjParams("hlt", "Hlt64", "ImmOp64",
- hltCode, ["IsNonSpeculative"])
+ hltCode,
["IsNonSpeculative", "IsSerializeAfter"])
header_output += ImmOp64Declare.subst(hltIop)
decoder_output += SemihostConstructor64.subst(hltIop)
exec_output += BasicExecute.subst(hltIop)
diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index 4f897e2..fa918d2 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -52,39 +52,37 @@
#include "sim/system.hh"
const std::map ArmSemihosting::calls{
-{ SYS_OPEN, { "SYS_OPEN", ::callOpen, 3, 3 } },
-{ SYS_CLOSE,{ "SYS_CLOSE", ::callClose, 1, 1 } },
-
-// Write(C|0) are special since we want to read the character
-// manually. We therefore declare them as having 0 params.
-{ SYS_WRITEC, { "SYS_WRITEC", ::callWriteC, 0, 0 } },
-{ SYS_WRITE0, { "SYS_WRITE0", ::callWrite0, 1, 1 } },
-
-{ SYS_WRITE,{ "SYS_WRITE", ::callWrite, 3, 3 } },
-{ SYS_READ, { "SYS_READ", ::callRead, 3, 3 } },
-{ SYS_READC,{ "SYS_READC", ::callReadC, 0, 0 } },
-{ SYS_ISERROR, { "SYS_ISERROR", ::callIsError, 1, 1 }
},
-{ SYS_ISTTY,{ "SYS_ISTTY", ::callIsTTY, 1, 1 } },
-{ SYS_SEEK, { "SYS_SEEK", ::callSeek, 2, 2 } },
-{ SYS_FLEN, { "SYS_FLEN", ::callFLen, 1, 1 } },
-{ SYS_TMPNAM, { "SYS_TMPNAM", ::callTmpNam, 3, 3 } },
-{ SYS_REMOVE, { "SYS_REMOVE", ::callRemove, 2, 2} },
-{ SYS_RENAME, { "SYS_RENAME", ::callRename, 4, 4} },
-{ SYS_CLOCK,{ "SYS_CLOCK", ::callClock, 0, 0} },
-{ SYS_TIME, { "SYS_TIME", ::callTime, 0, 0} },
-{ SYS_SYSTEM, { "SYS_SYSTEM", ::callSystem, 2, 2} },
-{ SYS_ERRNO,{ "SYS_ERRNO", ::callErrno, 0, 0 } },
+{ SYS_OPEN, { "SYS_OPEN", ::callOpen } },
+{ SYS_CLOSE,{ "SYS_CLOSE", ::callClose } },
+{ SYS_WRITEC, { "SYS_WRITEC", ::callWriteC } },
+{ SYS_WRITE0, { "SYS_WRITE0", ::callWrite0 } },
+{ SYS_WRITE,{ "SYS_WRITE", ::callWrite } },
+{ SYS_READ, { "SYS_READ", ::callRead } },
+{ SYS_READC,{ "SYS_READC", ::callReadC } },
+{ SYS_ISERROR, { "SYS_ISERROR", ::callIsError } },
+{ SYS_ISTTY,{ "SYS_ISTTY", ::callIsTTY } },
+{ SYS_SEEK, { "SYS_SEEK", ::callSeek } },
+{ SYS_FLEN, { "SYS_FLEN", ::callFLen } },
+{ SYS_TMPNAM, { "SYS_TMPNAM", ::callTmpNam } },
+{ SYS_REMOVE, {
[gem5-dev] Change in gem5/gem5[develop]: arm: Optionally enable gem5 extended semihosting calls.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/25947 )
Change subject: arm: Optionally enable gem5 extended semihosting calls.
..
arm: Optionally enable gem5 extended semihosting calls.
Change-Id: I34b01a4439c8a88242971ac486e34d810b054baf
---
M src/arch/arm/semihosting.cc
M src/arch/arm/semihosting.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
4 files changed, 20 insertions(+), 10 deletions(-)
diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index fa918d2..08728ed 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -154,9 +154,14 @@
}
void
-ArmSemihosting::call64(ThreadContext *tc)
+ArmSemihosting::call64(ThreadContext *tc, bool gem5_ops)
{
RegVal op = tc->readIntReg(ArmISA::INTREG_X0 & mask(32));
+if (op > MaxStandardOp && !gem5_ops) {
+unrecognizedCall(
+tc, "Gem5 semihosting op (0x%x) disabled from here.", op);
+return;
+}
auto it = calls.find(op);
if (it == calls.end()) {
@@ -173,9 +178,14 @@
}
void
-ArmSemihosting::call32(ThreadContext *tc)
+ArmSemihosting::call32(ThreadContext *tc, bool gem5_ops)
{
RegVal op = tc->readIntReg(ArmISA::INTREG_R0);
+if (op > MaxStandardOp && !gem5_ops) {
+unrecognizedCall(
+tc, "Gem5 semihosting op (0x%x) disabled from here.", op);
+return;
+}
auto it = calls.find(op);
if (it == calls.end()) {
diff --git a/src/arch/arm/semihosting.hh b/src/arch/arm/semihosting.hh
index fa070b6..7b575c0 100644
--- a/src/arch/arm/semihosting.hh
+++ b/src/arch/arm/semihosting.hh
@@ -214,9 +214,9 @@
ArmSemihosting(const ArmSemihostingParams *p);
/** Perform an Arm Semihosting call from aarch64 code. */
-void call64(ThreadContext *tc);
+void call64(ThreadContext *tc, bool gem5_ops=false);
/** Perform an Arm Semihosting call from aarch32 code. */
-void call32(ThreadContext *tc);
+void call32(ThreadContext *tc, bool gem5_ops=false);
public: // SimObject and related interfaces
void serialize(CheckpointOut ) const override;
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index e26dbc0..3cd8858 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -292,15 +292,15 @@
}
void
-ArmSystem::callSemihosting64(ThreadContext *tc)
+ArmSystem::callSemihosting64(ThreadContext *tc, bool gem5_ops)
{
-getArmSystem(tc)->semihosting->call64(tc);
+getArmSystem(tc)->semihosting->call64(tc, gem5_ops);
}
void
-ArmSystem::callSemihosting32(ThreadContext *tc)
+ArmSystem::callSemihosting32(ThreadContext *tc, bool gem5_ops)
{
-getArmSystem(tc)->semihosting->call32(tc);
+getArmSystem(tc)->semihosting->call32(tc, gem5_ops);
}
ArmSystem *
diff --git a/src/arch/arm/system.hh b/src/arch/arm/system.hh
index b712d56..b598977 100644
--- a/src/arch/arm/system.hh
+++ b/src/arch/arm/system.hh
@@ -334,10 +334,10 @@
static bool haveSemihosting(ThreadContext *tc);
/** Make a Semihosting call from aarch64 */
-static void callSemihosting64(ThreadContext *tc);
+static void callSemihosting64(ThreadContext *tc, bool gem5_ops=false);
/** Make a Semihosting call from aarch32 */
-static void callSemihosting32(ThreadContext *tc);
+static void callSemihosting32(ThreadContext *tc, bool gem5_ops=false);
};
class GenericArmSystem : public ArmSystem
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I34b01a4439c8a88242971ac486e34d810b054baf
Gerrit-Change-Number: 25947
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arm: Expose the constants which select a semihosting operation.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/25945 )
Change subject: arm: Expose the constants which select a semihosting
operation.
..
arm: Expose the constants which select a semihosting operation.
Give these constants meaningful names instead of opaque constants only
visible in the .cc file.
Change-Id: Ib88912dae79960f785099c236c337db52a69d563
---
M src/arch/arm/semihosting.cc
M src/arch/arm/semihosting.hh
2 files changed, 56 insertions(+), 24 deletions(-)
diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index e85fe7e..4f897e2 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -52,37 +52,39 @@
#include "sim/system.hh"
const std::map ArmSemihosting::calls{
-{ 0x01, { "SYS_OPEN", ::callOpen, 3, 3 } },
-{ 0x02, { "SYS_CLOSE", ::callClose, 1, 1 } },
+{ SYS_OPEN, { "SYS_OPEN", ::callOpen, 3, 3 } },
+{ SYS_CLOSE,{ "SYS_CLOSE", ::callClose, 1, 1 } },
// Write(C|0) are special since we want to read the character
// manually. We therefore declare them as having 0 params.
-{ 0x03, { "SYS_WRITEC", ::callWriteC, 0, 0 } },
-{ 0x04, { "SYS_WRITE0", ::callWrite0, 1, 1 } },
+{ SYS_WRITEC, { "SYS_WRITEC", ::callWriteC, 0, 0 } },
+{ SYS_WRITE0, { "SYS_WRITE0", ::callWrite0, 1, 1 } },
-{ 0x05, { "SYS_WRITE", ::callWrite, 3, 3 } },
-{ 0x06, { "SYS_READ", ::callRead, 3, 3 } },
-{ 0x07, { "SYS_READC", ::callReadC, 0, 0 } },
-{ 0x08, { "SYS_ISERROR", ::callIsError, 1, 1 } },
-{ 0x09, { "SYS_ISTTY", ::callIsTTY, 1, 1 } },
-{ 0x0A, { "SYS_SEEK", ::callSeek, 2, 2 } },
-{ 0x0C, { "SYS_FLEN", ::callFLen, 1, 1 } },
-{ 0x0D, { "SYS_TMPNAM", ::callTmpNam, 3, 3 } },
-{ 0x0E, { "SYS_REMOVE", ::callRemove, 2, 2} },
-{ 0x0F, { "SYS_RENAME", ::callRename, 4, 4} },
-{ 0x10, { "SYS_CLOCK", ::callClock, 0, 0} },
-{ 0x11, { "SYS_TIME", ::callTime, 0, 0} },
-{ 0x12, { "SYS_SYSTEM", ::callSystem, 2, 2} },
-{ 0x13, { "SYS_ERRNO", ::callErrno, 0, 0 } },
-{ 0x15, { "SYS_GET_CMDLINE", ::callGetCmdLine, 2, 2} },
-{ 0x16, { "SYS_HEAPINFO", ::callHeapInfo, 1, 1} },
+{ SYS_WRITE,{ "SYS_WRITE", ::callWrite, 3, 3 } },
+{ SYS_READ, { "SYS_READ", ::callRead, 3, 3 } },
+{ SYS_READC,{ "SYS_READC", ::callReadC, 0, 0 } },
+{ SYS_ISERROR, { "SYS_ISERROR", ::callIsError, 1, 1 }
},
+{ SYS_ISTTY,{ "SYS_ISTTY", ::callIsTTY, 1, 1 } },
+{ SYS_SEEK, { "SYS_SEEK", ::callSeek, 2, 2 } },
+{ SYS_FLEN, { "SYS_FLEN", ::callFLen, 1, 1 } },
+{ SYS_TMPNAM, { "SYS_TMPNAM", ::callTmpNam, 3, 3 } },
+{ SYS_REMOVE, { "SYS_REMOVE", ::callRemove, 2, 2} },
+{ SYS_RENAME, { "SYS_RENAME", ::callRename, 4, 4} },
+{ SYS_CLOCK,{ "SYS_CLOCK", ::callClock, 0, 0} },
+{ SYS_TIME, { "SYS_TIME", ::callTime, 0, 0} },
+{ SYS_SYSTEM, { "SYS_SYSTEM", ::callSystem, 2, 2} },
+{ SYS_ERRNO,{ "SYS_ERRNO", ::callErrno, 0, 0 } },
+{ SYS_GET_CMDLINE,
+{ "SYS_GET_CMDLINE", ::callGetCmdLine, 2, 2} },
+{ SYS_HEAPINFO, { "SYS_HEAPINFO", ::callHeapInfo, 1, 1}
},
// Exit is special and requires custom handling in aarch32.
-{ 0x18, { "SYS_EXIT", ::callExit, 0, 2 } },
-{ 0x20, { "SYS_EXIT_EXTENDED", ::callExitExtended, 2, 2
} },
+{ SYS_EXIT, { "SYS_EXIT", ::callExit, 0, 2 } },
+{ SYS_EXIT_EXTENDED,
+{ "SYS_EXIT_EXTENDED", ::callExitExtended, 2, 2 } },
-{ 0x30, { "SYS_ELAPSED", ::callElapsed, 0, 0 } },
-{ 0x31, { "SYS_TICKFREQ", ::callTickFreq, 0, 0 } },
+{ SYS_ELAPSED, { "SYS_ELAPSED", ::callElapsed, 0, 0 }
},
+{ SYS_TICKFREQ, { "SYS_TICKFREQ", ::callTickFreq, 0, 0
} },
};
const std::vector ArmSemihosting::fmodes{
diff --git a/src/arch/arm/semihosting.hh b/src/arch/arm/semihosting.hh
index 3b5b46e..104b479 100644
--- a/src/arch/arm/semihosting.hh
+++ b/src/arch/arm/semihosting.hh
@@ -68,6 +68,36 @@
class ArmSemihosting : public SimObject
{
public:
+
+enum Operation {
+SYS_OPEN = 0x01,
+SYS_CLOSE = 0x02,
+SYS_WRITEC = 0x03,
+SYS_WRITE0 = 0x04,
+SYS_WRITE = 0x05,
+SYS_READ = 0x06,
+SYS_READC = 0x07,
+SYS_ISERROR = 0x08,
+SYS_ISTTY = 0x09,
+SYS_SEEK = 0x0A,
+SYS_FLEN = 0x0C,
+SYS_TMPNAM = 0x0D,
+SYS_REMOVE = 0x0E,
+SYS_RENAME = 0x0F,
+SYS_CLOCK = 0x10,
+SYS_TIME = 0x11,
+SYS_SYSTEM = 0x12,
+SYS_ERRNO = 0x13,
+SYS_GET_CMDLINE = 0x15,
+SYS_HEAPINFO = 0x16,
+SYS_EXIT = 0x18,
+SYS_EXIT_EXTENDED = 0x20,
+SYS_ELAPSED = 0x30,
+SYS_TICKFREQ = 0x31,
+
+MaxStandardOp = 0xFF
+};
+
ArmSemihosting(const ArmSemihostingParams *p);
/** Perform an Arm Semihosting call from aarch64 code. */
--
To view, visit
[gem5-dev] Change in gem5/gem5[develop]: arch, sim: Return whether or not a pseudo inst was recognized.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/25948 )
Change subject: arch,sim: Return whether or not a pseudo inst was
recognized.
..
arch,sim: Return whether or not a pseudo inst was recognized.
Change-Id: I3e71c277f175c69af0d1adeb3299d88d095dfa84
---
M src/arch/arm/kvm/arm_cpu.cc
M src/arch/arm/mmapped_ipr.hh
M src/arch/x86/mmapped_ipr.hh
M src/sim/pseudo_inst.hh
4 files changed, 48 insertions(+), 37 deletions(-)
diff --git a/src/arch/arm/kvm/arm_cpu.cc b/src/arch/arm/kvm/arm_cpu.cc
index 02e6240..688cbd1 100644
--- a/src/arch/arm/kvm/arm_cpu.cc
+++ b/src/arch/arm/kvm/arm_cpu.cc
@@ -320,8 +320,8 @@
const uint8_t func((reg_ip >> 8) & 0xFF);
DPRINTF(Kvm, "KVM Hypercall: %#x/%#x\n", func, subfunc);
-const uint64_t ret =
-PseudoInst::pseudoInst(getContext(0), func);
+uint64_t ret;
+PseudoInst::pseudoInst(getContext(0), func, ret);
// Just set the return value using the KVM API instead of messing
// with the context. We could have used the context, but that
diff --git a/src/arch/arm/mmapped_ipr.hh b/src/arch/arm/mmapped_ipr.hh
index 7df6667..92b11dc 100644
--- a/src/arch/arm/mmapped_ipr.hh
+++ b/src/arch/arm/mmapped_ipr.hh
@@ -55,7 +55,8 @@
if (m5opRange.contains(addr)) {
uint8_t func;
PseudoInst::decodeAddrOffset(addr - m5opRange.start(), func);
-uint64_t ret = PseudoInst::pseudoInst(tc, func);
+uint64_t ret;
+PseudoInst::pseudoInst(tc, func, ret);
pkt->setLE(ret);
}
return Cycles(1);
@@ -68,8 +69,9 @@
auto m5opRange = tc->getSystemPtr()->m5opRange();
if (m5opRange.contains(addr)) {
uint8_t func;
+uint64_t ret;
PseudoInst::decodeAddrOffset(addr - m5opRange.start(), func);
-PseudoInst::pseudoInst(tc, func);
+PseudoInst::pseudoInst(tc, func, ret);
}
return Cycles(1);
}
diff --git a/src/arch/x86/mmapped_ipr.hh b/src/arch/x86/mmapped_ipr.hh
index 5b0a1e9..e2f0ccc 100644
--- a/src/arch/x86/mmapped_ipr.hh
+++ b/src/arch/x86/mmapped_ipr.hh
@@ -62,7 +62,8 @@
if (m5opRange.contains(addr)) {
uint8_t func;
PseudoInst::decodeAddrOffset(addr - m5opRange.start(), func);
-uint64_t ret = PseudoInst::pseudoInst(tc,
func);
+uint64_t ret;
+PseudoInst::pseudoInst(tc, func, ret);
pkt->setLE(ret);
} else {
Addr offset = addr & mask(3);
@@ -83,7 +84,8 @@
if (m5opRange.contains(addr)) {
uint8_t func;
PseudoInst::decodeAddrOffset(addr - m5opRange.start(), func);
-PseudoInst::pseudoInst(tc, func);
+uint64_t ret;
+PseudoInst::pseudoInst(tc, func, ret);
} else {
Addr offset = addr & mask(3);
MiscRegIndex index = (MiscRegIndex)(addr / sizeof(RegVal));
diff --git a/src/sim/pseudo_inst.hh b/src/sim/pseudo_inst.hh
index 9be742e..5b7a073 100644
--- a/src/sim/pseudo_inst.hh
+++ b/src/sim/pseudo_inst.hh
@@ -130,100 +130,109 @@
* manner using the ISA-specific getArguments functions.
*
* @param func M5 pseudo op major function number (see utility/m5/m5ops.h)
+ * @param result A reference to a uint64_t to store a result in.
+ * @return Whether the pseudo instruction was recognized/handled.
*/
template
-uint64_t
-pseudoInst(ThreadContext *tc, uint8_t func)
+bool
+pseudoInst(ThreadContext *tc, uint8_t func, uint64_t )
{
DPRINTF(PseudoInst, "PseudoInst::pseudoInst(%i)\n", func);
+result = 0;
+
switch (func) {
case M5OP_ARM:
invokeSimcall(tc, arm);
-break;
+return true;
case M5OP_QUIESCE:
invokeSimcall(tc, quiesce);
-break;
+return true;
case M5OP_QUIESCE_NS:
invokeSimcall(tc, quiesceNs);
-break;
+return true;
case M5OP_QUIESCE_CYCLE:
invokeSimcall(tc, quiesceCycles);
-break;
+return true;
case M5OP_QUIESCE_TIME:
-return invokeSimcall(tc, quiesceTime);
+result = invokeSimcall(tc, quiesceTime);
+return true;
case M5OP_RPNS:
-return invokeSimcall(tc, rpns);
+result = invokeSimcall(tc, rpns);
+return true;
case M5OP_WAKE_CPU:
invokeSimcall(tc, wakeCPU);
-break;
+return true;
case M5OP_EXIT:
invokeSimcall(tc, m5exit);
-break;
+return true;
case M5OP_FAIL:
invokeSimcall(tc, m5fail);
-break;
+return true;
case M5OP_INIT_PARAM:
-return invokeSimcall(tc, initParam);
+result = invokeSimcall(tc, initParam);
+return true;
case M5OP_LOAD_SYMBOL:
invokeSimcall(tc, loadsymbol);
-break;
+return true;
case M5OP_RESET_STATS:
invokeSimcall(tc, resetstats);
[gem5-dev] Change in gem5/gem5[develop]: arm: Add a gem5 specific pseudo op semihosting call.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/25950 )
Change subject: arm: Add a gem5 specific pseudo op semihosting call.
..
arm: Add a gem5 specific pseudo op semihosting call.
This is in the range of call numbers set aside for extensions. When
called, it will extract the function to use from the first argument
slot. Then it calls the pseudoInst dispatching function using an ABI
which drops the return value (which is handled by semihosting itself)
and which extracts arguments from the remaining slots in the param
structure.
Change-Id: Ic4817f2b1e6aad7784af77a1a494cf614d4d4c6c
---
M src/arch/arm/semihosting.cc
M src/arch/arm/semihosting.hh
2 files changed, 91 insertions(+), 1 deletion(-)
diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index 6e58556..c919b49 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -48,6 +48,7 @@
#include "mem/secure_port_proxy.hh"
#include "params/ArmSemihosting.hh"
#include "sim/byteswap.hh"
+#include "sim/pseudo_inst.hh"
#include "sim/sim_exit.hh"
#include "sim/system.hh"
@@ -83,6 +84,9 @@
{ SYS_ELAPSED, { "SYS_ELAPSED", ::callElapsed32,
::callElapsed64 } },
{ SYS_TICKFREQ, { "SYS_TICKFREQ", ::callTickFreq } },
+{ SYS_GEM5_PSEUDO_OP,
+{ "SYS_GEM5_PSEUDO_OP", ::callGem5PseudoOp32,
+::callGem5PseudoOp64 } },
};
const std::vector ArmSemihosting::fmodes{
@@ -651,6 +655,87 @@
return retOK(semiTick(SimClock::Frequency));
}
+
+struct SemiPseudoAbi32 : public ArmSemihosting::Abi32
+{
+class Position : public ArmSemihosting::Abi32::Position
+{
+ public:
+Position(const ThreadContext *tc) :
ArmSemihosting::Abi32::Position(tc)
+{
+// Use getAddr() to skip the func number in the first slot.
+getAddr();
+}
+};
+};
+
+struct SemiPseudoAbi64 : public ArmSemihosting::Abi64
+{
+class Position : public ArmSemihosting::Abi64::Position
+{
+ public:
+Position(const ThreadContext *tc) :
ArmSemihosting::Abi64::Position(tc)
+{
+// Use getAddr() to skip the func number in the first slot.
+getAddr();
+}
+};
+};
+
+namespace GuestABI
+{
+
+// Ignore return values since those will be handled by semihosting.
+template
+struct Result
+{
+static void store(ThreadContext *tc, const T ) {}
+};
+template
+struct Result
+{
+static void store(ThreadContext *tc, const T ) {}
+};
+
+// Handle arguments the same as for semihosting operations. Skipping the
first
+// slot is handled internally by the Position type.
+template
+struct Argument :
+public Argument
+{};
+template
+struct Argument :
+public Argument
+{};
+
+} // namespace GuestABI
+
+ArmSemihosting::RetErrno
+ArmSemihosting::callGem5PseudoOp32(ThreadContext *tc, uint32_t
encoded_func)
+{
+uint8_t func;
+PseudoInst::decodeAddrOffset(encoded_func, func);
+
+uint64_t ret;
+if (PseudoInst::pseudoInst(tc, func, ret))
+return retOK(ret);
+else
+return retError(EINVAL);
+}
+
+ArmSemihosting::RetErrno
+ArmSemihosting::callGem5PseudoOp64(ThreadContext *tc, uint64_t
encoded_func)
+{
+uint8_t func;
+PseudoInst::decodeAddrOffset(encoded_func, func);
+
+uint64_t ret;
+if (PseudoInst::pseudoInst(tc, func, ret))
+return retOK(ret);
+else
+return retError(EINVAL);
+}
+
FILE *
ArmSemihosting::getSTDIO(const char *stream_name,
const std::string , const char *mode)
diff --git a/src/arch/arm/semihosting.hh b/src/arch/arm/semihosting.hh
index d45aa74..07bd739 100644
--- a/src/arch/arm/semihosting.hh
+++ b/src/arch/arm/semihosting.hh
@@ -208,7 +208,9 @@
SYS_ELAPSED = 0x30,
SYS_TICKFREQ = 0x31,
-MaxStandardOp = 0xFF
+MaxStandardOp = 0xFF,
+
+SYS_GEM5_PSEUDO_OP = 0x100
};
ArmSemihosting(const ArmSemihostingParams *p);
@@ -544,6 +546,9 @@
RetErrno callElapsed64(ThreadContext *tc, InPlaceArg ticks);
RetErrno callTickFreq(ThreadContext *tc);
+RetErrno callGem5PseudoOp32(ThreadContext *tc, uint32_t encoded_func);
+RetErrno callGem5PseudoOp64(ThreadContext *tc, uint64_t encoded_func);
+
template
void
unrecognizedCall(ThreadContext *tc, const char *format, uint64_t op)
--
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Gerrit-Change-Number: 25950
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Gerrit-Owner: Gabe Black
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[gem5-dev] Change in gem5/gem5[develop]: arm: Use a const ThreadContext * and readMiscRegNoEffect in places.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/25944 )
Change subject: arm: Use a const ThreadContext * and readMiscRegNoEffect in
places.
..
arm: Use a const ThreadContext * and readMiscRegNoEffect in places.
Unlike readMiscReg, readMiscRegNoEffect won't have any read related
side effects and so can be used on a const ThreadContext. Also, using
a const ThreadContext * in a few functions which don't actually intend
to change state makes them usable in more situations.
Change-Id: I4fe538ba1158b25f512d3cccd779e12f6c91da6c
---
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index facb7f8..e1dffaf 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -397,17 +397,17 @@
}
bool
-isBigEndian64(ThreadContext *tc)
+isBigEndian64(const ThreadContext *tc)
{
switch (currEL(tc)) {
case EL3:
-return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).ee;
+return ((SCTLR) tc->readMiscRegNoEffect(MISCREG_SCTLR_EL3)).ee;
case EL2:
-return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).ee;
+return ((SCTLR) tc->readMiscRegNoEffect(MISCREG_SCTLR_EL2)).ee;
case EL1:
-return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).ee;
+return ((SCTLR) tc->readMiscRegNoEffect(MISCREG_SCTLR_EL1)).ee;
case EL0:
-return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).e0e;
+return ((SCTLR) tc->readMiscRegNoEffect(MISCREG_SCTLR_EL1)).e0e;
default:
panic("Invalid exception level");
break;
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index f16c0b5..4636d17 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -131,14 +131,14 @@
bool inAArch64(ThreadContext *tc);
static inline OperatingMode
-currOpMode(ThreadContext *tc)
+currOpMode(const ThreadContext *tc)
{
-CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
+CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
return (OperatingMode) (uint8_t) cpsr.mode;
}
static inline ExceptionLevel
-currEL(ThreadContext *tc)
+currEL(const ThreadContext *tc)
{
return opModeToEL(currOpMode(tc));
}
@@ -182,7 +182,7 @@
*/
bool ELIsInHost(ThreadContext *tc, ExceptionLevel el);
-bool isBigEndian64(ThreadContext *tc);
+bool isBigEndian64(const ThreadContext *tc);
/**
* badMode is checking if the execution mode provided as an argument is
@@ -368,7 +368,7 @@
*/
uint8_t encodePhysAddrRange64(int pa_size);
-inline ByteOrder byteOrder(ThreadContext *tc)
+inline ByteOrder byteOrder(const ThreadContext *tc)
{
return isBigEndian64(tc) ? BigEndianByteOrder : LittleEndianByteOrder;
};
--
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Gerrit-Change-Id: I4fe538ba1158b25f512d3cccd779e12f6c91da6c
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[gem5-dev] Change in gem5/gem5[develop]: arm: Add a callSemihosting method that figures out the width.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/25951 )
Change subject: arm: Add a callSemihosting method that figures out the
width.
..
arm: Add a callSemihosting method that figures out the width.
Change-Id: Ic94987fffd04648932e5dd085ffeef8500e335cf
---
M src/arch/arm/system.cc
M src/arch/arm/system.hh
2 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 950caee..e25e201 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -303,6 +303,15 @@
return getArmSystem(tc)->semihosting->call32(tc, gem5_ops);
}
+bool
+ArmSystem::callSemihosting(ThreadContext *tc, bool gem5_ops)
+{
+if (ArmISA::inAArch64(tc))
+return callSemihosting64(tc, gem5_ops);
+else
+return callSemihosting32(tc, gem5_ops);
+}
+
ArmSystem *
ArmSystemParams::create()
{
diff --git a/src/arch/arm/system.hh b/src/arch/arm/system.hh
index e890d10..709a12e 100644
--- a/src/arch/arm/system.hh
+++ b/src/arch/arm/system.hh
@@ -338,6 +338,9 @@
/** Make a Semihosting call from aarch32 */
static bool callSemihosting32(ThreadContext *tc, bool gem5_ops=false);
+
+/** Make a Semihosting call from either aarch64 or aarch32 */
+static bool callSemihosting(ThreadContext *tc, bool gem5_ops=false);
};
class GenericArmSystem : public ArmSystem
--
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[gem5-dev] Change in gem5/gem5[develop]: cpu: update info related direction into BP if mispredicted.
Trivikram Reddy has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/25903 )
Change subject: cpu: update info related direction into BP if mispredicted.
..
cpu: update info related direction into BP if mispredicted.
Update direction info of a branch into BP if, the branch is not
found in the target buffer. Therefore, this updated direction is
used to squash the branch later on. Previously, some mispredicted
branches were not sqaushed as the BP had old info.
Reported-by: Dimitrios Chasapis
Change-Id: I4be2eb706edc5ffa9935948fb52a01667286c721
jira-issue: https://gem5.atlassian.net/browse/GEM5-355
---
M src/cpu/pred/bpred_unit.cc
1 file changed, 2 insertions(+), 0 deletions(-)
diff --git a/src/cpu/pred/bpred_unit.cc b/src/cpu/pred/bpred_unit.cc
index 3d9e3ea..4b93e30 100644
--- a/src/cpu/pred/bpred_unit.cc
+++ b/src/cpu/pred/bpred_unit.cc
@@ -263,6 +263,7 @@
DPRINTF(Branch, "[tid:%i] [sn:%llu] BTB doesn't have
a "
"valid entry\n",tid,seqNum);
pred_taken = false;
+predict_record.predTaken = pred_taken;
// The Direction of the branch predictor is altered
// because the BTB did not have an entry
// The predictor needs to be updated accordingly
@@ -293,6 +294,7 @@
} else {
++indirectMisses;
pred_taken = false;
+predict_record.predTaken = pred_taken;
DPRINTF(Branch,
"[tid:%i] [sn:%llu] "
"Instruction %s no indirect "
--
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[gem5-dev] Change in gem5/gem5[develop]: cpu: change the location of BTBlookup
Trivikram Reddy has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/25625 )
Change subject: cpu: change the location of BTBlookup
..
cpu: change the location of BTBlookup
BTBlookup should be done only if BTB is used, previously
this stat was updated for indirector predictor as well.
https: //gem5.atlassian.net/browse/GEM5-338
Change-Id: I20695dc7a8677d4fd0c4ae9f4f7d279387d5ad62
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25625
Reviewed-by: Jason Lowe-Power
Reviewed-by: Ayaz Akram
Reviewed-by: Giacomo Travaglini
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/cpu/pred/bpred_unit.cc
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
Ayaz Akram: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/pred/bpred_unit.cc b/src/cpu/pred/bpred_unit.cc
index a2faad1..3d9e3ea 100644
--- a/src/cpu/pred/bpred_unit.cc
+++ b/src/cpu/pred/bpred_unit.cc
@@ -233,7 +233,6 @@
"RAS predicted target: %s, RAS index: %i\n",
tid, seqNum, pc, target, predict_record.RASIndex);
} else {
-++BTBLookups;
if (inst->isCall()) {
RAS[tid].push(pc);
@@ -250,6 +249,7 @@
}
if (inst->isDirectCtrl() || !iPred) {
+++BTBLookups;
// Check BTB on direct branches
if (BTB.valid(pc.instAddr(), tid)) {
++BTBHits;
--
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Gerrit-Change-Number: 25625
Gerrit-PatchSet: 2
Gerrit-Owner: Trivikram Reddy
Gerrit-Reviewer: Ayaz Akram
Gerrit-Reviewer: Giacomo Travaglini
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Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: tests, misc: Updated tests/.gitignore to ignore test resources
Bobby R. Bruce has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/24324 ) Change subject: tests,misc: Updated tests/.gitignore to ignore test resources .. tests,misc: Updated tests/.gitignore to ignore test resources Tests run via main.py create some temp resources. These are now ignored. Change-Id: I63e2b7e1d70f8813e12c2e538a633046d614f1d2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24324 Tested-by: kokoro Reviewed-by: Bobby R. Bruce Maintainer: Bobby R. Bruce --- M tests/.gitignore 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/tests/.gitignore b/tests/.gitignore index 63c0e1b..642f8e4 100644 --- a/tests/.gitignore +++ b/tests/.gitignore @@ -1 +1,6 @@ .testing-results +gem5/cpu_tests/benchmarks +gem5/fs/linux/arm/*.tar.bz2 +gem5/fs/linux/arm/binaries +gem5/fs/linux/arm/disks +gem5/test-progs -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/24324 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I63e2b7e1d70f8813e12c2e538a633046d614f1d2 Gerrit-Change-Number: 24324 Gerrit-PatchSet: 9 Gerrit-Owner: Bobby R. Bruce Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Cron /z/m5/regression/do-regression --scratch all
* build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-timing: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-ruby-MOESI_CMP_directory: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual: FAILED! * build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual-ruby-MOESI_CMP_directory: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-simple-timing-ruby-MOESI_CMP_directory: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-checkpoint: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-simple-timing-dual-ruby-MOESI_CMP_directory: FAILED! * build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3: FAILED! * build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing: FAILED! * build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-checkpoint: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker: FAILED! * build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor: FAILED! * build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker: FAILED! * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: FAILED! * build/NULL/tests/opt/quick/se/80.dram-openpage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-closepage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem: CHANGED! * build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: CHANGED! * build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer: CHANGED! * build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level: CHANGED! * build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token: CHANGED! * build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic: CHANGED! * build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level: CHANGED! * build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple: CHANGED! * build/X86_MESI_Two_Level/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_Two_Level: CHANGED! * build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing: CHANGED! * build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing: CHANGED! * build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing: CHANGED! * build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing: CHANGED! *
[gem5-dev] Change in gem5/gem5[develop]: tests: Fixed .testignore from 'arch64' to 'aarch64'
Bobby R. Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/25845 ) Change subject: tests: Fixed .testignore from 'arch64' to 'aarch64' .. tests: Fixed .testignore from 'arch64' to 'aarch64' Entries in `tests/gem5/.testignore` which were ignoring insttest tests, were stating the host system as 'arch64' instead of 'aarch64'. This has been fixed. Change-Id: Ib90bd89e0544d225afc012fefca98db0ea2d8dd0 --- M tests/gem5/.testignore 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/tests/gem5/.testignore b/tests/gem5/.testignore index 1c0c1bf..3a15144 100644 --- a/tests/gem5/.testignore +++ b/tests/gem5/.testignore @@ -67,39 +67,39 @@ test-insttest-rv64i-linux-DerivO3CPU-RISCV-x86_64-fast test-insttest-linux-AtomicSimpleCPU-SPARC-x86_64-fast test-insttest-linux-TimingSimpleCPU-SPARC-x86_64-fast -test-insttest-rv64a-linux-MinorCPU-RISCV-arch64-opt -test-insttest-rv64c-linux-MinorCPU-RISCV-arch64-opt -test-insttest-rv64d-linux-MinorCPU-RISCV-arch64-opt -test-insttest-rv64f-linux-MinorCPU-RISCV-arch64-opt -test-insttest-rv64i-linux-MinorCPU-RISCV-arch64-opt -test-insttest-rv64m-linux-MinorCPU-RISCV-arch64-opt -test-insttest-rv64i-linux-AtomicSimpleCPU-RISCV-arch64-opt -test-insttest-rv64i-linux-TimingSimpleCPU-RISCV-arch64-opt -test-insttest-rv64i-linux-DerivO3CPU-RISCV-arch64-opt -test-insttest-linux-AtomicSimpleCPU-SPARC-arch64-opt -test-insttest-linux-TimingSimpleCPU-SPARC-arch64-opt -test-insttest-rv64a-linux-MinorCPU-RISCV-arch64-debug -test-insttest-rv64c-linux-MinorCPU-RISCV-arch64-debug -test-insttest-rv64d-linux-MinorCPU-RISCV-arch64-debug -test-insttest-rv64f-linux-MinorCPU-RISCV-arch64-debug -test-insttest-rv64i-linux-MinorCPU-RISCV-arch64-debug -test-insttest-rv64m-linux-MinorCPU-RISCV-arch64-debug -test-insttest-rv64i-linux-AtomicSimpleCPU-RISCV-arch64-debug -test-insttest-rv64i-linux-TimingSimpleCPU-RISCV-arch64-debug -test-insttest-rv64i-linux-DerivO3CPU-RISCV-arch64-debug -test-insttest-linux-AtomicSimpleCPU-SPARC-arch64-debug -test-insttest-linux-TimingSimpleCPU-SPARC-arch64-debug -test-insttest-rv64a-linux-MinorCPU-RISCV-arch64-fast -test-insttest-rv64c-linux-MinorCPU-RISCV-arch64-fast -test-insttest-rv64d-linux-MinorCPU-RISCV-arch64-fast -test-insttest-rv64f-linux-MinorCPU-RISCV-arch64-fast -test-insttest-rv64i-linux-MinorCPU-RISCV-arch64-fast -test-insttest-rv64m-linux-MinorCPU-RISCV-arch64-fast -test-insttest-rv64i-linux-AtomicSimpleCPU-RISCV-arch64-fast -test-insttest-rv64i-linux-TimingSimpleCPU-RISCV-arch64-fast -test-insttest-rv64i-linux-DerivO3CPU-RISCV-arch64-fast -test-insttest-linux-AtomicSimpleCPU-SPARC-arch64-fast -test-insttest-linux-TimingSimpleCPU-SPARC-arch64-fast +test-insttest-rv64a-linux-MinorCPU-RISCV-aarch64-opt +test-insttest-rv64c-linux-MinorCPU-RISCV-aarch64-opt +test-insttest-rv64d-linux-MinorCPU-RISCV-aarch64-opt +test-insttest-rv64f-linux-MinorCPU-RISCV-aarch64-opt +test-insttest-rv64i-linux-MinorCPU-RISCV-aarch64-opt +test-insttest-rv64m-linux-MinorCPU-RISCV-aarch64-opt +test-insttest-rv64i-linux-AtomicSimpleCPU-RISCV-aarch64-opt +test-insttest-rv64i-linux-TimingSimpleCPU-RISCV-aarch64-opt +test-insttest-rv64i-linux-DerivO3CPU-RISCV-aarch64-opt +test-insttest-linux-AtomicSimpleCPU-SPARC-aarch64-opt +test-insttest-linux-TimingSimpleCPU-SPARC-aarch64-opt +test-insttest-rv64a-linux-MinorCPU-RISCV-aarch64-debug +test-insttest-rv64c-linux-MinorCPU-RISCV-aarch64-debug +test-insttest-rv64d-linux-MinorCPU-RISCV-aarch64-debug +test-insttest-rv64f-linux-MinorCPU-RISCV-aarch64-debug +test-insttest-rv64i-linux-MinorCPU-RISCV-aarch64-debug +test-insttest-rv64m-linux-MinorCPU-RISCV-aarch64-debug +test-insttest-rv64i-linux-AtomicSimpleCPU-RISCV-aarch64-debug +test-insttest-rv64i-linux-TimingSimpleCPU-RISCV-aarch64-debug +test-insttest-rv64i-linux-DerivO3CPU-RISCV-aarch64-debug +test-insttest-linux-AtomicSimpleCPU-SPARC-aarch64-debug +test-insttest-linux-TimingSimpleCPU-SPARC-aarch64-debug +test-insttest-rv64a-linux-MinorCPU-RISCV-aarch64-fast +test-insttest-rv64c-linux-MinorCPU-RISCV-aarch64-fast +test-insttest-rv64d-linux-MinorCPU-RISCV-aarch64-fast +test-insttest-rv64f-linux-MinorCPU-RISCV-aarch64-fast +test-insttest-rv64i-linux-MinorCPU-RISCV-aarch64-fast +test-insttest-rv64m-linux-MinorCPU-RISCV-aarch64-fast +test-insttest-rv64i-linux-AtomicSimpleCPU-RISCV-aarch64-fast +test-insttest-rv64i-linux-TimingSimpleCPU-RISCV-aarch64-fast +test-insttest-rv64i-linux-DerivO3CPU-RISCV-aarch64-fast +test-insttest-linux-AtomicSimpleCPU-SPARC-aarch64-fast +test-insttest-linux-TimingSimpleCPU-SPARC-aarch64-fast test-insttest-rv64a-linux-MinorCPU-RISCV-i386-opt test-insttest-rv64c-linux-MinorCPU-RISCV-i386-opt test-insttest-rv64d-linux-MinorCPU-RISCV-i386-opt -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/25845 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project:
[gem5-dev] Change in gem5/gem5[develop]: misc: merge branch 'release-staging-v19.0.0.0' into develop
Bobby R. Bruce has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/25825 ) Change subject: misc: merge branch 'release-staging-v19.0.0.0' into develop .. misc: merge branch 'release-staging-v19.0.0.0' into develop Change-Id: I8430c6717697563386d165a40a0d080b0d18832e --- 1 file changed, 0 insertions(+), 0 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/25825 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I8430c6717697563386d165a40a0d080b0d18832e Gerrit-Change-Number: 25825 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby R. Bruce Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[develop]: tests: Removed unneeded 02.insttest data
Bobby R. Bruce has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/25844 ) Change subject: tests: Removed unneeded 02.insttest data .. tests: Removed unneeded 02.insttest data This test has been migrated to be run via `./main.py`. Change-Id: I3608306da62c301bf0ebea6c5fbd1eebac703467 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25844 Reviewed-by: Bobby R. Bruce Maintainer: Bobby R. Bruce Tested-by: kokoro --- D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.ini D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.json D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simerr D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simout D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/config.ini D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/config.json D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/simerr D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/simout D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/stats.txt D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.ini D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.json D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simerr D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simout D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/stats.txt D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.ini D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.json D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simerr D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simout D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/stats.txt D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.ini D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.json D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simerr D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simout D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/stats.txt D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/minor-timing/config.ini D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/minor-timing/config.json D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/minor-timing/simerr D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/minor-timing/simout D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/minor-timing/stats.txt D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/o3-timing/config.ini D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/o3-timing/config.json D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/o3-timing/simerr D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/o3-timing/simout D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/o3-timing/stats.txt D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-atomic/config.ini D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-atomic/config.json D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-atomic/simerr D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-atomic/simout D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-atomic/stats.txt D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-timing-ruby/config.ini D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-timing-ruby/config.json D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-timing-ruby/simerr D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-timing-ruby/simout D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-timing-ruby/stats.txt D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-timing/config.ini D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-timing/config.json D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-timing/simerr D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-timing/simout D tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-timing/stats.txt D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.ini D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.json D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simerr D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simout D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/config.ini D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/config.json D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/simerr D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/simout D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/stats.txt D
[gem5-dev] Change in gem5/gem5[develop]: sim: print --debug-flag Event execution and instance ID
Ciro Santilli has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/25383 )
Change subject: sim: print --debug-flag Event execution and instance ID
..
sim: print --debug-flag Event execution and instance ID
This makes it much easier to determine what event is causing something to
happen, especially when there are multiple events happening at the
same time.
Change-Id: I17378e16bd3de1d98e936a6252aab2cd8c303b23
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25383
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/sim/eventq.cc
M src/sim/eventq.hh
2 files changed, 18 insertions(+), 8 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/eventq.cc b/src/sim/eventq.cc
index 6141380..25131b3 100644
--- a/src/sim/eventq.cc
+++ b/src/sim/eventq.cc
@@ -81,11 +81,7 @@
const std::string
Event::name() const
{
-#ifndef NDEBUG
-return csprintf("Event_%d", instance);
-#else
-return csprintf("Event_%x", (uintptr_t)this);
-#endif
+return csprintf("Event_%s", instanceString());
}
@@ -220,7 +216,8 @@
if (!event->squashed()) {
// forward current cycle to the time when this event occurs.
setCurTick(event->when());
-
+if (DTRACE(Event))
+event->trace("executed");
event->process();
if (event->isExitEvent()) {
assert(!event->flags.isSet(Event::Managed) ||
@@ -388,8 +385,18 @@
// more informative message in the trace, override this method on
// the particular subclass where you have the information that
// needs to be printed.
-DPRINTF_UNCONDITIONAL(Event, "%s event %s @ %d\n",
-description(), action, when());
+DPRINTF_UNCONDITIONAL(Event, "%s %s %s @ %d\n",
+description(), instanceString(), action, when());
+}
+
+const std::string
+Event::instanceString() const
+{
+#ifndef NDEBUG
+return csprintf("%d", instance);
+#else
+return csprintf("%#x", (uintptr_t)this);
+#endif
}
void
diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh
index a703363..2976e11 100644
--- a/src/sim/eventq.hh
+++ b/src/sim/eventq.hh
@@ -284,6 +284,9 @@
// This function isn't really useful if TRACING_ON is not defined
virtual void trace(const char *action); //!< trace event activity
+/// Return the instance number as a string.
+const std::string instanceString() const;
+
protected: /* Memory management */
/**
* @{
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/25383
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I17378e16bd3de1d98e936a6252aab2cd8c303b23
Gerrit-Change-Number: 25383
Gerrit-PatchSet: 2
Gerrit-Owner: Ciro Santilli
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs: Fix argument handling sweep.py
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/25710 )
Change subject: configs: Fix argument handling sweep.py
..
configs: Fix argument handling sweep.py
Change-Id: I6dacbda19971e1c940d1798febb54d20f971c2bc
Signed-off-by: Nikos Nikoleris
---
M configs/dram/sweep.py
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/configs/dram/sweep.py b/configs/dram/sweep.py
index f18e44e..af7ca74 100644
--- a/configs/dram/sweep.py
+++ b/configs/dram/sweep.py
@@ -79,9 +79,9 @@
help = "DRAM: Random traffic; \
DRAM_ROTATE: Traffic rotating across banks and
ranks")
-parser.add_argument("--addr-map",
-choices=m5.objects.AddrMap.vals,
-default="RoRaBaCoCh", help = "DRAM address map policy")
+parser.add_option("--addr-map", type="choice",
+ choices=m5.objects.AddrMap.vals,
+ default="RoRaBaCoCh", help = "DRAM address map policy")
(options, args) = parser.parse_args()
@@ -124,7 +124,7 @@
system.mem_ctrls[0].null = True
# Set the address mapping based on input argument
-system.mem_ctrls[0].addr_mapping = args.addr_map
+system.mem_ctrls[0].addr_mapping = options.addr_map
# stay in each state for 0.25 ms, long enough to warm things up, and
# short enough to avoid hitting a refresh
@@ -179,8 +179,7 @@
m5.instantiate()
-addr_map = m5.objects.AddrMap.map[args.addr_map]
-
+addr_map = m5.internal.params.enum_AddrMap.__members__[options.addr_map]
def trace():
generator = dram_generators[options.mode](system.tgen)
for bank in range(1, nbr_banks + 1):
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6dacbda19971e1c940d1798febb54d20f971c2bc
Gerrit-Change-Number: 25710
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: python: Remove unnecessary exports from pybind enums
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/25709 )
Change subject: python: Remove unnecessary exports from pybind enums
..
python: Remove unnecessary exports from pybind enums
According to pybind documentation [1], enum entries use
.export_values() to export the enum entries into the parent
scope. However, strongly typed C++11 class enums are in their own
scope and therefore do not need to be exported.
[1]: https://pybind11.readthedocs.io/en/stable/classes.html#enume
rations-and-internal-types
Change-Id: I6181306b530d59eaedcb3daf9cab0a03d01d56f4
Signed-off-by: Nikos Nikoleris
---
M src/python/m5/params.py
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index 9b4198b..e82e96a 100644
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -1438,7 +1438,8 @@
for val in cls.vals:
code('.value("${val}", ${wrapper_name}::${val})')
code('.value("Num_${name}", ${wrapper_name}::Num_${enum_name})')
-code('.export_values()')
+if not cls.is_class:
+code('.export_values()')
code(';')
code.dedent()
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I6181306b530d59eaedcb3daf9cab0a03d01d56f4
Gerrit-Change-Number: 25709
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: This commit allows checkpoints on o3 cpu & VecElem mode
Athanasios Chatzidimitriou has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/25708 )
Change subject: cpu-o3: This commit allows checkpoints on o3 cpu & VecElem
mode
..
cpu-o3: This commit allows checkpoints on o3 cpu & VecElem mode
This patch allows checkpoints to be taken/restored when VecElem mode is
enabled (e.g. ARMv7).
To allow this, the following parts are added:
- Initialize the full-vector interface on VecElemMode to be used by
serialize functions
- Add a method that "syncs" the VecElem regs to VecFlat
- Invoke this sync when CPU drains (in order to take checkpoints
correctly).
- Discard asserts that forbid VecRegClass lookups on VecElem mode as now
the interface allows it.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-371
Change-Id: Ia0d8377505b9b241578470f1c4aadb1adc021254
---
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/regfile.cc
M src/cpu/o3/rename_map.cc
M src/cpu/o3/rename_map.hh
5 files changed, 72 insertions(+), 35 deletions(-)
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index e2c7270..91f4970 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -246,16 +246,17 @@
/* Here we need two 'interfaces' the 'whole register' and the
* 'register element'. At any point only one of them will be
- * active. */
-if (vecMode == Enums::Full) {
-/* Initialize the full-vector interface */
-for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) {
-RegId rid = RegId(VecRegClass, ridx);
-PhysRegIdPtr phys_reg = freeList.getVecReg();
-renameMap[tid].setEntry(rid, phys_reg);
-commitRenameMap[tid].setEntry(rid, phys_reg);
-}
-} else {
+ * active, but we can Initialize both so that serialize calls
+ * allow whole access on register element mode */
+
+/* Initialize the full-vector interface */
+for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) {
+RegId rid = RegId(VecRegClass, ridx);
+PhysRegIdPtr phys_reg = freeList.getVecReg();
+renameMap[tid].setEntry(rid, phys_reg);
+commitRenameMap[tid].setEntry(rid, phys_reg);
+}
+if (vecMode == Enums::Elem) {
/* Initialize the vector-element interface */
for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) {
for (ElemIndex ldx = 0; ldx < TheISA::NumVecElemPerVecReg;
@@ -864,6 +865,21 @@
}
template
+void
+FullO3CPU::syncVecElem(ThreadID tid)
+{
+auto pc = this->pcState(tid);
+auto curr_mode = RenameMode::mode(pc);
+
+/*This is only required if we are on VecElem mode */
+if (curr_mode == Enums::Full) return;
+
+/* Sync the VecElem regs */
+renameMap[tid].syncVecElem();
+commitRenameMap[tid].syncVecElem();
+}
+
+template
Fault
FullO3CPU::getInterrupts()
{
@@ -990,6 +1006,11 @@
}
drainSanityCheck();
+
+/*Sync VecElem regs to VecRegs */
+for (int tid = 0; tid < numThreads; tid++)
+syncVecElem(tid);
+
return DrainState::Drained;
}
}
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 01f58df..ac504bc 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -321,6 +321,17 @@
*/
void switchRenameMode(ThreadID tid, UnifiedFreeList* freelist);
+/**
+ * Because operations such as thread serialize only use VecReg regfile
+ * it may happen that, if the cpu is on VecElem mode, state may be
+ * corrupt after CPU drain(). We add this utility method to "sync"
+ * the VecElem with the actual registers (aka. merge splitted portions)
+ * so that any access in the VecReg will not result in a corruption
+ *
+ * @param tid ThreadID
+ */
+void syncVecElem(ThreadID tid);
+
/** Returns the Fault for any valid interrupt. */
Fault getInterrupts();
diff --git a/src/cpu/o3/regfile.cc b/src/cpu/o3/regfile.cc
index de9cd5e..d1b7737 100644
--- a/src/cpu/o3/regfile.cc
+++ b/src/cpu/o3/regfile.cc
@@ -158,11 +158,10 @@
}
}
-/* depending on the mode we add the vector registers as whole units or
- * as different elements. */
-if (vecMode == Enums::Full)
-freeList->addRegs(vecRegIds.begin(), vecRegIds.end());
-else
+/* We add the vector registers as whole units at all cases and
+ * in addition, elements for the Elem vecMode. */
+freeList->addRegs(vecRegIds.begin(), vecRegIds.end());
+if (vecMode == Enums::Elem)
freeList->addRegs(vecElemIds.begin(), vecElemIds.end());
// The next batch of the registers are the predicate physical
diff --git a/src/cpu/o3/rename_map.cc b/src/cpu/o3/rename_map.cc
index fdb9894..8e59160 100644
--- a/src/cpu/o3/rename_map.cc
+++ b/src/cpu/o3/rename_map.cc
@@ -195,25 +195,29
