[gem5-dev] Change in gem5/gem5[develop]: util: Move m5op_arm_A64.S into an aarch64 subdirectory.
Gabe Black has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/27216 ) Change subject: util: Move m5op_arm_A64.S into an aarch64 subdirectory. .. util: Move m5op_arm_A64.S into an aarch64 subdirectory. Also rename it to m5op.S. These files will be distinguished by what directory they're in, rather than by their name. Change-Id: I3a89d529bb5b760579df22234cf9bf870711b56e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27216 Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini Tested-by: kokoro --- M util/m5/src/SConscript R util/m5/src/aarch64/m5op.S 2 files changed, 1 insertion(+), 1 deletion(-) Approvals: Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/util/m5/src/SConscript b/util/m5/src/SConscript index 464da64..7520841 100644 --- a/util/m5/src/SConscript +++ b/util/m5/src/SConscript @@ -29,7 +29,7 @@ # Raw source files. m5_mmap = 'm5_mmap.c' -m5op = 'm5op_arm_A64.S' +m5op = 'aarch64/m5op.S' m5 = 'm5.c' jni = 'jni_gem5Op.c' lua = 'lua_gem5Op.c' diff --git a/util/m5/src/m5op_arm_A64.S b/util/m5/src/aarch64/m5op.S similarity index 100% rename from util/m5/src/m5op_arm_A64.S rename to util/m5/src/aarch64/m5op.S -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/27216 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I3a89d529bb5b760579df22234cf9bf870711b56e Gerrit-Change-Number: 27216 Gerrit-PatchSet: 7 Gerrit-Owner: Gabe Black Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Earl Ou Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Yu-hsin Wang Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[develop]: util, scons: Detect java and lua51 in the m5 utility scons files.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27214 )
Change subject: util,scons: Detect java and lua51 in the m5 utility scons
files.
..
util,scons: Detect java and lua51 in the m5 utility scons files.
These will enable or disable the java and lua51 m5 op wrappers depending
on whether the required tools are available on the host system.
Change-Id: I2b11a13a39b2dfd5d45a9ed57702d2e225ef7d2e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27214
Maintainer: Bobby R. Bruce
Tested-by: kokoro
Reviewed-by: Daniel Carvalho
---
M util/m5/SConstruct
M util/m5/src/SConscript
2 files changed, 30 insertions(+), 23 deletions(-)
Approvals:
Daniel Carvalho: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/util/m5/SConstruct b/util/m5/SConstruct
index ab34112..c1cf193 100644
--- a/util/m5/SConstruct
+++ b/util/m5/SConstruct
@@ -51,6 +51,12 @@
main['LD'] = '${CROSS_COMPILE}ld'
main['AR'] = '${CROSS_COMPILE}ar'
+# Detect some dependencies of some forms of the m5 utility/library.
+main['HAVE_JAVA'] = all(key in main for key in ('JAVAC', 'JAR'))
+main['HAVE_PKG_CONFIG'] = main.Detect('pkg-config') is not None
+main['HAVE_LUA51'] = (main['HAVE_PKG_CONFIG'] and
+ os.system('pkg-config --exists lua51') == 0)
+
# Put the sconsign file in the build dir so everything can be deleted at
once.
main.SConsignFile(os.path.join(abspath(build_dir), 'sconsign'))
# Use soft links instead of hard links when setting up a build directory.
diff --git a/util/m5/src/SConscript b/util/m5/src/SConscript
index a3f7a8f..464da64 100644
--- a/util/m5/src/SConscript
+++ b/util/m5/src/SConscript
@@ -51,28 +51,29 @@
# The shared version of the m5 op call sights, used by mutliple targets
below.
m5op_shared = env.SharedObject(m5op)
-
-#
-# A wrapper to make the m5 ops available in Java through the JNI.
-#
-java_env = env.Clone()
-# SCons provides Java and JavaH builders, but the JavaH builder assumes
that
-# the javah tool exists. Java has dropped that tool in favor of a -h
option on
-# javac which the Java builder doesn't know how to use. To get around
this, we
-# set up our own builder which does the "right thing" here.
-java_env.Command([ 'jni_gem5Op.h', 'gem5OpJni.jar' ], 'jni/gem5Op.java',
- [ '${JAVAC} ${JAVACFLAGS} -d ${CWD} ${SOURCES} -h
${CWD} ',
- '${JAR} cvf ${TARGETS[1]} ${JNI_DIR}/*.class' ],
- JNI_DIR=Dir('jni'), CWD=Dir('.'))
-# Set include paths to the C headers from the JDK which scons found for us.
-java_env.Append(CPPPATH='${JAVAINCLUDES}')
-java_env.SharedLibrary('gem5OpJni', [ jni, m5op_shared ])
+if env['HAVE_JAVA']:
+#
+# A wrapper to make the m5 ops available in Java through the JNI.
+#
+java_env = env.Clone()
+# SCons provides Java and JavaH builders, but the JavaH builder assumes
+# that the javah tool exists. Java has dropped that tool in favor of a
-h
+# option on javac which the Java builder doesn't know how to use. To
get
+# around this, we set up our own builder which does the "right thing"
here.
+java_env.Command([ 'jni_gem5Op.h', 'gem5OpJni.jar'
], 'jni/gem5Op.java',
+ [ '${JAVAC} ${JAVACFLAGS} -d ${CWD} ${SOURCES} -h
${CWD}',
+ '${JAR} cvf ${TARGETS[1]} ${JNI_DIR}/*.class' ],
+ JNI_DIR=Dir('jni'), CWD=Dir('.'))
+# Set include paths to the C headers from the JDK which scons found
for us.
+java_env.Append(CPPPATH='${JAVAINCLUDES}')
+java_env.SharedLibrary('gem5OpJni', [ jni, m5op_shared ])
-#
-# A wrapper to make the m5 ops available in lua version 5.1.
-#
-lua_env = env.Clone()
-# Extract the include paths needed for lua51 using pkg-config.
-lua_env.ParseConfig('pkg-config --cflags lua51')
-lua_env.SharedLibrary('gem5OpLua', [ lua, m5op_shared, m5_mmap ])
+if env['HAVE_LUA51']:
+#
+# A wrapper to make the m5 ops available in lua version 5.1.
+#
+lua_env = env.Clone()
+# Extract the include paths needed for lua51 using pkg-config.
+lua_env.ParseConfig('pkg-config --cflags lua51')
+lua_env.SharedLibrary('gem5OpLua', [ lua, m5op_shared, m5_mmap ])
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/27214
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2b11a13a39b2dfd5d45a9ed57702d2e225ef7d2e
Gerrit-Change-Number: 27214
Gerrit-PatchSet: 7
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Earl Ou
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-MessageType:
[gem5-dev] Change in gem5/gem5[develop]: util: Add SCons build files for the aarch64 verson of the m5 utility.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27213 )
Change subject: util: Add SCons build files for the aarch64 verson of the
m5 utility.
..
util: Add SCons build files for the aarch64 verson of the m5 utility.
These are currently specific to aarch64, but will be expanded to cover
all other versions of the utility as well.
The intention of these new files is to centralize the build mechanism
for the different versions of the utility so that they have consistent
features, mechanisms, and targets, and so that new features will
automatically be shared by all versions without having to be implemented
in each.
This also sets up a separate build directory which will keep the source
tree clean, and will (with some more development) make it possible to
build multiple versions of the m5 utility at the same time without them
running into each other.
Change-Id: I10018eef6beb4af30a8d3bbab8b82cabd2b3f22c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27213
Reviewed-by: Bobby R. Bruce
Maintainer: Gabe Black
Tested-by: kokoro
---
A util/m5/SConstruct
A util/m5/src/SConscript
2 files changed, 139 insertions(+), 0 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/util/m5/SConstruct b/util/m5/SConstruct
new file mode 100644
index 000..ab34112
--- /dev/null
+++ b/util/m5/SConstruct
@@ -0,0 +1,61 @@
+# Copyright 2020 Google, Inc.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import os
+
+main = Environment()
+
+# Includes which are shared with gem5 itself.
+common_include = Dir('..').Dir('..').Dir('include')
+
+src_dir = Dir('src')
+build_dir = Dir('build')
+
+def abspath(d):
+return os.path.abspath(str(d))
+
+# Universal settings.
+main.Append(CCFLAGS=[ '-O2' ])
+main.Append(CPPPATH=[ common_include ])
+
+# Propogate the environment's PATH setting.
+main['ENV']['PATH'] = os.environ['PATH']
+
+# Cross compiler prefix.
+main['CROSS_COMPILE'] =
os.environ.get('CROSS_COMPILE', 'aarch64-linux-gnu-')
+
+main['CC'] = '${CROSS_COMPILE}gcc'
+main['AS'] = '${CROSS_COMPILE}as'
+main['LD'] = '${CROSS_COMPILE}ld'
+main['AR'] = '${CROSS_COMPILE}ar'
+
+# Put the sconsign file in the build dir so everything can be deleted at
once.
+main.SConsignFile(os.path.join(abspath(build_dir), 'sconsign'))
+# Use soft links instead of hard links when setting up a build directory.
+main.SetOption('duplicate', 'soft-copy')
+
+env = main.Clone()
+main.SConscript(src_dir.File('SConscript'),
+variant_dir=build_dir, exports='env')
diff --git a/util/m5/src/SConscript b/util/m5/src/SConscript
new file mode 100644
index 000..a3f7a8f
--- /dev/null
+++ b/util/m5/src/SConscript
@@ -0,0 +1,78 @@
+# Copyright 2020 Google, Inc.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software witho
[gem5-dev] Change in gem5/gem5[develop]: util: Delete the aarch64 Makefile for the m5 utility.
Gabe Black has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/27215 ) Change subject: util: Delete the aarch64 Makefile for the m5 utility. .. util: Delete the aarch64 Makefile for the m5 utility. Change-Id: I202f2b0986ef12ddb076045673d80405b1afb54a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27215 Reviewed-by: Giacomo Travaglini Reviewed-by: Daniel Carvalho Maintainer: Giacomo Travaglini Tested-by: kokoro --- D util/m5/src/Makefile.aarch64 1 file changed, 0 insertions(+), 93 deletions(-) Approvals: Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved Daniel Carvalho: Looks good to me, but someone else must approve kokoro: Regressions pass diff --git a/util/m5/src/Makefile.aarch64 b/util/m5/src/Makefile.aarch64 deleted file mode 100644 index 7724b85..000 --- a/util/m5/src/Makefile.aarch64 +++ /dev/null @@ -1,93 +0,0 @@ -# Copyright (c) 2010 ARM Limited -# All rights reserved. -# -# The license below extends only to copyright in the software and shall -# not be construed as granting a license to any other intellectual -# property including but not limited to intellectual property relating -# to a hardware implementation of the functionality of the software -# licensed hereunder. You may use the software subject to the license -# terms below provided that you ensure that this notice is replicated -# unmodified and in its entirety in all distributions of the software, -# modified or unmodified, in source code or in binary form. -# -# Copyright (c) 2005-2006 The Regents of The University of Michigan -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -### If we are not compiling on an arm v8, we must use cross tools ### -ifneq ($(shell uname -m), aarch64) -CROSS_COMPILE?=aarch64-linux-gnu- -endif -CC=$(CROSS_COMPILE)gcc -AS=$(CROSS_COMPILE)as -LD=$(CROSS_COMPILE)ld -AR=$(CROSS_COMPILE)ar - -JC=javac -JR=jar -### JDK_PATH must be set to build gem5OpJni -#JDK_PATH=/path/to/jdk/version_number - -CFLAGS=-O2 -I $(JDK_PATH)/include/ -I $(JDK_PATH)/include/linux \ - -I../../../include -march=armv8-a -LDFLAGS=-static -L. -lm5 - -LIB_OBJS=m5op_arm_A64.o m5_mmap.o -OBJS=m5.o -JNI_OBJS=m5op_arm_A64.o jni_gem5Op.o -LUA_OBJS=lua_gem5Op.o m5op_arm_A64.o m5_mmap.o - -### Need to install lua5.1 library to compile gem5OpLua.so -LUA_HEADER_INCLUDE=$(shell pkg-config --cflags lua51) -I/usr/include/x86_64-linux-gnu - -all: libm5.a m5 - -%.o: %.S - $(CC) $(CFLAGS) -o $@ -c $< - -%.o: %.c - $(CC) $(CFLAGS) -o $@ -c $< - -m5: $(OBJS) libm5.a - $(CC) -o $@ $^ $(LDFLAGS) - -libm5.a: $(LIB_OBJS) - $(AR) rcs $@ $^ - -gem5OpJni: gem5OpJni.jar $(JNI_OBJS) - $(CC) --shared -o lib$@.so $(JNI_OBJS) - -gem5OpJni.jar: - $(JC) jni/gem5Op.java -h .; \ - $(JR) cvf $@ jni/*.class - -lua_gem5Op.o: lua_gem5Op.c - $(CC) $(CFLAGS) $(LUA_HEADER_INCLUDE) -o $@ -c $< - -gem5OpLua.so: $(LUA_OBJS) - $(CC) $(CFLAGS) $^ -o $@ -shared - -clean: - rm -f *.o m5 libgem5OpJni.so gem5OpJni.jar jni/*.class libm5.a gem5OpLua.so -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/27215 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I202f2b0986ef12ddb076045673d80405b1afb54a Gerrit-Change-Number: 27215 Gerrit-PatchSet: 6 Gerrit-Owner: Gabe Black Gerrit-Reviewer:
[gem5-dev] Change in gem5/gem5[develop]: tests: Reduce checkpoint interval used by realview regressions
Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/27709 to review the following change. Change subject: tests: Reduce checkpoint interval used by realview regressions .. tests: Reduce checkpoint interval used by realview regressions With the current interval, the realview(64)-simple-atomic-checkpoint regressions are not actually checkpointing since they finish boot (and hit m5 exit) before creating the first checkpoint. Change-Id: I297864ccb7ec8a818c9eccd94406b69d89d1f8d3 Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper --- M tests/configs/realview-simple-atomic-checkpoint.py M tests/configs/realview64-simple-atomic-checkpoint.py 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/tests/configs/realview-simple-atomic-checkpoint.py b/tests/configs/realview-simple-atomic-checkpoint.py index 3525fc0..9c61deb 100644 --- a/tests/configs/realview-simple-atomic-checkpoint.py +++ b/tests/configs/realview-simple-atomic-checkpoint.py @@ -33,6 +33,8 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +import functools + from m5.objects import * from arm_generic import * import checkpoint @@ -42,4 +44,4 @@ mem_class=SimpleMemory, cpu_class=AtomicSimpleCPU).create_root() -run_test = checkpoint.run_test +run_test = functools.partial(checkpoint.run_test, interval=0.2) diff --git a/tests/configs/realview64-simple-atomic-checkpoint.py b/tests/configs/realview64-simple-atomic-checkpoint.py index 40302e0..2a3ee7a 100644 --- a/tests/configs/realview64-simple-atomic-checkpoint.py +++ b/tests/configs/realview64-simple-atomic-checkpoint.py @@ -43,5 +43,5 @@ mem_class=SimpleMemory, cpu_class=AtomicSimpleCPU).create_root() -run_test = functools.partial(checkpoint.run_test, interval=1.0) +run_test = functools.partial(checkpoint.run_test, interval=0.2) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/27709 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I297864ccb7ec8a818c9eccd94406b69d89d1f8d3 Gerrit-Change-Number: 27709 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[develop]: tests: Fail checkpoint regressions if no cpt has been taken
Hello Richard Cooper,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/27710
to review the following change.
Change subject: tests: Fail checkpoint regressions if no cpt has been taken
..
tests: Fail checkpoint regressions if no cpt has been taken
This is to avoid the scenario where a wrong interval is chosen
and no checkpoint is taken.
Change-Id: I524d797048ab04799555aaf7a051241b2917ad95
Signed-off-by: Giacomo Travaglini
Reviewed-by: Richard Cooper
---
M tests/configs/checkpoint.py
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/tests/configs/checkpoint.py b/tests/configs/checkpoint.py
index 4a7d15e..a652094 100644
--- a/tests/configs/checkpoint.py
+++ b/tests/configs/checkpoint.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2015 ARM Limited
+# Copyright (c) 2015, 2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -92,6 +92,7 @@
cpt_name = os.path.join(m5.options.outdir, "test.cpt")
restore = None
+checkpointed = False
for cpt_no in range(max_checkpoints):
# Create a checkpoint from a separate child process. This enables
@@ -112,10 +113,15 @@
restore = cpt_name
if p.exitcode == _exitcode_done:
-print("Test done.", file=sys.stderr)
-sys.exit(0)
+if checkpointed:
+print("Test done.", file=sys.stderr)
+sys.exit(0)
+else:
+print("Test done, but no checkpoint was created.",
+file=sys.stderr)
+sys.exit(1)
elif p.exitcode == _exitcode_checkpoint:
-pass
+checkpointed = True
else:
print("Test failed.", file=sys.stderr)
sys.exit(1)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/27710
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I524d797048ab04799555aaf7a051241b2917ad95
Gerrit-Change-Number: 27710
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Richard Cooper
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Fix checkpointing for the GenericTimer
Hello Ciro Santilli,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/27708
to review the following change.
Change subject: dev-arm: Fix checkpointing for the GenericTimer
..
dev-arm: Fix checkpointing for the GenericTimer
The revamp of the GenericTimer was not taking into account:
* The name of the variable will be printed on the checkpoint to label the
data. It is not possible to use different variable names when
serializing/unserializing, and it is not possible to use the same
temporary variable to serialize/unserialize different values.
* the serializeSection is creating a new sub section in the
checkpoint. Doing the following:
void
GenericTimerFrame::serialize(CheckpointOut &cp) const
{
physTimer.serializeSection(cp, "phys_timer");
virtTimer.serializeSection(cp, "virt_timer");
SERIALIZE_SCALAR(accessBits);
}
will serialize the accessBits under the virt_timer subsection
rather than the parent generic_timer_frame.
JIRA: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-426
Change-Id: I7676309965a33156789d2ef13e966c7a4ad88a71
Signed-off-by: Giacomo Travaglini
Reviewed-by: Ciro Santilli
---
M src/dev/arm/generic_timer.cc
1 file changed, 42 insertions(+), 32 deletions(-)
diff --git a/src/dev/arm/generic_timer.cc b/src/dev/arm/generic_timer.cc
index 6e19a3a..7ba0374 100644
--- a/src/dev/arm/generic_timer.cc
+++ b/src/dev/arm/generic_timer.cc
@@ -728,57 +728,65 @@
void
GenericTimer::CoreTimers::serialize(CheckpointOut &cp) const
{
-physS.serializeSection(cp, "phys_s_timer");
-physNS.serializeSection(cp, "phys_ns_timer");
-virt.serializeSection(cp, "virt_timer");
-hyp.serializeSection(cp, "hyp_timer");
-
SERIALIZE_SCALAR(cntfrq);
SERIALIZE_SCALAR(cntkctl);
SERIALIZE_SCALAR(cnthctl);
-bool ev_scheduled = physEvStream.event.scheduled();
-SERIALIZE_SCALAR(ev_scheduled);
-if (ev_scheduled)
-SERIALIZE_SCALAR(physEvStream.event.when());
+const bool phys_ev_scheduled = physEvStream.event.scheduled();
+SERIALIZE_SCALAR(phys_ev_scheduled);
+if (phys_ev_scheduled) {
+const Tick phys_ev_when = physEvStream.event.when();
+SERIALIZE_SCALAR(phys_ev_when);
+}
SERIALIZE_SCALAR(physEvStream.transitionTo);
SERIALIZE_SCALAR(physEvStream.transitionBit);
-ev_scheduled = virtEvStream.event.scheduled();
-SERIALIZE_SCALAR(ev_scheduled);
-if (ev_scheduled)
-SERIALIZE_SCALAR(virtEvStream.event.when());
+
+const bool virt_ev_scheduled = virtEvStream.event.scheduled();
+SERIALIZE_SCALAR(virt_ev_scheduled);
+if (virt_ev_scheduled) {
+const Tick virt_ev_when = virtEvStream.event.when();
+SERIALIZE_SCALAR(virt_ev_when);
+}
SERIALIZE_SCALAR(virtEvStream.transitionTo);
SERIALIZE_SCALAR(virtEvStream.transitionBit);
+
+physS.serializeSection(cp, "phys_s_timer");
+physNS.serializeSection(cp, "phys_ns_timer");
+virt.serializeSection(cp, "virt_timer");
+hyp.serializeSection(cp, "hyp_timer");
}
void
GenericTimer::CoreTimers::unserialize(CheckpointIn &cp)
{
-physS.unserializeSection(cp, "phys_s_timer");
-physNS.unserializeSection(cp, "phys_ns_timer");
-virt.unserializeSection(cp, "virt_timer");
-hyp.unserializeSection(cp, "hyp_timer");
-
UNSERIALIZE_SCALAR(cntfrq);
UNSERIALIZE_SCALAR(cntkctl);
UNSERIALIZE_SCALAR(cnthctl);
-bool ev_scheduled;
-Tick when;
-UNSERIALIZE_SCALAR(ev_scheduled);
-if (ev_scheduled) {
-UNSERIALIZE_SCALAR(when);
-parent.reschedule(physEvStream.event, when, true);
+bool phys_ev_scheduled;
+UNSERIALIZE_SCALAR(phys_ev_scheduled);
+if (phys_ev_scheduled) {
+Tick phys_ev_when;
+UNSERIALIZE_SCALAR(phys_ev_when);
+parent.reschedule(physEvStream.event, phys_ev_when, true);
}
UNSERIALIZE_SCALAR(physEvStream.transitionTo);
UNSERIALIZE_SCALAR(physEvStream.transitionBit);
-UNSERIALIZE_SCALAR(ev_scheduled);
-if (ev_scheduled) {
-UNSERIALIZE_SCALAR(when);
-parent.reschedule(virtEvStream.event, when, true);
+
+bool virt_ev_scheduled;
+UNSERIALIZE_SCALAR(virt_ev_scheduled);
+if (virt_ev_scheduled) {
+Tick virt_ev_when;
+UNSERIALIZE_SCALAR(virt_ev_when);
+parent.reschedule(virtEvStream.event, virt_ev_when, true);
}
UNSERIALIZE_SCALAR(virtEvStream.transitionTo);
UNSERIALIZE_SCALAR(virtEvStream.transitionBit);
+
+physS.unserializeSection(cp, "phys_s_timer");
+physNS.unserializeSection(cp, "phys_ns_timer");
+virt.unserializeSection(cp, "virt_timer");
+hyp.unserializeSection(cp, "hyp_timer");
}
void
@@ -823,23 +831,25 @@
void
GenericTimerFrame::serialize(CheckpointOut &cp) const
{
-physTimer.serializeSection(cp, "phys_timer");
-virtTimer.serializeSection(cp, "virt_timer");
SERIALIZE_SCALAR(acces
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Do not fixup faults in TLB
Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27507 )
Change subject: arch-x86: Do not fixup faults in TLB
..
arch-x86: Do not fixup faults in TLB
Faults in the TLB ought to cause a page walk. Force that by removing
the fixup in X86 TLB.
This fixes rare race conditions where a timing page walk is
intercepted by a TLB miss which fixes up the fault resulting in
double calls to allocateMem in Process class.
Change-Id: Iaef4d636cd2997144d8bc5012cd7c2a0a97102e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27507
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
---
M src/arch/x86/tlb.cc
1 file changed, 0 insertions(+), 7 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 53492b0..baeeb66 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -397,13 +397,6 @@
Process *p = tc->getProcessPtr();
const EmulationPageTable::Entry *pte =
p->pTable->lookup(vaddr);
-if (!pte && mode != Execute) {
-// Check if we just need to grow the stack.
-if (p->fixupFault(vaddr)) {
-// If we did, lookup the entry for the new
page.
-pte = p->pTable->lookup(vaddr);
-}
-}
if (!pte) {
return std::make_shared(vaddr, true,
mode,
true, false);
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/27507
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iaef4d636cd2997144d8bc5012cd7c2a0a97102e5
Gerrit-Change-Number: 27507
Gerrit-PatchSet: 2
Gerrit-Owner: Matthew Poremba
Gerrit-Reviewer: Alexandru Duțu
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Handle empty object_file scenario in ArmFsWorkload
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/27707 )
Change subject: arch-arm: Handle empty object_file scenario in ArmFsWorkload
..
arch-arm: Handle empty object_file scenario in ArmFsWorkload
At the moment it is actually possible to pass en empty object file
to the ArmFsWorkload (OsKernel) class. We need to handle this
situation as well.
In case no bootloader nor object file is passed, we default to
AArch64 (default value for ArmFsWorkload)
Change-Id: I3b4aa8b8d61a8fac08da218125984b3bb1d38fb9
Signed-off-by: Giacomo Travaglini
---
M src/arch/arm/fs_workload.cc
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/arch/arm/fs_workload.cc b/src/arch/arm/fs_workload.cc
index 3d81156..8f40293 100644
--- a/src/arch/arm/fs_workload.cc
+++ b/src/arch/arm/fs_workload.cc
@@ -96,7 +96,7 @@
bootldr->loadGlobalSymbols(debugSymbolTable);
_highestELIs64 = (bootldr->getArch() == ObjectFile::Arm64);
-} else {
+} else if (obj) {
_highestELIs64 = (obj->getArch() == ObjectFile::Arm64);
}
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/27707
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3b4aa8b8d61a8fac08da218125984b3bb1d38fb9
Gerrit-Change-Number: 27707
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[develop]: mem: Modify DRAM controller for flexibility and new memories
Wendy Elsasser has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/26236 )
Change subject: mem: Modify DRAM controller for flexibility and new memories
..
mem: Modify DRAM controller for flexibility and new memories
This change includes:
1) Verify available command bandwidth
2) Add support for multi-cycle commands
3) Add new timing parameters
4) Add ability to interleave bursts
5) Add LPDDR5 configurations
The DRAM controller historically does not verify contention on the
command bus and if there is adaquate command bandwidth to issue a
new command. As memory technologies evolve, multiple cycles are becoming
a requirement for some commands. Depending on the burst length, this
can stress the command bandwidth. A check was added to verify command
issue does not exceed a maximum value within a defined window. The
default window is a burst, with the maximum value defined based on the
burst length and media clocking characteristics. When the command bandwidth
is exceeded, commands will be shifted to subsequent burst windows.
Added support for multi-cycle commands, specifically Activate, which
requires a larger address width as capacities grow. Additionally,
added support for multi-cycle Read / Write bursts for low power
DRAM cases in which additional CLK synchronization may be required
to run at higher speeds.
To support emerging memories, added the following new timing parameters.
1) tPPD -- Precharge-to-Precharge delay
2) tAAD -- Max delay between Activate-1 and Activate-2 commands
I/O data rates are continuing to increase for DRAM but the core frequency
is still fairly stagnant for many technologies. As we increase the burst
length, either the core prefetch needs to increase (for a seamless burst)
or the burst will be transferred with gaps on the data bus. To support
the latter case, added the ability to interleave 2 bursts across bank
groups.
Using the changes above, added an initial set of LPDDR5 configurations.
Change-Id: I1b14fed221350e6e403f7cbf089fe6c7f033c181
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26236
Reviewed-by: Matthew Poremba
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
Tested-by: kokoro
---
M configs/dram/sweep.py
M src/mem/DRAMCtrl.py
M src/mem/dram_ctrl.cc
M src/mem/dram_ctrl.hh
M src/mem/drampower.cc
5 files changed, 624 insertions(+), 56 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Matthew Poremba: Looks good to me, but someone else must approve
kokoro: Regressions pass
Gem5 Cloud Project GCB service account: Regressions pass
diff --git a/configs/dram/sweep.py b/configs/dram/sweep.py
index c2650a7..d3c86c3 100644
--- a/configs/dram/sweep.py
+++ b/configs/dram/sweep.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2014-2015, 2018-2019 ARM Limited
+# Copyright (c) 2014-2015, 2018-2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -146,7 +146,8 @@
# match the maximum bandwidth of the memory, the parameter is in seconds
# and we need it in ticks (ps)
-itt = system.mem_ctrls[0].tBURST.value * 1
+itt = getattr(system.mem_ctrls[0].tBURST_MIN, 'value',
+ system.mem_ctrls[0].tBURST.value) * 1
# assume we start at 0
max_addr = mem_range.end
@@ -180,8 +181,8 @@
def trace():
addr_map = ObjectList.dram_addr_map_list.get(options.addr_map)
generator = dram_generators[options.mode](system.tgen)
-for bank in range(1, nbr_banks + 1):
-for stride_size in range(burst_size, max_stride + 1, burst_size):
+for stride_size in range(burst_size, max_stride + 1, burst_size):
+for bank in range(1, nbr_banks + 1):
num_seq_pkts = int(math.ceil(float(stride_size) / burst_size))
yield generator(period,
0, max_addr, burst_size, int(itt), int(itt),
@@ -194,5 +195,5 @@
m5.simulate()
-print("DRAM sweep with burst: %d, banks: %d, max stride: %d" %
-(burst_size, nbr_banks, max_stride))
+print("DRAM sweep with burst: %d, banks: %d, max stride: %d, request \
+ generation period: %d" % (burst_size, nbr_banks, max_stride, itt))
diff --git a/src/mem/DRAMCtrl.py b/src/mem/DRAMCtrl.py
index 121d004..0f70dff 100644
--- a/src/mem/DRAMCtrl.py
+++ b/src/mem/DRAMCtrl.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012-2019 ARM Limited
+# Copyright (c) 2012-2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -171,7 +171,17 @@
# tBURST is equivalent to the CAS-to-CAS delay (tCCD)
# With bank group architectures, tBURST represents the CAS-to-CAS
# delay for bursts to different bank groups (tCCD_S)
-tBURST = Param.Latency("Burst duration (for DDR burst len
[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Add VExpress_GEM5_Foundation platform
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27388 )
Change subject: dev-arm: Add VExpress_GEM5_Foundation platform
..
dev-arm: Add VExpress_GEM5_Foundation platform
A new VExpress_GEM5_Foundation platform has been added in order to match
the FVP Armv8-A Foundation Platform described in:
Armv8-A Foundation Platform - User Guide - Version 11.8
The VExpress_GEM5_V1/V2 are already loosely based on the Foundation
platform, however there are some differences in the PCI regions (V1/V2)
and the GICv3 regions (V2).
We hence introduce the VExpress_GEM5_Foundation to match closely the
FVP Foundation Platform
Change-Id: I1604c64ce566308d888c3a630019494b9fae7acf
Signed-off-by: Giacomo Travaglini
Reviewed-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27388
Tested-by: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
Tested-by: kokoro
Reviewed-by: Ciro Santilli
---
M src/dev/arm/RealView.py
1 file changed, 34 insertions(+), 0 deletions(-)
Approvals:
Ciro Santilli: Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
Gem5 Cloud Project GCB service account: Regressions pass
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 0a26a94..a22ac4a 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -1209,3 +1209,37 @@
self.hdlcd,
]
+class VExpress_GEM5_Foundation(VExpress_GEM5_Base):
+"""
+Based on Armv8-A FVP Foundation platform v11.8
+Reference for memory and interrupt map:
+Armv8-A Foundation Platform - User Guide - Version 11.8
+Document ID: 100961_1180_00_en
+"""
+_off_chip_ranges = [
+# CS1-CS5
+AddrRange(0x0c00, 0x2000),
+# External AXI interface (PCI)
+AddrRange(0x4000, 0x8000),
+]
+
+gic = Gicv3(dist_addr=0x2f00, redist_addr=0x2f10,
+maint_int=ArmPPI(num=25), gicv4=False,
+its=NULL)
+
+pci_host = GenericArmPciHost(
+conf_base=0x4000, conf_size='256MB', conf_device_bits=12,
+pci_pio_base=0x5000,
+pci_mem_base=0x4,
+int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4)
+
+def _on_chip_devices(self):
+return super(VExpress_GEM5_Foundation, self)._on_chip_devices() + [
+self.gic
+]
+
+def setupBootLoader(self, cur_sys, loc, boot_loader=None):
+if boot_loader is None:
+boot_loader = [ loc('boot_v2.arm64') ]
+super(VExpress_GEM5_Foundation, self).setupBootLoader(
+cur_sys, boot_loader)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/27388
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1604c64ce566308d888c3a630019494b9fae7acf
Gerrit-Change-Number: 27388
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Adrian Herrera
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Proposal: Replace license headers with SPDX identifiers
Great point. I had forgotten about that exception. The ARM lawyers are looking into this now :). Cheers, Jason On Wed, Apr 8, 2020 at 5:52 PM Bobby Bruce wrote: > I think this is a great idea. My only question is that some of our code has > a slightly extended BSD license. In particular I'm thinking about code ARM > is involved in (E.g. : > > https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/src/arch/arm/decoder.cc > ). Is the solution here something like?: > > ``` > Copyright (c) 2012-2014,2018 ARM Limited > All rights reserved > > The license below extends only to copyright in the software and shall > not be construed as granting a license to any other intellectual > property including but not limited to intellectual property relating > to a hardware implementation of the functionality of the software > licensed hereunder. You may use the software subject to the license > terms below provided that you ensure that this notice is replicated > unmodified and in its entirety in all distributions of the software, > modified or unmodified, in source code or in binary form. > > SPDX-License-Identifier: BSD-3-Clause > > ``` > > Software copyrights, patents, licencing, etc have always confused the heck > out of me, so sorry if it's a newbie question :). > > -- > Dr. Bobby R. Bruce > Room 2235, > Kemper Hall, UC Davis > Davis, > CA, 95616 > > web: https://www.bobbybruce.net > > > On Wed, Apr 8, 2020 at 4:49 PM Jason Lowe-Power > wrote: > > > Hi all, > > > > I propose to replace all of the BSD text in the headers of all files with > > the following: > > > > /* > > * Copyright (c) the > > University of California.> > > * All rights reserved. > > * > > * SPDX-License-Identifier: BSD-3-Clause > > */ > > > > We will also update the LICENSE file to say the following: > > > > ``` > > Note: Individual files contain the following tag instead of the full > > license text. > > > > SPDX-License-Identifier: BSD-3-Clause > > > > This enables machine processing of license information based on the SPDX > > License Identifiers that are here available: http://spdx.org/licenses/ > > ``` > > > > See https://spdx.org/ids-how for more information about SPDX license > IDs. > > > > Before we go through and make a giant changeset (or changesets) to do > this, > > I'd like to make sure this is something that will work for the community. > > > > Let me know what you think! > > > > Cheers, > > Jason > > ___ > > gem5-dev mailing list > > gem5-dev@gem5.org > > http://m5sim.org/mailman/listinfo/gem5-dev > ___ > gem5-dev mailing list > gem5-dev@gem5.org > http://m5sim.org/mailman/listinfo/gem5-dev ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] qemu ARM not dying on m5 ops?
This is what ends up in the si_addr field of the siginfo_t that gets passed to my signal handler. Since this is at the application level, I don't really know what's happening at the "hardware" level in QEMU, or how it translates that into signal stuff. Right now I'm trying out crosstool-ng to build a SPARC toolchain since that was also broken for some weird, toolchain looking reason, but once I have that handled I'll see if I can get ahold of the QEMU folks. Thanks! Gabe On Thu, Apr 9, 2020 at 5:38 AM Giacomo Travaglini < giacomo.travagl...@arm.com> wrote: > Agree with Ciro. > > What do you mean by PC here anyway? > > "Also I notice that the thumb version traps, but gives me some other PC > which doesn't actually correspond to the illegal instruction" > > Are you referring to the value stored in the ELR_EL1 (Exception link > register) or the PC of the exception handler? > > Giacomo > > -Original Message- > From: gem5-dev On Behalf Of Ciro Santilli > Sent: 09 April 2020 13:30 > To: gem5 Developer List > Subject: Re: [gem5-dev] qemu ARM not dying on m5 ops? > > Send an email to the QEMU mailing list with the instruction encoding, > possibly CC Peter Maydell, he usually replies super fast 🙂 > > From: gem5-dev on behalf of Gabe Black < > gabebl...@google.com> > Sent: Thursday, April 9, 2020 1:24 PM > To: gem5 Developer List > Subject: [gem5-dev] qemu ARM not dying on m5 ops? > > Hi ARM folks. I'm trying to run my shiny new instruction based m5 op test > on QEMU for ARM, and it's not actually exploding with an illegal > instruction when it tries to run an m5 op. I've tried this with the older > version of the utility as well, and I see the same behavior. > > I've dug into it, and the encoding is doing a move from a coprocessor > register into a regular register I think, and operating on coprocessor 1. I > *think* if the coprocessor doesn't exist, the CPU is supposed to trap > somehow, and not just plow ahead. > > Is this something wrong with QEMU? Do I need to pass it some magical flag > to get it to work like I expect? I'm not super worried about how correct > QEMU is, but I want to make sure the code in the m5 utility is correct. It > would be nice if QEMU ran it correctly too, since that would be a nice > independent way to verify that the utility is still working. > > Any help would be appreciated! > > Also I notice that the thumb version traps, but gives me some other PC > which doesn't actually correspond to the illegal instruction. I'm not sure > what's going on there. I'll probably try running these on real ARM hardware > I have with me to see if they do what I want there. > > Gabe > ___ > gem5-dev mailing list > gem5-dev@gem5.org > http://m5sim.org/mailman/listinfo/gem5-dev > ___ > gem5-dev mailing list > gem5-dev@gem5.org > http://m5sim.org/mailman/listinfo/gem5-dev > IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > ___ > gem5-dev mailing list > gem5-dev@gem5.org > http://m5sim.org/mailman/listinfo/gem5-dev ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] qemu ARM not dying on m5 ops?
Hi ARM folks. I'm trying to run my shiny new instruction based m5 op test on QEMU for ARM, and it's not actually exploding with an illegal instruction when it tries to run an m5 op. I've tried this with the older version of the utility as well, and I see the same behavior. I've dug into it, and the encoding is doing a move from a coprocessor register into a regular register I think, and operating on coprocessor 1. I *think* if the coprocessor doesn't exist, the CPU is supposed to trap somehow, and not just plow ahead. Is this something wrong with QEMU? Do I need to pass it some magical flag to get it to work like I expect? I'm not super worried about how correct QEMU is, but I want to make sure the code in the m5 utility is correct. It would be nice if QEMU ran it correctly too, since that would be a nice independent way to verify that the utility is still working. Any help would be appreciated! Also I notice that the thumb version traps, but gives me some other PC which doesn't actually correspond to the illegal instruction. I'm not sure what's going on there. I'll probably try running these on real ARM hardware I have with me to see if they do what I want there. Gabe ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] qemu ARM not dying on m5 ops?
Agree with Ciro. What do you mean by PC here anyway? "Also I notice that the thumb version traps, but gives me some other PC which doesn't actually correspond to the illegal instruction" Are you referring to the value stored in the ELR_EL1 (Exception link register) or the PC of the exception handler? Giacomo -Original Message- From: gem5-dev On Behalf Of Ciro Santilli Sent: 09 April 2020 13:30 To: gem5 Developer List Subject: Re: [gem5-dev] qemu ARM not dying on m5 ops? Send an email to the QEMU mailing list with the instruction encoding, possibly CC Peter Maydell, he usually replies super fast 🙂 From: gem5-dev on behalf of Gabe Black Sent: Thursday, April 9, 2020 1:24 PM To: gem5 Developer List Subject: [gem5-dev] qemu ARM not dying on m5 ops? Hi ARM folks. I'm trying to run my shiny new instruction based m5 op test on QEMU for ARM, and it's not actually exploding with an illegal instruction when it tries to run an m5 op. I've tried this with the older version of the utility as well, and I see the same behavior. I've dug into it, and the encoding is doing a move from a coprocessor register into a regular register I think, and operating on coprocessor 1. I *think* if the coprocessor doesn't exist, the CPU is supposed to trap somehow, and not just plow ahead. Is this something wrong with QEMU? Do I need to pass it some magical flag to get it to work like I expect? I'm not super worried about how correct QEMU is, but I want to make sure the code in the m5 utility is correct. It would be nice if QEMU ran it correctly too, since that would be a nice independent way to verify that the utility is still working. Any help would be appreciated! Also I notice that the thumb version traps, but gives me some other PC which doesn't actually correspond to the illegal instruction. I'm not sure what's going on there. I'll probably try running these on real ARM hardware I have with me to see if they do what I want there. Gabe ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] qemu ARM not dying on m5 ops?
Send an email to the QEMU mailing list with the instruction encoding, possibly CC Peter Maydell, he usually replies super fast 🙂 From: gem5-dev on behalf of Gabe Black Sent: Thursday, April 9, 2020 1:24 PM To: gem5 Developer List Subject: [gem5-dev] qemu ARM not dying on m5 ops? Hi ARM folks. I'm trying to run my shiny new instruction based m5 op test on QEMU for ARM, and it's not actually exploding with an illegal instruction when it tries to run an m5 op. I've tried this with the older version of the utility as well, and I see the same behavior. I've dug into it, and the encoding is doing a move from a coprocessor register into a regular register I think, and operating on coprocessor 1. I *think* if the coprocessor doesn't exist, the CPU is supposed to trap somehow, and not just plow ahead. Is this something wrong with QEMU? Do I need to pass it some magical flag to get it to work like I expect? I'm not super worried about how correct QEMU is, but I want to make sure the code in the m5 utility is correct. It would be nice if QEMU ran it correctly too, since that would be a nice independent way to verify that the utility is still working. Any help would be appreciated! Also I notice that the thumb version traps, but gives me some other PC which doesn't actually correspond to the illegal instruction. I'm not sure what's going on there. I'll probably try running these on real ARM hardware I have with me to see if they do what I want there. Gabe ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[develop]: util: Add stub unit tests for the call types in the m5 utility.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/27688 )
Change subject: util: Add stub unit tests for the call types in the m5
utility.
..
util: Add stub unit tests for the call types in the m5 utility.
These will be filled out in later changes. This CL just adds the
plumbing to the build script.
Change-Id: If58ea023d0c85eae0160f88217c83fca70346da2
---
M util/m5/SConstruct
M util/m5/src/SConscript
A util/m5/src/call_type/addr.test.cc
A util/m5/src/call_type/inst.test.cc
A util/m5/src/call_type/semi.test.cc
5 files changed, 124 insertions(+), 7 deletions(-)
diff --git a/util/m5/SConstruct b/util/m5/SConstruct
index cb67b50..da9543e 100644
--- a/util/m5/SConstruct
+++ b/util/m5/SConstruct
@@ -43,8 +43,8 @@
return os.path.abspath(str(d))
# Universal settings.
-main.Append(CXXFLAGS=[ '-O2' ])
-main.Append(CCFLAGS=[ '-O2' ])
+main.Append(CXXFLAGS=[ '-O2', '-g' ])
+main.Append(CCFLAGS=[ '-O2', '-g' ])
main.Append(CPPPATH=[ common_include ])
# Propogate the environment's PATH setting.
@@ -62,7 +62,7 @@
main.SetOption('duplicate', 'soft-copy')
def build_gtest_env(env):
-gtest_env = env.Clone(OBJSUFFIX='.to')
+gtest_env = env.Clone(OBJSUFFIX='.to', SHOBJSUFFIX='.sto')
gtest_env.Append(CPPFLAGS=[ '${GTEST_CPPFLAGS}' ])
gtest_env.Append(LIBS=[ '${GTEST_LIBS}' ])
return gtest_env
diff --git a/util/m5/src/SConscript b/util/m5/src/SConscript
index a8a5d8d..9420199 100644
--- a/util/m5/src/SConscript
+++ b/util/m5/src/SConscript
@@ -42,7 +42,9 @@
all_call_types = list(env['CALL_TYPE'].values())
call_types = list([ ct for ct in all_call_types if ct.enabled ])
-m5ops = list([ 'variant/${VARIANT}/%s' % ct.impl_file for ct in call_types
])
+m5ops = { ct.name: 'variant/${VARIANT}/%s' % ct.impl_file
+ for ct in call_types }
+all_m5ops = list(m5ops.values())
default_call_type = list([ ct for ct in call_types if ct.default ])
assert len(default_call_type) == 1, \
@@ -56,7 +58,7 @@
#
# The m5 library for use in other C/C++ programs.
#
-libm5 = static_env.StaticLibrary('out/m5', [ m5_mmap ] + m5ops)
+libm5 = static_env.StaticLibrary('out/m5', [ m5_mmap ] + all_m5ops)
commands = env.SConscript('command/SConscript', exports={ "env":
static_env })
@@ -76,7 +78,20 @@
# The shared version of the m5 op call sights, used by mutliple targets
below.
shared_env = env.Clone()
shared_env.Append(ASFLAGS='-DM5OP_PIC')
-m5op_shared = shared_env.SharedObject(m5ops)
+m5op_shared = shared_env.SharedObject(all_m5ops)
+
+#
+# Unit tests for enabled call types.
+#
+call_type_shared = shared_env.SharedObject(call_type)
+args_shared = shared_env.SharedObject(args)
+m5_mmap_shared = shared_env.SharedObject(m5_mmap)
+for ct in call_types:
+ct_env = shared_env.Clone()
+ct_env.Append(CXXFLAGS=[ '-DCALL_TYPE_IS_DEFAULT=false' ])
+ct_env.GTest('call_type/%s' % ct.name, 'call_type/%s.test.cc' %
ct.name,
+ 'call_type/%s.cc' % ct.name, call_type_shared,
args_shared,
+ m5_mmap_shared, m5ops[ct.name])
if env['HAVE_JAVA']:
#
@@ -106,4 +121,4 @@
# Extract the include paths needed for lua51 using pkg-config.
lua_env.ParseConfig('pkg-config --cflags lua51')
lib = lua_env.SharedLibrary('out/gem5OpLua',
-[ lua, m5_mmap ] + m5op_shared)
+[ lua, m5_mmap_shared ] + m5op_shared)
diff --git a/util/m5/src/call_type/addr.test.cc
b/util/m5/src/call_type/addr.test.cc
new file mode 100644
index 000..42b7341
--- /dev/null
+++ b/util/m5/src/call_type/addr.test.cc
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2020 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS IN
[gem5-dev] Change in gem5/gem5[develop]: util: Add a unit test for the "inst" call type in the m5 util.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/27689 )
Change subject: util: Add a unit test for the "inst" call type in the m5
util.
..
util: Add a unit test for the "inst" call type in the m5 util.
This test does two things. First, it makes sure that the "inst" call
type detects that it's being requested in the command line arguments
correctly.
Second, it detects whether it's running in gem5 or not, really just
detecting an environment variable which tells it whether it is. If it
is, then it attempts to run the "sum" op which it expects to succeed and
give the right answer.
If not, it expects to get a SIGILL signal from the OS when it tries to
execute the otherwise illegal instruction. It sets up a signal handler
to catch it, and in that handler saves off information about what
happened. It then uses siglongjmp to return to sanity (before the
signal) and to examine what happened to see if the right instruction was
attempted.
It looks like, depending on the architecture, Linux will either set
si_code to ILL_ILLOPC (illegal opcode) or ILL_ILLOPN (illegal operand).
The later doesn't seem right since the entire instruction is illegal,
not just some operand, but it is what it is and we need to handle
either.
The test also uses a little snippet of code, passed in from the
per-variant config within SCons as a macro, to extract the m5 op func
number from the instruction that failed. The instruction is located at
si_addr in the siginfo_t, and is passed to the macro as "ptr".
Finally, to avoid that macro leaking all over, and to centralize setting
the macro which lets a call type know that it's the default, the call
types are now also responsible for setting up their own tweaks to the
environment. Since the semihosting type is specific to ARM and hence
won't need to be parameterized and the addr type is consistent across
variants, we shouldn't need to specialize those other call types like we
did for inst.
Change-Id: I8710e39e20bd9c03b1375a2dccefb27bd6fe0c10
---
M util/m5/SConstruct
M util/m5/src/SConscript
M util/m5/src/call_type/inst.test.cc
M util/m5/src/variant/aarch64/SConsopts
M util/m5/src/variant/arm/SConsopts
M util/m5/src/variant/sparc/SConsopts
M util/m5/src/variant/thumb/SConsopts
M util/m5/src/variant/x86/SConsopts
8 files changed, 156 insertions(+), 6 deletions(-)
diff --git a/util/m5/SConstruct b/util/m5/SConstruct
index da9543e..0cc6253 100644
--- a/util/m5/SConstruct
+++ b/util/m5/SConstruct
@@ -104,9 +104,32 @@
self.enabled = True
self.default = default
+# Being the default can be disabled for testing purposes, so we can
tell if
+# a call type was selected because it was chosen, or because nobody
else
+# was.
+def setup_env(self, env, allow_default=True):
+env = env.Clone()
+is_default = 'true' if self.default and allow_default else 'false'
+env.Append(CXXFLAGS=[ '-DCALL_TYPE_IS_DEFAULT=%s' % is_default ])
+return env
+
+class InstCallType(CallType):
+def __init__(self):
+super(InstCallType, self).__init__('inst')
+self.ext = ""
+
+def extractor(self, extractor):
+self.ext = extractor
+
+def setup_env(self, env, allow_default=True):
+env = super(InstCallType, self).setup_env(env, allow_default)
+extractor_def = '-DEXTRACT_FUNC_FROM_INST(ptr)=%s' % self.ext
+env.Append(CXXFLAGS=[ extractor_def ])
+return env
+
call_types = {
# Magic instruction.
-'inst': CallType('inst'),
+'inst': InstCallType(),
# Magic address.
'addr': CallType('addr'),
# Semihosting extension.
diff --git a/util/m5/src/SConscript b/util/m5/src/SConscript
index 9420199..33dc191 100644
--- a/util/m5/src/SConscript
+++ b/util/m5/src/SConscript
@@ -67,9 +67,7 @@
#
ct_support = []
for ct in call_types:
-ct_env = static_env.Clone()
-is_default = 'true' if ct.default else 'false'
-ct_env.Append(CXXFLAGS=[ '-DCALL_TYPE_IS_DEFAULT=%s' % is_default ])
+ct_env = ct.setup_env(static_env)
ct_support.extend(ct_env.StaticObject('call_type/%s.cc' % ct.name))
m5_bin = static_env.Program('out/m5', ct_support +
[ args, call_type, command, commands, m5, m5_mmap, libm5, usage ])
@@ -87,8 +85,7 @@
args_shared = shared_env.SharedObject(args)
m5_mmap_shared = shared_env.SharedObject(m5_mmap)
for ct in call_types:
-ct_env = shared_env.Clone()
-ct_env.Append(CXXFLAGS=[ '-DCALL_TYPE_IS_DEFAULT=false' ])
+ct_env = ct.setup_env(shared_env, allow_default=False)
ct_env.GTest('call_type/%s' % ct.name, 'call_type/%s.test.cc' %
ct.name,
'call_type/%s.cc' % ct.name, call_type_shared,
args_shared,
m5_mmap_shared, m5ops[ct.name])
diff --git a/util/m5/src/call_type/inst.test.cc
b/util/m5/src/call_type/inst.test.cc
index e4a8520..1e83e31 100644
--- a/util/m5/src/ca
[gem5-dev] Change in gem5/gem5[develop]: util: Pull "usage()" out of the call types in the m5 utility.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/27687 )
Change subject: util: Pull "usage()" out of the call types in the m5
utility.
..
util: Pull "usage()" out of the call types in the m5 utility.
Also pull common implementations of some call type methods into the base
class, and make disappearing call types clean themselves up to make the
test a little simpler and less error prone.
Change-Id: Ie178fe02d41587647ddc90a084d1d1142b84dde9
---
M util/m5/src/SConscript.native
M util/m5/src/call_type.cc
M util/m5/src/call_type.hh
M util/m5/src/call_type.test.cc
M util/m5/src/call_type/addr.cc
M util/m5/src/call_type/inst.cc
M util/m5/src/call_type/semi.cc
M util/m5/src/m5.cc
8 files changed, 113 insertions(+), 110 deletions(-)
diff --git a/util/m5/src/SConscript.native b/util/m5/src/SConscript.native
index e4897ce..b9ae6bc 100644
--- a/util/m5/src/SConscript.native
+++ b/util/m5/src/SConscript.native
@@ -28,7 +28,7 @@
env.Append(CPPPATH=Dir('.'))
env.GTest('args')
-env.GTest('call_type')
+env.GTest('call_type', 'call_type.test.cc', 'call_type.cc', 'args.cc')
env.GTest('command', 'command.test.cc', 'command.cc', 'args.cc')
command_tests = env.SConscript('command/SConscript.native', exports='env')
diff --git a/util/m5/src/call_type.cc b/util/m5/src/call_type.cc
index 55499ba..21a2cc1 100644
--- a/util/m5/src/call_type.cc
+++ b/util/m5/src/call_type.cc
@@ -28,40 +28,58 @@
#include
#include
+#include "args.hh"
#include "call_type.hh"
-std::vector &
-CallType::allTypes()
+std::map &
+CallType::map()
{
-static std::vector all;
+static std::map all;
return all;
}
-CallType &
+CallType::CheckArgsResult
+CallType::checkArgs(Args &args)
+{
+if (args.size() && args[0] == "--" + name) {
+args.pop();
+return Match;
+}
+return NoMatch;
+}
+
+CallType *
CallType::detect(Args &args)
{
CallType *def = nullptr;
-for (auto *ct: allTypes()) {
-if (ct->checkArgs(args)) {
-ct->init();
-return *ct;
+for (auto p: map()) {
+auto &ct = p.second;
+if (ct.isDefault())
+def = &ct;
+auto result = ct.checkArgs(args);
+switch (result) {
+ case Match:
+ct.init();
+return &ct;
+ case NoMatch:
+continue;
+ case Usage:
+return nullptr;
}
-if (ct->isDefault())
-def = ct;
}
assert(def);
def->init();
-return *def;
+return def;
}
std::string
CallType::usageSummary()
{
std::string summary = "";
-for (auto *ct: allTypes())
-summary += ct->formattedUsage();
+for (auto p: map())
+summary += p.second.formattedUsage();
return summary;
}
diff --git a/util/m5/src/call_type.hh b/util/m5/src/call_type.hh
index 0244d20..89bb544 100644
--- a/util/m5/src/call_type.hh
+++ b/util/m5/src/call_type.hh
@@ -29,29 +29,49 @@
#define __CALL_TYPE_HH__
#include
+#include
#include
-#include
+#include
class Args;
class DispatchTable;
class CallType
{
+ public:
+enum CheckArgsResult {
+Match,
+NoMatch,
+Usage
+};
+
protected:
+const std::string name;
+
virtual bool isDefault() = 0;
-virtual bool checkArgs(Args &args) = 0;
+virtual CheckArgsResult checkArgs(Args &args);
virtual void init() {}
-static std::vector &allTypes();
+static std::map &map();
-virtual void printBrief(std::ostream &os) = 0;
+virtual void printBrief(std::ostream &os) { os << "--" << name; }
virtual void printDesc(std::ostream &os) = 0;
std::string formattedUsage();
public:
-CallType() { allTypes().push_back(this); }
+CallType(const std::string &_name) : name(_name)
+{
+map().emplace(std::piecewise_construct,
+std::forward_as_tuple(std::string(_name)),
+std::forward_as_tuple(*this));
+}
-static CallType &detect(Args &args);
+~CallType()
+{
+map().erase(name);
+}
+
+static CallType *detect(Args &args);
static std::string usageSummary();
virtual const DispatchTable &getDispatch() = 0;
diff --git a/util/m5/src/call_type.test.cc b/util/m5/src/call_type.test.cc
index a5ab21f..535926e 100644
--- a/util/m5/src/call_type.test.cc
+++ b/util/m5/src/call_type.test.cc
@@ -30,18 +30,17 @@
// For EXPECT_THAT and HasSubstr
#include
+#include "args.hh"
#include "call_type.hh"
// Simple substitute definitions for Args and DispatchTable, with an int so
// we can tell instances apart.
-class Args { public: int i; };
class DispatchTable { public: int i; };
class TestCallType : public CallType
{
protected:
bool isDefault() override { return testIsDefault; }
-bool checkArgs(Args &args) override { return args.i == testAcceptArgs;
}
void
init() override
[gem5-dev] Change in gem5/gem5[develop]: configs: add option for memory channel intlv.
Adrian Herrera has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27629 )
Change subject: configs: add option for memory channel intlv.
..
configs: add option for memory channel intlv.
Current memory channel interleave is hard-coded to be maximum between 128
and system's cache line size. Making this value configurable enables use
cases with DMA masters accessing at higher than 128 block granularity.
Change-Id: I8123fa307efd3fd8f16c815ee74a84844bb51edb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27629
Tested-by: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
Tested-by: kokoro
Reviewed-by: Daniel Carvalho
Reviewed-by: Bobby R. Bruce
Maintainer: Bobby R. Bruce
---
M configs/common/MemConfig.py
M configs/common/Options.py
2 files changed, 6 insertions(+), 3 deletions(-)
Approvals:
Daniel Carvalho: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
Gem5 Cloud Project GCB service account: Regressions pass
diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py
index d1cc655..9443520 100644
--- a/configs/common/MemConfig.py
+++ b/configs/common/MemConfig.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2013, 2017 ARM Limited
+# Copyright (c) 2013, 2017, 2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -109,6 +109,7 @@
opt_elastic_trace_en = getattr(options, "elastic_trace_en", False)
opt_mem_ranks = getattr(options, "mem_ranks", None)
opt_dram_powerdown = getattr(options, "enable_dram_powerdown", None)
+opt_mem_channels_intlv = getattr(options, "mem_channels_intlv", 128)
if opt_mem_type == "HMC_2500_1x32":
HMChost = HMC.config_hmc_host_ctrl(options, system)
@@ -154,7 +155,7 @@
# byte granularity, or cache line granularity if larger than 128
# byte. This value is based on the locality seen across a large
# range of workloads.
-intlv_size = max(128, system.cache_line_size.value)
+intlv_size = max(opt_mem_channels_intlv, system.cache_line_size.value)
# For every range (most systems will only have one), create an
# array of controllers and set their parameters to match their
diff --git a/configs/common/Options.py b/configs/common/Options.py
index 6c92f36..6d0c6c2 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2013-2019 ARM Limited
+# Copyright (c) 2013-2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -110,6 +110,8 @@
help="Specify the physical memory size (single
memory)")
parser.add_option("--enable-dram-powerdown", action="store_true",
help="Enable low-power states in DRAMCtrl")
+parser.add_option("--mem-channels-intlv", type="int",
+ help="Memory channels interleave")
parser.add_option("--memchecker", action="store_true")
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/27629
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8123fa307efd3fd8f16c815ee74a84844bb51edb
Gerrit-Change-Number: 27629
Gerrit-PatchSet: 2
Gerrit-Owner: Adrian Herrera
Gerrit-Reviewer: Adrian Herrera
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
