[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Support device memories
Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/29653 )
Change subject: mem-ruby: Support device memories
..
mem-ruby: Support device memories
Adds support for device memories in the system and RubySystem classes.
Devices may register memory ranges with the system class and packets
which originate from the device MasterID will update the device memory
in Ruby. In RubySystem functional access is updated to keep the packets
within the Ruby network they originated from.
Change-Id: I47850df1dc1994485d471ccd9da89e8d88eb0d20
JIRA: https://gem5.atlassian.net/browse/GEM5-470
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29653
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/network/Network.cc
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/ruby/system/RubyPort.cc
M src/mem/ruby/system/RubyPort.hh
M src/mem/ruby/system/RubySystem.cc
M src/mem/ruby/system/RubySystem.hh
M src/mem/ruby/system/RubySystem.py
M src/mem/slicc/symbols/StateMachine.py
M src/sim/system.cc
M src/sim/system.hh
11 files changed, 170 insertions(+), 29 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/network/Network.cc
b/src/mem/ruby/network/Network.cc
index 982b57e..ba847e5 100644
--- a/src/mem/ruby/network/Network.cc
+++ b/src/mem/ruby/network/Network.cc
@@ -55,6 +55,8 @@
m_virtual_networks = p->number_of_virtual_networks;
m_control_msg_size = p->control_msg_size;
+params()->ruby_system->registerNetwork(this);
+
// Populate localNodeVersions with the version of each MachineType in
// this network. This will be used to compute a global to local ID.
// Do this by looking at the ext_node for each ext_link. There is one
@@ -64,6 +66,7 @@
for (auto &it : params()->ext_links) {
AbstractController *cntrl = it->params()->ext_node;
localNodeVersions[cntrl->getType()].push_back(cntrl->getVersion());
+params()->ruby_system->registerMachineID(cntrl->getMachineID(),
this);
}
// Compute a local ID for each MachineType using the same order as
SLICC
@@ -104,8 +107,6 @@
m_ordered[i] = false;
}
-params()->ruby_system->registerNetwork(this);
-
// Initialize the controller's network pointers
for (std::vector::const_iterator i =
p->ext_links.begin();
i != p->ext_links.end(); ++i) {
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc
b/src/mem/ruby/slicc_interface/AbstractController.cc
index bdc88b9..9da8727 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -68,7 +68,6 @@
void
AbstractController::init()
{
-params()->ruby_system->registerAbstractController(this);
m_delayHistogram.init(10);
uint32_t size = Network::getNumberOfVirtualNetworks();
for (uint32_t i = 0; i < size; i++) {
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh
b/src/mem/ruby/slicc_interface/AbstractController.hh
index 1577cfa..750a620 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -147,6 +147,7 @@
public:
MachineID getMachineID() const { return m_machineID; }
+MasterID getMasterId() const { return m_masterId; }
Stats::Histogram& getDelayHist() { return m_delayHistogram; }
Stats::Histogram& getDelayVCHist(uint32_t index)
diff --git a/src/mem/ruby/system/RubyPort.cc
b/src/mem/ruby/system/RubyPort.cc
index 92fed81..0526e65 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -252,7 +252,7 @@
// Check for pio requests and directly send them to the dedicated
// pio port.
if (pkt->cmd != MemCmd::MemFenceReq) {
-if (!isPhysMemAddress(pkt->getAddr())) {
+if (!isPhysMemAddress(pkt)) {
assert(ruby_port->memMasterPort.isConnected());
DPRINTF(RubyPort, "Request address %#x assumed to be a "
"pio address\n", pkt->getAddr());
@@ -313,7 +313,7 @@
// Check for pio requests and directly send them to the dedicated
// pio port.
if (pkt->cmd != MemCmd::MemFenceReq) {
-if (!isPhysMemAddress(pkt->getAddr())) {
+if (!isPhysMemAddress(pkt)) {
assert(ruby_port->memMasterPort.isConnected());
DPRINTF(RubyPort, "Request address %#x assumed to be a "
"pio address\n", pkt->getAddr());
@@ -371,7 +371,7 @@
// Check for pio requests and directly send them to the dedicated
// pio port.
-if (!isPhysMemAddress(pkt->getAddr())) {
+if (!isPhysMemAddress(pkt)) {
DPRINTF(RubyPort, "Pio Request for address: 0x%#x\
[gem5-dev] Change in gem5/gem5[develop]: stats: add --stats-root option to dump only under some SimObjects
Ciro Santilli has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28628 )
Change subject: stats: add --stats-root option to dump only under some
SimObjects
..
stats: add --stats-root option to dump only under some SimObjects
This commit makes it possible to make invocations such as:
gem5.opt se.py --stats-root 'system.cpu[:].dtb' --stats-root 'system.membus'
When --stats-root is given, only stats that are under any of the root
SimObjects get dumped. E.g. the above invocation would dump stats such as:
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED
system.membus.pwrStateResidencyTicks::UNDEFINED
system.membus.trans_dist::ReadReq
but not for example `system.clk_domain.clock`.
If the --stats-root is given, only new stats as defined at:
Idc8ff448b9f70a796427b4a5231e7371485130b4 get dumped, and old ones are
ignored. The commits following that one have done some initial conversion
work, but many stats are still in the old format.
Change-Id: Iadaef26edf9a678b39f774515600884fbaeec497
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28628
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M RELEASE-NOTES.md
M configs/common/Options.py
M configs/common/Simulation.py
M src/python/m5/SimObject.py
M src/python/m5/stats/__init__.py
5 files changed, 61 insertions(+), 18 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/RELEASE-NOTES.md b/RELEASE-NOTES.md
index 3542de9..adf33b2 100644
--- a/RELEASE-NOTES.md
+++ b/RELEASE-NOTES.md
@@ -1,3 +1,7 @@
+# Version 20.1.0.0
+
+* m5.stats.dump() root argument renamed to roots to reflect the fact that
it now takes a list of SimObjects
+
# Version 20.0.0.2
**[HOTFIX]** A patch was applied to fix the RubyPrefetcher with
MESI_Three_Level. Prior to this fix a segfault occurred.
diff --git a/configs/common/Options.py b/configs/common/Options.py
index 3eff04b..0409fb8 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -361,6 +361,14 @@
parser.add_option("--arm-iset", default="arm", type="choice",
choices=["arm", "thumb", "aarch64"],
help="ARM instruction set.")
+parser.add_option("--stats-root", action="append", default=[], help=
+"If given, dump only stats of objects under the given SimObject. "
+"SimObjects are identified with Python notation as in: "
+"system.cpu[0].dtb. All elements of an array can be selected at "
+"once with: system.cpu[:].dtb. If given multiple times, dump
stats "
+"that are present under any of the roots. If not given, dump all "
+"stats. "
+)
def addSEOptions(parser):
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py
index e53c755..e7fb878 100644
--- a/configs/common/Simulation.py
+++ b/configs/common/Simulation.py
@@ -451,6 +451,12 @@
if options.repeat_switch and options.take_checkpoints:
fatal("Can't specify both --repeat-switch and --take-checkpoints")
+# Setup global stat filtering.
+stat_root_simobjs = []
+for stat_root_str in options.stats_root:
+stat_root_simobjs.extend(root.get_simobj(stat_root_str))
+m5.stats.global_dump_roots = stat_root_simobjs
+
np = options.num_cpus
switch_cpus = None
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index a045fb7..7f12856 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2017-2019 ARM Limited
+# Copyright (c) 2017-2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -1071,6 +1071,9 @@
out.extend(sim_object[i] for i in _range)
return SimObjectCliWrapper(out)
+def __iter__(self):
+return iter(self._sim_objects)
+
# The SimObject class is the root of the special hierarchy. Most of
# the code in this class deals with the configuration hierarchy itself
# (parent/child node relationships).
@@ -1695,6 +1698,18 @@
for param in params:
exec(param, d)
+def get_simobj(self, simobj_path):
+"""
+Get all sim objects that match a given string.
+
+The format is the same as that supported by SimObjectCliWrapper.
+
+:param simobj_path: Current state to be in.
+:type simobj_path: str
+"""
+d = self._apply_config_get_dict()
+return eval(simobj_path, d)
+
# Function to provide to C++ so it can look up instances based on paths
def resolveSimObject(name):
obj = instanceDict[name]
diff --git a/src/python/m5/stats/__init__.py
b/src/python/m5/stats/__init__.py
index 1e37a14..6c4a42c 100644
--- a/src/python/m5/stats/__init__.py
+++
