[gem5-dev] Change in gem5/gem5[develop]: learning-gem5: convert simple cache to new style stats

2020-09-04 Thread Eden Avivi (Gerrit) via gem5-dev
Eden Avivi has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34135 )


Change subject: learning-gem5: convert simple cache to new style stats
..

learning-gem5: convert simple cache to new style stats

Change-Id: I6988c45c13955825fde974f390460f4473af017a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34135
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/learning_gem5/part2/simple_cache.cc
M src/learning_gem5/part2/simple_cache.hh
2 files changed, 21 insertions(+), 36 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/learning_gem5/part2/simple_cache.cc  
b/src/learning_gem5/part2/simple_cache.cc

index 25f6bd7..ad5e663 100644
--- a/src/learning_gem5/part2/simple_cache.cc
+++ b/src/learning_gem5/part2/simple_cache.cc
@@ -38,7 +38,7 @@
 blockSize(params->system->cacheLineSize()),
 capacity(params->size / blockSize),
 memPort(params->name + ".mem_side", this),
-blocked(false), originalPacket(nullptr), waitingPortId(-1)
+blocked(false), originalPacket(nullptr), waitingPortId(-1), stats(this)
 {
 // Since the CPU side ports are a vector of ports, create an instance  
of

 // the CPUSidePort for each connection. This member of params is
@@ -221,7 +221,7 @@
 // for any added latency.
 insert(pkt);

-missLatency.sample(curTick() - missTime);
+stats.missLatency.sample(curTick() - missTime);

 // If we had to upgrade the request packet to a full cache line, now we
 // can use that packet to construct the response.
@@ -286,12 +286,12 @@

 if (hit) {
 // Respond to the CPU side
-hits++; // update stats
+stats.hits++; // update stats
 DDUMP(SimpleCache, pkt->getConstPtr(), pkt->getSize());
 pkt->makeResponse();
 sendResponse(pkt);
 } else {
-misses++; // update stats
+stats.misses++; // update stats
 missTime = curTick();
 // Forward to the memory side.
 // We can't directly forward the packet unless it is exactly the  
size

@@ -421,31 +421,15 @@
 }
 }

-void
-SimpleCache::regStats()
+SimpleCache::SimpleCacheStats::SimpleCacheStats(Stats::Group *parent)
+  : Stats::Group(parent),
+  ADD_STAT(hits, "Number of hits"),
+  ADD_STAT(misses, "Number of misses"),
+  ADD_STAT(missLatency, "Ticks for misses to the cache"),
+  ADD_STAT(hitRatio, "The ratio of hits to the total"
+ "accesses to the cache", hits / (hits + misses))
 {
-// If you don't do this you get errors about uninitialized stats.
-ClockedObject::regStats();
-
-hits.name(name() + ".hits")
-.desc("Number of hits")
-;
-
-misses.name(name() + ".misses")
-.desc("Number of misses")
-;
-
-missLatency.name(name() + ".missLatency")
-.desc("Ticks for misses to the cache")
-.init(16) // number of buckets
-;
-
-hitRatio.name(name() + ".hitRatio")
-.desc("The ratio of hits to the total accesses to the cache")
-;
-
-hitRatio = hits / (hits + misses);
-
+missLatency.init(16); // number of buckets
 }


diff --git a/src/learning_gem5/part2/simple_cache.hh  
b/src/learning_gem5/part2/simple_cache.hh

index 4e57c87..6dae1e4 100644
--- a/src/learning_gem5/part2/simple_cache.hh
+++ b/src/learning_gem5/part2/simple_cache.hh
@@ -292,10 +292,15 @@
 std::unordered_map cacheStore;

 /// Cache statistics
-Stats::Scalar hits;
-Stats::Scalar misses;
-Stats::Histogram missLatency;
-Stats::Formula hitRatio;
+  protected:
+struct SimpleCacheStats : public Stats::Group
+{
+SimpleCacheStats(Stats::Group *parent);
+Stats::Scalar hits;
+Stats::Scalar misses;
+Stats::Histogram missLatency;
+Stats::Formula hitRatio;
+} stats;

   public:

@@ -316,10 +321,6 @@
 Port (const std::string _name,
   PortID idx=InvalidPortID) override;

-/**
- * Register the stats
- */
-void regStats() override;
 };



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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6988c45c13955825fde974f390460f4473af017a
Gerrit-Change-Number: 34135
Gerrit-PatchSet: 3
Gerrit-Owner: Eden Avivi 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Eden Avivi 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-garnet: Flexible VCs per Vnet for each router

2020-09-04 Thread Srikant Bharadwaj (Gerrit) via gem5-dev
Srikant Bharadwaj has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32599 )


Change subject: mem-garnet: Flexible VCs per Vnet for each router
..

mem-garnet: Flexible VCs per Vnet for each router

This change allows configuring each router with a certain number
of VCs for each VNET. This is beneficial when dealing with
heterogenous link widths in a system. Configuring VCs
for each router allows one to ensure equal throughput
within the network while avoiding head-of-line blocking.
Changing a router's VCs number can be done in topology files
using the vcs_per_vnet value argument of router.

Change-Id: Icf4f510248128429a1a11f19f9802ee96f340611
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32599
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/mem/ruby/network/garnet2.0/GarnetNetwork.cc
M src/mem/ruby/network/garnet2.0/GarnetNetwork.hh
M src/mem/ruby/network/garnet2.0/NetworkBridge.cc
M src/mem/ruby/network/garnet2.0/NetworkBridge.hh
M src/mem/ruby/network/garnet2.0/NetworkInterface.cc
M src/mem/ruby/network/garnet2.0/NetworkInterface.hh
M src/mem/ruby/network/garnet2.0/NetworkLink.cc
M src/mem/ruby/network/garnet2.0/NetworkLink.hh
M src/mem/ruby/network/garnet2.0/OutVcState.cc
M src/mem/ruby/network/garnet2.0/OutVcState.hh
M src/mem/ruby/network/garnet2.0/OutputUnit.cc
M src/mem/ruby/network/garnet2.0/OutputUnit.hh
M src/mem/ruby/network/garnet2.0/Router.cc
M src/mem/ruby/network/garnet2.0/Router.hh
14 files changed, 124 insertions(+), 61 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/ruby/network/garnet2.0/GarnetNetwork.cc  
b/src/mem/ruby/network/garnet2.0/GarnetNetwork.cc

index 63562cd..bcc476f 100644
--- a/src/mem/ruby/network/garnet2.0/GarnetNetwork.cc
+++ b/src/mem/ruby/network/garnet2.0/GarnetNetwork.cc
@@ -58,7 +58,7 @@
 {
 m_num_rows = p->num_rows;
 m_ni_flit_size = p->ni_flit_size;
-m_vcs_per_vnet = p->vcs_per_vnet;
+m_max_vcs_per_vnet = 0;
 m_buffers_per_data_vc = p->buffers_per_data_vc;
 m_buffers_per_ctrl_vc = p->buffers_per_ctrl_vc;
 m_routing_algorithm = p->routing_algorithm;
@@ -166,6 +166,9 @@

 PortDirection dst_inport_dirn = "Local";

+m_max_vcs_per_vnet = std::max(m_max_vcs_per_vnet,
+ m_routers[dest]->get_vc_per_vnet());
+
 /*
  * We check if a bridge was enabled at any end of the link.
  * The bridge is enabled if either of clock domain
@@ -185,9 +188,10 @@
 m_nis[local_src]->
 addOutPort(garnet_link->extNetBridge[LinkDirection_In],
garnet_link->extCredBridge[LinkDirection_In],
-   dest);
+   dest, m_routers[dest]->get_vc_per_vnet());
 } else {
-m_nis[local_src]->addOutPort(net_link, credit_link, dest);
+m_nis[local_src]->addOutPort(net_link, credit_link, dest,
+m_routers[dest]->get_vc_per_vnet());
 }

 if (garnet_link->intBridgeEn) {
@@ -231,6 +235,9 @@

 PortDirection src_outport_dirn = "Local";

+m_max_vcs_per_vnet = std::max(m_max_vcs_per_vnet,
+ m_routers[src]->get_vc_per_vnet());
+
 /*
  * We check if a bridge was enabled at any end of the link.
  * The bridge is enabled if either of clock domain
@@ -261,12 +268,14 @@
 addOutPort(src_outport_dirn,
garnet_link->intNetBridge[LinkDirection_Out],
routing_table_entry, link->m_weight,
-   garnet_link->intCredBridge[LinkDirection_Out]);
+   garnet_link->intCredBridge[LinkDirection_Out],
+   m_routers[src]->get_vc_per_vnet());
 } else {
 m_routers[src]->
 addOutPort(src_outport_dirn, net_link,
routing_table_entry,
-   link->m_weight, credit_link);
+   link->m_weight, credit_link,
+   m_routers[src]->get_vc_per_vnet());
 }
 }

@@ -291,6 +300,10 @@
 m_networklinks.push_back(net_link);
 m_creditlinks.push_back(credit_link);

+m_max_vcs_per_vnet = std::max(m_max_vcs_per_vnet,
+ std::max(m_routers[dest]->get_vc_per_vnet(),
+ m_routers[src]->get_vc_per_vnet()));
+
 /*
  * We check if a bridge was enabled at any end of the link.
  * The bridge is enabled if either of clock domain
@@ -319,11 +332,13 @@
 m_routers[src]->
 addOutPort(src_outport_dirn, garnet_link->srcNetBridge,
routing_table_entry,
-   link->m_weight, garnet_link->srcCredBridge);
+   link->m_weight, garnet_link->srcCredBridge,
+   m_routers[dest]->get_vc_per_vnet());
 } else {

[gem5-dev] Change in gem5/gem5[develop]: mem-garnet: Initialize unused Credit members

2020-09-04 Thread Srikant Bharadwaj (Gerrit) via gem5-dev
Srikant Bharadwaj has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32598 )


Change subject: mem-garnet: Initialize unused Credit members
..

mem-garnet: Initialize unused Credit members

The Credit class doesn't initialize a number of its unused base class
fields.  This leads to non-determanistic traces when printing flits that
are Credits.  This patch initializes all unused fields to 0.

Change-Id: Ib73c652c71a10be57b24c0d6e1ac22eafa421e11
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32598
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/mem/ruby/network/garnet2.0/CommonTypes.hh
M src/mem/ruby/network/garnet2.0/Credit.cc
2 files changed, 6 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/ruby/network/garnet2.0/CommonTypes.hh  
b/src/mem/ruby/network/garnet2.0/CommonTypes.hh

index 94aa600..643ce8c 100644
--- a/src/mem/ruby/network/garnet2.0/CommonTypes.hh
+++ b/src/mem/ruby/network/garnet2.0/CommonTypes.hh
@@ -46,6 +46,11 @@

 struct RouteInfo
 {
+RouteInfo()
+: vnet(0), src_ni(0), src_router(0), dest_ni(0), dest_router(0),
+  hops_traversed(0)
+{}
+
 // destination format for table-based routing
 int vnet;
 NetDest net_dest;
diff --git a/src/mem/ruby/network/garnet2.0/Credit.cc  
b/src/mem/ruby/network/garnet2.0/Credit.cc

index 3e56b4e..bde9484 100644
--- a/src/mem/ruby/network/garnet2.0/Credit.cc
+++ b/src/mem/ruby/network/garnet2.0/Credit.cc
@@ -37,11 +37,9 @@
 // and m_is_free_signal (whether VC is free or not)

 Credit::Credit(int vc, bool is_free_signal, Tick curTime)
+: flit(0, vc, 0, RouteInfo(), 0, nullptr, 0, 0, curTime)
 {
-m_id = 0;
-m_vc = vc;
 m_is_free_signal = is_free_signal;
-m_time = curTime;
 m_type = CREDIT_;
 }


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib73c652c71a10be57b24c0d6e1ac22eafa421e11
Gerrit-Change-Number: 32598
Gerrit-PatchSet: 7
Gerrit-Owner: Srikant Bharadwaj 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Michael LeBeane 
Gerrit-Reviewer: Srikant Bharadwaj 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-garnet: Add a check to see if router is already scheduled

2020-09-04 Thread Srikant Bharadwaj (Gerrit) via gem5-dev
Srikant Bharadwaj has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32600 )


Change subject: mem-garnet: Add a check to see if router is already  
scheduled

..

mem-garnet: Add a check to see if router is already scheduled

Currently the Switch Allocator takes up most of the simulation
wall clock time. This function checks for all VCs to see if it
should wakeup next. The input units which are simulated before
the switch allocator could have scheduled it already. This patch
adds a check for it.

Change-Id: I8609d4e7f925aa5e97198f6cd07466530f6fcf4c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32600
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/mem/ruby/network/garnet2.0/SwitchAllocator.cc
1 file changed, 4 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/ruby/network/garnet2.0/SwitchAllocator.cc  
b/src/mem/ruby/network/garnet2.0/SwitchAllocator.cc

index 144f208..3241343 100644
--- a/src/mem/ruby/network/garnet2.0/SwitchAllocator.cc
+++ b/src/mem/ruby/network/garnet2.0/SwitchAllocator.cc
@@ -350,6 +350,10 @@
 {
 Tick nextCycle = m_router->clockEdge(Cycles(1));

+if (m_router->alreadyScheduled(nextCycle)) {
+return;
+}
+
 for (int i = 0; i < m_num_inports; i++) {
 for (int j = 0; j < m_num_vcs; j++) {
 if (m_router->getInputUnit(i)->need_stage(j, SA_, nextCycle)) {

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Gerrit-Change-Id: I8609d4e7f925aa5e97198f6cd07466530f6fcf4c
Gerrit-Change-Number: 32600
Gerrit-PatchSet: 9
Gerrit-Owner: Srikant Bharadwaj 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Srikant Bharadwaj 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-garnet: Separable allocator in Garnet not fair enough.

2020-09-04 Thread Srikant Bharadwaj (Gerrit) via gem5-dev
Srikant Bharadwaj has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32601 )


Change subject: mem-garnet: Separable allocator in Garnet not fair enough.
..

mem-garnet: Separable allocator in Garnet not fair enough.

Currently there are independent round robin arbiter at each
input port and output port. Every time a VC is selected for
output allocation round robin is incremented irrespective of
if it is selected by its output port or not. This leads to
unfair arbitration at input port and is well known[1]. This
patch fixes it to increment only if the output port also
selects it.

[1] D. U. Becker and W. J. Dally, "Allocator implementations
for network-on-chip routers," Proceedings of the Conference
on High Performance Computing Networking, Storage and
Analysis, Portland, OR, 2009, pp. 1-12

Change-Id: I65963fb8082c51c0e3c6e031a8b87b4f5c3626e1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32601
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/mem/ruby/network/garnet2.0/SwitchAllocator.cc
1 file changed, 9 insertions(+), 5 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/ruby/network/garnet2.0/SwitchAllocator.cc  
b/src/mem/ruby/network/garnet2.0/SwitchAllocator.cc

index 3241343..1ed6de1 100644
--- a/src/mem/ruby/network/garnet2.0/SwitchAllocator.cc
+++ b/src/mem/ruby/network/garnet2.0/SwitchAllocator.cc
@@ -130,11 +130,6 @@
 m_port_requests[outport][inport] = true;
 m_vc_winners[outport][inport]= invc;

-// Update Round Robin pointer to the next VC
-m_round_robin_invc[inport] = invc + 1;
-if (m_round_robin_invc[inport] >= m_num_vcs)
-m_round_robin_invc[inport] = 0;
-
 break; // got one vc winner for this port
 }
 }
@@ -248,6 +243,15 @@
 if (m_round_robin_inport[outport] >= m_num_inports)
 m_round_robin_inport[outport] = 0;

+// Update Round Robin pointer to the next VC
+// We do it here to keep it fair.
+// Only the VC which got switch traversal
+// is updated.
+m_round_robin_invc[inport] = invc + 1;
+if (m_round_robin_invc[inport] >= m_num_vcs)
+m_round_robin_invc[inport] = 0;
+
+
 break; // got a input winner for this outport
 }


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Gerrit-Change-Id: I65963fb8082c51c0e3c6e031a8b87b4f5c3626e1
Gerrit-Change-Number: 32601
Gerrit-PatchSet: 9
Gerrit-Owner: Srikant Bharadwaj 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Srikant Bharadwaj 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Failure to restore RAS during squash

2020-09-04 Thread Sungkeun Kim (Gerrit) via gem5-dev
Sungkeun Kim has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33214 )


Change subject: cpu: Failure to restore RAS during squash
..

cpu: Failure to restore RAS during squash

During squash of branch predictor history, RAS recovery mess up the
stack because of function "restore" in RAS (src/cpu/pred/ras.cc). In
restore function, it does not update "usedEntries" variable resulting in
restore failure.

To be specific, in order to remove mispredicted call, it uses pop() and
it updates tos. However in order to restore mispredicted ret
instruction, it uses restore() but it does not update tos. This pair of
function call mess up the RAS resulting in many misspeculation.

The solution is to update usedEntries variable as “push” function does.
This is possible because restoration is done with reverse order of push
and pop.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-732

Change-Id: Ia14e71c26d20b2795fd55a6a0dd3284c03570614
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33214
Reviewed-by: Trivikram Reddy 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/cpu/pred/ras.cc
1 file changed, 4 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Trivikram Reddy: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/pred/ras.cc b/src/cpu/pred/ras.cc
index e07ac6a..33eec0e 100644
--- a/src/cpu/pred/ras.cc
+++ b/src/cpu/pred/ras.cc
@@ -74,4 +74,8 @@
 tos = top_entry_idx;

 addrStack[tos] = restored;
+
+if (usedEntries != numEntries) {
+++usedEntries;
+}
 }

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia14e71c26d20b2795fd55a6a0dd3284c03570614
Gerrit-Change-Number: 33214
Gerrit-PatchSet: 2
Gerrit-Owner: Sungkeun Kim 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Sungkeun Kim 
Gerrit-Reviewer: Sungkeun Kim 
Gerrit-Reviewer: Trivikram Reddy 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Jason Lowe-Power 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu: convert memtest to new style stats

2020-09-04 Thread Eden Avivi (Gerrit) via gem5-dev
Eden Avivi has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34137 )



Change subject: cpu: convert memtest to new style stats
..

cpu: convert memtest to new style stats

Change-Id: I91b17dd46fd0f70816159ea14c1c8f498048c696
---
M src/cpu/testers/memtest/memtest.cc
M src/cpu/testers/memtest/memtest.hh
2 files changed, 14 insertions(+), 22 deletions(-)



diff --git a/src/cpu/testers/memtest/memtest.cc  
b/src/cpu/testers/memtest/memtest.cc

index 720b273..b66dcae 100644
--- a/src/cpu/testers/memtest/memtest.cc
+++ b/src/cpu/testers/memtest/memtest.cc
@@ -99,7 +99,7 @@
   nextProgressMessage(p->progress_interval),
   maxLoads(p->max_loads),
   atomic(p->system->isAtomicMode()),
-  suppressFuncErrors(p->suppress_func_errors)
+  suppressFuncErrors(p->suppress_func_errors), stats(this)
 {
 id = TESTER_ALLOCATOR++;
 fatal_if(id >= blockSize, "Too many testers, only %d allowed\n",
@@ -160,7 +160,7 @@
 }

 numReads++;
-numReadsStat++;
+stats.numReadsStat++;

 if (numReads == (uint64_t)nextProgressMessage) {
 ccprintf(cerr, "%s: completed %d read, %d write accesses  
@%d\n",

@@ -176,7 +176,7 @@
 // update the reference data
 referenceData[req->getPaddr()] = pkt_data[0];
 numWrites++;
-numWritesStat++;
+stats.numWritesStat++;
 }
 }

@@ -190,23 +190,12 @@
 else if (noResponseEvent.scheduled())
 deschedule(noResponseEvent);
 }
-
-void
-MemTest::regStats()
+MemTest::MemTestStats::MemTestStats(Stats::Group *parent)
+  : Stats::Group(parent),
+  ADD_STAT(numReadsStat, "number of read accesses completed"),
+  ADD_STAT(numWritesStat, "number of write accesses completed")
 {
-ClockedObject::regStats();

-using namespace Stats;
-
-numReadsStat
-.name(name() + ".num_reads")
-.desc("number of read accesses completed")
-;
-
-numWritesStat
-.name(name() + ".num_writes")
-.desc("number of write accesses completed")
-;
 }

 void
diff --git a/src/cpu/testers/memtest/memtest.hh  
b/src/cpu/testers/memtest/memtest.hh

index 86b27a4..db0c048 100644
--- a/src/cpu/testers/memtest/memtest.hh
+++ b/src/cpu/testers/memtest/memtest.hh
@@ -72,7 +72,6 @@
 typedef MemTestParams Params;
 MemTest(const Params *p);

-void regStats() override;

 Port (const std::string _name,
   PortID idx=InvalidPortID) override;
@@ -166,9 +165,13 @@
 const bool atomic;

 const bool suppressFuncErrors;
-
-Stats::Scalar numReadsStat;
-Stats::Scalar numWritesStat;
+  protected:
+struct MemTestStats : public Stats::Group
+{
+MemTestStats(Stats::Group *parent);
+Stats::Scalar numReadsStat;
+Stats::Scalar numWritesStat;
+} stats;

 /**
  * Complete a request by checking the response.

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Gerrit-Branch: develop
Gerrit-Change-Id: I91b17dd46fd0f70816159ea14c1c8f498048c696
Gerrit-Change-Number: 34137
Gerrit-PatchSet: 1
Gerrit-Owner: Eden Avivi 
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[gem5-dev] Change in gem5/gem5[develop]: tests,arch-sparc: Move SPARC insttests to long

2020-09-04 Thread Bobby R. Bruce (Gerrit) via gem5-dev
Bobby R. Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34136 )



Change subject: tests,arch-sparc: Move SPARC insttests to long
..

tests,arch-sparc: Move SPARC insttests to long

We should not compile and run SPARC tests as part of the quick tests.
The SPARC insttests have thefore been moved to be part of the long
tests.

Change-Id: I8e4263414af2d7a882715202124671dc0723d961
---
M tests/gem5/insttest_se/test.py
1 file changed, 1 insertion(+), 0 deletions(-)



diff --git a/tests/gem5/insttest_se/test.py b/tests/gem5/insttest_se/test.py
index 8f9fd58..c58a42b 100644
--- a/tests/gem5/insttest_se/test.py
+++ b/tests/gem5/insttest_se/test.py
@@ -72,4 +72,5 @@
 config_args=['--cmd', joinpath(path, binary),
 '--cpu-type', cpu, '--caches'],
 valid_isas=(isa.upper(),),
+length = constants.long_tag,
 )

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Gerrit-Branch: develop
Gerrit-Change-Id: I8e4263414af2d7a882715202124671dc0723d961
Gerrit-Change-Number: 34136
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: learning-gem5: convert simple cache to new style stats

2020-09-04 Thread Eden Avivi (Gerrit) via gem5-dev
Eden Avivi has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34135 )



Change subject: learning-gem5: convert simple cache to new style stats
..

learning-gem5: convert simple cache to new style stats

Change-Id: I6988c45c13955825fde974f390460f4473af017a
---
M src/learning_gem5/part2/simple_cache.cc
M src/learning_gem5/part2/simple_cache.hh
2 files changed, 22 insertions(+), 36 deletions(-)



diff --git a/src/learning_gem5/part2/simple_cache.cc  
b/src/learning_gem5/part2/simple_cache.cc

index 25f6bd7..ad5e663 100644
--- a/src/learning_gem5/part2/simple_cache.cc
+++ b/src/learning_gem5/part2/simple_cache.cc
@@ -38,7 +38,7 @@
 blockSize(params->system->cacheLineSize()),
 capacity(params->size / blockSize),
 memPort(params->name + ".mem_side", this),
-blocked(false), originalPacket(nullptr), waitingPortId(-1)
+blocked(false), originalPacket(nullptr), waitingPortId(-1), stats(this)
 {
 // Since the CPU side ports are a vector of ports, create an instance  
of

 // the CPUSidePort for each connection. This member of params is
@@ -221,7 +221,7 @@
 // for any added latency.
 insert(pkt);

-missLatency.sample(curTick() - missTime);
+stats.missLatency.sample(curTick() - missTime);

 // If we had to upgrade the request packet to a full cache line, now we
 // can use that packet to construct the response.
@@ -286,12 +286,12 @@

 if (hit) {
 // Respond to the CPU side
-hits++; // update stats
+stats.hits++; // update stats
 DDUMP(SimpleCache, pkt->getConstPtr(), pkt->getSize());
 pkt->makeResponse();
 sendResponse(pkt);
 } else {
-misses++; // update stats
+stats.misses++; // update stats
 missTime = curTick();
 // Forward to the memory side.
 // We can't directly forward the packet unless it is exactly the  
size

@@ -421,31 +421,15 @@
 }
 }

-void
-SimpleCache::regStats()
+SimpleCache::SimpleCacheStats::SimpleCacheStats(Stats::Group *parent)
+  : Stats::Group(parent),
+  ADD_STAT(hits, "Number of hits"),
+  ADD_STAT(misses, "Number of misses"),
+  ADD_STAT(missLatency, "Ticks for misses to the cache"),
+  ADD_STAT(hitRatio, "The ratio of hits to the total"
+ "accesses to the cache", hits / (hits + misses))
 {
-// If you don't do this you get errors about uninitialized stats.
-ClockedObject::regStats();
-
-hits.name(name() + ".hits")
-.desc("Number of hits")
-;
-
-misses.name(name() + ".misses")
-.desc("Number of misses")
-;
-
-missLatency.name(name() + ".missLatency")
-.desc("Ticks for misses to the cache")
-.init(16) // number of buckets
-;
-
-hitRatio.name(name() + ".hitRatio")
-.desc("The ratio of hits to the total accesses to the cache")
-;
-
-hitRatio = hits / (hits + misses);
-
+missLatency.init(16); // number of buckets
 }


diff --git a/src/learning_gem5/part2/simple_cache.hh  
b/src/learning_gem5/part2/simple_cache.hh

index 4e57c87..ccfdcb9 100644
--- a/src/learning_gem5/part2/simple_cache.hh
+++ b/src/learning_gem5/part2/simple_cache.hh
@@ -292,10 +292,15 @@
 std::unordered_map cacheStore;

 /// Cache statistics
-Stats::Scalar hits;
-Stats::Scalar misses;
-Stats::Histogram missLatency;
-Stats::Formula hitRatio;
+  protected:
+struct SimpleCacheStats : public Stats::Group
+{
+SimpleCacheStats(Stats::Group *parent);
+Stats::Scalar hits;
+Stats::Scalar misses;
+Stats::Histogram missLatency;
+Stats::Formula hitRatio;
+} stats;

   public:

@@ -316,10 +321,7 @@
 Port (const std::string _name,
   PortID idx=InvalidPortID) override;

-/**
- * Register the stats
- */
-void regStats() override;
+
 };



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Gerrit-Branch: develop
Gerrit-Change-Id: I6988c45c13955825fde974f390460f4473af017a
Gerrit-Change-Number: 34135
Gerrit-PatchSet: 1
Gerrit-Owner: Eden Avivi 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: tests,arch-arm: Pass gem5_root as an arg in run.py

2020-09-04 Thread Bobby R. Bruce (Gerrit) via gem5-dev
Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33955 )


Change subject: tests,arch-arm: Pass gem5_root as an arg in run.py
..

tests,arch-arm: Pass gem5_root as an arg in run.py

Previously `tests/gem5/fs/linux/arm/run.py` contained an ugly,
hard-coded `gem5_root` variable. In this commit we pass `gem5_root`
as an argument from `tests/gem5/fs/linux/arm/test.py`, utilizing
`config.base_dir`.

Change-Id: I2b1e3369b1078cce9375fadb7c39fa4292648658
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33955
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
---
M tests/gem5/fs/linux/arm/run.py
M tests/gem5/fs/linux/arm/test.py
2 files changed, 5 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/gem5/fs/linux/arm/run.py b/tests/gem5/fs/linux/arm/run.py
index f0ba9bd..a0d782b 100644
--- a/tests/gem5/fs/linux/arm/run.py
+++ b/tests/gem5/fs/linux/arm/run.py
@@ -57,9 +57,9 @@

 config = sys.argv[1]
 os.environ['M5_PATH'] = sys.argv[2]
+gem5_root = sys.argv[3]

 # path setup
-gem5_root =  
joinpath(os.path.dirname(__file__), '..', '..', '..', '..', '..')

 sys.path.append(joinpath(gem5_root, 'configs'))
 tests_root = joinpath(gem5_root, 'tests')
 sys.path.append(joinpath(tests_root, 'gem5', 'configs'))
diff --git a/tests/gem5/fs/linux/arm/test.py  
b/tests/gem5/fs/linux/arm/test.py

index 80a2af6..33ca33e 100644
--- a/tests/gem5/fs/linux/arm/test.py
+++ b/tests/gem5/fs/linux/arm/test.py
@@ -97,7 +97,8 @@
 for name in arm_fs_quick_tests:
 args = [
 joinpath(config.base_dir, 'tests', 'gem5', 'configs', name  
+ '.py'),

-path
+path,
+config.base_dir
 ]
 gem5_verify_config(
 name=name,
@@ -112,7 +113,8 @@
 for name in arm_fs_long_tests:
 args = [
 joinpath(config.base_dir, 'tests', 'gem5', 'configs', name  
+ '.py'),

-path
+path,
+config.base_dir
 ]
 gem5_verify_config(
 name=name,

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2b1e3369b1078cce9375fadb7c39fa4292648658
Gerrit-Change-Number: 33955
Gerrit-PatchSet: 6
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: tests: Removed author info from insttest test.py

2020-09-04 Thread Bobby R. Bruce (Gerrit) via gem5-dev
Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33976 )


Change subject: tests: Removed author info from insttest test.py
..

tests: Removed author info from insttest test.py

We no longer include author information directly in gem5 source.

Change-Id: I460d399f25ea955e7cf3bf5ed002246199ef4436
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33976
Reviewed-by: Bobby R. Bruce 
Reviewed-by: Jason Lowe-Power 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M tests/gem5/insttest_se/test.py
1 file changed, 0 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/gem5/insttest_se/test.py b/tests/gem5/insttest_se/test.py
index 519b349..8f9fd58 100644
--- a/tests/gem5/insttest_se/test.py
+++ b/tests/gem5/insttest_se/test.py
@@ -23,8 +23,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Bobby R. Bruce

 '''
 Test file for the insttest binary running on the SPARC ISA

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I460d399f25ea955e7cf3bf5ed002246199ef4436
Gerrit-Change-Number: 33976
Gerrit-PatchSet: 3
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: tests: Moved realview config files

2020-09-04 Thread Bobby R. Bruce (Gerrit) via gem5-dev
Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33143 )


Change subject: tests: Moved realview config files
..

tests: Moved realview config files

This is part of a process of getting rid of the `tests/config`
directory, and placing these configs either where they are used,
removing them if unneeded, or moving them to `configs/example`.

These config files, in this patchset, are part of the realview tests
found in `tests/gem5/fs/linux/arm/`. They have been moved to
`tests/gem5/configs`.

Change-Id: I7706b59c58da6413f5f3dd816a1e5cd54a834a58
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33143
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
R tests/gem5/configs/arm_generic.py
R tests/gem5/configs/base_config.py
R tests/gem5/configs/checkpoint.py
R tests/gem5/configs/realview-minor-dual.py
R tests/gem5/configs/realview-minor.py
R tests/gem5/configs/realview-o3-checker.py
R tests/gem5/configs/realview-o3-dual.py
R tests/gem5/configs/realview-o3.py
R tests/gem5/configs/realview-simple-atomic-checkpoint.py
R tests/gem5/configs/realview-simple-atomic-dual.py
R tests/gem5/configs/realview-simple-atomic.py
R tests/gem5/configs/realview-simple-timing-dual-ruby.py
R tests/gem5/configs/realview-simple-timing-dual.py
R tests/gem5/configs/realview-simple-timing-ruby.py
R tests/gem5/configs/realview-simple-timing.py
R tests/gem5/configs/realview-switcheroo-atomic.py
R tests/gem5/configs/realview-switcheroo-full.py
R tests/gem5/configs/realview-switcheroo-noncaching-timing.py
R tests/gem5/configs/realview-switcheroo-o3.py
R tests/gem5/configs/realview-switcheroo-timing.py
R tests/gem5/configs/realview64-minor-dual.py
R tests/gem5/configs/realview64-minor.py
R tests/gem5/configs/realview64-o3-checker.py
R tests/gem5/configs/realview64-o3-dual.py
R tests/gem5/configs/realview64-o3.py
R tests/gem5/configs/realview64-simple-atomic-checkpoint.py
R tests/gem5/configs/realview64-simple-atomic-dual.py
R tests/gem5/configs/realview64-simple-atomic.py
R tests/gem5/configs/realview64-simple-timing-dual-ruby.py
R tests/gem5/configs/realview64-simple-timing-dual.py
R tests/gem5/configs/realview64-simple-timing-ruby.py
R tests/gem5/configs/realview64-simple-timing.py
R tests/gem5/configs/realview64-switcheroo-atomic.py
R tests/gem5/configs/realview64-switcheroo-full.py
R tests/gem5/configs/realview64-switcheroo-o3.py
R tests/gem5/configs/realview64-switcheroo-timing.py
R tests/gem5/configs/switcheroo.py
M tests/gem5/fs/linux/arm/run.py
M tests/gem5/fs/linux/arm/test.py
39 files changed, 4 insertions(+), 4 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/configs/arm_generic.py  
b/tests/gem5/configs/arm_generic.py

similarity index 100%
rename from tests/configs/arm_generic.py
rename to tests/gem5/configs/arm_generic.py
diff --git a/tests/configs/base_config.py  
b/tests/gem5/configs/base_config.py

similarity index 99%
rename from tests/configs/base_config.py
rename to tests/gem5/configs/base_config.py
index b124a13..b5bddf4 100644
--- a/tests/configs/base_config.py
+++ b/tests/gem5/configs/base_config.py
@@ -38,7 +38,6 @@
 import m5
 from m5.objects import *
 from m5.proxy import *
-m5.util.addToPath('../configs/')
 from common import FSConfig
 from common import Options
 from common.Caches import *
diff --git a/tests/configs/checkpoint.py b/tests/gem5/configs/checkpoint.py
similarity index 100%
rename from tests/configs/checkpoint.py
rename to tests/gem5/configs/checkpoint.py
diff --git a/tests/configs/realview-minor-dual.py  
b/tests/gem5/configs/realview-minor-dual.py

similarity index 100%
rename from tests/configs/realview-minor-dual.py
rename to tests/gem5/configs/realview-minor-dual.py
diff --git a/tests/configs/realview-minor.py  
b/tests/gem5/configs/realview-minor.py

similarity index 100%
rename from tests/configs/realview-minor.py
rename to tests/gem5/configs/realview-minor.py
diff --git a/tests/configs/realview-o3-checker.py  
b/tests/gem5/configs/realview-o3-checker.py

similarity index 100%
rename from tests/configs/realview-o3-checker.py
rename to tests/gem5/configs/realview-o3-checker.py
diff --git a/tests/configs/realview-o3-dual.py  
b/tests/gem5/configs/realview-o3-dual.py

similarity index 100%
rename from tests/configs/realview-o3-dual.py
rename to tests/gem5/configs/realview-o3-dual.py
diff --git a/tests/configs/realview-o3.py  
b/tests/gem5/configs/realview-o3.py

similarity index 100%
rename from tests/configs/realview-o3.py
rename to tests/gem5/configs/realview-o3.py
diff --git a/tests/configs/realview-simple-atomic-checkpoint.py  
b/tests/gem5/configs/realview-simple-atomic-checkpoint.py

similarity index 100%
rename from tests/configs/realview-simple-atomic-checkpoint.py
rename to tests/gem5/configs/realview-simple-atomic-checkpoint.py
diff 

[gem5-dev] Change in gem5/gem5[develop]: tests: Removed test-progs/asmtest

2020-09-04 Thread Bobby R. Bruce (Gerrit) via gem5-dev
Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33142 )


Change subject: tests: Removed test-progs/asmtest
..

tests: Removed test-progs/asmtest

The insttests source is now found in gem5-resources:
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/master/src/asmtest

The pre-compiled binaries are pulled from dist.gem5.org.

There is no reason to keep these here. They are therefore being
removed.

Change-Id: Ic7869677278248f77b2703497ae7fc808d8f767a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33142
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
D tests/test-progs/asmtest/src/riscv/LICENSE
D tests/test-progs/asmtest/src/riscv/Makefile
D tests/test-progs/asmtest/src/riscv/README.md
D tests/test-progs/asmtest/src/riscv/env/LICENSE
D tests/test-progs/asmtest/src/riscv/env/encoding.h
D tests/test-progs/asmtest/src/riscv/env/p/link.ld
D tests/test-progs/asmtest/src/riscv/env/p/riscv_test.h
D tests/test-progs/asmtest/src/riscv/env/pm/link.ld
D tests/test-progs/asmtest/src/riscv/env/pm/riscv_test.h
D tests/test-progs/asmtest/src/riscv/env/ps/link.ld
D tests/test-progs/asmtest/src/riscv/env/ps/riscv_test.h
D tests/test-progs/asmtest/src/riscv/env/pt/link.ld
D tests/test-progs/asmtest/src/riscv/env/pt/riscv_test.h
D tests/test-progs/asmtest/src/riscv/env/v/entry.S
D tests/test-progs/asmtest/src/riscv/env/v/link.ld
D tests/test-progs/asmtest/src/riscv/env/v/riscv_test.h
D tests/test-progs/asmtest/src/riscv/env/v/string.c
D tests/test-progs/asmtest/src/riscv/env/v/vm.c
D tests/test-progs/asmtest/src/riscv/isa/.gitignore
D tests/test-progs/asmtest/src/riscv/isa/macros/mt/test_macros_mt.h
D tests/test-progs/asmtest/src/riscv/isa/macros/mt/test_macros_mt_ecall.h
D tests/test-progs/asmtest/src/riscv/isa/macros/scalar/test_macros.h
D tests/test-progs/asmtest/src/riscv/isa/rv64mi/Makefrag
D tests/test-progs/asmtest/src/riscv/isa/rv64mi/access.S
D tests/test-progs/asmtest/src/riscv/isa/rv64mi/breakpoint.S
D tests/test-progs/asmtest/src/riscv/isa/rv64mi/csr.S
D tests/test-progs/asmtest/src/riscv/isa/rv64mi/illegal.S
D tests/test-progs/asmtest/src/riscv/isa/rv64mi/ma_addr.S
D tests/test-progs/asmtest/src/riscv/isa/rv64mi/ma_fetch.S
D tests/test-progs/asmtest/src/riscv/isa/rv64mi/mcsr.S
D tests/test-progs/asmtest/src/riscv/isa/rv64mi/sbreak.S
D tests/test-progs/asmtest/src/riscv/isa/rv64mi/scall.S
D tests/test-progs/asmtest/src/riscv/isa/rv64samt/Makefrag
D tests/test-progs/asmtest/src/riscv/isa/rv64samt/sysclone_d.S
D tests/test-progs/asmtest/src/riscv/isa/rv64samt/sysfutex1_d.S
D tests/test-progs/asmtest/src/riscv/isa/rv64samt/sysfutex2_d.S
D tests/test-progs/asmtest/src/riscv/isa/rv64samt/sysfutex3_d.S
D tests/test-progs/asmtest/src/riscv/isa/rv64samt/sysfutex_d.S
D tests/test-progs/asmtest/src/riscv/isa/rv64si/Makefrag
D tests/test-progs/asmtest/src/riscv/isa/rv64si/csr.S
D tests/test-progs/asmtest/src/riscv/isa/rv64si/dirty.S
D tests/test-progs/asmtest/src/riscv/isa/rv64si/ma_fetch.S
D tests/test-progs/asmtest/src/riscv/isa/rv64si/sbreak.S
D tests/test-progs/asmtest/src/riscv/isa/rv64si/scall.S
D tests/test-progs/asmtest/src/riscv/isa/rv64si/wfi.S
D tests/test-progs/asmtest/src/riscv/isa/rv64ua/Makefrag
D tests/test-progs/asmtest/src/riscv/isa/rv64ua/amoadd_d.S
D tests/test-progs/asmtest/src/riscv/isa/rv64ua/amoadd_w.S
D tests/test-progs/asmtest/src/riscv/isa/rv64ua/amoand_d.S
D tests/test-progs/asmtest/src/riscv/isa/rv64ua/amoand_w.S
D tests/test-progs/asmtest/src/riscv/isa/rv64ua/amomax_d.S
D tests/test-progs/asmtest/src/riscv/isa/rv64ua/amomax_w.S
D tests/test-progs/asmtest/src/riscv/isa/rv64ua/amomaxu_d.S
D tests/test-progs/asmtest/src/riscv/isa/rv64ua/amomaxu_w.S
D tests/test-progs/asmtest/src/riscv/isa/rv64ua/amomin_d.S
D tests/test-progs/asmtest/src/riscv/isa/rv64ua/amomin_w.S
D tests/test-progs/asmtest/src/riscv/isa/rv64ua/amominu_d.S
D tests/test-progs/asmtest/src/riscv/isa/rv64ua/amominu_w.S
D tests/test-progs/asmtest/src/riscv/isa/rv64ua/amoor_d.S
D tests/test-progs/asmtest/src/riscv/isa/rv64ua/amoor_w.S
D tests/test-progs/asmtest/src/riscv/isa/rv64ua/amoswap_d.S
D tests/test-progs/asmtest/src/riscv/isa/rv64ua/amoswap_w.S
D tests/test-progs/asmtest/src/riscv/isa/rv64ua/amoxor_d.S
D tests/test-progs/asmtest/src/riscv/isa/rv64ua/amoxor_w.S
D tests/test-progs/asmtest/src/riscv/isa/rv64ua/lrsc.S
D tests/test-progs/asmtest/src/riscv/isa/rv64ua/test.S
D tests/test-progs/asmtest/src/riscv/isa/rv64uamt/Makefrag
D tests/test-progs/asmtest/src/riscv/isa/rv64uamt/amoadd_d.S
D tests/test-progs/asmtest/src/riscv/isa/rv64uamt/amoand_d.S
D tests/test-progs/asmtest/src/riscv/isa/rv64uamt/amomax_d.S
D tests/test-progs/asmtest/src/riscv/isa/rv64uamt/amomaxu_d.S
D tests/test-progs/asmtest/src/riscv/isa/rv64uamt/amomin_d.S
D tests/test-progs/asmtest/src/riscv/isa/rv64uamt/amominu_d.S
D 

[gem5-dev] Change in gem5/gem5[develop]: tests: Removed the ignoring of tests

2020-09-04 Thread Bobby R. Bruce (Gerrit) via gem5-dev
Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33139 )


Change subject: tests: Removed the ignoring of tests
..

tests: Removed the ignoring of tests

This commit reverts
https://gem5-review.googlesource.com/c/public/gem5/+/23023.

It has proven to be an unpopular piece of functionality which makes it
too easy to silently ignore failing tests. The new policy will be to
remove/comment-out failing tests in the testing source and tag with Jira
issues as to why.

Change-Id: I17d69fc57a9171ce3702e019615390a9aa3da250
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33139
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M tests/gem5/suite.py
1 file changed, 0 insertions(+), 14 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/gem5/suite.py b/tests/gem5/suite.py
index 329e31f..cba3d43 100644
--- a/tests/gem5/suite.py
+++ b/tests/gem5/suite.py
@@ -88,15 +88,6 @@
 fixtures = list(fixtures)
 testsuites = []

-# Obtain the set of tests to ignore. This is found in the
-# ".testignore" file.
-__location__ = os.path.realpath(
-os.path.join(os.getcwd(), os.path.dirname(__file__)))
-_test_ignore_file_loc = os.path.join(__location__,".testignore")
-ignore = set()
-if os.path.exists(_test_ignore_file_loc):
-ignore.update(open(_test_ignore_file_loc).read().splitlines())
-
 for host in valid_hosts:
 for opt in valid_variants:
 for isa in valid_isas:
@@ -115,11 +106,6 @@
 if protocol:
 _name += '-'+protocol

-# We check to see if this test suite is to be ignored. If  
so,

-# we skip it.
-if _name in ignore:
-continue
-
 # Create the running of gem5 subtest.  NOTE: We  
specifically

 # create this test before our verifiers so this is listed
 # first.

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I17d69fc57a9171ce3702e019615390a9aa3da250
Gerrit-Change-Number: 33139
Gerrit-PatchSet: 9
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: tests: Removed tests/configs/tgen files

2020-09-04 Thread Bobby R. Bruce (Gerrit) via gem5-dev
Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33136 )


Change subject: tests: Removed tests/configs/tgen files
..

tests: Removed tests/configs/tgen files

These files were needed by the memory tests found in `tests/memory`, but
this directory already has local copies.

Change-Id: I04628b151d2ab60b1127990dbe8baaab77e768b1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33136
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
D tests/configs/tgen-dram-ctrl.py
D tests/configs/tgen-simple-mem.py
2 files changed, 0 insertions(+), 151 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/configs/tgen-dram-ctrl.py  
b/tests/configs/tgen-dram-ctrl.py

deleted file mode 100644
index ef8df81..000
--- a/tests/configs/tgen-dram-ctrl.py
+++ /dev/null
@@ -1,74 +0,0 @@
-# Copyright (c) 2012 ARM Limited
-# All rights reserved.
-#
-# The license below extends only to copyright in the software and shall
-# not be construed as granting a license to any other intellectual
-# property including but not limited to intellectual property relating
-# to a hardware implementation of the functionality of the software
-# licensed hereunder.  You may use the software subject to the license
-# terms below provided that you ensure that this notice is replicated
-# unmodified and in its entirety in all distributions of the software,
-# modified or unmodified, in source code or in binary form.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-import m5
-from m5.objects import *
-
-# both traffic generator and communication monitor are only available
-# if we have protobuf support, so potentially skip this test
-require_sim_object("TrafficGen")
-require_sim_object("CommMonitor")
-
-# even if this is only a traffic generator, call it cpu to make sure
-# the scripts are happy
-cpu = TrafficGen(
-config_file=srcpath("tests/quick/se/70.tgen/tgen-dram-ctrl.cfg"))
-
-# system simulated
-system = System(cpu = cpu, physmem = DDR3_1600_8x8(),
-membus = IOXBar(width = 16),
-clk_domain = SrcClockDomain(clock = '1GHz',
-voltage_domain =
-VoltageDomain()))
-
-# add a communication monitor
-system.monitor = CommMonitor()
-
-# connect the traffic generator to the bus via a communication monitor
-system.cpu.port = system.monitor.slave
-system.monitor.master = system.membus.slave
-
-# connect the system port even if it is not used in this example
-system.system_port = system.membus.slave
-
-# connect memory to the membus
-system.physmem.port = system.membus.master
-
-# ---
-# run simulation
-# ---
-
-root = Root(full_system = False, system = system)
-root.system.mem_mode = 'timing'
diff --git a/tests/configs/tgen-simple-mem.py  
b/tests/configs/tgen-simple-mem.py

deleted file mode 100644
index 99a8e3d..000
--- a/tests/configs/tgen-simple-mem.py
+++ /dev/null
@@ -1,77 +0,0 @@
-# Copyright (c) 2012 ARM Limited
-# All rights reserved.
-#
-# The license below extends only to copyright in the software and shall
-# not be construed as granting a license to any other intellectual
-# property including but not limited to intellectual property relating
-# to a hardware implementation of the functionality of the software

[gem5-dev] Change in gem5/gem5[develop]: tests: Removed `tests/halt.sh`

2020-09-04 Thread Bobby R. Bruce (Gerrit) via gem5-dev
Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33135 )


Change subject: tests: Removed `tests/halt.sh`
..

tests: Removed `tests/halt.sh`

`tests/halt.sh` is a duplicate of `configs/tests/halt.sh`. The one
instance of using `halt.sh`, `tests/gem5/fs/linux/arm/run.py`, has been
updated to use `configs/tests/halt.sh` and `tests/halt.sh` has been
removed.

Change-Id: I42f77a22b5985959a579c75541e4a0fdc135aa0c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33135
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Giacomo Travaglini 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M tests/gem5/fs/linux/arm/run.py
D tests/halt.sh
2 files changed, 1 insertion(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/gem5/fs/linux/arm/run.py b/tests/gem5/fs/linux/arm/run.py
index 427fae8..1783439 100644
--- a/tests/gem5/fs/linux/arm/run.py
+++ b/tests/gem5/fs/linux/arm/run.py
@@ -67,7 +67,7 @@
 exec(compile(open(config).read(), config, 'exec'))

 system = root.system
-system.readfile = os.path.join(tests_root, 'halt.sh')
+system.readfile = os.path.join(gem5_root, 'configs', 'boot', 'halt.sh')

 # The CPU can either be a list of CPUs or a single object.
 if isinstance(system.cpu, list):
diff --git a/tests/halt.sh b/tests/halt.sh
deleted file mode 100644
index b1332eb..000
--- a/tests/halt.sh
+++ /dev/null
@@ -1 +0,0 @@
-m5 exit

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I42f77a22b5985959a579c75541e4a0fdc135aa0c
Gerrit-Change-Number: 33135
Gerrit-PatchSet: 5
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: tests: Standardized test resources download dir

2020-09-04 Thread Bobby R. Bruce (Gerrit) via gem5-dev
Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33145 )


Change subject: tests: Standardized test resources download dir
..

tests: Standardized test resources download dir

We were downloading resources to various different locations, for no
real reason. This standardizes the process. From this commit onwards,
all testing resources are downloaded to `tests/gem5/resources` by
default. This may be overriden via the `--bin-path` TestLib argument.

Note: In order to do this I have changed the meaning of the `bin-path`
TestLib argument slightly. Previously the `bin-path` assumed a flat
(non-existant) hierarchy. A simple directory of local resources. This
new bin-path functionality maintains logical sub-directories. This is
technically an API change and will be noted in the release notes.

Change-Id: I4df85c121fa65f787fd71f03d74361afea121380
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33145
Reviewed-by: Hoa Nguyen 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
---
M ext/testlib/configuration.py
M tests/.gitignore
M tests/gem5/cpu_tests/test.py
M tests/gem5/fixture.py
M tests/gem5/fs/linux/arm/test.py
M tests/gem5/hello_se/test_hello_se.py
M tests/gem5/insttest_se/test.py
M tests/gem5/m5_util/test_exit.py
M tests/gem5/m5threads_test_atomic/test.py
9 files changed, 13 insertions(+), 32 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Hoa Nguyen: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/ext/testlib/configuration.py b/ext/testlib/configuration.py
index 4e2b695..48fd2a0 100644
--- a/ext/testlib/configuration.py
+++ b/ext/testlib/configuration.py
@@ -215,6 +215,10 @@
   os.pardir))
 defaults.result_path = os.path.join(os.getcwd(), '.testing-results')
 defaults.resource_url = 'http://dist.gem5.org/dist/develop'
+defaults.resource_path =  
os.path.abspath(os.path.join(defaults.base_dir,

+'tests',
+'gem5',
+'resources'))

 def define_constants(constants):
 '''
@@ -569,8 +573,8 @@
 Argument(
 '--bin-path',
 action='store',
-default=None,
-help='Path where binaries are stored (downloaded if not  
present)'

+default=config._defaults.resource_path,
+help='Path where resources are stored (downloaded if not  
present)'

 ),
 Argument(
 '--resource-url',
diff --git a/tests/.gitignore b/tests/.gitignore
index 7c78cf7..6e620f5 100644
--- a/tests/.gitignore
+++ b/tests/.gitignore
@@ -1,7 +1,2 @@
 .testing-results
-gem5/cpu_tests/benchmarks
-gem5/fs/linux/arm/*.tar.bz2
-gem5/fs/linux/arm/binaries
-gem5/fs/linux/arm/disks
-gem5/test-progs
 gem5/resources
diff --git a/tests/gem5/cpu_tests/test.py b/tests/gem5/cpu_tests/test.py
index a21c4b9..44f0574 100644
--- a/tests/gem5/cpu_tests/test.py
+++ b/tests/gem5/cpu_tests/test.py
@@ -51,10 +51,7 @@
 'riscv':  
('AtomicSimpleCPU', 'TimingSimpleCPU', 'MinorCPU', 'DerivO3CPU'),

 }

-if config.bin_path:
-base_path = config.bin_path
-else:
-base_path = joinpath(absdirpath(__file__), 'benchmarks', 'bin')
+base_path = joinpath(config.bin_path, 'cpu_tests')

 base_url = config.resource_url + '/gem5/cpu_tests/benchmarks/bin/'
 for isa in valid_isas:
diff --git a/tests/gem5/fixture.py b/tests/gem5/fixture.py
index fc6aee8..94f3581 100644
--- a/tests/gem5/fixture.py
+++ b/tests/gem5/fixture.py
@@ -223,7 +223,7 @@

 class TestProgram(MakeTarget):
 def __init__(self, program, isa, os, recompile=False):
-make_dir = joinpath('test-progs', program)
+make_dir = joinpath(config.bin_dir, program)
 make_fixture = MakeFixture(make_dir)
 target = joinpath('bin', isa, os, program)
 super(TestProgram, self).__init__(target, make_fixture)
diff --git a/tests/gem5/fs/linux/arm/test.py  
b/tests/gem5/fs/linux/arm/test.py

index 89e9e65..80a2af6 100644
--- a/tests/gem5/fs/linux/arm/test.py
+++ b/tests/gem5/fs/linux/arm/test.py
@@ -91,7 +91,7 @@
 tarball = 'aarch-system-201901106.tar.bz2'
 url = config.resource_url + "/arm/" + tarball
 filepath = os.path.dirname(os.path.abspath(__file__))
-path = config.bin_path if config.bin_path else filepath
+path = joinpath(config.bin_path, 'arm')
 arm_fs_binaries = DownloadedArchive(url, path, tarball)

 for name in arm_fs_quick_tests:
diff --git a/tests/gem5/hello_se/test_hello_se.py  
b/tests/gem5/hello_se/test_hello_se.py

index c7cf7fe..abae3cf 100644
--- a/tests/gem5/hello_se/test_hello_se.py
+++ b/tests/gem5/hello_se/test_hello_se.py
@@ -82,11 +82,7 @@
 'sparc' : constants.long_tag,
 }

-if config.bin_path:
-base_path = 

[gem5-dev] Change in gem5/gem5[develop]: tests: Removed realview tests from .testignore

2020-09-04 Thread Bobby R. Bruce (Gerrit) via gem5-dev
Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33134 )


Change subject: tests: Removed realview tests from .testignore
..

tests: Removed realview tests from .testignore

The tests still fail, as recorded in
https://gem5.atlassian.net/browse/GEM5-364, though they have been
removed from the .testignore file as part of our goal of removing the
.testignore directory: https://gem5.atlassian.net/browse/GEM5-361.

Change-Id: I74f8a6c86e24835acbb4891ab4c88320baf12346
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33134
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M tests/gem5/.testignore
M tests/gem5/fs/linux/arm/test.py
2 files changed, 8 insertions(+), 4 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/gem5/.testignore b/tests/gem5/.testignore
index 366a622..40934ff 100644
--- a/tests/gem5/.testignore
+++ b/tests/gem5/.testignore
@@ -10,5 +10,3 @@
 test-insttest-linux-TimingSimpleCPU-SPARC-aarch64-debug
 test-insttest-linux-AtomicSimpleCPU-SPARC-aarch64-fast
 test-insttest-linux-TimingSimpleCPU-SPARC-aarch64-fast
-realview-o3-checker-ARM-x86_64-opt
-realview64-o3-checker-ARM-x86_64-opt
diff --git a/tests/gem5/fs/linux/arm/test.py  
b/tests/gem5/fs/linux/arm/test.py

index d68e434..a7eacec 100644
--- a/tests/gem5/fs/linux/arm/test.py
+++ b/tests/gem5/fs/linux/arm/test.py
@@ -58,13 +58,11 @@
 'realview-switcheroo-atomic',
 'realview-switcheroo-timing',
 'realview-o3',
-'realview-o3-checker',
 'realview-minor',
 'realview-switcheroo-noncaching-timing',
 'realview-switcheroo-o3',
 'realview-switcheroo-full',
 'realview64-o3',
-'realview64-o3-checker',
 'realview64-o3-dual',
 'realview64-minor',
 'realview64-minor-dual',
@@ -74,12 +72,20 @@
 'realview64-simple-timing-ruby',
 'realview64-simple-timing-dual-ruby',

+
+# The following tests fail. These are recorded in the GEM5-640 and  
GEM5-364

+# Jira issues.
+#
 # https://gem5.atlassian.net/browse/GEM5-640
 #'realview-simple-atomic-dual',
 #'realview-simple-timing-dual',
 #'realview-o3-dual',
 #'realview-minor-dual',
 #'realview-simple-timing-dual-ruby',
+#
+# https://gem5.atlassian.net/browse/GEM5-364
+#'realview-o3-checker',
+#'realview64-o3-checker',
 ]

 tarball = 'aarch-system-201901106.tar.bz2'

--
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To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I74f8a6c86e24835acbb4891ab4c88320baf12346
Gerrit-Change-Number: 33134
Gerrit-PatchSet: 5
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: tests: Removed SPARC Insttests from .testignore

2020-09-04 Thread Bobby R. Bruce (Gerrit) via gem5-dev
Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33138 )


Change subject: tests: Removed SPARC Insttests from .testignore
..

tests: Removed SPARC Insttests from .testignore

Due to the fixing of the SPARC insttest binary, recorded here:
https://gem5-review.googlesource.com/c/public/gem5-resources/+/33396,
these tests now pass.

Change-Id: I4dca4504476f6d388e607a1075d44e9be69b5259
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33138
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
D tests/gem5/.testignore
A tests/gem5/insttest_se/ref/sparc/linux/insttest/simout
D tests/gem5/insttest_se/ref/sparc/linux/simout
M tests/gem5/insttest_se/test.py
4 files changed, 19 insertions(+), 36 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/gem5/.testignore b/tests/gem5/.testignore
deleted file mode 100644
index 40934ff..000
--- a/tests/gem5/.testignore
+++ /dev/null
@@ -1,12 +0,0 @@
-test-insttest-linux-AtomicSimpleCPU-SPARC-x86_64-opt
-test-insttest-linux-TimingSimpleCPU-SPARC-x86_64-opt
-test-insttest-linux-AtomicSimpleCPU-SPARC-x86_64-debug
-test-insttest-linux-TimingSimpleCPU-SPARC-x86_64-debug
-test-insttest-linux-AtomicSimpleCPU-SPARC-x86_64-fast
-test-insttest-linux-TimingSimpleCPU-SPARC-x86_64-fast
-test-insttest-linux-AtomicSimpleCPU-SPARC-aarch64-opt
-test-insttest-linux-TimingSimpleCPU-SPARC-aarch64-opt
-test-insttest-linux-AtomicSimpleCPU-SPARC-aarch64-debug
-test-insttest-linux-TimingSimpleCPU-SPARC-aarch64-debug
-test-insttest-linux-AtomicSimpleCPU-SPARC-aarch64-fast
-test-insttest-linux-TimingSimpleCPU-SPARC-aarch64-fast
diff --git a/tests/gem5/insttest_se/ref/sparc/linux/insttest/simout  
b/tests/gem5/insttest_se/ref/sparc/linux/insttest/simout

new file mode 100644
index 000..4665746
--- /dev/null
+++ b/tests/gem5/insttest_se/ref/sparc/linux/insttest/simout
@@ -0,0 +1,17 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+
+Global frequency set at 1 ticks per second
+ REAL SIMULATION 
+Begining test of difficult SPARC instructions...
+LDSTUB:Passed
+SWAP:  Passed
+CAS FAIL:  Passed
+CAS WORK:  Passed
+CASX FAIL: Passed
+CASX WORK: Passed
+LDTX:  Passed
+LDTW:  Passed
+STTW:  Passed
+Done
diff --git a/tests/gem5/insttest_se/ref/sparc/linux/simout  
b/tests/gem5/insttest_se/ref/sparc/linux/simout

deleted file mode 100755
index bf2b3f4..000
--- a/tests/gem5/insttest_se/ref/sparc/linux/simout
+++ /dev/null
@@ -1,23 +0,0 @@
-Redirecting stdout to  
build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic/simout
-Redirecting stderr to  
build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic/simerr

-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Apr  3 2017 18:41:19
-gem5 started Apr  3 2017 18:41:41
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64897
-command line:  
/usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d  
build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic  
--stats-file 'text://stats.txt?desc=False' -re  
/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py  
quick/se/02.insttest/sparc/linux/simple-atomic

-
-Global frequency set at 1 ticks per second
-Begining test of difficult SPARC instructions...
-LDSTUB:Passed
-SWAP:  Passed
-CAS FAIL:  Passed
-CAS WORK:  Passed
-CASX FAIL: Passed
-CASX WORK: Passed
-LDTX:  Passed
-LDTW:  Passed
-STTW:  Passed
-Done
-Exiting @ tick 7612000 because exiting with last active thread context
diff --git a/tests/gem5/insttest_se/test.py b/tests/gem5/insttest_se/test.py
index 878d978..4009d69 100644
--- a/tests/gem5/insttest_se/test.py
+++ b/tests/gem5/insttest_se/test.py
@@ -34,10 +34,11 @@
 test_progs = {
 'sparc': ('insttest',)
 }
-#o3-timing  simple-atomic  simple-timing
+
 cpu_types = {
 'sparc' : ('AtomicSimpleCPU', 'TimingSimpleCPU')
 }
+
 supported_os = {
 'sparc' : ('linux',)
 }

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4dca4504476f6d388e607a1075d44e9be69b5259
Gerrit-Change-Number: 33138
Gerrit-PatchSet: 9
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged

[gem5-dev] Change in gem5/gem5[develop]: tests: Removed learning-gem5 tests/configs

2020-09-04 Thread Bobby R. Bruce (Gerrit) via gem5-dev
Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33144 )


Change subject: tests: Removed learning-gem5 tests/configs
..

tests: Removed learning-gem5 tests/configs

These configs are currently unused, and only served as redirects. They
are therefore being removed.

Change-Id: I12e5c2adb3a9c63ffc3177472eaa698b1cf80e41
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33144
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
D tests/configs/learning-gem5-p1-simple.py
D tests/configs/learning-gem5-p1-two-level.py
2 files changed, 0 insertions(+), 68 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/configs/learning-gem5-p1-simple.py  
b/tests/configs/learning-gem5-p1-simple.py

deleted file mode 100644
index 2f3288a..000
--- a/tests/configs/learning-gem5-p1-simple.py
+++ /dev/null
@@ -1,34 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2015 Jason Lowe-Power
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-# A wrapper around configs/learning_gem5/part1/simple.py
-
-# For some reason, this is implicitly needed by run.py
-root = None
-
-def run_test(root):
-run_config('configs/learning_gem5/part1/simple.py')
diff --git a/tests/configs/learning-gem5-p1-two-level.py  
b/tests/configs/learning-gem5-p1-two-level.py

deleted file mode 100644
index 2815617..000
--- a/tests/configs/learning-gem5-p1-two-level.py
+++ /dev/null
@@ -1,34 +0,0 @@
-# -*- coding: utf-8 -*-
-# Copyright (c) 2015 Jason Lowe-Power
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-# A wrapper around configs/learning_gem5/part1/two_level.py
-
-# For some reason, this is implicitly needed by run.py
-root = None
-
-def run_test(root):
-run_config('configs/learning_gem5/part1/two_level.py')

--
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[gem5-dev] Change in gem5/gem5[develop]: util: add dev-hsa commit message tag

2020-09-04 Thread Matt Sinclair (Gerrit) via gem5-dev
Matt Sinclair has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34095 )


Change subject: util: add dev-hsa commit message tag
..

util: add dev-hsa commit message tag

The dev-hsa commit message tag was originally an option, but
appears to have been removed during the merge of the AMD GCN3
staging branch.  This commit adds it back.

Change-Id: Ie755b5ebe6ca1e5e92583b1588fd7aaeddcb5b00
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34095
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M util/git-commit-msg.py
1 file changed, 4 insertions(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/git-commit-msg.py b/util/git-commit-msg.py
index d33b5b0..9cba896 100755
--- a/util/git-commit-msg.py
+++ b/util/git-commit-msg.py
@@ -91,10 +91,10 @@
 valid_tags = ["arch", "arch-arm", "arch-gcn3",
 "arch-mips", "arch-power", "arch-riscv", "arch-sparc", "arch-x86",
 "base", "configs", "cpu", "cpu-kvm", "cpu-minor", "cpu-o3",
-"cpu-simple", "dev", "dev-arm", "dev-virtio", "ext", "fastmodel",
-"gpu-compute", "learning-gem5", "mem", "mem-cache", "mem-garnet",
-"mem-ruby", "misc", "python", "scons", "sim", "sim-se", "sim-power",
-"stats", "system", "system-arm", "systemc", "tests",
+"cpu-simple", "dev", "dev-arm", "dev-hsa", "dev-virtio", "ext",
+"fastmodel", "gpu-compute", "learning-gem5", "mem", "mem-cache",
+"mem-garnet", "mem-ruby", "misc", "python", "scons", "sim", "sim-se",
+"sim-power", "stats", "system", "system-arm", "systemc", "tests",
 "util", "RFC", "WIP"]

 tags = ''.join(commit_header.split(':')[0].split()).split(',')

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie755b5ebe6ca1e5e92583b1588fd7aaeddcb5b00
Gerrit-Change-Number: 34095
Gerrit-PatchSet: 2
Gerrit-Owner: Matt Sinclair 
Gerrit-Reviewer: Alexandru Duțu 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Anthony Gutierrez 
Gerrit-CC: Bradford Beckmann 
Gerrit-CC: Kyle Roarty 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Set ContextId on request from trace CPU

2020-09-04 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34035 )


Change subject: cpu: Set ContextId on request from trace CPU
..

cpu: Set ContextId on request from trace CPU

Adds a contextId to the trace CPU in one more case that was missing.
Without this a panic is triggered in the cache.

Change-Id: I78bd70ad1e3657c9a6a1d56c234c007c2e2b586c
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34035
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/cpu/trace/trace_cpu.cc
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc
index dd91257..13f194c 100644
--- a/src/cpu/trace/trace_cpu.cc
+++ b/src/cpu/trace/trace_cpu.cc
@@ -653,6 +653,9 @@
 node_ptr->physAddr, node_ptr->size, node_ptr->flags, masterID);
 req->setReqInstSeqNum(node_ptr->seqNum);

+// If this is not done it triggers assert in L1 cache for invalid  
contextId

+req->setContext(ContextID(0));
+
 req->setPC(node_ptr->pc);
 // If virtual address is valid, set the virtual address field
 // of the request.

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I78bd70ad1e3657c9a6a1d56c234c007c2e2b586c
Gerrit-Change-Number: 34035
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: python: Remove unused debug APIs

2020-09-04 Thread Andreas Sandberg (Gerrit) via gem5-dev
Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34120 )



Change subject: python: Remove unused debug APIs
..

python: Remove unused debug APIs

The following APIs are not exported from the _m5 namespace and not
used by any of the debug glue code:

 * m5.debug.findFlag
 * m5.debug.setDebugFlag
 * m5.debug.clearDebugFlag
 * m5.debug.dumpDebugFlags

All of them have a clean Python interface where flags are exported
using the m5.debug.flags dictionary. There is also an m5.debug.help
function that lists the available debug flags.

Remove the unused APIs to avoid confusion.

Change-Id: I74738451eb5874f83b135adaccd30a0c6b478996
Signed-off-by: Andreas Sandberg 
---
M src/python/pybind11/debug.cc
1 file changed, 0 insertions(+), 4 deletions(-)



diff --git a/src/python/pybind11/debug.cc b/src/python/pybind11/debug.cc
index 69c497c..84673f1 100644
--- a/src/python/pybind11/debug.cc
+++ b/src/python/pybind11/debug.cc
@@ -83,10 +83,6 @@
 m_debug
 .def("getAllFlagsVersion", []() { return Debug::allFlagsVersion; })
 .def("allFlags", ::allFlags,  
py::return_value_policy::reference)

-.def("findFlag", ::findFlag)
-.def("setDebugFlag", )
-.def("clearDebugFlag", )
-.def("dumpDebugFlags", )

 .def("schedBreak", )
 .def("setRemoteGDBPort", )

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I74738451eb5874f83b135adaccd30a0c6b478996
Gerrit-Change-Number: 34120
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: python: Add the ability to check if a debug flag has been enabled

2020-09-04 Thread Andreas Sandberg (Gerrit) via gem5-dev
Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34119 )



Change subject: python: Add the ability to check if a debug flag has been  
enabled

..

python: Add the ability to check if a debug flag has been enabled

There is currently no Python API to check if a debug flag is
enabled. Add a new status property that can be read or set to control
the status of a flag. The stat of a flag can also be queried by
converting it to a bool.

For example:

  m5.debug.flags["XBar"].status = True

  if m5.debug.flags["XBar"]:
  print("XBar debugging is on")

Change-Id: I5a50c39ced182ab44e18c061c463d7d9c41ef186
Signed-off-by: Andreas Sandberg 
---
M src/python/pybind11/debug.cc
1 file changed, 14 insertions(+), 0 deletions(-)



diff --git a/src/python/pybind11/debug.cc b/src/python/pybind11/debug.cc
index ed2942b..69c497c 100644
--- a/src/python/pybind11/debug.cc
+++ b/src/python/pybind11/debug.cc
@@ -98,6 +98,20 @@
 .def_property_readonly("desc", ::Flag::desc)
 .def("enable", ::Flag::enable)
 .def("disable", ::Flag::disable)
+.def_property("status",
+  [](const Debug::Flag *flag) {
+  return flag->status();
+  },
+  [](Debug::Flag *flag, bool state) {
+  if (state) {
+  flag->enable();
+  } else {
+  flag->disable();
+  }
+  })
+.def("__bool__", [](const Debug::Flag *flag) {
+return flag->status();
+})
 ;

 py::class_(m_debug, "SimpleFlag", c_flag);

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I5a50c39ced182ab44e18c061c463d7d9c41ef186
Gerrit-Change-Number: 34119
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: base: Cleanup debug flags API

2020-09-04 Thread Andreas Sandberg (Gerrit) via gem5-dev
Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34118 )



Change subject: base: Cleanup debug flags API
..

base: Cleanup debug flags API

The debug flags API has a couple of quirks that should be cleaned
up. Specifically:

 * Only CompoundFlag should expose a list of children.
 * The global enable flag is just called "active", this isn't very
   descriptive.
 * Only SimpleFlag exposed a status member. This should be in the base
   class to make the API symmetric.
 * Flag::Sync() is an implementation detail and needs to be protected.

Change-Id: I4d7fd32c80891191aa04f0bd0c334c8cf8d372f5
Signed-off-by: Andreas Sandberg 
---
M src/base/debug.cc
M src/base/debug.hh
M src/base/trace.cc
M src/python/m5/debug.py
M src/python/pybind11/debug.cc
5 files changed, 79 insertions(+), 44 deletions(-)



diff --git a/src/base/debug.cc b/src/base/debug.cc
index 47febd0..45d9f9d 100644
--- a/src/base/debug.cc
+++ b/src/base/debug.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -67,7 +79,7 @@
 return flags;
 }

-bool SimpleFlag::_active = false;
+bool Flag::_globalEnable = false;

 Flag *
 findFlag(const std::string )
@@ -96,17 +108,17 @@
 }

 void
-SimpleFlag::enableAll()
+Flag::globalEnable()
 {
-_active = true;
+_globalEnable = true;
 for (auto& i : allFlags())
 i.second->sync();
 }

 void
-SimpleFlag::disableAll()
+Flag::globalDisable()
 {
-_active = false;
+_globalEnable = false;
 for (auto& i : allFlags())
 i.second->sync();
 }
@@ -125,6 +137,19 @@
 k->disable();
 }

+bool
+CompoundFlag::status() const
+{
+if (_kids.empty())
+return false;
+
+for (auto& k : _kids) {
+if (!k->status())
+return false;
+}
+
+return true;
+}

 bool
 changeFlag(const char *s, bool value)
diff --git a/src/base/debug.hh b/src/base/debug.hh
index 1d35be0..a5dc43c 100644
--- a/src/base/debug.hh
+++ b/src/base/debug.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  * Copyright (c) 2010 The Hewlett-Packard Development Company
  * All rights reserved.
@@ -42,45 +54,48 @@
 class Flag
 {
   protected:
+static bool _globalEnable; // whether debug tracings are enabled
+
 const char *_name;
 const char *_desc;

+virtual void sync() { }
+
   public:
 Flag(const char *name, const char *desc);
 virtual ~Flag();

 std::string name() const { return _name; }
 std::string desc() const { return _desc; }
-virtual std::vector kids() { return std::vector(); }

 virtual void enable() = 0;
 virtual void disable() = 0;
-virtual void sync() {}
+virtual bool status() const = 0;
+
+operator bool() const { return status(); }
+bool operator!() const { return !status(); }
+
+static void globalEnable();
+static void globalDisable();
 };

 class SimpleFlag : public Flag
 {
-static bool _active; // whether debug tracings are enabled
   protected:
 bool _tracing; // tracing is enabled and flag is on
 bool _status;  // flag status

+void sync() override { _tracing = _globalEnable && _status; }
+
   public:
 SimpleFlag(const char *name, const char *desc)
 : Flag(name, desc), _status(false)
 { }

-bool status() const { return _tracing; }
-operator bool() const { return _tracing; }
-bool operator!() const { return !_tracing; }
+bool status() const override { return _tracing; }

-void enable()  { _status = true;  sync(); }
-void disable() { _status = false; sync(); }
-
- 

[gem5-dev] Change in gem5/gem5[develop]: base: Remove unused Debug::All flag

2020-09-04 Thread Andreas Sandberg (Gerrit) via gem5-dev
Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34117 )



Change subject: base: Remove unused Debug::All flag
..

base: Remove unused Debug::All flag

The Debug::All flag doesn't seem to be used. Remove it.

Change-Id: I3d6ad1b2f61a2a0a5c52cbc6d520112855946007
Signed-off-by: Andreas Sandberg 
---
M src/base/debug.cc
M src/base/debug.hh
2 files changed, 0 insertions(+), 31 deletions(-)



diff --git a/src/base/debug.cc b/src/base/debug.cc
index b165f64..47febd0 100644
--- a/src/base/debug.cc
+++ b/src/base/debug.cc
@@ -125,35 +125,6 @@
 k->disable();
 }

-struct AllFlags : public Flag
-{
-AllFlags()
-: Flag("All", "All Flags")
-{}
-
-void
-enable()
-{
-FlagsMap::iterator i = allFlags().begin();
-FlagsMap::iterator end = allFlags().end();
-for (; i != end; ++i)
-if (i->second != this)
-i->second->enable();
-}
-
-void
-disable()
-{
-FlagsMap::iterator i = allFlags().begin();
-FlagsMap::iterator end = allFlags().end();
-for (; i != end; ++i)
-if (i->second != this)
-i->second->disable();
-}
-};
-
-AllFlags theAllFlags;
-Flag *const All = 

 bool
 changeFlag(const char *s, bool value)
diff --git a/src/base/debug.hh b/src/base/debug.hh
index 479a830..1d35be0 100644
--- a/src/base/debug.hh
+++ b/src/base/debug.hh
@@ -108,8 +108,6 @@

 Flag *findFlag(const std::string );

-extern Flag *const All;
-
 bool changeFlag(const char *s, bool value);

 } // namespace Debug

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3d6ad1b2f61a2a0a5c52cbc6d520112855946007
Gerrit-Change-Number: 34117
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: scons: Simplify arch enum generation

2020-09-04 Thread Andreas Sandberg (Gerrit) via gem5-dev
Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34116 )



Change subject: scons: Simplify arch enum generation
..

scons: Simplify arch enum generation

C++ allows a trailing comma after the last item in an enum, so there
is no need for a special case.

Change-Id: I6ead36b4a8562b4a7a5aec88e4f6390182eedf56
Signed-off-by: Andreas Sandberg 
---
M src/SConscript
1 file changed, 4 insertions(+), 10 deletions(-)



diff --git a/src/SConscript b/src/SConscript
index 4b6db44..9f82bdc 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -645,11 +645,8 @@
 # create an enum for any run-time determination of the ISA, we
 # reuse the same name as the namespaces
 code('enum class Arch {')
-for i,isa in enumerate(isas):
-if i + 1 == len(isas):
-code('  $0 = $1', namespace(isa), define(isa))
-else:
-code('  $0 = $1,', namespace(isa), define(isa))
+for isa in isas:
+code('  $0 = $1,', namespace(isa), define(isa))
 code('};')

 code('''
@@ -690,11 +687,8 @@
 # create an enum for any run-time determination of the ISA, we
 # reuse the same name as the namespaces
 code('enum class GPUArch {')
-for i,isa in enumerate(isas):
-if i + 1 == len(isas):
-code('  $0 = $1', namespace(isa), define(isa))
-else:
-code('  $0 = $1,', namespace(isa), define(isa))
+for isa in isas:
+code('  $0 = $1,', namespace(isa), define(isa))
 code('};')

 code('''

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I6ead36b4a8562b4a7a5aec88e4f6390182eedf56
Gerrit-Change-Number: 34116
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: base: Cleanup Debug::CompoundFlag

2020-09-04 Thread Andreas Sandberg (Gerrit) via gem5-dev
Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34115 )



Change subject: base: Cleanup Debug::CompoundFlag
..

base: Cleanup Debug::CompoundFlag

Compound flags are currently constructed using a constructor with a
finite set of arguments that default to nullptr that refer to child
flags. C++11 introduces two cleaner ways to achieve the same thing,
variadic templates and initializer_list. Use an initializer list to
pass dependent flags.

Change-Id: Iadcd04986ab20efccfae9b92b26c079b9612262e
Signed-off-by: Andreas Sandberg 
---
M src/SConscript
M src/base/debug.hh
2 files changed, 9 insertions(+), 29 deletions(-)



diff --git a/src/SConscript b/src/SConscript
index d9cde28..4b6db44 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -1071,15 +1071,12 @@
 if not compound:
 code('SimpleFlag $name("$name", "$desc");')
 else:
-comp_code('CompoundFlag $name("$name", "$desc",')
+comp_code('CompoundFlag $name("$name", "$desc", {')
 comp_code.indent()
-last = len(compound) - 1
-for i,flag in enumerate(compound):
-if i != last:
-comp_code('&$flag,')
-else:
-comp_code('&$flag);')
+for flag in compound:
+comp_code('&$flag,')
 comp_code.dedent()
+comp_code('});')

 code.append(comp_code)
 code()
diff --git a/src/base/debug.hh b/src/base/debug.hh
index 7c9834c..479a830 100644
--- a/src/base/debug.hh
+++ b/src/base/debug.hh
@@ -30,6 +30,7 @@
 #ifndef __BASE_DEBUG_HH__
 #define __BASE_DEBUG_HH__

+#include 
 #include 
 #include 
 #include 
@@ -87,31 +88,13 @@
   protected:
 std::vector _kids;

-void
-addFlag(Flag *f)
-{
-if (f != nullptr)
-_kids.push_back(f);
-}
-
   public:
+template
 CompoundFlag(const char *name, const char *desc,
-Flag *f00 = nullptr, Flag *f01 = nullptr,
-Flag *f02 = nullptr, Flag *f03 = nullptr,
-Flag *f04 = nullptr, Flag *f05 = nullptr,
-Flag *f06 = nullptr, Flag *f07 = nullptr,
-Flag *f08 = nullptr, Flag *f09 = nullptr,
-Flag *f10 = nullptr, Flag *f11 = nullptr,
-Flag *f12 = nullptr, Flag *f13 = nullptr,
-Flag *f14 = nullptr, Flag *f15 = nullptr,
-Flag *f16 = nullptr, Flag *f17 = nullptr,
-Flag *f18 = nullptr, Flag *f19 = nullptr)
-: Flag(name, desc)
+ std::initializer_list flags)
+: Flag(name, desc),
+  _kids(flags)
 {
-addFlag(f00); addFlag(f01); addFlag(f02); addFlag(f03);  
addFlag(f04);
-addFlag(f05); addFlag(f06); addFlag(f07); addFlag(f08);  
addFlag(f09);
-addFlag(f10); addFlag(f11); addFlag(f12); addFlag(f13);  
addFlag(f14);
-addFlag(f15); addFlag(f16); addFlag(f17); addFlag(f18);  
addFlag(f19);

 }

 std::vector kids() { return _kids; }

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iadcd04986ab20efccfae9b92b26c079b9612262e
Gerrit-Change-Number: 34115
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg 
Gerrit-MessageType: newchange
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