[gem5-dev] Change in gem5/gem5[develop]: arch: Build the operand REs in the isa_parser on demand.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35237 )


Change subject: arch: Build the operand REs in the isa_parser on demand.
..

arch: Build the operand REs in the isa_parser on demand.

These regular expressions search code snippets to find places where
operands are used. Rather than build them explicitly at the end of
processing the operands{{}} construct, wait until they're first going to
be used. That way, we'll be able to define operands in as many places as
we want, as long as we've done all we're going to do before the first
instructions are defined.

This will pave the way to defining operands in regular python in let
blocks, and then possibly outside of the parser altogether, perhaps into
scons where having lots of output files for individual instructions will
be easier to manage. For now, this just lets you define multiple
operands blocks which is not all that exciting on its own :)

Change-Id: I1179092316c1c0ac2613810bfd236a32235502fb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35237
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Richard Cooper 
Reviewed-by: Steve Reinhardt 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/isa_parser.py
1 file changed, 30 insertions(+), 11 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve
  Steve Reinhardt: Looks good to me, approved
  Richard Cooper: Looks good to me, but someone else must approve
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index 86f5089..955d4e2 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -1133,7 +1133,7 @@
 # search for operands
 next_pos = 0
 while 1:
-match = parser.operandsRE.search(code, next_pos)
+match = parser.operandsRE().search(code, next_pos)
 if not match:
 # no more matches: we're done
 break
@@ -1303,7 +1303,7 @@
 # search for operands
 next_pos = 0
 while 1:
-match = parser.operandsRE.search(code, next_pos)
+match = parser.operandsRE().search(code, next_pos)
 if not match:
 # no more matches: we're done
 break
@@ -1558,6 +1558,13 @@
 # variable to hold templates
 self.templateMap = {}

+# variable to hold operands
+self.operandNameMap = {}
+
+# Regular expressions for working with operands
+self._operandsRE = None
+self._operandsWithExtRE = None
+
 # This dictionary maps format name strings to Format objects.
 self.formatMap = {}

@@ -1590,6 +1597,16 @@
 self.maxInstDestRegs = 0
 self.maxMiscDestRegs = 0

+def operandsRE(self):
+if not self._operandsRE:
+self.buildOperandREs()
+return self._operandsRE
+
+def operandsWithExtRE(self):
+if not self._operandsWithExtRE:
+self.buildOperandREs()
+return self._operandsWithExtRE
+
 def __getitem__(self, i):# Allow object (self) to be
 return getattr(self, i)  # passed to %-substitutions

@@ -2581,18 +2598,19 @@
 # in tmp_dict, just as if we evaluated a class declaration.
 operand_name[op_name] = type(cls_name, (base_cls,), tmp_dict)

-self.operandNameMap = operand_name
+self.operandNameMap.update(operand_name)

+def buildOperandREs(self):
 # Define operand variables.
-operands = list(user_dict.keys())
+operands = list(self.operandNameMap.keys())
 # Add the elems defined in the vector operands and
 # build a map elem -> vector (used in OperandList)
 elem_to_vec = {}
-for op in user_dict.keys():
-if hasattr(self.operandNameMap[op], 'elems'):
-for elem in self.operandNameMap[op].elems.keys():
+for op_name, op in self.operandNameMap.items():
+if hasattr(op, 'elems'):
+for elem in op.elems.keys():
 operands.append(elem)
-elem_to_vec[elem] = op
+elem_to_vec[elem] = op_name
 self.elemToVector = elem_to_vec
 extensions = self.operandTypeMap.keys()

@@ -2602,7 +2620,8 @@
 (?!\w)   # neg. lookahead assertion: prevent partial matches
 ''' % ('|'.join(operands), '|'.join(extensions))

-self.operandsRE = re.compile(operandsREString, re.MULTILINE| 
re.VERBOSE)

+self._operandsRE = re.compile(operandsREString,
+  re.MULTILINE | re.VERBOSE)

 # Same as operandsREString, but extension is mandatory, and only  
two

 # groups are returned (base and ext, not full name as above).
@@ -2610,14 +2629,14 @@
 operandsWithExtREString = 

[gem5-dev] Change in gem5/gem5[develop]: mem: Add support to tag tlb entries with PCID

[Ayaz Akram (Gerrit) via gem5-dev]

Ayaz Akram has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35836 )



Change subject: mem: Add support to tag tlb entries with PCID
..

mem: Add support to tag tlb entries with PCID

This change adds support to tag tlb entries with PCID to
avoid the conflict between different processes with same
virtual addresses sharing a tlb. This eventually is required
to enable smt support for x86.

Change-Id: Ia91dc371482793962e3fc83afe7a3fd2cdb60eab
---
M src/arch/x86/pagetable_walker.cc
M src/arch/x86/tlb.cc
M src/arch/x86/tlb.hh
3 files changed, 49 insertions(+), 8 deletions(-)



diff --git a/src/arch/x86/pagetable_walker.cc  
b/src/arch/x86/pagetable_walker.cc

index fd9d043..07d20b4 100644
--- a/src/arch/x86/pagetable_walker.cc
+++ b/src/arch/x86/pagetable_walker.cc
@@ -510,8 +510,22 @@
 }
 if (doEndWalk) {
 if (doTLBInsert)
-if (!functional)
-walker->tlb->insert(entry.vaddr, entry);
+if (!functional) {
+
+// Check if PCIDE is set in CR4
+CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4);
+if (cr4.pcide){
+CR3 cr3 = tc->readMiscRegNoEffect(MISCREG_CR3);
+walker->tlb->insert(entry.vaddr, entry, cr3.pcid);
+}
+else{
+// The current PCID is always 000H if PCIDE
+// is not set [sec 4.10.1 of Intel's Software
+// Developer Manual]
+walker->tlb->insert(entry.vaddr, entry, 0x000);
+}
+}
+
 endWalk();
 } else {
 PacketPtr oldRead = read;
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 11ce660..0eebdcf 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -94,8 +94,14 @@
 }

 TlbEntry *
-TLB::insert(Addr vpn, const TlbEntry )
+TLB::insert(Addr vpn, const TlbEntry , uint64_t pcid)
 {
+//Adding pcid to the page address so
+//that multiple processes using the same
+//tlb do not conflict when using the same
+//virtual addresses
+vpn = concAddrPcid(vpn, pcid);
+
 // If somebody beat us to it, just use that existing entry.
 TlbEntry *newEntry = trie.lookup(vpn);
 if (newEntry) {
@@ -113,7 +119,7 @@
 newEntry->lruSeq = nextSeq();
 newEntry->vaddr = vpn;
 newEntry->trieHandle =
-trie.insert(vpn, TlbEntryTrie::MaxBits - entry.logBytes, newEntry);
+trie.insert(vpn, TlbEntryTrie::MaxBits, newEntry);
 return newEntry;
 }

@@ -371,7 +377,22 @@
 if (m5Reg.paging) {
 DPRINTF(TLB, "Paging enabled.\n");
 // The vaddr already has the segment base applied.
-TlbEntry *entry = lookup(vaddr);
+
+//Appending the pcid (last 12 bits of CR3) to the
+//page aligned vaddr if pcide is set
+CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4);
+Addr pageAlignedVaddr = vaddr & mask(X86ISA::PageShift);
+CR3 cr3 = tc->readMiscRegNoEffect(MISCREG_CR3);
+uint64_t pcid;
+
+if (cr4.pcide)
+pcid = cr3.pcid;
+else
+pcid = 0x000;
+
+pageAlignedVaddr = concAddrPcid(pageAlignedVaddr, pcid);
+TlbEntry *entry = lookup(pageAlignedVaddr);
+
 if (mode == Read) {
 stats.rdAccesses++;
 } else {
@@ -393,7 +414,7 @@
 delayedResponse = true;
 return fault;
 }
-entry = lookup(vaddr);
+entry = lookup(pageAlignedVaddr);
 assert(entry);
 } else {
 Process *p = tc->getProcessPtr();
@@ -409,7 +430,8 @@
 entry = insert(alignedVaddr, TlbEntry(
 p->pTable->pid(), alignedVaddr, pte->paddr,
 pte->flags &  
EmulationPageTable::Uncacheable,
-pte->flags &  
EmulationPageTable::ReadOnly));

+pte->flags & EmulationPageTable::ReadOnly),
+pcid);
 }
 DPRINTF(TLB, "Miss was serviced.\n");
 }
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 671b165..c5fe3a6 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -73,6 +73,11 @@
 TlbEntry *lookup(Addr va, bool update_lru = true);

 void setConfigAddress(uint32_t addr);
+//concatenate Page Addr and pcid
+inline Addr concAddrPcid(Addr vpn, uint64_t pcid)
+{
+  return (vpn | pcid);
+}

   protected:

@@ -150,7 +155,7 @@
 Fault finalizePhysical(const RequestPtr , ThreadContext *tc,
Mode mode) const override;

-TlbEntry 

[gem5-dev] Change in gem5/gem5[develop]: mem: Add support for PCID to x86

[Ayaz Akram (Gerrit) via gem5-dev]

Ayaz Akram has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35835 )



Change subject: mem: Add support for PCID to x86
..

mem: Add support for PCID to x86

This change adds Process Context Identifier (PCID) support
to x86, so that tlb entries can be tagged using pcid.

Change-Id: I695eccc4b08476b32d4b3728fc3c42b2ad6f5a28
---
M src/arch/x86/cpuid.cc
M src/arch/x86/pagetable_walker.cc
M src/arch/x86/process.cc
M src/arch/x86/regs/misc.hh
4 files changed, 19 insertions(+), 3 deletions(-)



diff --git a/src/arch/x86/cpuid.cc b/src/arch/x86/cpuid.cc
index 64d4544..0210111 100644
--- a/src/arch/x86/cpuid.cc
+++ b/src/arch/x86/cpuid.cc
@@ -102,7 +102,7 @@
 break;
   case FamilyModelSteppingBrandFeatures:
 result = CpuidResult(0x00020f51, 0x0405,
- 0xe3d3fbff, 0x0001);
+ 0xe3d3fbff, 0x00020001);
 break;
   case NameString1:
   case NameString2:
diff --git a/src/arch/x86/pagetable_walker.cc  
b/src/arch/x86/pagetable_walker.cc

index f5b5521..fd9d043 100644
--- a/src/arch/x86/pagetable_walker.cc
+++ b/src/arch/x86/pagetable_walker.cc
@@ -549,6 +549,7 @@
 {
 VAddr addr = vaddr;
 CR3 cr3 = tc->readMiscRegNoEffect(MISCREG_CR3);
+CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4);
 // Check if we're in long mode or not
 Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
 dataSize = 8;
@@ -560,7 +561,6 @@
 enableNX = efer.nxe;
 } else {
 // We're in some flavor of legacy mode.
-CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4);
 if (cr4.pae) {
 // Do legacy PAE.
 state = PAEPDP;
@@ -584,7 +584,10 @@
 entry.vaddr = vaddr;

 Request::Flags flags = Request::PHYSICAL;
-if (cr3.pcd)
+
+// PCD can't be used if CR4.PCIDE=1 [sec 2.5
+// of Intel's Software Developer's manual]
+if (!cr4.pcide && cr3.pcd)
 flags.set(Request::UNCACHEABLE);

 RequestPtr request = std::make_shared(
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index 7718fdc..2d0439f 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -580,6 +580,17 @@
 tc->setMiscReg(MISCREG_CR0, cr0);

 tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
+
+// Setting CR3 to the process pid so that concatinated
+// page addr with lower 12 bits of CR3 can be used in SE
+// mode as well to avoid conflicts between tlb entries with
+// same virtual addresses belonging to different processes
+tc->setMiscReg(MISCREG_CR3, pTable->pid());
+
+// Setting pcide bit in CR4
+CR4 cr4 = 0;
+cr4.pcide = 1;
+tc->setMiscReg(MISCREG_CR4, cr4);
 }
 }
 }
diff --git a/src/arch/x86/regs/misc.hh b/src/arch/x86/regs/misc.hh
index 42b1862..2de38a6 100644
--- a/src/arch/x86/regs/misc.hh
+++ b/src/arch/x86/regs/misc.hh
@@ -616,12 +616,14 @@
// Base Address
 Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
  // Base Address
+Bitfield<11, 0> pcid; // Process-Context Identifier
 Bitfield<4> pcd; // Page-Level Cache Disable
 Bitfield<3> pwt; // Page-Level Writethrough
 EndBitUnion(CR3)

 BitUnion64(CR4)
 Bitfield<18> osxsave; // Enable XSAVE and Proc Extended States
+Bitfield<17> pcide; // PCID Enable
 Bitfield<16> fsgsbase; // Enable RDFSBASE, RDGSBASE, WRFSBASE,
// WRGSBASE instructions
 Bitfield<10> osxmmexcpt; // Operating System Unmasked

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I695eccc4b08476b32d4b3728fc3c42b2ad6f5a28
Gerrit-Change-Number: 35835
Gerrit-PatchSet: 1
Gerrit-Owner: Ayaz Akram 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Append thread number to APIC id

[Ayaz Akram (Gerrit) via gem5-dev]

Ayaz Akram has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35837 )



Change subject: arch-x86: Append thread number to APIC id
..

arch-x86: Append thread number to APIC id

This change appends the smt thread number to APIC id to enable
smt support for x86

Change-Id: I3e7034b358623577c5ad4be3e51f08e48291ce49
---
M src/arch/x86/interrupts.cc
1 file changed, 2 insertions(+), 1 deletion(-)



diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc
index 7767c80..c955f67 100644
--- a/src/arch/x86/interrupts.cc
+++ b/src/arch/x86/interrupts.cc
@@ -279,7 +279,8 @@

 BaseInterrupts::setThreadContext(_tc);

-initialApicId = tc->cpuId();
+//Update APIC id to consider SMT threads
+initialApicId = (tc->cpuId() << sys->threads.size()) + _tc->threadId();
 regs[APIC_ID] = (initialApicId << 24);
 pioAddr = x86LocalAPICAddress(initialApicId, 0);
 }

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3e7034b358623577c5ad4be3e51f08e48291ce49
Gerrit-Change-Number: 35837
Gerrit-PatchSet: 1
Gerrit-Owner: Ayaz Akram 
Gerrit-MessageType: newchange
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[gem5-dev] Re: Build failed in Jenkins: Nightly #91

[Jieming Yin via gem5-dev]

Hi Matt,

My workaround is to do it in a python2 manner:

class SEWorkload(Workload):
type = 'SEWorkload'
__metaclass__ = SEWorkloadMeta

I have the same syntax error because I am running the gem5-gcn docker, and
I have both python2 and python3 installed. But I don't really know how to
fix it, it seems python2 is used sometimes.

Jieming

On Thu, Oct 8, 2020 at 7:43 PM Bobby Bruce via gem5-dev 
wrote:

> Hey Matt,
>
> Before the nightly tests were run on Jenkins server which was an Ubuntu
> 18.04 machine with Python2.
>
> The nightly tests will now run using our Ubuntu 20.04 docker image:
> gcr.io/gem5-test/ubuntu-20.04_all-dependencies (Dockerfile source:
> https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/util/dockerfiles/ubuntu-20.04_all-dependencies/Dockerfile).
>
>
> So, to compile gem5.opt for the ARM ISA, the nightly will use:
>
> ```
> docker run -u $UID:$GID --volume $(pwd):$(pwd) -w $(pwd) --rm
> gcr.io/gem5-test/ubuntu-20.04_all-dependencies scons build/ARM/gem5.opt
> ```
>
> I'm going to guess you probably still have Python2 somewhere on your
> machine and it's using it during the compilation. I'll setup some tests on
> my end and see if I can recreate this problem. I _think_ right now we only
> test in environments that either have only Python2 or have only Python3, so
> we should probably have some tests to check what happens if someone has
> both.
>
> Kind regards,
> Bobby
> --
> Dr. Bobby R. Bruce
> Room 2235,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
> web: https://www.bobbybruce.net
>
>
> On Thu, Oct 8, 2020 at 4:10 PM Poremba, Matthew 
> wrote:
>
>> [AMD Public Use]
>>
>>
>>
>> Hi Bobby,
>>
>>
>>
>>
>>
>> What is/was the fix for this issue? I also cannot build even though I
>> have python 3.6 installed (via apt-get on Ubuntu 20.04).  I am manually
>> passing python3-config to scons but I’m getting a syntax error when it sees
>> the metaclass keyword.
>>
>>
>>
>>
>>
>> -Matt
>>
>>
>>
>> *From:* Bobby Bruce via gem5-dev 
>> *Sent:* Thursday, October 8, 2020 3:19 PM
>> *To:* gem5 Developer List 
>> *Cc:* Bobby Bruce 
>> *Subject:* [gem5-dev] Re: Build failed in Jenkins: Nightly #91
>>
>>
>>
>> [CAUTION: External Email]
>>
>> Hey all,
>>
>>
>>
>> The source of this issue is that our Jenkin's server was using Python2,
>> and a commit was merged which utilized some Python3 exclusive features:
>> https://gem5-review.googlesource.com/c/public/gem5/+/33900
>> 
>>
>>
>>
>> We are going to drop support for Python2 in the next release, so I've
>> upgraded our nightly tests to use Python3. They should pass tonight.
>>
>>
>>
>> I'm unsure if this has been officially announced in any capacity, but as
>> we're dropping Python2 support in the next release, you may submit patches
>> containing Python3 code without any requirement of providing some Python2
>> backwards compatibility.
>>
>>
>>
>> The compilation tests also failed as we're using Python2 there as well.
>> I'm currently working on a fix for these tests.
>>
>>
>>
>> Kind regards,
>>
>> Bobby
>>
>> --
>>
>> Dr. Bobby R. Bruce
>> Room 2235,
>> Kemper Hall, UC Davis
>> Davis,
>> CA, 95616
>>
>>
>>
>> web: https://www.bobbybruce.net
>> 
>>
>>
>>
>>
>>
>> On Wed, Oct 7, 2020 at 11:49 PM jenkins-no-reply--- via gem5-dev <
>> gem5-dev@gem5.org> wrote:
>>
>> See <
>> https://jenkins.gem5.org/job/Nightly/91/display/redirect?page=changes
>> 
>> >
>>
>> Changes:
>>
>> [giacomo.travaglini] arch: Add generic BaseMMU
>>
>> [giacomo.travaglini] fastmodel: Add IrisMMU model
>>
>> [gabeblack] sim: Add a mechanism for finding an compatible SE workload.
>>
>> [gabeblack] sparc: Clean up some code in base.isa.
>>
>> [gabeblack] sparc: Simplify the IntOp format slightly.
>>
>>
>> --
>> [...truncated 47.05 KB...]
>>  [SO PyBind] QoSMemSinkInterface ->
>> NULL/python/_m5/param_QoSMemSinkInterface.cc
>>  [ CXX] NULL/python/_m5/param_QoSMemSinkInterface.cc -> .o
>>  [SO PyBind] QoSPolicy -> NULL/python/_m5/param_QoSPolicy.cc
>>  [ CXX] NULL/python/_m5/param_QoSPolicy.cc -> .o
>>  [SO PyBind] 

[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: additional WriteMask methods

[Gerrit]

Tiago Mück has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31257 )


Change subject: mem-ruby: additional WriteMask methods
..

mem-ruby: additional WriteMask methods

Change-Id: Ib5d5f892075b38f46d1d802c043853f56e19ea12
Signed-off-by: Tiago Mück 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31257
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/mem/ruby/common/WriteMask.hh
M src/mem/ruby/protocol/RubySlicc_Exports.sm
2 files changed, 51 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/ruby/common/WriteMask.hh  
b/src/mem/ruby/common/WriteMask.hh

index 6a0a041..6e3ea29 100644
--- a/src/mem/ruby/common/WriteMask.hh
+++ b/src/mem/ruby/common/WriteMask.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2012-15 Advanced Micro Devices, Inc.
  * All rights reserved.
  *
@@ -69,18 +81,18 @@
 }

 bool
-test(int offset)
+test(int offset) const
 {
 assert(offset < mSize);
 return mMask[offset];
 }

 void
-setMask(int offset, int len)
+setMask(int offset, int len, bool val = true)
 {
 assert(mSize >= (offset + len));
 for (int i = 0; i < len; i++) {
-mMask[offset + i] = true;
+mMask[offset + i] = val;
 }
 }
 void
@@ -163,6 +175,33 @@
 }
 }

+void
+setInvertedMask(const WriteMask & writeMask)
+{
+assert(mSize == writeMask.mSize);
+for (int i = 0; i < mSize; i++) {
+mMask[i] = !writeMask.mMask.at(i);
+}
+}
+
+int
+firstBitSet(bool val, int offset = 0) const
+{
+for (int i = offset; i < mSize; ++i)
+if (mMask[i] == val)
+return i;
+return mSize;
+}
+
+int
+count(int offset = 0) const
+{
+int count = 0;
+for (int i = offset; i < mSize; ++i)
+count += mMask[i];
+return count;
+}
+
 void print(std::ostream& out) const;

 void
diff --git a/src/mem/ruby/protocol/RubySlicc_Exports.sm  
b/src/mem/ruby/protocol/RubySlicc_Exports.sm

index ea61350..1b67dc6 100644
--- a/src/mem/ruby/protocol/RubySlicc_Exports.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Exports.sm
@@ -58,7 +58,16 @@
   bool isFull();
   bool isOverlap(WriteMask);
   void orMask(WriteMask);
+  void setInvertedMask(WriteMask);
   void fillMask();
+  void setMask(int,int);
+  bool getMask(int,int);
+  void setMask(int,int,bool);
+  int firstBitSet(bool);
+  int firstBitSet(bool,int);
+  int count();
+  int count(int);
+  bool test(int);
 }

 structure(DataBlock, external = "yes", desc="..."){

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib5d5f892075b38f46d1d802c043853f56e19ea12
Gerrit-Change-Number: 31257
Gerrit-PatchSet: 4
Gerrit-Owner: Tiago Mück 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: Tiago Mück 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Allow same-cycle enqueue

[Gerrit]

Tiago Mück has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31255 )


Change subject: mem-ruby: Allow same-cycle enqueue
..

mem-ruby: Allow same-cycle enqueue

Messages may be enqueued and be ready in the same cycle.

Using this feature may introduce nondeterminism in the protocol and
should be used in specific cases. A case study is to avoid needing an
additional cycle for internal protocol triggers (e.g. the All_Acks
event in src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm).
To mitigate modeling mistakes, the 'allow_zero_latency' parameter must
be set for a MessageBuffer where this behavior is acceptable.

This changes also updates the Consumer to schedule events according to
this new behavior. The original implementation would not schedule a new
wakeup event if the wakeup for the Consumer had already been executed
in that cycle.

Additional authors:
- Tuan Ta 

Change-Id: Ib194e7b4b4ee4b06da1baea17c0eb743f650dfdd
Signed-off-by: Tiago Mück 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31255
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/mem/ruby/common/Consumer.cc
M src/mem/ruby/common/Consumer.hh
M src/mem/ruby/network/MessageBuffer.cc
M src/mem/ruby/network/MessageBuffer.hh
M src/mem/ruby/network/MessageBuffer.py
5 files changed, 92 insertions(+), 29 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/ruby/common/Consumer.cc  
b/src/mem/ruby/common/Consumer.cc

index f68ee14..d5db717 100644
--- a/src/mem/ruby/common/Consumer.cc
+++ b/src/mem/ruby/common/Consumer.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2012 Mark D. Hill and David A. Wood
  * All rights reserved.
  *
@@ -30,26 +42,51 @@

 using namespace std;

+Consumer::Consumer(ClockedObject *_em)
+: m_wakeup_event([this]{ processCurrentEvent(); },
+"Consumer Event", false),
+  em(_em)
+{ }
+
 void
 Consumer::scheduleEvent(Cycles timeDelta)
 {
-scheduleEventAbsolute(em->clockEdge(timeDelta));
+m_wakeup_ticks.insert(em->clockEdge(timeDelta));
+scheduleNextWakeup();
 }

 void
 Consumer::scheduleEventAbsolute(Tick evt_time)
 {
-if (!alreadyScheduled(evt_time)) {
-// This wakeup is not redundant
-auto *evt = new EventFunctionWrapper(
-[this]{ wakeup(); }, "Consumer Event", true);
+m_wakeup_ticks.insert(
+divCeil(evt_time, em->clockPeriod()) * em->clockPeriod());
+scheduleNextWakeup();
+}

-em->schedule(evt, evt_time);
-insertScheduledWakeupTime(evt_time);
+void
+Consumer::scheduleNextWakeup()
+{
+// look for the next tick in the future to schedule
+auto it = m_wakeup_ticks.lower_bound(em->clockEdge());
+if (it != m_wakeup_ticks.end()) {
+Tick when = *it;
+assert(when >= em->clockEdge());
+if (m_wakeup_event.scheduled() && (when < m_wakeup_event.when()))
+em->reschedule(m_wakeup_event, when, true);
+else if (!m_wakeup_event.scheduled())
+em->schedule(m_wakeup_event, when);
 }
+}

-Tick t = em->clockEdge();
-set::iterator bit = m_scheduled_wakeups.begin();
-set::iterator eit = m_scheduled_wakeups.lower_bound(t);
-m_scheduled_wakeups.erase(bit,eit);
+void
+Consumer::processCurrentEvent()
+{
+auto curr = m_wakeup_ticks.begin();
+assert(em->clockEdge() == *curr);
+
+// remove the current tick from the wakeup list, wake up, and then  
schedule

+// the next wakeup
+m_wakeup_ticks.erase(curr);
+wakeup();
+scheduleNextWakeup();
 }
diff --git a/src/mem/ruby/common/Consumer.hh  
b/src/mem/ruby/common/Consumer.hh

index 2e18684..2c7065b 100644
--- a/src/mem/ruby/common/Consumer.hh
+++ b/src/mem/ruby/common/Consumer.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * 

[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: MessageBuffer capacity check

[Gerrit]

Tiago Mück has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31254 )


Change subject: mem-ruby: MessageBuffer capacity check
..

mem-ruby: MessageBuffer capacity check

Trip assert if call enqueue on a full message buffer.

Change-Id: I842183d8bf2c681787f1b6ac23c95825095ad05d
Signed-off-by: Tiago Mück 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31254
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Matthew Poremba 
---
M src/mem/ruby/network/MessageBuffer.cc
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Matthew Poremba: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/ruby/network/MessageBuffer.cc  
b/src/mem/ruby/network/MessageBuffer.cc

index 3db8515..fb1d734 100644
--- a/src/mem/ruby/network/MessageBuffer.cc
+++ b/src/mem/ruby/network/MessageBuffer.cc
@@ -225,6 +225,9 @@
 // Increment the number of messages statistic
 m_buf_msgs++;

+assert((m_max_size == 0) ||
+   ((m_prio_heap.size() + m_stall_map_size) <= m_max_size));
+
 DPRINTF(RubyQueue, "Enqueue arrival_time: %lld, Message: %s\n",
 arrival_time, *(message.get()));


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I842183d8bf2c681787f1b6ac23c95825095ad05d
Gerrit-Change-Number: 31254
Gerrit-PatchSet: 4
Gerrit-Owner: Tiago Mück 
Gerrit-Reviewer: Bradford Beckmann 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: Tiago Mück 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: fix include dependency

[Gerrit]

Tiago Mück has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31258 )


Change subject: mem-ruby: fix include dependency
..

mem-ruby: fix include dependency

Removed include dependency between WriteMask and RubySystem.

Change-Id: I3e81267341e3875b1bb0fc3cb39f1a308e383dfd
Signed-off-by: Tiago Mück 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31258
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/mem/ruby/common/WriteMask.cc
M src/mem/ruby/common/WriteMask.hh
M src/mem/ruby/slicc_interface/RubySlicc_Util.hh
3 files changed, 9 insertions(+), 5 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/ruby/common/WriteMask.cc  
b/src/mem/ruby/common/WriteMask.cc

index 4585077..54ba8ff 100644
--- a/src/mem/ruby/common/WriteMask.cc
+++ b/src/mem/ruby/common/WriteMask.cc
@@ -32,6 +32,11 @@

 #include "mem/ruby/system/RubySystem.hh"

+WriteMask::WriteMask()
+: mSize(RubySystem::getBlockSizeBytes()), mMask(mSize, false),
+  mAtomic(false)
+{}
+
 void
 WriteMask::print(std::ostream& out) const
 {
diff --git a/src/mem/ruby/common/WriteMask.hh  
b/src/mem/ruby/common/WriteMask.hh

index 6e3ea29..f1e5f37 100644
--- a/src/mem/ruby/common/WriteMask.hh
+++ b/src/mem/ruby/common/WriteMask.hh
@@ -46,18 +46,16 @@
 #include 
 #include 

+#include "base/amo.hh"
+#include "mem/ruby/common/DataBlock.hh"
 #include "mem/ruby/common/TypeDefines.hh"
-#include "mem/ruby/system/RubySystem.hh"

 class WriteMask
 {
   public:
 typedef std::vector> AtomicOpVector;

-WriteMask()
-  : mSize(RubySystem::getBlockSizeBytes()), mMask(mSize, false),
-mAtomic(false)
-{}
+WriteMask();

 WriteMask(int size)
   : mSize(size), mMask(size, false), mAtomic(false)
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh  
b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh

index 155d134..a5a18ff 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
@@ -55,6 +55,7 @@
 #include "mem/ruby/common/DataBlock.hh"
 #include "mem/ruby/common/TypeDefines.hh"
 #include "mem/ruby/common/WriteMask.hh"
+#include "mem/ruby/protocol/RubyRequestType.hh"

 inline Cycles zero_time() { return Cycles(0); }


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3e81267341e3875b1bb0fc3cb39f1a308e383dfd
Gerrit-Change-Number: 31258
Gerrit-PatchSet: 4
Gerrit-Owner: Tiago Mück 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: Tiago Mück 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Network can use custom data msg size

[Gerrit]

Tiago Mück has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31256 )


Change subject: mem-ruby: Network can use custom data msg size
..

mem-ruby: Network can use custom data msg size

The size for network data messages can be set using a configuration
parameter. This is necessary so line transfers may be split in multiple
messages at the protocol level.

Change-Id: I86a272de597b04a898071db412b921cbe1651ef0
Signed-off-by: Tiago Mück 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31256
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Srikant Bharadwaj 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/mem/ruby/network/Network.cc
M src/mem/ruby/network/Network.hh
M src/mem/ruby/network/Network.py
3 files changed, 10 insertions(+), 7 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Srikant Bharadwaj: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/ruby/network/Network.cc  
b/src/mem/ruby/network/Network.cc

index cda99b1..a676a38 100644
--- a/src/mem/ruby/network/Network.cc
+++ b/src/mem/ruby/network/Network.cc
@@ -55,6 +55,10 @@
 m_virtual_networks = p->number_of_virtual_networks;
 m_control_msg_size = p->control_msg_size;

+fatal_if(p->data_msg_size > p->ruby_system->getBlockSizeBytes(),
+ "%s: data message size > cache line size", name());
+m_data_msg_size = p->data_msg_size + m_control_msg_size;
+
 params()->ruby_system->registerNetwork(this);

 // Populate localNodeVersions with the version of each MachineType in
@@ -150,12 +154,6 @@
 delete m_topology_ptr;
 }

-void
-Network::init()
-{
-m_data_msg_size = RubySystem::getBlockSizeBytes() + m_control_msg_size;
-}
-
 uint32_t
 Network::MessageSizeType_to_int(MessageSizeType size_type)
 {
diff --git a/src/mem/ruby/network/Network.hh  
b/src/mem/ruby/network/Network.hh

index f151aed..371ceb8 100644
--- a/src/mem/ruby/network/Network.hh
+++ b/src/mem/ruby/network/Network.hh
@@ -82,7 +82,6 @@
 { return dynamic_cast(_params); }

 virtual ~Network();
-void init() override;

 static uint32_t getNumberOfVirtualNetworks() { return  
m_virtual_networks; }

 int getNumNodes() const { return m_nodes; }
diff --git a/src/mem/ruby/network/Network.py  
b/src/mem/ruby/network/Network.py

index 8999ff1..5febaad 100644
--- a/src/mem/ruby/network/Network.py
+++ b/src/mem/ruby/network/Network.py
@@ -25,6 +25,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 from m5.params import *
+from m5.proxy import *
 from m5.objects.ClockedObject import ClockedObject
 from m5.objects.BasicLink import BasicLink

@@ -53,3 +54,8 @@
 slave = DeprecatedParam(in_port, '`slave` is now called `in_port`')
 out_port = VectorRequestPort("CPU output port")
 master = DeprecatedParam(out_port, '`master` is now called `out_port`')
+
+data_msg_size = Param.Int(Parent.block_size_bytes,
+"Size of data messages. Defaults to the  
parent "

+"RubySystem cache line size.")
+

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I86a272de597b04a898071db412b921cbe1651ef0
Gerrit-Change-Number: 31256
Gerrit-PatchSet: 4
Gerrit-Owner: Tiago Mück 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Srikant Bharadwaj 
Gerrit-Reviewer: Tiago Mück 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Bradford Beckmann 
Gerrit-CC: Matthew Poremba 
Gerrit-MessageType: merged
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[gem5-dev] Re: Build failed in Jenkins: Nightly #91

[Bobby Bruce via gem5-dev]

Hey Matt,

Before the nightly tests were run on Jenkins server which was an Ubuntu
18.04 machine with Python2.

The nightly tests will now run using our Ubuntu 20.04 docker image:
gcr.io/gem5-test/ubuntu-20.04_all-dependencies (Dockerfile source:
https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/util/dockerfiles/ubuntu-20.04_all-dependencies/Dockerfile).


So, to compile gem5.opt for the ARM ISA, the nightly will use:

```
docker run -u $UID:$GID --volume $(pwd):$(pwd) -w $(pwd) --rm
gcr.io/gem5-test/ubuntu-20.04_all-dependencies scons build/ARM/gem5.opt
```

I'm going to guess you probably still have Python2 somewhere on your
machine and it's using it during the compilation. I'll setup some tests on
my end and see if I can recreate this problem. I _think_ right now we only
test in environments that either have only Python2 or have only Python3, so
we should probably have some tests to check what happens if someone has
both.

Kind regards,
Bobby
--
Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Thu, Oct 8, 2020 at 4:10 PM Poremba, Matthew 
wrote:

> [AMD Public Use]
>
>
>
> Hi Bobby,
>
>
>
>
>
> What is/was the fix for this issue? I also cannot build even though I have
> python 3.6 installed (via apt-get on Ubuntu 20.04).  I am manually passing
> python3-config to scons but I’m getting a syntax error when it sees the
> metaclass keyword.
>
>
>
>
>
> -Matt
>
>
>
> *From:* Bobby Bruce via gem5-dev 
> *Sent:* Thursday, October 8, 2020 3:19 PM
> *To:* gem5 Developer List 
> *Cc:* Bobby Bruce 
> *Subject:* [gem5-dev] Re: Build failed in Jenkins: Nightly #91
>
>
>
> [CAUTION: External Email]
>
> Hey all,
>
>
>
> The source of this issue is that our Jenkin's server was using Python2,
> and a commit was merged which utilized some Python3 exclusive features:
> https://gem5-review.googlesource.com/c/public/gem5/+/33900
> 
>
>
>
> We are going to drop support for Python2 in the next release, so I've
> upgraded our nightly tests to use Python3. They should pass tonight.
>
>
>
> I'm unsure if this has been officially announced in any capacity, but as
> we're dropping Python2 support in the next release, you may submit patches
> containing Python3 code without any requirement of providing some Python2
> backwards compatibility.
>
>
>
> The compilation tests also failed as we're using Python2 there as well.
> I'm currently working on a fix for these tests.
>
>
>
> Kind regards,
>
> Bobby
>
> --
>
> Dr. Bobby R. Bruce
> Room 2235,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
>
>
> web: https://www.bobbybruce.net
> 
>
>
>
>
>
> On Wed, Oct 7, 2020 at 11:49 PM jenkins-no-reply--- via gem5-dev <
> gem5-dev@gem5.org> wrote:
>
> See  
> >
>
> Changes:
>
> [giacomo.travaglini] arch: Add generic BaseMMU
>
> [giacomo.travaglini] fastmodel: Add IrisMMU model
>
> [gabeblack] sim: Add a mechanism for finding an compatible SE workload.
>
> [gabeblack] sparc: Clean up some code in base.isa.
>
> [gabeblack] sparc: Simplify the IntOp format slightly.
>
>
> --
> [...truncated 47.05 KB...]
>  [SO PyBind] QoSMemSinkInterface ->
> NULL/python/_m5/param_QoSMemSinkInterface.cc
>  [ CXX] NULL/python/_m5/param_QoSMemSinkInterface.cc -> .o
>  [SO PyBind] QoSPolicy -> NULL/python/_m5/param_QoSPolicy.cc
>  [ CXX] NULL/python/_m5/param_QoSPolicy.cc -> .o
>  [SO PyBind] QoSPropFairPolicy ->
> NULL/python/_m5/param_QoSPropFairPolicy.cc
>  [SO PARAM] QoSPropFairPolicy -> NULL/params/QoSPropFairPolicy.hh
>  [ CXX] NULL/python/_m5/param_QoSPropFairPolicy.cc -> .o
>  [SO PyBind] QoSTurnaroundPolicy ->
> NULL/python/_m5/param_QoSTurnaroundPolicy.cc
>  [ CXX] NULL/python/_m5/param_QoSTurnaroundPolicy.cc -> .o
>  [SO PyBind] QoSTurnaroundPolicyIdeal ->
> NULL/python/_m5/param_QoSTurnaroundPolicyIdeal.cc
>  [SO PARAM] QoSTurnaroundPolicyIdeal ->
> NULL/params/QoSTurnaroundPolicyIdeal.hh
>  [ CXX] NULL/python/_m5/param_QoSTurnaroundPolicyIdeal.cc -> 

[gem5-dev] Re: Build failed in Jenkins: Nightly #91

[Poremba, Matthew via gem5-dev]

[AMD Public Use]

Hi Bobby,


What is/was the fix for this issue? I also cannot build even though I have 
python 3.6 installed (via apt-get on Ubuntu 20.04).  I am manually passing 
python3-config to scons but I'm getting a syntax error when it sees the 
metaclass keyword.


-Matt

From: Bobby Bruce via gem5-dev 
Sent: Thursday, October 8, 2020 3:19 PM
To: gem5 Developer List 
Cc: Bobby Bruce 
Subject: [gem5-dev] Re: Build failed in Jenkins: Nightly #91

[CAUTION: External Email]
Hey all,

The source of this issue is that our Jenkin's server was using Python2, and a 
commit was merged which utilized some Python3 exclusive features: 
https://gem5-review.googlesource.com/c/public/gem5/+/33900

We are going to drop support for Python2 in the next release, so I've upgraded 
our nightly tests to use Python3. They should pass tonight.

I'm unsure if this has been officially announced in any capacity, but as we're 
dropping Python2 support in the next release, you may submit patches containing 
Python3 code without any requirement of providing some Python2 backwards 
compatibility.

The compilation tests also failed as we're using Python2 there as well. I'm 
currently working on a fix for these tests.

Kind regards,
Bobby
--
Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: 
https://www.bobbybruce.net


On Wed, Oct 7, 2020 at 11:49 PM jenkins-no-reply--- via gem5-dev 
mailto:gem5-dev@gem5.org>> wrote:
See 
>

Changes:

[giacomo.travaglini] arch: Add generic BaseMMU

[giacomo.travaglini] fastmodel: Add IrisMMU model

[gabeblack] sim: Add a mechanism for finding an compatible SE workload.

[gabeblack] sparc: Clean up some code in base.isa.

[gabeblack] sparc: Simplify the IntOp format slightly.


--
[...truncated 47.05 KB...]
 [SO PyBind] QoSMemSinkInterface -> NULL/python/_m5/param_QoSMemSinkInterface.cc
 [ CXX] NULL/python/_m5/param_QoSMemSinkInterface.cc -> .o
 [SO PyBind] QoSPolicy -> NULL/python/_m5/param_QoSPolicy.cc
 [ CXX] NULL/python/_m5/param_QoSPolicy.cc -> .o
 [SO PyBind] QoSPropFairPolicy -> NULL/python/_m5/param_QoSPropFairPolicy.cc
 [SO PARAM] QoSPropFairPolicy -> NULL/params/QoSPropFairPolicy.hh
 [ CXX] NULL/python/_m5/param_QoSPropFairPolicy.cc -> .o
 [SO PyBind] QoSTurnaroundPolicy -> NULL/python/_m5/param_QoSTurnaroundPolicy.cc
 [ CXX] NULL/python/_m5/param_QoSTurnaroundPolicy.cc -> .o
 [SO PyBind] QoSTurnaroundPolicyIdeal -> 
NULL/python/_m5/param_QoSTurnaroundPolicyIdeal.cc
 [SO PARAM] QoSTurnaroundPolicyIdeal -> NULL/params/QoSTurnaroundPolicyIdeal.hh
 [ CXX] NULL/python/_m5/param_QoSTurnaroundPolicyIdeal.cc -> .o
 [SO PyBind] QueuedPrefetcher -> NULL/python/_m5/param_QueuedPrefetcher.cc
 [ CXX] NULL/python/_m5/param_QueuedPrefetcher.cc -> .o
 [SO PyBind] RandomRP -> NULL/python/_m5/param_RandomRP.cc
 [SO PARAM] RandomRP -> NULL/params/RandomRP.hh
 [ CXX] NULL/python/_m5/param_RandomRP.cc -> .o
 [SO PyBind] RangeAddrMapper -> NULL/python/_m5/param_RangeAddrMapper.cc
 [ CXX] NULL/python/_m5/param_RangeAddrMapper.cc -> .o
 [SO PyBind] RedirectPath -> NULL/python/_m5/param_RedirectPath.cc
 [ CXX] NULL/python/_m5/param_RedirectPath.cc -> .o
 [SO PyBind] RepeatedQwordsCompressor -> 
NULL/python/_m5/param_RepeatedQwordsCompressor.cc
 [SO PARAM] RepeatedQwordsCompressor -> NULL/params/RepeatedQwordsCompressor.hh
 [ CXX] NULL/python/_m5/param_RepeatedQwordsCompressor.cc -> .o
 [SO PyBind] Root -> NULL/python/_m5/param_Root.cc
 [SO PARAM] Root -> NULL/params/Root.hh
 [ CXX] NULL/python/_m5/param_Root.cc -> .o
 [SO PyBind] RubyCache -> NULL/python/_m5/param_RubyCache.cc
 [ CXX] NULL/python/_m5/param_RubyCache.cc -> .o
 [SO PyBind] RubyController -> NULL/python/_m5/param_RubyController.cc
 [ CXX] NULL/python/_m5/param_RubyController.cc -> .o
 [SO PyBind] RubyDirectedTester -> NULL/python/_m5/param_RubyDirectedTester.cc
 [ CXX] NULL/python/_m5/param_RubyDirectedTester.cc -> .o
 [SO PyBind] RubyDirectoryMemory -> 

[gem5-dev] Re: Build failed in Jenkins: Nightly #91

[Bobby Bruce via gem5-dev]

Hey all,

The source of this issue is that our Jenkin's server was using Python2, and
a commit was merged which utilized some Python3 exclusive features:
https://gem5-review.googlesource.com/c/public/gem5/+/33900

We are going to drop support for Python2 in the next release, so I've
upgraded our nightly tests to use Python3. They should pass tonight.

I'm unsure if this has been officially announced in any capacity, but as
we're dropping Python2 support in the next release, you may submit patches
containing Python3 code without any requirement of providing some Python2
backwards compatibility.

The compilation tests also failed as we're using Python2 there as well. I'm
currently working on a fix for these tests.

Kind regards,
Bobby
--
Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Wed, Oct 7, 2020 at 11:49 PM jenkins-no-reply--- via gem5-dev <
gem5-dev@gem5.org> wrote:

> See  >
>
> Changes:
>
> [giacomo.travaglini] arch: Add generic BaseMMU
>
> [giacomo.travaglini] fastmodel: Add IrisMMU model
>
> [gabeblack] sim: Add a mechanism for finding an compatible SE workload.
>
> [gabeblack] sparc: Clean up some code in base.isa.
>
> [gabeblack] sparc: Simplify the IntOp format slightly.
>
>
> --
> [...truncated 47.05 KB...]
>  [SO PyBind] QoSMemSinkInterface ->
> NULL/python/_m5/param_QoSMemSinkInterface.cc
>  [ CXX] NULL/python/_m5/param_QoSMemSinkInterface.cc -> .o
>  [SO PyBind] QoSPolicy -> NULL/python/_m5/param_QoSPolicy.cc
>  [ CXX] NULL/python/_m5/param_QoSPolicy.cc -> .o
>  [SO PyBind] QoSPropFairPolicy ->
> NULL/python/_m5/param_QoSPropFairPolicy.cc
>  [SO PARAM] QoSPropFairPolicy -> NULL/params/QoSPropFairPolicy.hh
>  [ CXX] NULL/python/_m5/param_QoSPropFairPolicy.cc -> .o
>  [SO PyBind] QoSTurnaroundPolicy ->
> NULL/python/_m5/param_QoSTurnaroundPolicy.cc
>  [ CXX] NULL/python/_m5/param_QoSTurnaroundPolicy.cc -> .o
>  [SO PyBind] QoSTurnaroundPolicyIdeal ->
> NULL/python/_m5/param_QoSTurnaroundPolicyIdeal.cc
>  [SO PARAM] QoSTurnaroundPolicyIdeal ->
> NULL/params/QoSTurnaroundPolicyIdeal.hh
>  [ CXX] NULL/python/_m5/param_QoSTurnaroundPolicyIdeal.cc -> .o
>  [SO PyBind] QueuedPrefetcher -> NULL/python/_m5/param_QueuedPrefetcher.cc
>  [ CXX] NULL/python/_m5/param_QueuedPrefetcher.cc -> .o
>  [SO PyBind] RandomRP -> NULL/python/_m5/param_RandomRP.cc
>  [SO PARAM] RandomRP -> NULL/params/RandomRP.hh
>  [ CXX] NULL/python/_m5/param_RandomRP.cc -> .o
>  [SO PyBind] RangeAddrMapper -> NULL/python/_m5/param_RangeAddrMapper.cc
>  [ CXX] NULL/python/_m5/param_RangeAddrMapper.cc -> .o
>  [SO PyBind] RedirectPath -> NULL/python/_m5/param_RedirectPath.cc
>  [ CXX] NULL/python/_m5/param_RedirectPath.cc -> .o
>  [SO PyBind] RepeatedQwordsCompressor ->
> NULL/python/_m5/param_RepeatedQwordsCompressor.cc
>  [SO PARAM] RepeatedQwordsCompressor ->
> NULL/params/RepeatedQwordsCompressor.hh
>  [ CXX] NULL/python/_m5/param_RepeatedQwordsCompressor.cc -> .o
>  [SO PyBind] Root -> NULL/python/_m5/param_Root.cc
>  [SO PARAM] Root -> NULL/params/Root.hh
>  [ CXX] NULL/python/_m5/param_Root.cc -> .o
>  [SO PyBind] RubyCache -> NULL/python/_m5/param_RubyCache.cc
>  [ CXX] NULL/python/_m5/param_RubyCache.cc -> .o
>  [SO PyBind] RubyController -> NULL/python/_m5/param_RubyController.cc
>  [ CXX] NULL/python/_m5/param_RubyController.cc -> .o
>  [SO PyBind] RubyDirectedTester ->
> NULL/python/_m5/param_RubyDirectedTester.cc
>  [ CXX] NULL/python/_m5/param_RubyDirectedTester.cc -> .o
>  [SO PyBind] RubyDirectoryMemory ->
> NULL/python/_m5/param_RubyDirectoryMemory.cc
>  [ CXX] NULL/python/_m5/param_RubyDirectoryMemory.cc -> .o
>  [SO PyBind] RubyHTMSequencer -> NULL/python/_m5/param_RubyHTMSequencer.cc
>  [ CXX] NULL/python/_m5/param_RubyHTMSequencer.cc -> .o
>  [SO PyBind] RubyNetwork -> NULL/python/_m5/param_RubyNetwork.cc
>  [ CXX] NULL/python/_m5/param_RubyNetwork.cc -> .o
>  [SO PyBind] RubyPort -> NULL/python/_m5/param_RubyPort.cc
>  [ CXX] NULL/python/_m5/param_RubyPort.cc -> .o
>  [SO PyBind] RubyPortProxy -> NULL/python/_m5/param_RubyPortProxy.cc
>  [SO PARAM] RubyPortProxy -> NULL/params/RubyPortProxy.hh
>  [ CXX] NULL/python/_m5/param_RubyPortProxy.cc -> .o
>  [SO PyBind] RubyPrefetcher -> NULL/python/_m5/param_RubyPrefetcher.cc
>  [ CXX] NULL/python/_m5/param_RubyPrefetcher.cc -> .o
>  [SO PyBind] RubySequencer -> NULL/python/_m5/param_RubySequencer.cc
>  [ CXX] NULL/python/_m5/param_RubySequencer.cc -> .o
>  [SO PyBind] RubySystem -> NULL/python/_m5/param_RubySystem.cc
>  [ CXX] NULL/python/_m5/param_RubySystem.cc -> .o
>  [SO PyBind] RubyTester -> NULL/python/_m5/param_RubyTester.cc
>  [SO PARAM] RubyTester -> NULL/params/RubyTester.hh
>  [ CXX] NULL/python/_m5/param_RubyTester.cc -> .o
>  [SO PyBind] RubyWireBuffer -> NULL/python/_m5/param_RubyWireBuffer.cc

[gem5-dev] Build failed in Jenkins: Compiler-Checks #27

[jenkins-no-reply--- via gem5-dev]

See 


Changes:

[matthew.poremba] configs: Set kvm_map in DRAMInterface in Ruby.py

[gabeblack] mem: When loading an image directly in memory, use the right CL 
size.

[nikos.nikoleris] mem: Fix some reference use in range loops

[giacomo.travaglini] cpu: Allow storing an invalid HTM checkpoint

[giacomo.travaglini] arch-arm: Instantiate a single HTM checkpoint at 
ISA::startup

[Bobby R. Bruce] python: Flush the simulation stdout/stderr buffers

[Bobby R. Bruce] scons,python: Prioritize Python3 for PYTHON_CONFIG

[Bobby R. Bruce] scons,python: Add python2-config to PYTHON_CONFIG

[Bobby R. Bruce] tests: Removing gem5/hello_se/ref/simerr

[Bobby R. Bruce] scons,python: Add warning for when python3-config is not used

[Bobby R. Bruce] tests,misc: Updated TestLib and boot-tests for gzipped imgs

[giacomo.travaglini] arch: Do value-initialization for MemOperand

[giacomo.travaglini] arch: Add raw read/writeMem helpers

[giacomo.travaglini] arch-arm: Using new "raw" memhelpers

[giacomo.travaglini] arch-x86: Add byteEnable mask in x86 memhelpers

[giacomo.travaglini] cpu: Never use a empty byteEnable

[matthew.poremba] configs: Fix typo in apu_se.py

[matthew.poremba] configs,gpu-compute: Fixes to connect gmTokenPort

[matthew.poremba] mem-ruby: Fixing token port responses in GPUCoalescer

[Bobby R. Bruce] ext: Disable range-loop-analysis warnings for pybind11

[Bobby R. Bruce] sim: Adding missing argument of panic function

[Jason Lowe-Power] misc: Add release notes for 20.1

[Bobby R. Bruce] misc: Updated CONTRIBUTING.md: 'master' -> 'stable'

[Bobby R. Bruce] scons: Removed -Werror for the gem5 20.1 release

[Bobby R. Bruce] misc: Updated version to 20.1.0.0

[gabeblack] misc: Re-add -Werror for the gem5 20.2 development

[gabeblack] base: Add some error handling to compiler.hh.

[Bobby R. Bruce] misc: Changed gem5 version info for gem5 20.2 dev

[shunhsingou] scons: avoid interactive access in non-tty

[shunhsingou] scons: only wrap message with positive value

[odanrc] mem-cache: Protect tag from being mishandled

[odanrc] mem-cache: Encapsulate CacheBlk's task_id

[odanrc] mem-cache: Encapsulate CacheBlk's refCount

[odanrc] mem-cache: Encapsulate CacheBlk's tickInserted

[odanrc] mem-cache: Encapsulate CacheBlk's srcRequestorId

[pierre.ayoub.pro] arch-arm: Add recursion for DTB entry generation inside 
ArmISA

[pierre.ayoub.pro] cpu: Add recursion for DTB entry generation inside BaseCPU

[hoanguyen] arch-arm: Replace call to `tmpnam()` by a deterministic one


--
Started by timer
Running as SYSTEM
Building in workspace 
The recommended git tool is: git
No credentials specified
 > git rev-parse --is-inside-work-tree # timeout=10
Fetching changes from the remote Git repository
 > git config remote.origin.url https://gem5.googlesource.com/public/gem5 # 
 > timeout=10
Fetching upstream changes from https://gem5.googlesource.com/public/gem5
 > git --version # timeout=10
 > git --version # 'git version 2.25.1'
 > git fetch --tags --force --progress -- 
 > https://gem5.googlesource.com/public/gem5 
 > +refs/heads/*:refs/remotes/origin/* # timeout=10
 > git rev-parse refs/remotes/origin/develop^{commit} # timeout=10
 > git rev-parse refs/remotes/origin/origin/develop^{commit} # timeout=10
Checking out Revision e504ce6bc65aa3a4ab06eca1b2c8ec9e435b6561 
(refs/remotes/origin/develop)
 > git config core.sparsecheckout # timeout=10
 > git checkout -f e504ce6bc65aa3a4ab06eca1b2c8ec9e435b6561 # timeout=10
Commit message: "arch-arm: Replace call to `tmpnam()` by a deterministic one"
 > git rev-list --no-walk ba197c116368bbab05af6d636ab24cb65c73b291 # timeout=10
[Compiler-Checks] $ /bin/sh -xe /tmp/jenkins5992155312626752916.sh
+ ./util/compiler-tests.sh -j 4
Starting build tests with 'gcc-version-10'...
'gcc-version-10' was found in the comprehensive tests. All ISAs will be built.
  * Building target 'POWER.opt' with 'gcc-version-10'...
Done.
  * Building target 'POWER.fast' with 'gcc-version-10'...
Done.
  * Building target 'NULL_MOESI_CMP_directory.opt' with 'gcc-version-10'...
Done.
  * Building target 'NULL_MOESI_CMP_directory.fast' with 'gcc-version-10'...
Done.
  * Building target 'NULL_MESI_Two_Level.opt' with 'gcc-version-10'...
Done.
  * Building target 'NULL_MESI_Two_Level.fast' with 'gcc-version-10'...
Done.
  * Building target 'X86_MOESI_AMD_Base.opt' with 'gcc-version-10'...
Done.
  * Building target 'X86_MOESI_AMD_Base.fast' with 'gcc-version-10'...
Done.
  * Building target 'ARM_MESI_Three_Level.opt' with 'gcc-version-10'...
Done.
  * Building target 'ARM_MESI_Three_Level.fast' with 'gcc-version-10'...
Done.
  * Building target 'ARM.opt' with 'gcc-version-10'...
Done.
  * Building target 'ARM.fast' with 'gcc-version-10'...
Done.
  * Building target 'RISCV.opt' with 'gcc-version-10'...

[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Create a tagged entry class

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35698 )


Change subject: mem-cache: Create a tagged entry class
..

mem-cache: Create a tagged entry class

The TaggedEntry class inherits from the ReplaceableEntry
class. Its purpose is to define a replaceable entry with
tagging attributes.

It has been created as a separate class because both the
replacement policies and the AbstractCacheEntry use
ReplaceableEntry, and do not need the tagging information
to perform their operations.

Change-Id: I24e87c865fc21c79dea7e488507a8cafc5223b39
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35698
Reviewed-by: Nikos Nikoleris 
Maintainer: Nikos Nikoleris 
Tested-by: kokoro 
---
M src/mem/cache/cache_blk.cc
M src/mem/cache/cache_blk.hh
M src/mem/cache/prefetch/associative_set.hh
M src/mem/cache/prefetch/associative_set_impl.hh
M src/mem/cache/tags/sector_blk.cc
M src/mem/cache/tags/sector_blk.hh
A src/mem/cache/tags/tagged_entry.hh
7 files changed, 190 insertions(+), 321 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/cache/cache_blk.cc b/src/mem/cache/cache_blk.cc
index 01b71c5..b747f39 100644
--- a/src/mem/cache/cache_blk.cc
+++ b/src/mem/cache/cache_blk.cc
@@ -43,12 +43,6 @@

 #include "base/cprintf.hh"

-bool
-CacheBlk::matchTag(Addr tag, bool is_secure) const
-{
-return isValid() && (getTag() == tag) && (isSecure() == is_secure);
-}
-
 void
 CacheBlk::insert(const Addr tag, const bool is_secure,
  const int src_requestor_ID, const uint32_t task_ID)
@@ -56,8 +50,7 @@
 // Make sure that the block has been properly invalidated
 assert(status == 0);

-// Set block tag
-setTag(tag);
+insert(tag, is_secure);

 // Set source requestor ID
 setSrcRequestorId(src_requestor_ID);
@@ -70,14 +63,6 @@

 // Insertion counts as a reference to the block
 increaseRefCount();
-
-// Set secure state
-if (is_secure) {
-setSecure();
-}
-
-// Validate block
-setValid();
 }

 void
diff --git a/src/mem/cache/cache_blk.hh b/src/mem/cache/cache_blk.hh
index 0ad355c..b0d45af 100644
--- a/src/mem/cache/cache_blk.hh
+++ b/src/mem/cache/cache_blk.hh
@@ -54,7 +54,7 @@

 #include "base/printable.hh"
 #include "base/types.hh"
-#include "mem/cache/replacement_policies/base.hh"
+#include "mem/cache/tags/tagged_entry.hh"
 #include "mem/packet.hh"
 #include "mem/request.hh"
 #include "sim/core.hh"
@@ -63,8 +63,6 @@
  * Cache block status bit assignments
  */
 enum CacheBlkStatusBits : unsigned {
-/** valid, readable */
-BlkValid =  0x01,
 /** write permission */
 BlkWritable =   0x02,
 /** read permission (yes, block can be valid but not readable) */
@@ -73,17 +71,16 @@
 BlkDirty =  0x08,
 /** block was a hardware prefetch yet unaccessed*/
 BlkHWPrefetched =   0x20,
-/** block holds data from the secure memory space */
-BlkSecure = 0x40,
 /** block holds compressed data */
 BlkCompressed = 0x80
 };

 /**
  * A Basic Cache block.
- * Contains the tag, status, and a pointer to data.
+ * Contains information regarding its coherence, prefetching and  
compression

+ * status, as well as a pointer to its data.
  */
-class CacheBlk : public ReplaceableEntry
+class CacheBlk : public TaggedEntry
 {
   public:
 /**
@@ -150,7 +147,7 @@
 std::list lockList;

   public:
-CacheBlk() : data(nullptr), _tickInserted(0)
+CacheBlk() : TaggedEntry(), data(nullptr), _tickInserted(0)
 {
 invalidate();
 }
@@ -163,11 +160,7 @@
  * Checks the write permissions of this block.
  * @return True if the block is writable.
  */
-bool isWritable() const
-{
-const State needed_bits = BlkWritable | BlkValid;
-return (status & needed_bits) == needed_bits;
-}
+bool isWritable() const { return isValid() && (status & BlkWritable); }

 /**
  * Checks the read permissions of this block.  Note that a block
@@ -175,27 +168,14 @@
  * upgrade miss.
  * @return True if the block is readable.
  */
-bool isReadable() const
-{
-const State needed_bits = BlkReadable | BlkValid;
-return (status & needed_bits) == needed_bits;
-}
-
-/**
- * Checks that a block is valid.
- * @return True if the block is valid.
- */
-bool isValid() const
-{
-return (status & BlkValid) != 0;
-}
+bool isReadable() const { return isValid() && (status & BlkReadable); }

 /**
  * Invalidate the block and clear all state.
  */
 virtual void invalidate()
 {
-setTag(MaxAddr);
+TaggedEntry::invalidate();
 setTaskId(ContextSwitchTaskId::Unknown);
 status = 0;
 whenReady = 

[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Encapsulate CacheBlk's status

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34960 )


Change subject: mem-cache: Encapsulate CacheBlk's status
..

mem-cache: Encapsulate CacheBlk's status

Encapsulate this variable to facilitate polymorphism.

- The status enum was renamed to CoherenceBits, since it
  lists the coherence bits supported by the CacheBlk.
- status was made protected and renamed to coherence since
  it contains the coherence bits.
- Functions to set, clear and get the coherence bits were
  created.
- To set a status bit, the block must be validated first.
  This guarantees a constant flow and helps catching bugs.

As a side effect, some of the modified files contained long
lines, which had to be split.

Change-Id: I558cc51ac685d30b6bf298c78f86a6e24ff06973
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34960
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Nikos Nikoleris 
Maintainer: Jason Lowe-Power 
Maintainer: Nikos Nikoleris 
Tested-by: kokoro 
---
M src/mem/cache/base.cc
M src/mem/cache/cache.cc
M src/mem/cache/cache_blk.cc
M src/mem/cache/cache_blk.hh
M src/mem/cache/noncoherent_cache.cc
5 files changed, 151 insertions(+), 118 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 7b6b3c3..a24ffc7 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -318,9 +318,10 @@
 // internally, and have a sufficiently weak memory
 // model, this is probably unnecessary, but at some
 // point it must have seemed like we needed it...
-assert((pkt->needsWritable() && !blk->isWritable()) ||
-   pkt->req->isCacheMaintenance());
-blk->status &= ~BlkReadable;
+assert((pkt->needsWritable() &&
+!blk->isSet(CacheBlk::WritableBit)) ||
+pkt->req->isCacheMaintenance());
+blk->clearCoherenceBits(CacheBlk::ReadableBit);
 }
 // Here we are using forward_time, modelling the latency of
 // a miss (outbound) just as forwardLatency, neglecting the
@@ -476,7 +477,7 @@
 if (blk && blk->isValid() && pkt->isClean() && !pkt->isInvalidate()) {
 // The block was marked not readable while there was a pending
 // cache maintenance operation, restore its flag.
-blk->status |= BlkReadable;
+blk->setCoherenceBits(CacheBlk::ReadableBit);

 // This was a cache clean operation (without invalidate)
 // and we have a copy of the block already. Since there
@@ -485,7 +486,8 @@
 mshr->promoteReadable();
 }

-if (blk && blk->isWritable() && !pkt->req->isCacheInvalidate()) {
+if (blk && blk->isSet(CacheBlk::WritableBit) &&
+!pkt->req->isCacheInvalidate()) {
 // If at this point the referenced block is writable and the
 // response is not a cache invalidate, we promote targets that
 // were deferred as we couldn't guarrantee a writable copy
@@ -498,7 +500,7 @@
 // avoid later read getting stale data while write miss is
 // outstanding.. see comment in timingAccess()
 if (blk) {
-blk->status &= ~BlkReadable;
+blk->clearCoherenceBits(CacheBlk::ReadableBit);
 }
 mshrQueue.markPending(mshr);
 schedMemSideSendEvent(clockEdge() + pkt->payloadDelay);
@@ -551,7 +553,7 @@
 PacketList writebacks;
 bool satisfied = access(pkt, blk, lat, writebacks);

-if (pkt->isClean() && blk && blk->isDirty()) {
+if (pkt->isClean() && blk && blk->isSet(CacheBlk::DirtyBit)) {
 // A cache clean opearation is looking for a dirty
 // block. If a dirty block is encountered a WriteClean
 // will update any copies to the path to the memory
@@ -641,7 +643,7 @@
 // data we have is dirty if marked as such or if we have an
 // in-service MSHR that is pending a modified line
 bool have_dirty =
-have_data && (blk->isDirty() ||
+have_data && (blk->isSet(CacheBlk::DirtyBit) ||
   (mshr && mshr->inService &&  
mshr->isPendingModified()));


 bool done = have_dirty ||
@@ -709,7 +711,7 @@

 if (overwrite_mem) {
 std::memcpy(blk_data, _val, pkt->getSize());
-blk->status |= BlkDirty;
+blk->setCoherenceBits(CacheBlk::DirtyBit);
 }
 }

@@ -805,8 +807,8 @@
 if (mshr) {
 // Must be an outstanding upgrade or clean request on a  
block

 // we're about to replace
-assert((!blk->isWritable() && mshr->needsWritable()) ||
-   

[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Isolate compression bit

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35700 )


Change subject: mem-cache: Isolate compression bit
..

mem-cache: Isolate compression bit

The compression bit does not belong with the coherence bits.

Change-Id: I6e9f201a9961b8c6051ba599f051a444d585f0e4
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35700
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Nikos Nikoleris 
Maintainer: Nikos Nikoleris 
Tested-by: kokoro 
---
M src/mem/cache/cache_blk.hh
M src/mem/cache/tags/super_blk.cc
M src/mem/cache/tags/super_blk.hh
3 files changed, 18 insertions(+), 8 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/cache/cache_blk.hh b/src/mem/cache/cache_blk.hh
index 4483fb1..bf9bfe6 100644
--- a/src/mem/cache/cache_blk.hh
+++ b/src/mem/cache/cache_blk.hh
@@ -69,14 +69,12 @@
 BlkReadable =   0x04,
 /** dirty (modified) */
 BlkDirty =  0x08,
-/** block holds compressed data */
-BlkCompressed = 0x80
 };

 /**
  * A Basic Cache block.
- * Contains information regarding its coherence, prefetching and  
compression

- * status, as well as a pointer to its data.
+ * Contains information regarding its coherence, prefetching status, as
+ * well as a pointer to its data.
  */
 class CacheBlk : public TaggedEntry
 {
diff --git a/src/mem/cache/tags/super_blk.cc  
b/src/mem/cache/tags/super_blk.cc

index 982d9b0..0f570f9 100644
--- a/src/mem/cache/tags/super_blk.cc
+++ b/src/mem/cache/tags/super_blk.cc
@@ -37,26 +37,26 @@
 #include "base/logging.hh"

 CompressionBlk::CompressionBlk()
-: SectorSubBlk(), _size(0), _decompressionLatency(0)
+: SectorSubBlk(), _size(0), _decompressionLatency(0),  
_compressed(false)

 {
 }

 bool
 CompressionBlk::isCompressed() const
 {
-return (status & BlkCompressed) != 0;
+return _compressed;
 }

 void
 CompressionBlk::setCompressed()
 {
-status |= BlkCompressed;
+_compressed = true;
 }

 void
 CompressionBlk::setUncompressed()
 {
-status &= ~BlkCompressed;
+_compressed = false;
 }

 std::size_t
@@ -83,6 +83,13 @@
 _decompressionLatency = lat;
 }

+void
+CompressionBlk::invalidate()
+{
+SectorSubBlk::invalidate();
+setUncompressed();
+}
+
 std::string
 CompressionBlk::print() const
 {
diff --git a/src/mem/cache/tags/super_blk.hh  
b/src/mem/cache/tags/super_blk.hh

index a1c3ff4..bca3266 100644
--- a/src/mem/cache/tags/super_blk.hh
+++ b/src/mem/cache/tags/super_blk.hh
@@ -59,6 +59,9 @@
  */
 Cycles _decompressionLatency;

+/** Compression bit. */
+bool _compressed;
+
   public:
 CompressionBlk();
 CompressionBlk(const CompressionBlk&) = delete;
@@ -110,6 +113,8 @@
  */
 void setDecompressionLatency(const Cycles lat);

+void invalidate() override;
+
 /**
  * Pretty-print sector offset and other CacheBlk information.
  *

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6e9f201a9961b8c6051ba599f051a444d585f0e4
Gerrit-Change-Number: 35700
Gerrit-PatchSet: 2
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Isolate prefetching bit

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35699 )


Change subject: mem-cache: Isolate prefetching bit
..

mem-cache: Isolate prefetching bit

Previously the prefetching bit was among the status bits;
yet, it has no correlation with the other bits. It has
been isolated as a single boolean, with a respective getter
and setter.

Change-Id: Ibe76e1196ca17a7c9ab9bda2216186707427cb64
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35699
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Nikos Nikoleris 
Maintainer: Nikos Nikoleris 
Tested-by: kokoro 
---
M src/mem/cache/base.cc
M src/mem/cache/cache.cc
M src/mem/cache/cache_blk.hh
M src/mem/cache/noncoherent_cache.cc
4 files changed, 17 insertions(+), 9 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index fc2115a..7b6b3c3 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -367,7 +367,7 @@
 ppHit->notify(pkt);

 if (prefetcher && blk && blk->wasPrefetched()) {
-blk->status &= ~BlkHWPrefetched;
+blk->clearPrefetched();
 }

 handleTimingReqHit(pkt, blk, request_time);
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 8e45ea3..9e87c2a 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -850,7 +850,7 @@
   case MSHR::Target::FromPrefetcher:
 assert(tgt_pkt->cmd == MemCmd::HardPFReq);
 if (blk)
-blk->status |= BlkHWPrefetched;
+blk->setPrefetched();
 delete tgt_pkt;
 break;

diff --git a/src/mem/cache/cache_blk.hh b/src/mem/cache/cache_blk.hh
index b0d45af..4483fb1 100644
--- a/src/mem/cache/cache_blk.hh
+++ b/src/mem/cache/cache_blk.hh
@@ -69,8 +69,6 @@
 BlkReadable =   0x04,
 /** dirty (modified) */
 BlkDirty =  0x08,
-/** block was a hardware prefetch yet unaccessed*/
-BlkHWPrefetched =   0x20,
 /** block holds compressed data */
 BlkCompressed = 0x80
 };
@@ -176,6 +174,7 @@
 virtual void invalidate()
 {
 TaggedEntry::invalidate();
+clearPrefetched();
 setTaskId(ContextSwitchTaskId::Unknown);
 status = 0;
 whenReady = MaxTick;
@@ -198,10 +197,16 @@
  * be touched.
  * @return True if the block was a hardware prefetch, unaccesed.
  */
-bool wasPrefetched() const
-{
-return (status & BlkHWPrefetched) != 0;
-}
+bool wasPrefetched() const { return _prefetched; }
+
+/**
+ * Clear the prefetching bit. Either because it was recently used, or  
due

+ * to the block being invalidated.
+ */
+void clearPrefetched() { _prefetched = false; }
+
+/** Marks this blocks as a recently prefetched block. */
+void setPrefetched() { _prefetched = false; }

 /**
  * Get tick at which block's data will be available for access.
@@ -423,6 +428,9 @@
  * meaningful if the block is valid.
  */
 Tick _tickInserted;
+
+/** Whether this block is an unaccessed hardware prefetch. */
+bool _prefetched;
 };

 /**
diff --git a/src/mem/cache/noncoherent_cache.cc  
b/src/mem/cache/noncoherent_cache.cc

index 5ca1da0..0cea494 100644
--- a/src/mem/cache/noncoherent_cache.cc
+++ b/src/mem/cache/noncoherent_cache.cc
@@ -288,7 +288,7 @@
 assert(tgt_pkt->cmd == MemCmd::HardPFReq);

 if (blk)
-blk->status |= BlkHWPrefetched;
+blk->setPrefetched();

 // We have filled the block and the prefetcher does not
 // require responses.

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibe76e1196ca17a7c9ab9bda2216186707427cb64
Gerrit-Change-Number: 35699
Gerrit-PatchSet: 2
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Debug with blk's information instead of its state.

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35697 )


Change subject: mem-cache: Debug with blk's information instead of its  
state.

..

mem-cache: Debug with blk's information instead of its state.

The print() function has been defined to facilitate debugging
regarding a block's metadata. Use it instead of accessing the
coherence bits directly.

Change-Id: Iba41f4ac067561970621a4bba809e1b315b0210d
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35697
Reviewed-by: Nikos Nikoleris 
Reviewed-by: Jason Lowe-Power 
Maintainer: Nikos Nikoleris 
Tested-by: kokoro 
---
M src/mem/cache/base.cc
M src/mem/cache/cache.cc
2 files changed, 4 insertions(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 4b7333c..fc2115a 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -1310,7 +1310,7 @@
 Addr addr = pkt->getAddr();
 bool is_secure = pkt->isSecure();
 #if TRACING_ON
-CacheBlk::State old_state = blk ? blk->status : 0;
+const std::string old_state = blk ? blk->print() : "";
 #endif

 // When handling a fill, we should have no writes to this line.
@@ -1380,7 +1380,7 @@
 }
 }

-DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n",
+DPRINTF(Cache, "Block addr %#llx (%s) moving from %s to %s\n",
 addr, is_secure ? "s" : "ns", old_state, blk->print());

 // if we got new data, copy it in (checking for a read response
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index a46404b..8e45ea3 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -590,7 +590,7 @@
 bus_pkt->print());

 #if TRACING_ON
-CacheBlk::State old_state = blk ? blk->status : 0;
+const std::string old_state = blk ? blk->print() : "";
 #endif

 Cycles latency = ticksToCycles(memSidePort.sendAtomic(bus_pkt));
@@ -598,7 +598,7 @@
 bool is_invalidate = bus_pkt->isInvalidate();

 // We are now dealing with the response handling
-DPRINTF(Cache, "%s: Receive response: %s in state %i\n", __func__,
+DPRINTF(Cache, "%s: Receive response: %s for %s\n", __func__,
 bus_pkt->print(), old_state);

 // If packet was a forward, the response (if any) is already

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iba41f4ac067561970621a4bba809e1b315b0210d
Gerrit-Change-Number: 35697
Gerrit-PatchSet: 2
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Add missing StridePrefetcher invalidation

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35696 )


Change subject: mem-cache: Add missing StridePrefetcher invalidation
..

mem-cache: Add missing StridePrefetcher invalidation

A call to the entry's parent's invalidate function was missing.
Since an entry was only invalidated right before being used,
previous behavior was not breaking anything.

Change-Id: Ibbf31a0099600a8f6be70b3426bac9fcd1e5c749
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35696
Reviewed-by: Nikos Nikoleris 
Reviewed-by: Jason Lowe-Power 
Maintainer: Nikos Nikoleris 
Tested-by: kokoro 
---
M src/mem/cache/prefetch/stride.cc
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve
  Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/cache/prefetch/stride.cc  
b/src/mem/cache/prefetch/stride.cc

index 9b58943..8141af2 100644
--- a/src/mem/cache/prefetch/stride.cc
+++ b/src/mem/cache/prefetch/stride.cc
@@ -68,6 +68,7 @@
 void
 Stride::StrideEntry::invalidate()
 {
+TaggedEntry::invalidate();
 lastAddr = 0;
 stride = 0;
 confidence.reset();

--
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Gerrit-Branch: develop
Gerrit-Change-Id: Ibbf31a0099600a8f6be70b3426bac9fcd1e5c749
Gerrit-Change-Number: 35696
Gerrit-PatchSet: 2
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Re: Register bank abstraction

[Giacomo Travaglini via gem5-dev]

This looks great Gabe! Just so you know, there is already something (old) on 
review:

https://gem5-review.googlesource.com/c/public/gem5/+/10805/3

Giacomo

From: Gabe Black via gem5-dev 
Sent: 08 October 2020 13:59
To: gem5 Developer List 
Cc: Gabe Black 
Subject: [gem5-dev] Register bank abstraction

Hey folks! I've been looking at some device models recently, both to fix them 
and to develop them, and I've seen a lot of boilerplate code which tries to 
figure out what size of data to extract from the packet, how to map that to 
registers, sometimes handling accesses that aren't on register boundaries, 
sometimes handling partial register writes/reads, etc. It's a real mess much of 
the time, and I think people usually write some code that's stretched 
jst far enough to cover the way, for instance, a Linux kernel driver 
pokes at their device.

To simplify that boiler-plate and to make device models significantly more 
robust in general, I thought it would be a good idea to add a RegisterBank 
abstraction which collects a contiguous bunch of registers together. It figures 
out what registers are touched by an access, and divies up the access to send 
the right data to the right registers, aligned to their base offset and 
expanded to their full size. The registers themselves by default act as dumb 
storage locations, but it's easy to add callbacks which let them implement 
whatever behavior they need to on reads or writes, or to mark some/all bits as 
read only. Partial reads/writes are handled automatically with masking and 
read/modify/write operations for reads, but that can be overridden too. The 
registers can be different sizes, have no alignment requirements, and can have 
arbitrary endianness, although the will have a default based on the settings of 
their containing RegisterBank.

I have this written up, and with the very VERY limited testing I've done so far 
it seems to work. I think tomorrow I'll continue working on a unit test, and 
you should hopefully see a review in the not too distant future.

Suggestions welcome, mostly I wanted to give people the 10 second elevator 
pitch before tossing another review on the pile!

Gabe
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[gem5-dev] Register bank abstraction

[Gabe Black via gem5-dev]

Hey folks! I've been looking at some device models recently, both to fix
them and to develop them, and I've seen a lot of boilerplate code which
tries to figure out what size of data to extract from the packet, how to
map that to registers, sometimes handling accesses that aren't on register
boundaries, sometimes handling partial register writes/reads, etc. It's a
real mess much of the time, and I think people usually write some code
that's stretched jst far enough to cover the way, for instance, a
Linux kernel driver pokes at their device.

To simplify that boiler-plate and to make device models significantly more
robust in general, I thought it would be a good idea to add a RegisterBank
abstraction which collects a contiguous bunch of registers together. It
figures out what registers are touched by an access, and divies up the
access to send the right data to the right registers, aligned to their base
offset and expanded to their full size. The registers themselves by default
act as dumb storage locations, but it's easy to add callbacks which let
them implement whatever behavior they need to on reads or writes, or to
mark some/all bits as read only. Partial reads/writes are handled
automatically with masking and read/modify/write operations for reads, but
that can be overridden too. The registers can be different sizes, have no
alignment requirements, and can have arbitrary endianness, although the
will have a default based on the settings of their containing RegisterBank.

I have this written up, and with the very VERY limited testing I've done so
far it seems to work. I think tomorrow I'll continue working on a unit
test, and you should hopefully see a review in the not too distant future.

Suggestions welcome, mostly I wanted to give people the 10 second elevator
pitch before tossing another review on the pile!

Gabe
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[gem5-dev] Change in gem5/gem5[develop]: stats: Make Stats::Group::mergeStatGroup public

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35615 )


Change subject: stats: Make Stats::Group::mergeStatGroup public
..

stats: Make Stats::Group::mergeStatGroup public

The stat system currently assumes that the decision to merge groups is
done at construction time. This makes it hard to implement global
statistics that live in a single global group.

This change adds some error checking to mergeStatGroup and marks it as
a public method.

Change-Id: I6a42f48545c5ccfcd0672bae66a5bc86bb042f13
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35615
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/base/stats/group.cc
M src/base/stats/group.hh
2 files changed, 17 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/stats/group.cc b/src/base/stats/group.cc
index a76ad4f..f1eda1d 100644
--- a/src/base/stats/group.cc
+++ b/src/base/stats/group.cc
@@ -47,7 +47,7 @@
 namespace Stats {

 Group::Group(Group *parent, const char *name)
-: mergedParent(name ? nullptr : parent)
+: mergedParent(nullptr)
 {
 if (parent && name) {
 parent->addStatGroup(name, this);
@@ -152,7 +152,22 @@
 void
 Group::mergeStatGroup(Group *block)
 {
+panic_if(!block, "No stat block provided");
+panic_if(block->mergedParent,
+ "Stat group already merged into another group");
+panic_if(block == this, "Stat group can't merge with itself");
+
+// Track the new stat group
 mergedStatGroups.push_back(block);
+
+// We might not have seen stats that were associated with the
+// child group before it was merged, so add them here.
+for (auto  : block->stats)
+addStat(s);
+
+// Setup the parent pointer so the child know that it needs to
+// register new stats with the parent.
+block->mergedParent = this;
 }

 const std::map &
diff --git a/src/base/stats/group.hh b/src/base/stats/group.hh
index 985bf61..ef223bc 100644
--- a/src/base/stats/group.hh
+++ b/src/base/stats/group.hh
@@ -194,7 +194,6 @@
  */
 const Info * resolveStat(std::string name) const;

-  private:
 /**
  * Merge the contents (stats & children) of a block to this block.
  *
@@ -205,7 +204,7 @@

   private:
 /** Parent pointer if merged into parent */
-Group *const mergedParent;
+Group *mergedParent;

 std::map statGroups;
 std::vector mergedStatGroups;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6a42f48545c5ccfcd0672bae66a5bc86bb042f13
Gerrit-Change-Number: 35615
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Default ArmSystem to AArch64

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35775 )


Change subject: arch-arm: Default ArmSystem to AArch64
..

arch-arm: Default ArmSystem to AArch64

Change-Id: I4dad29086c0b3e50bd2011363cb23625811b4b27
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35775
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/arch/arm/ArmSystem.py
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 0ca782f..13f0c2d 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -60,7 +60,7 @@
 "Reset address (ARMv8)")
 auto_reset_addr = Param.Bool(True,
 "Determine reset address from kernel entry point if no boot  
loader")

-highest_el_is_64 = Param.Bool(False,
+highest_el_is_64 = Param.Bool(True,
 "True if the register width of the highest implemented exception  
level "

 "is 64 bits (ARMv8)")
 phys_addr_range_64 = Param.UInt8(40,

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4dad29086c0b3e50bd2011363cb23625811b4b27
Gerrit-Change-Number: 35775
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Build failed in Jenkins: Nightly #91

[jenkins-no-reply--- via gem5-dev]

See 

Changes:

[giacomo.travaglini] arch: Add generic BaseMMU

[giacomo.travaglini] fastmodel: Add IrisMMU model

[gabeblack] sim: Add a mechanism for finding an compatible SE workload.

[gabeblack] sparc: Clean up some code in base.isa.

[gabeblack] sparc: Simplify the IntOp format slightly.


--
[...truncated 47.05 KB...]
 [SO PyBind] QoSMemSinkInterface -> NULL/python/_m5/param_QoSMemSinkInterface.cc
 [ CXX] NULL/python/_m5/param_QoSMemSinkInterface.cc -> .o
 [SO PyBind] QoSPolicy -> NULL/python/_m5/param_QoSPolicy.cc
 [ CXX] NULL/python/_m5/param_QoSPolicy.cc -> .o
 [SO PyBind] QoSPropFairPolicy -> NULL/python/_m5/param_QoSPropFairPolicy.cc
 [SO PARAM] QoSPropFairPolicy -> NULL/params/QoSPropFairPolicy.hh
 [ CXX] NULL/python/_m5/param_QoSPropFairPolicy.cc -> .o
 [SO PyBind] QoSTurnaroundPolicy -> NULL/python/_m5/param_QoSTurnaroundPolicy.cc
 [ CXX] NULL/python/_m5/param_QoSTurnaroundPolicy.cc -> .o
 [SO PyBind] QoSTurnaroundPolicyIdeal -> 
NULL/python/_m5/param_QoSTurnaroundPolicyIdeal.cc
 [SO PARAM] QoSTurnaroundPolicyIdeal -> NULL/params/QoSTurnaroundPolicyIdeal.hh
 [ CXX] NULL/python/_m5/param_QoSTurnaroundPolicyIdeal.cc -> .o
 [SO PyBind] QueuedPrefetcher -> NULL/python/_m5/param_QueuedPrefetcher.cc
 [ CXX] NULL/python/_m5/param_QueuedPrefetcher.cc -> .o
 [SO PyBind] RandomRP -> NULL/python/_m5/param_RandomRP.cc
 [SO PARAM] RandomRP -> NULL/params/RandomRP.hh
 [ CXX] NULL/python/_m5/param_RandomRP.cc -> .o
 [SO PyBind] RangeAddrMapper -> NULL/python/_m5/param_RangeAddrMapper.cc
 [ CXX] NULL/python/_m5/param_RangeAddrMapper.cc -> .o
 [SO PyBind] RedirectPath -> NULL/python/_m5/param_RedirectPath.cc
 [ CXX] NULL/python/_m5/param_RedirectPath.cc -> .o
 [SO PyBind] RepeatedQwordsCompressor -> 
NULL/python/_m5/param_RepeatedQwordsCompressor.cc
 [SO PARAM] RepeatedQwordsCompressor -> NULL/params/RepeatedQwordsCompressor.hh
 [ CXX] NULL/python/_m5/param_RepeatedQwordsCompressor.cc -> .o
 [SO PyBind] Root -> NULL/python/_m5/param_Root.cc
 [SO PARAM] Root -> NULL/params/Root.hh
 [ CXX] NULL/python/_m5/param_Root.cc -> .o
 [SO PyBind] RubyCache -> NULL/python/_m5/param_RubyCache.cc
 [ CXX] NULL/python/_m5/param_RubyCache.cc -> .o
 [SO PyBind] RubyController -> NULL/python/_m5/param_RubyController.cc
 [ CXX] NULL/python/_m5/param_RubyController.cc -> .o
 [SO PyBind] RubyDirectedTester -> NULL/python/_m5/param_RubyDirectedTester.cc
 [ CXX] NULL/python/_m5/param_RubyDirectedTester.cc -> .o
 [SO PyBind] RubyDirectoryMemory -> NULL/python/_m5/param_RubyDirectoryMemory.cc
 [ CXX] NULL/python/_m5/param_RubyDirectoryMemory.cc -> .o
 [SO PyBind] RubyHTMSequencer -> NULL/python/_m5/param_RubyHTMSequencer.cc
 [ CXX] NULL/python/_m5/param_RubyHTMSequencer.cc -> .o
 [SO PyBind] RubyNetwork -> NULL/python/_m5/param_RubyNetwork.cc
 [ CXX] NULL/python/_m5/param_RubyNetwork.cc -> .o
 [SO PyBind] RubyPort -> NULL/python/_m5/param_RubyPort.cc
 [ CXX] NULL/python/_m5/param_RubyPort.cc -> .o
 [SO PyBind] RubyPortProxy -> NULL/python/_m5/param_RubyPortProxy.cc
 [SO PARAM] RubyPortProxy -> NULL/params/RubyPortProxy.hh
 [ CXX] NULL/python/_m5/param_RubyPortProxy.cc -> .o
 [SO PyBind] RubyPrefetcher -> NULL/python/_m5/param_RubyPrefetcher.cc
 [ CXX] NULL/python/_m5/param_RubyPrefetcher.cc -> .o
 [SO PyBind] RubySequencer -> NULL/python/_m5/param_RubySequencer.cc
 [ CXX] NULL/python/_m5/param_RubySequencer.cc -> .o
 [SO PyBind] RubySystem -> NULL/python/_m5/param_RubySystem.cc
 [ CXX] NULL/python/_m5/param_RubySystem.cc -> .o
 [SO PyBind] RubyTester -> NULL/python/_m5/param_RubyTester.cc
 [SO PARAM] RubyTester -> NULL/params/RubyTester.hh
 [ CXX] NULL/python/_m5/param_RubyTester.cc -> .o
 [SO PyBind] RubyWireBuffer -> NULL/python/_m5/param_RubyWireBuffer.cc
 [ CXX] NULL/python/_m5/param_RubyWireBuffer.cc -> .o
 [SO PyBind] SBOOEPrefetcher -> NULL/python/_m5/param_SBOOEPrefetcher.cc
 [SO PARAM] SBOOEPrefetcher -> NULL/params/SBOOEPrefetcher.hh
 [ CXX] NULL/python/_m5/param_SBOOEPrefetcher.cc -> .o
 [SO PyBind] SEWorkload -> NULL/python/_m5/param_SEWorkload.cc
 [SO PARAM] SEWorkload -> NULL/params/SEWorkload.hh
 [ CXX] NULL/python/_m5/param_SEWorkload.cc -> .o
 [SO PyBind] STeMSPrefetcher -> NULL/python/_m5/param_STeMSPrefetcher.cc
 [SO PARAM] STeMSPrefetcher -> NULL/params/STeMSPrefetcher.hh
 [ CXX] NULL/python/_m5/param_STeMSPrefetcher.cc -> .o
 [SO PyBind] SecondChanceRP -> NULL/python/_m5/param_SecondChanceRP.cc
 [SO PARAM] SecondChanceRP -> NULL/params/SecondChanceRP.hh
 [ CXX] NULL/python/_m5/param_SecondChanceRP.cc -> .o
 [SO PyBind] SectorTags -> NULL/python/_m5/param_SectorTags.cc
 [ CXX] NULL/python/_m5/param_SectorTags.cc -> .o
 [SO PyBind] SerialLink -> NULL/python/_m5/param_SerialLink.cc
 [SO PARAM] SerialLink -> NULL/params/SerialLink.hh
 [ CXX] NULL/python/_m5/param_SerialLink.cc -> .o
 [SO