[gem5-dev] Change in gem5/gem5[develop]: misc: Merge branch hotfix v20.1.0.2 branch into develop
Bobby R. Bruce has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/37635 ) Change subject: misc: Merge branch hotfix v20.1.0.2 branch into develop .. misc: Merge branch hotfix v20.1.0.2 branch into develop This merge commit also reverts the version info back to 'DEVELOP-FOR-V20.2' for the develop branch. Change-Id: If6fd326cc23edf2aeaa67353d4d3fed573e9ddd6 --- M src/Doxyfile M src/base/version.cc 3 files changed, 0 insertions(+), 8 deletions(-) Approvals: Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/Doxyfile b/src/Doxyfile index 497a781..d453314 100644 --- a/src/Doxyfile +++ b/src/Doxyfile @@ -31,11 +31,7 @@ # This could be handy for archiving the generated documentation or # if some version control system is used. -<<< HEAD (9a01d3 dev-hsa,gpu-compute: Agent Packet handler implemented.) PROJECT_NUMBER = DEVELOP-FOR-V20.2 -=== -PROJECT_NUMBER = v20.1.0.2 ->>> BRANCH (0d7030 misc: Updated the RELEASE-NOTES and version number) # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) # base path where the generated documentation will be put. diff --git a/src/base/version.cc b/src/base/version.cc index 0eb7507..cfa98f9 100644 --- a/src/base/version.cc +++ b/src/base/version.cc @@ -29,8 +29,4 @@ /** * @ingroup api_base_utils */ -<<< HEAD (9a01d3 dev-hsa,gpu-compute: Agent Packet handler implemented.) const char *gem5Version = "[DEVELOP-FOR-V20.2]"; -=== -const char *gem5Version = "20.1.0.2"; ->>> BRANCH (0d7030 misc: Updated the RELEASE-NOTES and version number) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37635 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: If6fd326cc23edf2aeaa67353d4d3fed573e9ddd6 Gerrit-Change-Number: 37635 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby R. Bruce Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: sim: Update stats style of System and Process
Hoa Nguyen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/37995 )
Change subject: sim: Update stats style of System and Process
..
sim: Update stats style of System and Process
Change-Id: I3af072a61a18f4fbba3f7d4b632c58501e7b7ae8
Signed-off-by: Hoa Nguyen
---
M src/sim/process.cc
M src/sim/process.hh
M src/sim/system.cc
3 files changed, 5 insertions(+), 20 deletions(-)
diff --git a/src/sim/process.cc b/src/sim/process.cc
index 315f86b..7819820 100644
--- a/src/sim/process.cc
+++ b/src/sim/process.cc
@@ -128,7 +128,8 @@
_pid(params.pid), _ppid(params.ppid),
_pgid(params.pgid), drivers(params.drivers),
fds(make_shared(params.input, params.output,
params.errout)),
- childClearTID(0)
+ childClearTID(0),
+ ADD_STAT(numSyscalls, "Number of system calls")
{
if (_pid >= System::maxPID)
fatal("_pid is too large: %d", _pid);
@@ -252,19 +253,6 @@
}
void
-Process::regStats()
-{
-SimObject::regStats();
-
-using namespace Stats;
-
-numSyscalls
-.name(name() + ".numSyscalls")
-.desc("Number of system calls")
-;
-}
-
-void
Process::revokeThreadContext(int context_id)
{
std::vector::iterator it;
diff --git a/src/sim/process.hh b/src/sim/process.hh
index 2234cb0..c9e6a8b 100644
--- a/src/sim/process.hh
+++ b/src/sim/process.hh
@@ -105,9 +105,6 @@
Addr getStartPC();
::Loader::ObjectFile *getInterpreter();
-// override of virtual SimObject method: register statistics
-void regStats() override;
-
void allocateMem(Addr vaddr, int64_t size, bool clobber = false);
/// Attempt to fix up a fault at vaddr by allocating a page on the
stack.
@@ -162,8 +159,6 @@
// system object which owns this process
System *system;
-Stats::Scalar numSyscalls; // track how many system calls are executed
-
// flag for using architecture specific page table
bool useArchPT;
// running KVM requires special initialization
@@ -286,6 +281,8 @@
// Process was forked with SIGCHLD set.
bool *sigchld;
+
+Stats::Scalar numSyscalls; // track how many system calls are executed
};
#endif // __PROCESS_HH__
diff --git a/src/sim/system.cc b/src/sim/system.cc
index d31238c..44daeb8 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -490,7 +490,7 @@
SimObject::regStats();
for (uint32_t j = 0; j < numWorkIds ; j++) {
-workItemStats[j] = new Stats::Histogram();
+workItemStats[j] = new Stats::Histogram(this);
stringstream namestr;
ccprintf(namestr, "work_item_type%d", j);
workItemStats[j]->init(20)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3af072a61a18f4fbba3f7d4b632c58501e7b7ae8
Gerrit-Change-Number: 37995
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: sim: add test for IniFile::visitSection
Ciro Santilli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/37975 )
Change subject: sim: add test for IniFile::visitSection
..
sim: add test for IniFile::visitSection
iniFile was used as a global variable, and thee tests were relying on
MatchNotFound running after MatchFound, which would first empty the
istringstream.
Therefore, the only way to reuse that test file was to rewind
istringstream. Since this is a bit ugly, and it is better practice not to
rely on a specific test order, this commit instead creates a separate
istringstream per test.
Change-Id: If3cf5ef74ba7dfaf2f90b55acd1c3a8bdda04947
---
M src/base/inifile.test.cc
1 file changed, 31 insertions(+), 7 deletions(-)
diff --git a/src/base/inifile.test.cc b/src/base/inifile.test.cc
index 0d1600e..0cabb55 100644
--- a/src/base/inifile.test.cc
+++ b/src/base/inifile.test.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 ARM Limited
+ * Copyright (c) 2018, 2020 ARM Limited
* All rights reserved
*
* Copyright (c) 2002-2005 The Regents of The University of Michigan
@@ -29,20 +29,27 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wdeprecated-copy"
+#include
#include
+#pragma GCC diagnostic pop
#include
#include
#include
+#include
#include
#include "base/inifile.hh"
using namespace std;
+using testing::ElementsAre;
+using testing::Pair;
namespace {
-std::istringstream iniFile(R"ini_file(
+const char *iniFileString = R"ini_file(
[General]
Test1=BARasdf
Test2=bar
@@ -60,14 +67,13 @@
[Junk]
Test4+=mia
-)ini_file");
-
-};
+)ini_file";
TEST(Initest, MatchFound)
{
IniFile simConfigDB;
-simConfigDB.load(iniFile);
+std::istringstream is{iniFileString};
+simConfigDB.load(is);
std::string value;
@@ -95,7 +101,8 @@
TEST(Initest, MatchNotFound)
{
IniFile simConfigDB;
-simConfigDB.load(iniFile);
+std::istringstream is;
+simConfigDB.load(is);
std::string value;
@@ -105,3 +112,20 @@
ret = simConfigDB.find("Junk", "test4", value);
ASSERT_FALSE(ret);
}
+
+TEST(Initest, visitSection)
+{
+IniFile simConfigDB;
+std::istringstream is{iniFileString};
+simConfigDB.load(is);
+std::vector> keys_values;
+simConfigDB.visitSection("Junk", [&](std::string key, std::string
value)
+{
+keys_values.emplace_back(key, value);
+});
+ASSERT_THAT(keys_values, ElementsAre(
+Pair("Test4", "mama mia"),
+Pair("Test3", "yo")
+));
+}
+}
--
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Gerrit-Branch: develop
Gerrit-Change-Id: If3cf5ef74ba7dfaf2f90b55acd1c3a8bdda04947
Gerrit-Change-Number: 37975
Gerrit-PatchSet: 1
Gerrit-Owner: Ciro Santilli
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add SECURE_RD/WR flags to miscRegInfo
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/37615 )
Change subject: arch-arm: Add SECURE_RD/WR flags to miscRegInfo
..
arch-arm: Add SECURE_RD/WR flags to miscRegInfo
The introduction of Secure EL2 in gem5 requires the introduction
of new miscReg flags as there are some EL2 registers which are
accessible from secure mode only
Change-Id: Ib1f0633ed23ea2364670d37c1fefd345ab2363ae
Signed-off-by: Giacomo Travaglini
Reviewed-by: Ciro Santilli
Reviewed-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37615
Tested-by: kokoro
---
M src/arch/arm/isa.hh
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
3 files changed, 71 insertions(+), 14 deletions(-)
Approvals:
Ciro Santilli: Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 6b9dd3c..dce5e37 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -252,12 +252,30 @@
privNonSecureRead(v);
return *this;
}
+chain hypE2HSecureRead(bool v = true) const {
+info[MISCREG_HYP_E2H_S_RD] = v;
+return *this;
+}
+chain hypE2HNonSecureRead(bool v = true) const {
+info[MISCREG_HYP_E2H_NS_RD] = v;
+return *this;
+}
chain hypE2HRead(bool v = true) const {
-info[MISCREG_HYP_E2H_RD] = v;
+hypE2HSecureRead(v);
+hypE2HNonSecureRead(v);
+return *this;
+}
+chain hypE2HSecureWrite(bool v = true) const {
+info[MISCREG_HYP_E2H_S_WR] = v;
+return *this;
+}
+chain hypE2HNonSecureWrite(bool v = true) const {
+info[MISCREG_HYP_E2H_NS_WR] = v;
return *this;
}
chain hypE2HWrite(bool v = true) const {
-info[MISCREG_HYP_E2H_WR] = v;
+hypE2HSecureWrite(v);
+hypE2HNonSecureWrite(v);
return *this;
}
chain hypE2H(bool v = true) const {
@@ -265,14 +283,39 @@
hypE2HWrite(v);
return *this;
}
+chain hypSecureRead(bool v = true) const {
+info[MISCREG_HYP_S_RD] = v;
+return *this;
+}
+chain hypNonSecureRead(bool v = true) const {
+info[MISCREG_HYP_NS_RD] = v;
+return *this;
+}
chain hypRead(bool v = true) const {
hypE2HRead(v);
-info[MISCREG_HYP_RD] = v;
+hypSecureRead(v);
+hypNonSecureRead(v);
+return *this;
+}
+chain hypSecureWrite(bool v = true) const {
+info[MISCREG_HYP_S_WR] = v;
+return *this;
+}
+chain hypNonSecureWrite(bool v = true) const {
+info[MISCREG_HYP_NS_WR] = v;
return *this;
}
chain hypWrite(bool v = true) const {
hypE2HWrite(v);
-info[MISCREG_HYP_WR] = v;
+hypSecureWrite(v);
+hypNonSecureWrite(v);
+return *this;
+}
+chain hypSecure(bool v = true) const {
+hypE2HSecureRead(v);
+hypE2HSecureWrite(v);
+hypSecureRead(v);
+hypSecureWrite(v);
return *this;
}
chain hyp(bool v = true) const {
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 585b713..8110a19 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -1230,7 +1230,7 @@
miscRegInfo[reg][MISCREG_MON_NS1_RD];
break;
case MODE_HYP:
-canRead = miscRegInfo[reg][MISCREG_HYP_RD];
+canRead = miscRegInfo[reg][MISCREG_HYP_NS_RD];
break;
default:
undefined = true;
@@ -1276,7 +1276,7 @@
miscRegInfo[reg][MISCREG_MON_NS1_WR];
break;
case MODE_HYP:
-canWrite = miscRegInfo[reg][MISCREG_HYP_WR];
+canWrite = miscRegInfo[reg][MISCREG_HYP_NS_WR];
break;
default:
undefined = true;
@@ -1397,8 +1397,13 @@
return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
miscRegInfo[reg][MISCREG_PRI_NS_RD];
case EL2:
-return el2_host ? miscRegInfo[reg][MISCREG_HYP_E2H_RD] :
-miscRegInfo[reg][MISCREG_HYP_RD];
+if (el2_host) {
+return secure ? miscRegInfo[reg][MISCREG_HYP_E2H_S_RD] :
+miscRegInfo[reg][MISCREG_HYP_E2H_NS_RD];
+} el
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: VSTCR_EL2/VSTTBR_EL2 accessible in secure mode only
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/37616 ) Change subject: arch-arm: VSTCR_EL2/VSTTBR_EL2 accessible in secure mode only .. arch-arm: VSTCR_EL2/VSTTBR_EL2 accessible in secure mode only We should trigger an Undefined Instruction if those registers are accessed in non-secure mode Change-Id: I45ec01e9e4ae9a38d59e56a51e198b4199a7d814 Signed-off-by: Giacomo Travaglini Reviewed-by: Ciro Santilli Reviewed-by: Nikos Nikoleris Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37616 Tested-by: kokoro --- M src/arch/arm/miscregs.cc 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: Ciro Santilli: Looks good to me, approved Giacomo Travaglini: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 8110a19..825811f 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -4907,9 +4907,9 @@ .hyp().mon() .mapsTo(MISCREG_VTCR); InitReg(MISCREG_VSTTBR_EL2) - .hyp().mon(); + .hypSecure().mon(); InitReg(MISCREG_VSTCR_EL2) - .hyp().mon(); + .hypSecure().mon(); InitReg(MISCREG_TTBR0_EL3) .mon(); InitReg(MISCREG_TCR_EL3) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37616 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I45ec01e9e4ae9a38d59e56a51e198b4199a7d814 Gerrit-Change-Number: 37616 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Ciro Santilli Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: dev: -Wdeprecated-copy not available on all supported compilers
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/37795 ) Change subject: dev: -Wdeprecated-copy not available on all supported compilers .. dev: -Wdeprecated-copy not available on all supported compilers This option has been introduced in: 1) gcc/9.0 [1] 2) clang/10.0.0 [2] [1]: https://gcc.gnu.org/gcc-9/changes.html [2]: https://releases.llvm.org/10.0.0/tools/clang/docs/ReleaseNotes.html Change-Id: Iee9de40ca462107ec78603ffe5bc0891d6904730 Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37795 Reviewed-by: Richard Cooper Reviewed-by: Jason Lowe-Power Reviewed-by: Gabe Black Maintainer: Jason Lowe-Power Maintainer: Gabe Black Tested-by: kokoro --- M src/dev/reg_bank.test.cc 1 file changed, 22 insertions(+), 1 deletion(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved Gabe Black: Looks good to me, approved; Looks good to me, approved Richard Cooper: Looks good to me, but someone else must approve kokoro: Regressions pass diff --git a/src/dev/reg_bank.test.cc b/src/dev/reg_bank.test.cc index 348900b..6e655e2 100644 --- a/src/dev/reg_bank.test.cc +++ b/src/dev/reg_bank.test.cc @@ -1,4 +1,16 @@ /* + * Copyright (c) 2020 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright 2020 Google, Inc. * * Redistribution and use in source and binary forms, with or without @@ -26,7 +38,16 @@ */ #pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wdeprecated-copy" + +// __GNUC__ defined for both clang and gcc +// -Wdeprecated-copy has been added in clang10.0.0 and gcc9.0 +#if defined(__GNUC__) +#if (defined(__clang__) && __GNUC__ >= 10) || \ +(!defined(__clang__) && __GNUC__ >= 9) +#pragma GCC diagnostic ignored "-Wdeprecated-copy" +#endif +#endif + #include #include -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37795 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Iee9de40ca462107ec78603ffe5bc0891d6904730 Gerrit-Change-Number: 37795 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Ciro Santilli Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: implement the aarch64 ID_ISAR6_EL1 miscregister
Ciro Santilli has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30935 )
Change subject: arch-arm: implement the aarch64 ID_ISAR6_EL1 miscregister
..
arch-arm: implement the aarch64 ID_ISAR6_EL1 miscregister
This register is used since the Linux kernel 5.6 aarch64 boot.
This register indicates CPU capabilities in aarch32 mode, and it has the
same value as the aarch32 ID_ISAR6 miscregister, which is also added.
The capability values of those registers are analogous to those present in
aarch64 accessible ID_AA64ISAR0_EL1 and ID_AA64ISAR1_EL1, which refer to
aarch64 capabilities however, and were already implemented before this
commit.
The arm architecture document clarifies that reads to this system register
location before it had been defined should return 0, but we were faulting
instead:
Prior to the introduction of the features described by this register,
this register was unnamed and reserved, RES0 from EL1, EL2, and EL3.
Change-Id: I70e99536dc98925e88233fd4c6887bbcdd5d87dc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30935
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/ArmISA.py
M src/arch/arm/fastmodel/CortexA76/thread_context.cc
M src/arch/arm/insts/misc64.cc
M src/arch/arm/isa.cc
M src/arch/arm/kvm/arm_cpu.cc
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/tracers/tarmac_parser.cc
M src/arch/arm/utility.cc
9 files changed, 27 insertions(+), 4 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 3e18665..0cb973a 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -81,6 +81,8 @@
id_isar3 = Param.UInt32(0x01112131, "Instruction Set Attribute
Register 3")
id_isar4 = Param.UInt32(0x10010142, "Instruction Set Attribute
Register 4")
id_isar5 = Param.UInt32(0x1100, "Instruction Set Attribute
Register 5")
+# !I8MM | !BF16 | SPECRES = 0 | !SB | !FHM | DP | JSCVT
+id_isar6 = Param.UInt32(0x0001, "Instruction Set Attribute
Register 6")
fpsid = Param.UInt32(0x410430a0, "Floating-point System ID Register")
@@ -98,10 +100,11 @@
id_aa64dfr1_el1 = Param.UInt64(0x,
"AArch64 Debug Feature Register 1")
-# !TME | !Atomic | !CRC32 | !SHA2 | RDM | !SHA1 | !AES
+# !FHM | !TME | !Atomic | !CRC32 | !SHA2 | RDM | !SHA1 | !AES
id_aa64isar0_el1 = Param.UInt64(0x1000,
"AArch64 Instruction Set Attribute Register 0")
+# !I8MM | !BF16 | SPECRES = 0 | !SB |
# GPI = 0x0 | GPA = 0x1 | API=0x0 | FCMA | JSCVT | APA=0x1
id_aa64isar1_el1 = Param.UInt64(0x01011010,
"AArch64 Instruction Set Attribute Register 1")
diff --git a/src/arch/arm/fastmodel/CortexA76/thread_context.cc
b/src/arch/arm/fastmodel/CortexA76/thread_context.cc
index 9c9b933..d2aca9b 100644
--- a/src/arch/arm/fastmodel/CortexA76/thread_context.cc
+++ b/src/arch/arm/fastmodel/CortexA76/thread_context.cc
@@ -306,6 +306,7 @@
{ ArmISA::MISCREG_ID_ISAR3, "ID_ISAR3" },
{ ArmISA::MISCREG_ID_ISAR4, "ID_ISAR4" },
{ ArmISA::MISCREG_ID_ISAR5, "ID_ISAR5" },
+{ ArmISA::MISCREG_ID_ISAR6, "ID_ISAR6" },
{ ArmISA::MISCREG_CCSIDR, "CCSIDR" },
{ ArmISA::MISCREG_CLIDR, "CLIDR" },
{ ArmISA::MISCREG_AIDR, "AIDR" },
@@ -587,6 +588,7 @@
{ ArmISA::MISCREG_ID_ISAR3_EL1, "ID_ISAR3_EL1" },
{ ArmISA::MISCREG_ID_ISAR4_EL1, "ID_ISAR4_EL1" },
{ ArmISA::MISCREG_ID_ISAR5_EL1, "ID_ISAR5_EL1" },
+{ ArmISA::MISCREG_ID_ISAR6_EL1, "ID_ISAR6_EL1" },
{ ArmISA::MISCREG_MVFR0_EL1, "MVFR0_EL1" },
{ ArmISA::MISCREG_MVFR1_EL1, "MVFR1_EL1" },
{ ArmISA::MISCREG_MVFR2_EL1, "MVFR2_EL1" },
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 47a8ad9..4d6a95b 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -372,6 +372,7 @@
case MISCREG_ID_ISAR3_EL1:
case MISCREG_ID_ISAR4_EL1:
case MISCREG_ID_ISAR5_EL1:
+ case MISCREG_ID_ISAR6_EL1:
case MISCREG_MVFR0_EL1:
case MISCREG_MVFR1_EL1:
case MISCREG_MVFR2_EL1:
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 9b0b957..dd6a680 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -344,6 +344,7 @@
miscRegs[MISCREG_ID_ISAR3] = p.id_isar3;
miscRegs[MISCREG_ID_ISAR4] = p.id_isar4;
miscRegs[MISCREG_ID_ISAR5] = p.id_isar5;
+miscRegs[MISCREG_ID_ISAR6] = p.id_isar6;
miscRegs[MISCREG_ID_MMFR0] = p.id_mmfr0;
miscRegs[MISCREG_ID_MMFR1] = p.id_mmfr1;
diff --git a/src/arch/arm/kvm/arm_cpu.cc b/src/arch/arm/kvm/arm_cpu.cc
index 4fbb78e..a52b506 100644
--- a/src/arch/arm/kvm/arm_cpu.cc
+++ b/src/arch/arm/kvm/arm_cpu.c
