[gem5-dev] Change in gem5/gem5[develop]: util: Fix typo in cpt upgrader

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46799 )


Change subject: util: Fix typo in cpt upgrader
..

util: Fix typo in cpt upgrader

The module is errno, not ennro.

Change-Id: I3f17bdc12a7acd680ac407042a75d5099f5f7339
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46799
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M util/cpt_upgrader.py
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/cpt_upgrader.py b/util/cpt_upgrader.py
index ee82a7a..0639dc1 100755
--- a/util/cpt_upgrader.py
+++ b/util/cpt_upgrader.py
@@ -185,7 +185,7 @@
 def process_file(path, **kwargs):
 if not osp.isfile(path):
 import errno
-raise IOError(ennro.ENOENT, "No such file", path)
+raise IOError(errno.ENOENT, "No such file", path)

 verboseprint("Processing file %s" % path)


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3f17bdc12a7acd680ac407042a75d5099f5f7339
Gerrit-Change-Number: 46799
Gerrit-PatchSet: 2
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: util: Add scripts to recreate amdgpu ROM and MMIOs

[Matthew Poremba (Gerrit) via gem5-dev]

Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46162 )


Change subject: util: Add scripts to recreate amdgpu ROM and MMIOs
..

util: Add scripts to recreate amdgpu ROM and MMIOs

Although the binary ROM blob and MMIO trace will be placed in
gem5-resources later as 'golden' versions, the scripts are added to
provide instructions for power users of Full System amdgpu that may want
to recreate the files themselves or use a GPU other than the Vega10 GPU
currently modeled.

Change-Id: Ica7ef3b9820b30be32a148ce6cf1d2f81dc2adf9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46162
Tested-by: kokoro 
Reviewed-by: Matt Sinclair 
Reviewed-by: Jason Lowe-Power 
Maintainer: Matt Sinclair 
---
A util/amdgpu/fs_files/README.md
A util/amdgpu/fs_files/collect_mmio_trace.sh
A util/amdgpu/fs_files/dump_gpu_rom.sh
3 files changed, 148 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/amdgpu/fs_files/README.md b/util/amdgpu/fs_files/README.md
new file mode 100644
index 000..c0ca316
--- /dev/null
+++ b/util/amdgpu/fs_files/README.md
@@ -0,0 +1,38 @@
+The utility scripts provided in this directly can be used to recreate the
+files needed to run Full System amdgpu. Golden versions of these files are
+provided in the gem5-resources repository.
+
+These scripts are intended to be run on a Linux system with a discrete AMD
+GPU card running the same kernel version as the disk image which will be  
used

+for Full System simulations. To ensure the kernel versions match, it is
+recommended that the user uses the `dd` utility to make a copy of the disk
+image to a secondary physical disk and then boot from that disk image.
+
+# MMIO Trace collection
+
+The script `collect_mmio_trace.sh` collects an MMIO trace. For this to  
work,

+MMIO tracing must be enabled in the kernel. Using the disk image approach
+above and/or using recent kernel versions based on Ubuntu, this is enabled
+by default.
+
+Before collecting the trace, the amdgpu module must be blacklisted such  
that

+we can enable tracing before the modprobe occurs and disabled once modprobe
+is complete.
+
+This can be done using either:
+`echo 'blacklist amdgpu' >> /etc/modprobe.d/blacklist.conf`
+or
+add `modprobe.blacklist=amdgpu` to kernel boot command (e.g., in grub)
+And then reboot.
+
+The script will take care of the proper options and run the mmiotrace
+commands. The output trace will likely contain unrelated from other MMIOs
+and therefore will be around 500MB in size. You will want to reboot again
+as mmiotrace disables SMP.
+
+# GPU ROM Dump
+
+The script `dump_gpu_rom.sh` dumps the GPU ROM. The GPU ROM on x86 resides
+in the memory range 0xC - 0xD. The script simply uses the `dd`
+command to copy this range from /dev/mem. The amdgpu driver must be loaded
+in order for the ROM to be written to this region, so run `modprobe` first.
diff --git a/util/amdgpu/fs_files/collect_mmio_trace.sh  
b/util/amdgpu/fs_files/collect_mmio_trace.sh

new file mode 100755
index 000..7dbaade
--- /dev/null
+++ b/util/amdgpu/fs_files/collect_mmio_trace.sh
@@ -0,0 +1,67 @@
+# Copyright (c) 2021 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# For use for simulation and test purposes only
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are  
met:

+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright  
notice,

+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from this
+# software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS  
IS"

+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR  
PURPOSE

+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF  

[gem5-dev] Change in gem5/gem5[develop]: mem-ruby,sim: Add support for VGA ROM memory region

[Matthew Poremba (Gerrit) via gem5-dev]

Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46159 )


Change subject: mem-ruby,sim: Add support for VGA ROM memory region
..

mem-ruby,sim: Add support for VGA ROM memory region

Checks if the address is in a shadowed region, and sends the request
to pio to be serviced by the device backing up that range.

Based on: https://gem5-review.googlesource.com/c/amd/gem5/+/23484

Change-Id: I4d5b46cccd6203523008b2e9545d55eb62130964
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46159
Reviewed-by: Matt Sinclair 
Reviewed-by: Jason Lowe-Power 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M configs/example/gpufs/system/system.py
M src/mem/ruby/system/RubyPort.cc
M src/mem/ruby/system/RubyPort.hh
M src/sim/System.py
M src/sim/system.cc
M src/sim/system.hh
6 files changed, 37 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/example/gpufs/system/system.py  
b/configs/example/gpufs/system/system.py

index be4dd57..4ec3618 100644
--- a/configs/example/gpufs/system/system.py
+++ b/configs/example/gpufs/system/system.py
@@ -75,6 +75,9 @@
  voltage_domain =
  system.cpu_voltage_domain)

+# Setup VGA ROM region
+system.shadow_rom_ranges = [AddrRange(0xc, size = Addr('128kB'))]
+
 # Create specified number of CPUs. GPUFS really only needs one.
 system.cpu = [TestCPUClass(clk_domain=system.cpu_clk_domain, cpu_id=i)
 for i in range(args.num_cpus)]
diff --git a/src/mem/ruby/system/RubyPort.cc  
b/src/mem/ruby/system/RubyPort.cc

index 110ed3b..741a410 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -607,11 +607,27 @@
 }

 bool
+RubyPort::MemResponsePort::isShadowRomAddress(Addr addr) const
+{
+RubyPort *ruby_port = static_cast();
+AddrRangeList ranges = ruby_port->system->getShadowRomRanges();
+
+for (auto it = ranges.begin(); it != ranges.end(); ++it) {
+if (it->contains(addr)) {
+return true;
+}
+}
+
+return false;
+}
+
+bool
 RubyPort::MemResponsePort::isPhysMemAddress(PacketPtr pkt) const
 {
 RubyPort *ruby_port = static_cast();
-return ruby_port->system->isMemAddr(pkt->getAddr())
-|| ruby_port->system->isDeviceMemAddr(pkt);
+Addr addr = pkt->getAddr();
+return (ruby_port->system->isMemAddr(addr)  
&& !isShadowRomAddress(addr))

+   || ruby_port->system->isDeviceMemAddr(pkt);
 }

 void
diff --git a/src/mem/ruby/system/RubyPort.hh  
b/src/mem/ruby/system/RubyPort.hh

index 1d25ae9..e28dc6e 100644
--- a/src/mem/ruby/system/RubyPort.hh
+++ b/src/mem/ruby/system/RubyPort.hh
@@ -99,6 +99,7 @@
 void addToRetryList();

   private:
+bool isShadowRomAddress(Addr addr) const;
 bool isPhysMemAddress(PacketPtr pkt) const;
 };

diff --git a/src/sim/System.py b/src/sim/System.py
index a2f6056..224a318 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -83,6 +83,10 @@
 # I/O bridge or cache
 mem_ranges = VectorParam.AddrRange([], "Ranges that constitute main  
memory")


+# The ranges backed by a shadowed ROM
+shadow_rom_ranges = VectorParam.AddrRange([], "Ranges  backed by a " \
+  "shadowed ROM")
+
 shared_backstore = Param.String("", "backstore's shmem segment  
filename, "
 "use to directly address the backstore from another host-OS  
process. "

 "Leave this empty to unset the MAP_SHARED flag.")
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 57ae62f..3c244d8 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -202,6 +202,8 @@
 #endif
   physmem(name() + ".physmem", p.memories, p.mmap_using_noreserve,
   p.shared_backstore),
+  ShadowRomRanges(p.shadow_rom_ranges.begin(),
+  p.shadow_rom_ranges.end()),
   memoryMode(p.mem_mode),
   _cacheLineSize(p.cache_line_size),
   numWorkIds(p.num_work_ids),
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 6beba1f..09798c3 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -378,6 +378,13 @@
  */
 AbstractMemory *getDeviceMemory(RequestorID _id) const;

+/*
+ * Return the list of address ranges backed by a shadowed ROM.
+ *
+ * @return List of address ranges backed by a shadowed ROM
+ */
+AddrRangeList getShadowRomRanges() const { return ShadowRomRanges; }
+
 /**
  * Get the architecture.
  */
@@ -413,6 +420,8 @@

 PhysicalMemory physmem;

+AddrRangeList ShadowRomRanges;
+
 enums::MemoryMode memoryMode;

 const unsigned int _cacheLineSize;

--
To view, visit 

[gem5-dev] Change in gem5/gem5[develop]: dev-amdgpu,configs: checkpoint before MMIOs

[Matthew Poremba (Gerrit) via gem5-dev]

Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46161 )


Change subject: dev-amdgpu,configs: checkpoint before MMIOs
..

dev-amdgpu,configs: checkpoint before MMIOs

The flow for Full System amdgpu is the use KVM to boot linux and begin
loading the driver module. However, the amdgpu module requires reading
the VGA ROM located at 0xc in X86. KVM does not support having a
small 128KiB hole at this location, therefore we take a checkpoint and
switch to a timing CPU to continue loading the drivers before the VGA
ROM is read.

This creates a checkpoint just before the first MMIOs. This is indicated
by three interrupts being sent to the PCI device. After three interrupts
in a row are counted a checkpoint exit event occurs. The interrupt
counter is reset if a non-interrupt PCI read is seen.

Change-Id: I23b320abe81ff6e766cb3f604eca2979339938e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46161
Reviewed-by: Matt Sinclair 
Reviewed-by: Jason Lowe-Power 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M configs/example/gpufs/runfs.py
M configs/example/gpufs/system/amdgpu.py
M src/dev/amdgpu/AMDGPU.py
M src/dev/amdgpu/amdgpu_device.cc
M src/dev/amdgpu/amdgpu_device.hh
5 files changed, 54 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/example/gpufs/runfs.py b/configs/example/gpufs/runfs.py
index 2e60633..fc32a61 100644
--- a/configs/example/gpufs/runfs.py
+++ b/configs/example/gpufs/runfs.py
@@ -58,6 +58,8 @@
 parser.add_argument("--host-parallel", default=False,
 action="store_true",
 help="Run multiple host threads in KVM mode")
+parser.add_argument("--restore-dir", type=str, default=None,
+help="Directory to restore checkpoints from")
 parser.add_argument("--disk-image", default="",
 help="The boot disk image to mount (/dev/sda)")
 parser.add_argument("--second-disk", default=None,
@@ -66,6 +68,11 @@
 parser.add_argument("--gpu-rom", default=None, help="GPU BIOS to load")
 parser.add_argument("--gpu-mmio-trace", default=None,
 help="GPU MMIO trace to load")
+parser.add_argument("--checkpoint-before-mmios", default=False,
+action="store_true",
+help="Take a checkpoint before driver sends  
MMIOs. "

+"This is used to switch out of KVM mode and into "
+"timing mode required to read the VGA ROM on  
boot.")



 def runGpuFSSystem(args):
@@ -89,7 +96,10 @@
 if args.script is not None:
 system.readfile = args.script

-m5.instantiate()
+if args.restore_dir is None:
+m5.instantiate()
+else:
+m5.instantiate(args.restore_dir)


 print("Running the simulation")
@@ -97,6 +107,20 @@

 exit_event = m5.simulate(sim_ticks)

+# Keep executing while there is something to do
+while True:
+if exit_event.getCause() == "m5_exit instruction encountered" or \
+exit_event.getCause() == "user interrupt received" or \
+exit_event.getCause() == "simulate() limit reached":
+break
+elif "checkpoint" in exit_event.getCause():
+assert(args.checkpoint_dir is not None)
+m5.checkpoint(args.checkpoint_dir)
+break
+else:
+print('Unknown exit event: %s. Continuing...'
+% exit_event.getCause())
+
 print('Exiting @ tick %i because %s' %
   (m5.curTick(), exit_event.getCause()))

diff --git a/configs/example/gpufs/system/amdgpu.py  
b/configs/example/gpufs/system/amdgpu.py

index b6bf821..b30892c 100644
--- a/configs/example/gpufs/system/amdgpu.py
+++ b/configs/example/gpufs/system/amdgpu.py
@@ -148,3 +148,5 @@

 system.pc.south_bridge.gpu.trace_file = args.gpu_mmio_trace
 system.pc.south_bridge.gpu.rom_binary = args.gpu_rom
+system.pc.south_bridge.gpu.checkpoint_before_mmios = \
+args.checkpoint_before_mmios
diff --git a/src/dev/amdgpu/AMDGPU.py b/src/dev/amdgpu/AMDGPU.py
index 29526c4..092a380 100644
--- a/src/dev/amdgpu/AMDGPU.py
+++ b/src/dev/amdgpu/AMDGPU.py
@@ -70,3 +70,5 @@

 rom_binary = Param.String("ROM binary dumped from hardware")
 trace_file = Param.String("MMIO trace collected on hardware")
+checkpoint_before_mmios = Param.Bool(False, "Take a checkpoint before  
the"
+" device begins sending  
MMIOs")
diff --git a/src/dev/amdgpu/amdgpu_device.cc  
b/src/dev/amdgpu/amdgpu_device.cc

index afe28f3..08e6987 100644
--- a/src/dev/amdgpu/amdgpu_device.cc
+++ b/src/dev/amdgpu/amdgpu_device.cc
@@ -40,9 +40,11 @@
 #include 

[gem5-dev] Change in gem5/gem5[develop]: dev-amdgpu: Implement MMIO trace reader

[Matthew Poremba (Gerrit) via gem5-dev]

Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46160 )


Change subject: dev-amdgpu: Implement MMIO trace reader
..

dev-amdgpu: Implement MMIO trace reader

Helper class to read Linux kernel MMIO trace from amdgpu modprobes. This
class is used rather than implementing MMIOs in code as it is easier to
update to newer kernel versions this way. It also helps with setting
values for registers which are not documented.

Based on https://gem5-review.googlesource.com/c/amd/gem5/+/23743

Change-Id: Ia9b85c269c98b6ae0d5bcfe89141a4c30ef2f914
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46160
Reviewed-by: Matt Sinclair 
Reviewed-by: Jason Lowe-Power 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/dev/amdgpu/SConscript
M src/dev/amdgpu/amdgpu_device.cc
M src/dev/amdgpu/amdgpu_device.hh
A src/dev/amdgpu/mmio_reader.cc
A src/dev/amdgpu/mmio_reader.hh
5 files changed, 400 insertions(+), 14 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/amdgpu/SConscript b/src/dev/amdgpu/SConscript
index 78b73ab..7c67e4c 100644
--- a/src/dev/amdgpu/SConscript
+++ b/src/dev/amdgpu/SConscript
@@ -38,5 +38,6 @@
 SimObject('AMDGPU.py')

 Source('amdgpu_device.cc')
+Source('mmio_reader.cc')

 DebugFlag('AMDGPUDevice')
diff --git a/src/dev/amdgpu/amdgpu_device.cc  
b/src/dev/amdgpu/amdgpu_device.cc

index e409be5..afe28f3 100644
--- a/src/dev/amdgpu/amdgpu_device.cc
+++ b/src/dev/amdgpu/amdgpu_device.cc
@@ -55,6 +55,10 @@
 } else {
 romRange = RangeSize(VGA_ROM_DEFAULT, ROM_SIZE);
 }
+
+if (p.trace_file != "") {
+mmioReader.readMMIOTrace(p.trace_file);
+}
 }

 void
@@ -124,36 +128,42 @@
 AMDGPUDevice::readFrame(PacketPtr pkt, Addr offset)
 {
 DPRINTF(AMDGPUDevice, "Read framebuffer address %#lx\n", offset);
+mmioReader.readFromTrace(pkt, FRAMEBUFFER_BAR, offset);
 }

 void
 AMDGPUDevice::readDoorbell(PacketPtr pkt, Addr offset)
 {
 DPRINTF(AMDGPUDevice, "Read doorbell %#lx\n", offset);
+mmioReader.readFromTrace(pkt, DOORBELL_BAR, offset);
 }

 void
-AMDGPUDevice::readMmio(PacketPtr pkt, Addr offset)
+AMDGPUDevice::readMMIO(PacketPtr pkt, Addr offset)
 {
 DPRINTF(AMDGPUDevice, "Read MMIO %#lx\n", offset);
+mmioReader.readFromTrace(pkt, MMIO_BAR, offset);
 }

 void
 AMDGPUDevice::writeFrame(PacketPtr pkt, Addr offset)
 {
 DPRINTF(AMDGPUDevice, "Wrote framebuffer address %#lx\n", offset);
+mmioReader.writeFromTrace(pkt, FRAMEBUFFER_BAR, offset);
 }

 void
 AMDGPUDevice::writeDoorbell(PacketPtr pkt, Addr offset)
 {
 DPRINTF(AMDGPUDevice, "Wrote doorbell %#lx\n", offset);
+mmioReader.writeFromTrace(pkt, DOORBELL_BAR, offset);
 }

 void
-AMDGPUDevice::writeMmio(PacketPtr pkt, Addr offset)
+AMDGPUDevice::writeMMIO(PacketPtr pkt, Addr offset)
 {
 DPRINTF(AMDGPUDevice, "Wrote MMIO %#lx\n", offset);
+mmioReader.writeFromTrace(pkt, MMIO_BAR, offset);
 }

 Tick
@@ -167,14 +177,14 @@
 getBAR(pkt->getAddr(), barnum, offset);

 switch (barnum) {
-  case 0:
+  case FRAMEBUFFER_BAR:
   readFrame(pkt, offset);
   break;
-  case 2:
+  case DOORBELL_BAR:
   readDoorbell(pkt, offset);
   break;
-  case 5:
-  readMmio(pkt, offset);
+  case MMIO_BAR:
+  readMMIO(pkt, offset);
   break;
   default:
 panic("Request with address out of mapped range!");
@@ -193,14 +203,14 @@
 getBAR(pkt->getAddr(), barnum, offset);

 switch (barnum) {
-  case 0:
+  case FRAMEBUFFER_BAR:
   writeFrame(pkt, offset);
   break;
-  case 2:
+  case DOORBELL_BAR:
   writeDoorbell(pkt, offset);
   break;
-  case 5:
-  writeMmio(pkt, offset);
+  case MMIO_BAR:
+  writeMMIO(pkt, offset);
   break;
   default:
 panic("Request with address out of mapped range!");
diff --git a/src/dev/amdgpu/amdgpu_device.hh  
b/src/dev/amdgpu/amdgpu_device.hh

index 0cff651..892d021 100644
--- a/src/dev/amdgpu/amdgpu_device.hh
+++ b/src/dev/amdgpu/amdgpu_device.hh
@@ -37,11 +37,17 @@
 #include 

 #include "base/bitunion.hh"
+#include "dev/amdgpu/mmio_reader.hh"
 #include "dev/io_device.hh"
 #include "dev/pci/device.hh"
 #include "params/AMDGPUDevice.hh"

-// By default (no expansion enabled), X86 kernel expects the vga ROM at  
0xc

+/* Names of BARs used by the device. */
+constexpr int FRAMEBUFFER_BAR = 0;
+constexpr int DOORBELL_BAR = 2;
+constexpr int MMIO_BAR = 5;
+
+/* By default the X86 kernel expects the vga ROM at 0xc. */
 constexpr uint32_t VGA_ROM_DEFAULT = 0xc;
 constexpr uint32_t ROM_SIZE = 0x2;// 128kB

@@ -67,15 +73,15 

[gem5-dev] Change in gem5/gem5[develop]: dev-amdgpu: Handle framebuffer counter accesses

[Matthew Poremba (Gerrit) via gem5-dev]

Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46163 )


Change subject: dev-amdgpu: Handle framebuffer counter accesses
..

dev-amdgpu: Handle framebuffer counter accesses

There are special counters in the framebuffer that are tested during
driver initialization. The expected behavior of the counters is to
return the previously read value + 1. There is one (known) counter used
in driver initialization at a fixed BAR address offset.

Change-Id: Id2dbb5fa9365b0a0453b15013c45aa67a2eec190
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46163
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
---
M src/dev/amdgpu/amdgpu_device.cc
1 file changed, 13 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/amdgpu/amdgpu_device.cc  
b/src/dev/amdgpu/amdgpu_device.cc

index 08e6987..23d22bb 100644
--- a/src/dev/amdgpu/amdgpu_device.cc
+++ b/src/dev/amdgpu/amdgpu_device.cc
@@ -148,7 +148,20 @@
 AMDGPUDevice::readFrame(PacketPtr pkt, Addr offset)
 {
 DPRINTF(AMDGPUDevice, "Read framebuffer address %#lx\n", offset);
+
 mmioReader.readFromTrace(pkt, FRAMEBUFFER_BAR, offset);
+
+/* Handle special counter addresses in framebuffer. */
+if (offset == 0xa28000) {
+/* Counter addresses expect the read to return previous value + 1.  
*/

+if (regs.find(pkt->getAddr()) == regs.end()) {
+regs[pkt->getAddr()] = 1;
+} else {
+regs[pkt->getAddr()]++;
+}
+
+pkt->setUintX(regs[pkt->getAddr()], ByteOrder::little);
+}
 }

 void



4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id2dbb5fa9365b0a0453b15013c45aa67a2eec190
Gerrit-Change-Number: 46163
Gerrit-PatchSet: 6
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons,python: revert Always generate default create() methods.

[Jason Lowe-Power (Gerrit) via gem5-dev]

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46819 )



Change subject: scons,python: revert Always generate default create()  
methods.

..

scons,python: revert Always generate default create() methods.

This reverts commit 7bb690c1ee70b1c82b23eeb68dcda3dc6e5c97f7.

Change-Id: If1b44162b24409fb44daec0159852fa44937184d
---
M src/SConscript
M src/python/m5/SimObject.py
2 files changed, 72 insertions(+), 94 deletions(-)



diff --git a/src/SConscript b/src/SConscript
index cc51b9f..d8e8249 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -976,7 +976,7 @@
 # Create all of the SimObject param headers and enum headers
 #

-def createSimObjectParamDecl(target, source, env):
+def createSimObjectParamStruct(target, source, env):
 assert len(target) == 1 and len(source) == 1

 name = source[0].get_text_contents()
@@ -986,16 +986,6 @@
 obj.cxx_param_decl(code)
 code.write(target[0].abspath)

-def createSimObjectParamDef(target, source, env):
-assert len(target) == 1 and len(source) == 1
-
-name = source[0].get_text_contents()
-obj = sim_objects[name]
-
-code = code_formatter()
-obj.cxx_param_def(code)
-code.write(target[0].abspath)
-
 def createSimObjectCxxConfig(is_header):
 def body(target, source, env):
 assert len(target) == 1 and len(source) == 1
@@ -1056,16 +1046,9 @@
 hh_file = File('params/%s.hh' % name)
 params_hh_files.append(hh_file)
 env.Command(hh_file, Value(name),
-MakeAction(createSimObjectParamDecl,  
Transform("SOPARMHH")))
+MakeAction(createSimObjectParamStruct, Transform("SO  
PARAM")))

 env.Depends(hh_file, depends + extra_deps)

-if not getattr(simobj, 'abstract', False) and hasattr(simobj, 'type'):
-cc_file = File('params/%s.cc' % name)
-env.Command(cc_file, Value(name),
-MakeAction(createSimObjectParamDef,  
Transform("SOPARMCC")))

-env.Depends(cc_file, depends + extra_deps)
-Source(cc_file)
-
 # C++ parameter description files
 if GetOption('with_cxx_config'):
 for name,simobj in sorted(sim_objects.items()):
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index bb17a38..88abc43 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -368,7 +368,7 @@

 if not is_header:
 code('{')
-if getattr(simobj, 'abstract', False):
+if hasattr(simobj, 'abstract') and simobj.abstract:
 code('return NULL;')
 else:
 code('return this->create();')
@@ -700,80 +700,6 @@
 def pybind_predecls(cls, code):
 code('#include "${{cls.cxx_header}}"')

-def cxx_param_def(cls, code):
-code('''
-#include 
-
-#include "base/compiler.hh"
-
-#include "${{cls.cxx_header}}"
-#include "params/${cls}.hh"
-
-''')
-code()
-code('namespace')
-code('{')
-code()
-# If we can't define a default create() method for this params  
struct

-# because the SimObject doesn't have the right constructor, use
-# template magic to make it so we're actually defining a create  
method

-# for this class instead.
-code('class Dummy${cls}ParamsClass')
-code('{')
-code('  public:')
-code('${{cls.cxx_class}} *create() const;')
-code('};')
-code()
-code('template ')
-code('class Dummy${cls}Shunt;')
-code()
-# This version directs to the real Params struct and the default
-# behavior of create if there's an appropriate constructor.
-code('template ')
-code('class Dummy${cls}Shunt::value>>')
-code('{')
-code('  public:')
-code('using Params = ${cls}Params;')
-code('static ${{cls.cxx_class}} *')
-code('create(const Params )')
-code('{')
-code('return new CxxClass(p);')
-code('}')
-code('};')
-code()
-# This version diverts to the DummyParamsClass and a dummy
-# implementation of create if the appropriate constructor does not
-# exist.
-code('template ')
-code('class Dummy${cls}Shunt::value>>')
-code('{')
-code('  public:')
-code('using Params = Dummy${cls}ParamsClass;')
-code('static ${{cls.cxx_class}} *')
-code('create(const Params )')
-code('{')
-code('return nullptr;')
-code('}')
-code('};')
-code()
-code('} // anonymous namespace')
-code()
-# An implementation of either the real Params struct's create
-# method, or the Dummy one. Either an implementation is
-# mandantory since this was shunted off to the dummy class, or
-# one is optional which will override 

[gem5-dev] Change in gem5/gem5[develop]: python,scons: Only generate pybind if using python

[Jason Lowe-Power (Gerrit) via gem5-dev]

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46820 )



Change subject: python,scons: Only generate pybind if using python
..

python,scons: Only generate pybind if using python

This reimplements the previously reverted change: Always generate default
create() methods.

The pybind code should only be generated when python is enabled. This
change passes whether python is enabled into the SimObject code creation
method. Then, the params code is optionally included.

Note: Due to some problems in GCC's linker (or something else...) we
need to have a single file with all of the generated code for the
SimObject.

Change-Id: I0f93b3d787d47f26db2de6c4447730f7df87a0dc
Issue-on: https://gem5.atlassian.net/browse/GEM5-1003
Signed-off-by: Jason Lowe-Power 
---
M src/SConscript
M src/python/m5/SimObject.py
2 files changed, 105 insertions(+), 84 deletions(-)



diff --git a/src/SConscript b/src/SConscript
index d8e8249..ef6207e 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -1021,12 +1021,16 @@
 obj.cxx_decl(code)
 code.write(target[0].abspath)

-def createSimObjectPyBindWrapper(target, source, env):
+def createSimObjectWrappers(target, source, env):
 name = source[0].get_text_contents()
 obj = sim_objects[name]

 code = code_formatter()
-obj.pybind_decl(code)
+# We want to generate a single .cc file which contains most of the
+# SimObject autogenerated code to reduce the number of files to  
compile and

+# link. We need to pass in whether python is enabled so that the pybind
+# wrappers are only generated when python is enabled
+obj.params_create_decl(code, env['USE_PYTHON'])
 code.write(target[0].abspath)

 # Generate all of the SimObject param C++ struct header files
@@ -1120,17 +1124,16 @@
 MakeAction(createEnumDecls, Transform("ENUMDECL")))
 env.Depends(hh_file, depends + extra_deps)

-# Generate SimObject Python bindings wrapper files
-if env['USE_PYTHON']:
-for name,simobj in sorted(sim_objects.items()):
-py_source = PySource.modules[simobj.__module__]
-extra_deps = [ py_source.tnode ]
-cc_file = File('python/_m5/param_%s.cc' % name)
-env.Command(cc_file, Value(name),
-MakeAction(createSimObjectPyBindWrapper,
-   Transform("SO PyBind")))
-env.Depends(cc_file, depends + extra_deps)
-Source(cc_file)
+# Generate SimObject Python bindings and create method wrapper files
+for name,simobj in sorted(sim_objects.items()):
+py_source = PySource.modules[simobj.__module__]
+extra_deps = [ py_source.tnode ]
+cc_file = File('python/_m5/param_%s.cc' % name)
+env.Command(cc_file, Value(name),
+MakeAction(createSimObjectWrappers,
+Transform("SO PyBind/Create")))
+env.Depends(cc_file, depends + extra_deps)
+Source(cc_file)

 #
 # Handle debug flags
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index 88abc43..ec3ae06 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -700,103 +700,121 @@
 def pybind_predecls(cls, code):
 code('#include "${{cls.cxx_header}}"')

-def pybind_decl(cls, code):
+def params_create_decl(cls, code, python_enabled):
 py_class_name = cls.pybind_class

 # The 'local' attribute restricts us to the params declared in
 # the object itself, not including inherited params (which
 # will also be inherited from the base class's param struct
 # here). Sort the params based on their key
-params = list(map(lambda k_v: k_v[1],  
sorted(cls._params.local.items(

+params = list(map(lambda k_v: k_v[1],
+  sorted(cls._params.local.items(
 ports = cls._ports.local

-code('''#include "pybind11/pybind11.h"
-#include "pybind11/stl.h"
+# only include pybind if python is enabled in the build
+if python_enabled:

-#include 
+code('''#include "pybind11/pybind11.h"
+#include "pybind11/stl.h"

-#include "base/compiler.hh"
-#include "params/$cls.hh"
-#include "python/pybind11/core.hh"
-#include "sim/init.hh"
-#include "sim/sim_object.hh"
+#include 

-#include "${{cls.cxx_header}}"
+#include "base/compiler.hh"
+#include "params/$cls.hh"
+#include "python/pybind11/core.hh"
+#include "sim/init.hh"
+#include "sim/sim_object.hh"
+
+#include "${{cls.cxx_header}}"

 ''')
+else:
+code('''
+#include 

-for param in params:
-param.pybind_predecls(code)
+#include "base/compiler.hh"
+#include "params/$cls.hh"

-code('''namespace py = pybind11;
+#include "${{cls.cxx_header}}"
+
+''')
+# only include the python params code if python is enabled.
+if python_enabled:
+  

[gem5-dev] Change in gem5/gem5[develop]: util: Fix typo in cpt upgrader

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46799 )



Change subject: util: Fix typo in cpt upgrader
..

util: Fix typo in cpt upgrader

The module is errno, not ennro.

Change-Id: I3f17bdc12a7acd680ac407042a75d5099f5f7339
Signed-off-by: Daniel R. Carvalho 
---
M util/cpt_upgrader.py
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/util/cpt_upgrader.py b/util/cpt_upgrader.py
index ee82a7a..0639dc1 100755
--- a/util/cpt_upgrader.py
+++ b/util/cpt_upgrader.py
@@ -185,7 +185,7 @@
 def process_file(path, **kwargs):
 if not osp.isfile(path):
 import errno
-raise IOError(ennro.ENOENT, "No such file", path)
+raise IOError(errno.ENOENT, "No such file", path)

 verboseprint("Processing file %s" % path)


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3f17bdc12a7acd680ac407042a75d5099f5f7339
Gerrit-Change-Number: 46799
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Implement basic HTM capabilities in the CheckerCPU

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46624 )


Change subject: cpu: Implement basic HTM capabilities in the CheckerCPU
..

cpu: Implement basic HTM capabilities in the CheckerCPU

The O3CPU, which supports transactional memory (HTM), is using
the inHtmTransactionalState and getHtmCheckpointPtr methods
to check if we are in the middle of a transaction and return
false or a nullptr if that's not the case.

We need to avoid aborting simulation (panic) when those methods are
called in the O3CPU + Checker simulation.

This patch is providing the minimal support to re-enable O3 + Checker
runs and it is not providing HTM support in the CheckerCPU (meaning, we
won't be able to use the Checker in a transactional simulation)

Signed-off-by: Giacomo Travaglini 
Change-Id: I7f71d5290c53b0402763d69f137ecaa1208253fb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46624
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Richard Cooper 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/cpu/checker/cpu.hh
M src/cpu/checker/thread_context.hh
2 files changed, 5 insertions(+), 6 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Richard Cooper: Looks good to me, but someone else must approve
  kokoro: Regressions pass



diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 6d19174..b6c3747 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011, 2016-2018, 2020 ARM Limited
+ * Copyright (c) 2011, 2016-2018, 2020-2021 Arm Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -380,15 +380,14 @@
 bool
 inHtmTransactionalState() const override
 {
-panic("not yet supported!");
-return false;
+return (getHtmTransactionalDepth() > 0);
 }

 uint64_t
 getHtmTransactionalDepth() const override
 {
-panic("not yet supported!");
-return 0;
+assert(thread->htmTransactionStarts >=  
thread->htmTransactionStops);
+return (thread->htmTransactionStarts -  
thread->htmTransactionStops);

 }

 TheISA::PCState pcState() const override { return thread->pcState(); }
diff --git a/src/cpu/checker/thread_context.hh  
b/src/cpu/checker/thread_context.hh

index 1e961c5..9a00488 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -497,7 +497,7 @@
 BaseHTMCheckpointPtr&
 getHtmCheckpointPtr() override
 {
-panic("function not implemented");
+return actualTC->getHtmCheckpointPtr();
 }

 void

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7f71d5290c53b0402763d69f137ecaa1208253fb
Gerrit-Change-Number: 46624
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Build failed in Jenkins: weekly #30

[jenkins-no-reply--- via gem5-dev]

See 

Changes:

[Bobby R. Bruce] tests: Revert "Add sleep and debug to the jenkins ..."

[odanrc] cpu-kvm: Fix missing includes

[odanrc] mem-ruby: Appease compiler with return values

[arthurperais] mem: Fix bandwidth-delay calculation in AMPM prefetcher

[odanrc] systemc: Fix module not found

[odanrc] util,systemc: Fix create and params signature

[odanrc] util: Rename recently renamed namespaces

[mytbk920423] dev: add a falsely removed if condition check in commit 03a00e5d3

[mytbk920423] systemc: include 

[hoanguyen] util: Make sorted includes verifier less confusing

[yazakram] arch-riscv: Update the way a valid virtual address is computed

[garbage2collector] mem-ruby: Fix wrong test in CHI functional reads

[garbage2collector] mem-ruby: Rename WriteMask::cmpMask to containsMask

[garbage2collector] mem-ruby: Fix RubySystem::functionalRead with partial data

[hoanguyen] configs: Improve error message of missing files

[tom.rollet] cpu-o3: fix dispatch assert triggering on debug mode

[tom.rollet] cpu-o3: fix commit DPRINTF ROB arguments order

[Giacomo Travaglini] arch-arm: Remove Stage2MMU

[tom.rollet] cpu-o3: Add loadToUse stat

[Giacomo Travaglini] cpu: Fix import in O3 CheckerCPU

[Giacomo Travaglini] cpu: Fix MMU port addition from the CheckerCPU

[Giacomo Travaglini] cpu: Do not generate a DTB node in the CheckerCPU

[Giacomo Travaglini] cpu: Register the ThreadContext in the CheckerCPU's ISA

[Giacomo Travaglini] arch-arm: Remove stage2 TLBI flushes from stage1 flushes

[Giacomo Travaglini] arch-arm: Remove the TLB::flush overload for TLBI IPA

[Bobby R. Bruce] tests: Move compiler-tests.sh script from "util" to "tests"

[Bobby R. Bruce] tests: Add nightly tests script to the gem5 repo


--
[...truncated 573.75 KB...]
 [ CXX] GCN3_X86/cpu/pred/multiperspective_perceptron_8KB.cc -> .o
 [SOPARMHH] MultiperspectivePerceptron64KB -> 
GCN3_X86/params/MultiperspectivePerceptron64KB.hh
 [ CXX] GCN3_X86/cpu/pred/multiperspective_perceptron_64KB.cc -> .o
 [SOPARMHH] MPP_LoopPredictor -> GCN3_X86/params/MPP_LoopPredictor.hh
 [SOPARMHH] MPP_StatisticalCorrector -> 
GCN3_X86/params/MPP_StatisticalCorrector.hh
 [SOPARMHH] MPP_TAGE -> GCN3_X86/params/MPP_TAGE.hh
 [SOPARMHH] MultiperspectivePerceptronTAGE -> 
GCN3_X86/params/MultiperspectivePerceptronTAGE.hh
 [SOPARMHH] StatisticalCorrector -> GCN3_X86/params/StatisticalCorrector.hh
 [ CXX] GCN3_X86/cpu/pred/multiperspective_perceptron_tage.cc -> .o
 [SOPARMHH] MPP_LoopPredictor_8KB -> GCN3_X86/params/MPP_LoopPredictor_8KB.hh
 [SOPARMHH] MPP_StatisticalCorrector_8KB -> 
GCN3_X86/params/MPP_StatisticalCorrector_8KB.hh
 [SOPARMHH] MPP_TAGE_8KB -> GCN3_X86/params/MPP_TAGE_8KB.hh
 [SOPARMHH] MultiperspectivePerceptronTAGE8KB -> 
GCN3_X86/params/MultiperspectivePerceptronTAGE8KB.hh
 [ CXX] GCN3_X86/cpu/pred/multiperspective_perceptron_tage_8KB.cc -> .o
 [SOPARMHH] MPP_StatisticalCorrector_64KB -> 
GCN3_X86/params/MPP_StatisticalCorrector_64KB.hh
 [SOPARMHH] MultiperspectivePerceptronTAGE64KB -> 
GCN3_X86/params/MultiperspectivePerceptronTAGE64KB.hh
 [ CXX] GCN3_X86/cpu/pred/multiperspective_perceptron_tage_64KB.cc -> .o
 [ CXX] GCN3_X86/cpu/pred/statistical_corrector.cc -> .o
 [ TRACING]  -> GCN3_X86/debug/TageSCL.hh
 [SOPARMHH] TAGE_SC_L -> GCN3_X86/params/TAGE_SC_L.hh
 [SOPARMHH] TAGE_SC_L_LoopPredictor -> 
GCN3_X86/params/TAGE_SC_L_LoopPredictor.hh
 [SOPARMHH] TAGE_SC_L_TAGE -> GCN3_X86/params/TAGE_SC_L_TAGE.hh
 [ CXX] GCN3_X86/cpu/pred/tage_sc_l.cc -> .o
 [SOPARMHH] TAGE_SC_L_8KB -> GCN3_X86/params/TAGE_SC_L_8KB.hh
 [SOPARMHH] TAGE_SC_L_8KB_StatisticalCorrector -> 
GCN3_X86/params/TAGE_SC_L_8KB_StatisticalCorrector.hh
 [SOPARMHH] TAGE_SC_L_TAGE_8KB -> GCN3_X86/params/TAGE_SC_L_TAGE_8KB.hh
 [ CXX] GCN3_X86/cpu/pred/tage_sc_l_8KB.cc -> .o
 [SOPARMHH] TAGE_SC_L_64KB -> GCN3_X86/params/TAGE_SC_L_64KB.hh
 [SOPARMHH] TAGE_SC_L_64KB_StatisticalCorrector -> 
GCN3_X86/params/TAGE_SC_L_64KB_StatisticalCorrector.hh
 [SOPARMHH] TAGE_SC_L_TAGE_64KB -> GCN3_X86/params/TAGE_SC_L_TAGE_64KB.hh
 [ CXX] GCN3_X86/cpu/pred/tage_sc_l_64KB.cc -> .o
 [ CXX] GCN3_X86/cpu/testers/gpu_ruby_test/address_manager.cc -> .o
 [SOPARMHH] ProtocolTester -> GCN3_X86/params/ProtocolTester.hh
 [SOPARMHH] CpuThread -> GCN3_X86/params/CpuThread.hh
 [SOPARMHH] DmaThread -> GCN3_X86/params/DmaThread.hh
 [SOPARMHH] GpuWavefront -> GCN3_X86/params/GpuWavefront.hh
 [SOPARMHH] TesterThread -> GCN3_X86/params/TesterThread.hh
 [ CXX] GCN3_X86/cpu/testers/gpu_ruby_test/episode.cc -> .o
 [ TRACING]  -> GCN3_X86/debug/ProtocolTest.hh
 [ CXX] GCN3_X86/cpu/testers/gpu_ruby_test/protocol_tester.cc -> .o
 [ CXX] GCN3_X86/cpu/testers/gpu_ruby_test/cpu_thread.cc -> .o
 [ CXX] GCN3_X86/cpu/testers/gpu_ruby_test/dma_thread.cc -> .o
 [ CXX] GCN3_X86/cpu/testers/gpu_ruby_test/gpu_wavefront.cc -> .o
 [ CXX]