[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: Add Data Abort handler for Atomic Instructions
Bobby R. Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/35295 )
Change subject: cpu-o3: Add Data Abort handler for Atomic Instructions
..
cpu-o3: Add Data Abort handler for Atomic Instructions
Bug fixing patch for Data Abort exception when executing an
atomic instruction. You can see the details in this JIRA ticket:
https://gem5.atlassian.net/browse/GEM5-784
Change-Id: I79e7113efd8157fba61b6d4a0b0c09bc6f85ec29
Signed-off-by: Víctor Soria
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35295
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/cpu/o3/lsq_unit.cc
1 file changed, 11 insertions(+), 0 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/o3/lsq_unit.cc b/src/cpu/o3/lsq_unit.cc
index 039184d..34f65b9 100644
--- a/src/cpu/o3/lsq_unit.cc
+++ b/src/cpu/o3/lsq_unit.cc
@@ -700,6 +700,17 @@
DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n",
store_inst->pcState(), store_inst->seqNum);
+if (store_inst->isAtomic()) {
+// If the instruction faulted, then we need to send it along
+// to commit without the instruction completing.
+if (!(store_inst->hasRequest() &&
store_inst->strictlyOrdered()) ||
+store_inst->isAtCommit()) {
+store_inst->setExecuted();
+}
+iewStage->instToCommit(store_inst);
+iewStage->activityThisCycle();
+}
+
return store_fault;
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I79e7113efd8157fba61b6d4a0b0c09bc6f85ec29
Gerrit-Change-Number: 35295
Gerrit-PatchSet: 4
Gerrit-Owner: Victor Soria
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jordi Vaquero
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Allow clean non-interactive builds
Eric Ye has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/50410 )
Change subject: scons: Allow clean non-interactive builds
..
scons: Allow clean non-interactive builds
On a clean build, the git tool will wait for input() before installing
git hooks. Allow bypassing this via a command-line flag, making it
possible to perform a clean build non-interactively.
Bug: 199780674
Test: build_gem5 --install-hooks
Change-Id: I48be2c1a7c2335a2f4f6359adf582ca8b0ae5939
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50410
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M SConstruct
M site_scons/site_tools/git.py
2 files changed, 11 insertions(+), 5 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/SConstruct b/SConstruct
index a865e09..de7cdef 100755
--- a/SConstruct
+++ b/SConstruct
@@ -123,6 +123,8 @@
help='Build with Address Sanitizer if available')
AddOption('--with-systemc-tests', action='store_true',
help='Build systemc tests')
+AddOption('--install-hooks', action='store_true',
+ help='Install revision control hooks non-interactively')
# Imports of gem5_scons happen here since it depends on some options which
are
# declared above.
diff --git a/site_scons/site_tools/git.py b/site_scons/site_tools/git.py
index 3a71c9f..e95c62f 100644
--- a/site_scons/site_tools/git.py
+++ b/site_scons/site_tools/git.py
@@ -42,6 +42,7 @@
import sys
import gem5_scons.util
+import SCons.Script
git_style_message = """
You're missing the gem5 style or commit message hook. These hooks help
@@ -99,11 +100,14 @@
return
print(git_style_message, end=' ')
-try:
-input()
-except:
-print("Input exception, exiting scons.\n")
-sys.exit(1)
+if SCons.Script.GetOption('install-hooks'):
+print("Installing revision control hooks automatically.")
+else:
+try:
+input()
+except:
+print("Input exception, exiting scons.\n")
+sys.exit(1)
git_style_script = env.Dir("#util").File("git-pre-commit.py")
git_msg_script = env.Dir("#ext").File("git-commit-msg")
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I48be2c1a7c2335a2f4f6359adf582ca8b0ae5939
Gerrit-Change-Number: 50410
Gerrit-PatchSet: 5
Gerrit-Owner: Eric Ye
Gerrit-Reviewer: Eric Ye
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: kokoro
Gerrit-CC: Jason Lowe-Power
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Remove unused TLBType
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50527 )
Change subject: arch-arm: Remove unused TLBType
..
arch-arm: Remove unused TLBType
The cached state is global now (per-MMU)
Change-Id: I70bc847813086f678b4ff32722b7f6e3ceaae6f5
Signed-off-by: Giacomo Travaglini
---
M src/arch/arm/isa.cc
M src/arch/arm/mmu.cc
M src/arch/arm/mmu.hh
3 files changed, 4 insertions(+), 14 deletions(-)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 8d5addc..9439d0e 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -905,10 +905,7 @@
CPSR old_cpsr = miscRegs[MISCREG_CPSR];
int old_mode = old_cpsr.mode;
CPSR cpsr = val;
-if (cpsr.pan != old_cpsr.pan) {
-getMMUPtr(tc)->invalidateMiscReg(MMU::D_TLBS);
-}
-if (cpsr.il != old_cpsr.il) {
+if (cpsr.pan != old_cpsr.pan || cpsr.il != old_cpsr.il) {
getMMUPtr(tc)->invalidateMiscReg();
}
@@ -2271,7 +2268,7 @@
case MISCREG_PAN:
{
// PAN is affecting data accesses
-getMMUPtr(tc)->invalidateMiscReg(MMU::D_TLBS);
+getMMUPtr(tc)->invalidateMiscReg();
CPSR cpsr = miscRegs[MISCREG_CPSR];
cpsr.pan = (uint8_t) ((CPSR) newVal).pan;
diff --git a/src/arch/arm/mmu.cc b/src/arch/arm/mmu.cc
index d2fc706..5f0b64e 100644
--- a/src/arch/arm/mmu.cc
+++ b/src/arch/arm/mmu.cc
@@ -160,7 +160,7 @@
}
void
-MMU::invalidateMiscReg(TLBType type)
+MMU::invalidateMiscReg()
{
s1State.miscRegValid = false;
}
diff --git a/src/arch/arm/mmu.hh b/src/arch/arm/mmu.hh
index 0e1fd87..f6ebd89 100644
--- a/src/arch/arm/mmu.hh
+++ b/src/arch/arm/mmu.hh
@@ -117,13 +117,6 @@
S12E1Tran = 0x100
};
-enum TLBType
-{
-I_TLBS = 0x01,
-D_TLBS = 0x10,
-ALL_TLBS = 0x11
-};
-
struct CachedState {
explicit CachedState(MMU *_mmu, bool stage2)
: mmu(_mmu), isStage2(stage2)
@@ -250,7 +243,7 @@
void takeOverFrom(BaseMMU *old_mmu) override;
-void invalidateMiscReg(TLBType type = ALL_TLBS);
+void invalidateMiscReg();
template
void
--
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Gerrit-Change-Id: I70bc847813086f678b4ff32722b7f6e3ceaae6f5
Gerrit-Change-Number: 50527
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Define ArmFault::invoke32 to match invoke64
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50507 )
Change subject: arch-arm: Define ArmFault::invoke32 to match invoke64
..
arch-arm: Define ArmFault::invoke32 to match invoke64
Just providing some symmetry to the ArmFault::invoke method
Change-Id: I244e69eee684b9935bea49cf28c6ed99a01192bf
Signed-off-by: Giacomo Travaglini
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
2 files changed, 17 insertions(+), 10 deletions(-)
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 102ce84..69366af 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -497,15 +497,20 @@
if (to64) {
// Invoke exception handler in AArch64 state
invoke64(tc, inst);
-return;
+} else {
+// Invoke exception handler in AArch32 state
+invoke32(tc, inst);
}
+}
+void
+ArmFault::invoke32(ThreadContext *tc, const StaticInstPtr )
+{
if (vectorCatch(tc, inst))
return;
// ARMv7 (ARM ARM issue C B1.9)
-
-bool have_security = ArmSystem::haveSecurity(tc);
+bool have_security = ArmSystem::haveSecurity(tc);
FaultBase::invoke(tc);
if (!FullSystem)
@@ -520,7 +525,7 @@
saved_cpsr.v = tc->readCCReg(CCREG_V);
saved_cpsr.ge = tc->readCCReg(CCREG_GE);
-[[maybe_unused]] Addr curPc = tc->pcState().pc();
+[[maybe_unused]] Addr cur_pc = tc->pcState().pc();
ITSTATE it = tc->pcState().itstate();
saved_cpsr.it2 = it.top6;
saved_cpsr.it1 = it.bottom2;
@@ -578,10 +583,10 @@
tc->setMiscReg(MISCREG_LOCKFLAG, 0);
if (cpsr.mode == MODE_HYP) {
-tc->setMiscReg(MISCREG_ELR_HYP, curPc +
+tc->setMiscReg(MISCREG_ELR_HYP, cur_pc +
(saved_cpsr.t ? thumbPcOffset(true) : armPcOffset(true)));
} else {
-tc->setIntReg(INTREG_LR, curPc +
+tc->setIntReg(INTREG_LR, cur_pc +
(saved_cpsr.t ? thumbPcOffset(false) :
armPcOffset(false)));
}
@@ -616,12 +621,12 @@
panic("unknown Mode\n");
}
-Addr newPc = getVector(tc);
+Addr new_pc = getVector(tc);
DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x "
-"%s\n", name(), cpsr, curPc, tc->readIntReg(INTREG_LR),
-newPc, arm_inst ? csprintf("inst: %#x", arm_inst->encoding()) :
+"%s\n", name(), cpsr, cur_pc, tc->readIntReg(INTREG_LR),
+new_pc, arm_inst ? csprintf("inst: %#x",
arm_inst->encoding()) :
std::string());
-PCState pc(newPc);
+PCState pc(new_pc);
pc.thumb(cpsr.t);
pc.nextThumb(pc.thumb());
pc.jazelle(cpsr.j);
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 6d5411f..139d477 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -226,6 +226,8 @@
void invoke(ThreadContext *tc, const StaticInstPtr =
nullStaticInstPtr) override;
+void invoke32(ThreadContext *tc, const StaticInstPtr =
+ nullStaticInstPtr);
void invoke64(ThreadContext *tc, const StaticInstPtr =
nullStaticInstPtr);
void update(ThreadContext *tc);
--
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Gerrit-Change-Id: I244e69eee684b9935bea49cf28c6ed99a01192bf
Gerrit-Change-Number: 50507
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Syncronize GIC CPU interface when changing EL
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50508 )
Change subject: arch-arm: Syncronize GIC CPU interface when changing EL
..
arch-arm: Syncronize GIC CPU interface when changing EL
From the GIC architecture specification (ihi0069) [1]
"The assertion and de-assertion of IRQs and FIQs are affected by the
current Exception level and Security state of the PE. As part of the
Context Synchronization that occurs as the result of taking or returning
from an exception, the CPU interface ensures that IRQ and FIQ are both
appropriately asserted or deasserted for the Exception level and
Security state that the PE is entering."
[1]: https://developer.arm.com/documentation/ihi0069/latest
Change-Id: I10444a3aad5c06aabc13e1cbd70a32192531a31d
Signed-off-by: Giacomo Travaglini
---
M src/arch/arm/isa.cc
M src/dev/arm/gic_v3_cpu_interface.hh
2 files changed, 28 insertions(+), 5 deletions(-)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 51856ca..8d5addc 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -905,13 +905,12 @@
CPSR old_cpsr = miscRegs[MISCREG_CPSR];
int old_mode = old_cpsr.mode;
CPSR cpsr = val;
-if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) {
-getMMUPtr(tc)->invalidateMiscReg();
-}
-
if (cpsr.pan != old_cpsr.pan) {
getMMUPtr(tc)->invalidateMiscReg(MMU::D_TLBS);
}
+if (cpsr.il != old_cpsr.il) {
+getMMUPtr(tc)->invalidateMiscReg();
+}
DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d
mode:%#x\n",
miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a,
cpsr.mode);
@@ -931,6 +930,24 @@
} else {
tc->pcState(pc);
}
+
+setMiscRegNoEffect(misc_reg, newVal);
+
+if (old_mode != cpsr.mode) {
+getMMUPtr(tc)->invalidateMiscReg();
+if (gicv3CpuInterface) {
+// The assertion and de-assertion of IRQs and FIQs are
+// affected by the current Exception level and Security
+// state of the PE. As part of the Context
+// Synchronization that occurs as the result of taking
+// or returning from an exception, the CPU interface
+// ensures that IRQ and FIQ are both appropriately
+// asserted or deasserted for the Exception level and
+// Security state that the PE is entering.
+static_cast(
+getGICv3CPUInterface()).update();
+}
+}
} else {
#ifndef NDEBUG
if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
@@ -2333,8 +2350,8 @@
tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits() >> 7)
- 1);
break;
}
+setMiscRegNoEffect(misc_reg, newVal);
}
-setMiscRegNoEffect(misc_reg, newVal);
}
BaseISADevice &
diff --git a/src/dev/arm/gic_v3_cpu_interface.hh
b/src/dev/arm/gic_v3_cpu_interface.hh
index 9f60d84..7058d66 100644
--- a/src/dev/arm/gic_v3_cpu_interface.hh
+++ b/src/dev/arm/gic_v3_cpu_interface.hh
@@ -50,12 +50,18 @@
class Gicv3Distributor;
class Gicv3Redistributor;
+namespace ArmISA
+{
+class ISA;
+}
+
class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
{
private:
friend class Gicv3Distributor;
friend class Gicv3Redistributor;
+friend class ArmISA::ISA;
protected:
--
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[gem5-dev] Change in gem5/gem5[develop]: cpu-minor: Fix for minor CPU scoreboard
Daecheol You has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/50287 )
Change subject: cpu-minor: Fix for minor CPU scoreboard
..
cpu-minor: Fix for minor CPU scoreboard
When the scoreboard checks RAW dependency, it determines whether
the source registers can be forwarded or not to evaluate
relative latency. To do that, fuIndices[index] should be used
as an index for accessing cant_forward_from_fu_indices, not register
index itself. Moreover, since fuIndices[index] is cleared as -1
by clearInstDests(), the first compare should be fuIndices[index] != -1
instead of 1.
Change-Id: Ic62546855a8ad5365064d2ea2e2a0fbc1ccc6f41
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50287
Reviewed-by: ZHENGRONG WANG
Maintainer: ZHENGRONG WANG
Tested-by: kokoro
---
M src/cpu/minor/scoreboard.cc
M src/cpu/minor/scoreboard.hh
2 files changed, 7 insertions(+), 5 deletions(-)
Approvals:
ZHENGRONG WANG: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/minor/scoreboard.cc b/src/cpu/minor/scoreboard.cc
index b957c3d..4637b8d 100644
--- a/src/cpu/minor/scoreboard.cc
+++ b/src/cpu/minor/scoreboard.cc
@@ -195,7 +195,7 @@
if (numResults[index] == 0) {
returnCycle[index] = Cycles(0);
writingInst[index] = 0;
-fuIndices[index] = -1;
+fuIndices[index] = invalidFUIndex;
}
DPRINTF(MinorScoreboard, "Clearing inst: %s"
@@ -245,10 +245,11 @@
unsigned short int index;
if (findIndex(reg, index)) {
-bool cant_forward = fuIndices[index] != 1 &&
+int src_reg_fu = fuIndices[index];
+bool cant_forward = src_reg_fu != invalidFUIndex &&
cant_forward_from_fu_indices &&
-index < cant_forward_from_fu_indices->size() &&
-(*cant_forward_from_fu_indices)[index];
+src_reg_fu < cant_forward_from_fu_indices->size() &&
+(*cant_forward_from_fu_indices)[src_reg_fu];
Cycles relative_latency = (cant_forward ? Cycles(0) :
(src_index >= num_relative_latencies ?
diff --git a/src/cpu/minor/scoreboard.hh b/src/cpu/minor/scoreboard.hh
index a928444..3ae0b65 100644
--- a/src/cpu/minor/scoreboard.hh
+++ b/src/cpu/minor/scoreboard.hh
@@ -96,6 +96,7 @@
/** Index of the FU generating this result */
std::vector fuIndices;
+static constexpr int invalidFUIndex = -1;
/** The estimated cycle number that the result will be presented.
* This can be offset from to allow forwarding to be simulated as
@@ -121,7 +122,7 @@
zeroReg(reg_classes.at(IntRegClass).zeroReg()),
numResults(numRegs, 0),
numUnpredictableResults(numRegs, 0),
-fuIndices(numRegs, 0),
+fuIndices(numRegs, invalidFUIndex),
returnCycle(numRegs, Cycles(0)),
writingInst(numRegs, 0)
{ }
--
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Gerrit-Change-Id: Ic62546855a8ad5365064d2ea2e2a0fbc1ccc6f41
Gerrit-Change-Number: 50287
Gerrit-PatchSet: 3
Gerrit-Owner: Daecheol You
Gerrit-Reviewer: Daecheol You
Gerrit-Reviewer: ZHENGRONG WANG
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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