[gem5-dev] [M] Change in gem5/gem5[develop]: mem: Implemement backdoor interface for Bridge

[Yu-hsin Wang (Gerrit) via gem5-dev]

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67291?usp=email )



Change subject: mem: Implemement backdoor interface for Bridge
..

mem: Implemement backdoor interface for Bridge

Change-Id: I5ff62b03c34e41395a957a0799925ddd9c275458
---
M src/mem/bridge.cc
M src/mem/bridge.hh
2 files changed, 44 insertions(+), 8 deletions(-)



diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc
index 0f744f7..36832eb 100644
--- a/src/mem/bridge.cc
+++ b/src/mem/bridge.cc
@@ -347,6 +347,14 @@
 return delay * bridge.clockPeriod() + memSidePort.sendAtomic(pkt);
 }

+Tick
+Bridge::BridgeResponsePort::recvAtomicBackdoor(
+PacketPtr pkt, MemBackdoorPtr )
+{
+return delay * bridge.clockPeriod() + memSidePort.sendAtomicBackdoor(
+pkt, backdoor);
+}
+
 void
 Bridge::BridgeResponsePort::recvFunctional(PacketPtr pkt)
 {
@@ -371,6 +379,13 @@
 memSidePort.sendFunctional(pkt);
 }

+void
+Bridge::BridgeResponsePort::recvMemBackdoorReq(
+const MemBackdoorReq , MemBackdoorPtr )
+{
+memSidePort.sendMemBackdoorReq(req, backdoor);
+}
+
 bool
 Bridge::BridgeRequestPort::trySatisfyFunctional(PacketPtr pkt)
 {
diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh
index f56cef1..e4a6837 100644
--- a/src/mem/bridge.hh
+++ b/src/mem/bridge.hh
@@ -195,23 +195,35 @@

 /** When receiving a timing request from the peer port,
 pass it to the bridge. */
-bool recvTimingReq(PacketPtr pkt);
+bool recvTimingReq(PacketPtr pkt) override;

 /** When receiving a retry request from the peer port,
 pass it to the bridge. */
-void recvRespRetry();
+void recvRespRetry() override;

-/** When receiving a Atomic requestfrom the peer port,
+/** When receiving an Atomic request from the peer port,
 pass it to the bridge. */
-Tick recvAtomic(PacketPtr pkt);
+Tick recvAtomic(PacketPtr pkt) override;
+
+/** When receiving an Atomic backdoor request from the peer port,
+pass it to the bridge. */
+Tick recvAtomicBackdoor(
+PacketPtr pkt, MemBackdoorPtr ) override;
+

 /** When receiving a Functional request from the peer port,
 pass it to the bridge. */
-void recvFunctional(PacketPtr pkt);
+void recvFunctional(PacketPtr pkt) override;
+
+/** When receiving a Functional backdoor request from the peer  
port,

+pass it to the bridge. */
+void recvMemBackdoorReq(
+const MemBackdoorReq , MemBackdoorPtr ) override;
+

 /** When receiving a address range request the peer port,
 pass it to the bridge. */
-AddrRangeList getAddrRanges() const;
+AddrRangeList getAddrRanges() const override;
 };


@@ -303,11 +315,11 @@

 /** When receiving a timing request from the peer port,
 pass it to the bridge. */
-bool recvTimingResp(PacketPtr pkt);
+bool recvTimingResp(PacketPtr pkt) override;

 /** When receiving a retry request from the peer port,
 pass it to the bridge. */
-void recvReqRetry();
+void recvReqRetry() override;
 };

 /** Response port of the bridge. */

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5ff62b03c34e41395a957a0799925ddd9c275458
Gerrit-Change-Number: 67291
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang 
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Correct interrupt order

[Roger Chang (Gerrit) via gem5-dev]

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67211?usp=email )


 (

3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-riscv: Correct interrupt order
..

arch-riscv: Correct interrupt order

In Section 3.1.14 of Volume II Riscv Spec., the interrupt order
should be MEI, MSI, MTI, SEI, SSI, STI and so on.

issues:
https://gem5.atlassian.net/browse/GEM5-889

Change-Id: I357c86eecd74e9e65bbfd3d4d31e68bc276f8760
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67211
Maintainer: Jason Lowe-Power 
Reviewed-by: Yu-hsin Wang 
Tested-by: kokoro 
Reviewed-by: Jui-min Lee 
Reviewed-by: Jason Lowe-Power 
---
M src/arch/riscv/interrupts.hh
1 file changed, 24 insertions(+), 3 deletions(-)

Approvals:
  kokoro: Regressions pass
  Jui-min Lee: Looks good to me, but someone else must approve
  Yu-hsin Wang: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved





diff --git a/src/arch/riscv/interrupts.hh b/src/arch/riscv/interrupts.hh
index f10c5f3..a1ee396 100644
--- a/src/arch/riscv/interrupts.hh
+++ b/src/arch/riscv/interrupts.hh
@@ -125,9 +125,9 @@
 return std::make_shared();
 std::bitset mask = globalMask();
 const std::vector interrupt_order {
-INT_EXT_MACHINE, INT_TIMER_MACHINE, INT_SOFTWARE_MACHINE,
-INT_EXT_SUPER, INT_TIMER_SUPER, INT_SOFTWARE_SUPER,
-INT_EXT_USER, INT_TIMER_USER, INT_SOFTWARE_USER
+INT_EXT_MACHINE, INT_SOFTWARE_MACHINE, INT_TIMER_MACHINE,
+INT_EXT_SUPER, INT_SOFTWARE_SUPER, INT_TIMER_SUPER,
+INT_EXT_USER, INT_SOFTWARE_USER, INT_TIMER_USER
 };
 for (const int  : interrupt_order)
 if (checkInterrupt(id) && mask[id])

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I357c86eecd74e9e65bbfd3d4d31e68bc276f8760
Gerrit-Change-Number: 67211
Gerrit-PatchSet: 5
Gerrit-Owner: Roger Chang 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jui-min Lee 
Gerrit-Reviewer: Peter Yuen 
Gerrit-Reviewer: Roger Chang 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Earl Ou 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Check RISCV process run in matched CPU

[Roger Chang (Gerrit) via gem5-dev]

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67251?usp=email )


Change subject: arch-riscv: Check RISCV process run in matched CPU
..

arch-riscv: Check RISCV process run in matched CPU

1. Remove set RV32 flag in RiscvProcess32
2. Check if binary run appropriate CPU

Change-Id: I00b0725f3eb4f29e45b8ec719317af79355dc728
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67251
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/riscv/process.cc
1 file changed, 24 insertions(+), 5 deletions(-)

Approvals:
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved




diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index dc7abae..cd00f5d 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -101,8 +101,12 @@
 Process::initState();

 argsInit(PageBytes);
-for (ContextID ctx: contextIds)
-system->threads[ctx]->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
+for (ContextID ctx: contextIds) {
+auto *tc = system->threads[ctx];
+tc->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
+auto *isa = dynamic_cast(tc->getIsaPtr());
+fatal_if(isa->rvType() != RV64, "RISC V CPU should run in 64 bits  
mode");

+}
 }

 void
@@ -114,9 +118,8 @@
 for (ContextID ctx: contextIds) {
 auto *tc = system->threads[ctx];
 tc->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
-PCState pc = tc->pcState().as();
-pc.rvType(RV32);
-tc->pcState(pc);
+auto *isa = dynamic_cast(tc->getIsaPtr());
+fatal_if(isa->rvType() != RV32, "RISC V CPU should run in 32 bits  
mode");

 }
 }


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I00b0725f3eb4f29e45b8ec719317af79355dc728
Gerrit-Change-Number: 67251
Gerrit-PatchSet: 4
Gerrit-Owner: Roger Chang 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jui-min Lee 
Gerrit-Reviewer: Roger Chang 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Earl Ou 
Gerrit-MessageType: merged
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[gem5-dev] PerfKvmCounter::attach failed (2)

[Atlas Kaan Yilmaz via gem5-dev]

Hi Everyone,

I’ve been trying to use KVM in gem5 simulation; however, when I try to run I 
get the output below with PerfKvmCounter::attach failed (2) error. 

I’m running gem5 on an Azure VM with Ubuntu 20.04. I’m trying to run the 
vSwarm-u suite for serverless architecture.

I have found a proposed fix on a previous thread that said to 'echo -1 > 
/proc/sys/kernel/perf_event_paranoid’ on the host machine. I have done this 
(assuming the host machine means the VM I’m running gem5 on or does it mean the 
bare metal host?) but there has been no changes to the output message. 

Any help or ideas about how to go about this would be greatly appreciated!

Thanks,
Atlas

Create CPU:  X86KvmCPU
Created CPU: 2x X86KvmCPU, Mem mode: atomic_noncaching
--- Setup Mode ---
Global frequency set at 1 ticks per second
warn: system.workload.acpi_description_table_pointer.rsdt adopting orphan 
SimObject param 'entries'
warn: failed to generate dot output from results/fibonacci-go/config.dot
build/X86/sim/kernel_workload.cc:46: info: kernel located at: kernel
  0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan  1 
00:00:00 2012
system.pc.com_1.device: Listening for connections on port 3456
0: system.remote_gdb: listening for remote gdb on port 7000
build/X86/mem/coherent_xbar.cc:140: warn: CoherentXBar system.llc_bus has no 
snooping ports attached!
build/X86/dev/intel_8254_timer.cc:128: warn: Reading current count from 
inactive timer.
Start simulation...
build/X86/cpu/kvm/base.cc:150: info: KVM: Coalesced MMIO disabled by config.
build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x: unimplemented 
function 2
build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x: unimplemented 
function 3
build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x: unimplemented 
function 4
build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x: unimplemented 
function 5
build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x: unimplemented 
function 6
build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x: unimplemented 
function 8
build/X86/cpu/kvm/base.cc:150: info: KVM: Coalesced MMIO disabled by config.
build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x: unimplemented 
function 2
build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x: unimplemented 
function 3
build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x: unimplemented 
function 4
build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x: unimplemented 
function 5
build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x: unimplemented 
function 6
build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x: unimplemented 
function 8
build/X86/sim/simulate.cc:194: info: Entering event queue @ 0.  Starting 
simulation...
build/X86/cpu/kvm/perfevent.cc:183: panic: PerfKvmCounter::attach failed (2)
Memory Usage: 2390716 KBytes
build/X86/cpu/kvm/perfevent.cc:183: panic: PerfKvmCounter::attach failed (2)
Memory Usage: 2390716 KBytes
Program aborted at tick 0

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[gem5-dev] [M] Change in gem5/gem5[develop]: dev: Add a "resetter" callback to the typed register class.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67203?usp=email )



Change subject: dev: Add a "resetter" callback to the typed register class.
..

dev: Add a "resetter" callback to the typed register class.

When using the typed register template, most functionality of the class
can be controlled using callbacks. For instance, callbacks can be
installed to handle reads or writes to a register without having to
subclass the template and override those methods using inheritance.

The recently added reset() method did not follow this pattern though,
which has two problems. First, it's inconsistent with how the class is
normally used. Second, once you've defined a subclass, the reader,
writer, etc, callbacks still expect the type of the original class.
That means these have to either awkwardly use a type different from the
actual real type of the register, or use awkward, inefficient, and/or
dangerous casting to get back to the true type.

To address these problems, this change adds a resetter(...) method
which works like the reader(...) or writer(...) methods to optionally
install a callback to implement any special reset behavior.

Change-Id: Ia74b36616fd459c1dbed9304568903a76a4b55de
---
M src/dev/reg_bank.hh
M src/dev/reg_bank.test.cc
2 files changed, 116 insertions(+), 2 deletions(-)



diff --git a/src/dev/reg_bank.hh b/src/dev/reg_bank.hh
index 32d9058..dd68554 100644
--- a/src/dev/reg_bank.hh
+++ b/src/dev/reg_bank.hh
@@ -270,6 +270,12 @@
  * is an alternative form of update which also takes a custom bitmask, if  
you

  * need to update bits other than the normally writeable ones.
  *
+ * Similarly, you can set a "resetter" handler which is responsible for
+ * resetting the register. It takes a reference to the current Register,  
and
+ * no other parameters. The "initialValue" accessor can retrieve the value  
the

+ * register was constructed with. The register is simply set to this value
+ * in the default resetter implementation.
+ *
  * = Read only bits =
  *
  * Often registers have bits which are fixed and not affected by writes. To
@@ -547,13 +553,14 @@
   protected:
 using This = Register;

-  public:
+  public:&
 using ReadFunc = std::function;
 using PartialReadFunc = std::function<
 Data (This , int first, int last)>;
 using WriteFunc = std::function)>;

 using PartialWriteFunc = std::function<
 void (This , const Data , int first, int last)>;
+using ResetFunc = std::function;

   private:
 Data _data = {};
@@ -564,6 +571,7 @@
 WriteFunc _writer = defaultWriter;
 PartialWriteFunc _partialWriter = defaultPartialWriter;
 PartialReadFunc _partialReader = defaultPartialReader;
+ResetFunc _resetter = defaultResetter;

   protected:
 static Data defaultReader(This ) { return reg.get(); }
@@ -587,6 +595,12 @@
  mask(first, last)));
 }

+static void
+defaultResetter(This )
+{
+reg.get() = reg.initialValue();
+}
+
 constexpr Data
 htoreg(Data data)
 {
@@ -721,6 +735,30 @@
 return partialWriter(wrapper);
 }

+// Set the callables which handle resetting.
+//
+// The default resetter restores the initial value used in the
+// constructor.
+constexpr This &
+resetter(const ResetFunc _resetter)
+{
+_resetter = new_resetter;
+return *this;
+}
+template 
+constexpr This &
+resetter(Parent *parent, void (Parent::*nr)(Args... args))
+{
+auto wrapper = [parent, nr](Args&&... args) {
+return (parent->*nr)(std::forward(args)...);
+};
+return resetter(wrapper);
+}
+
+// An accessor which returns the initial value as set in the
+// constructor. This is intended to be used in a resetter function.
+const Data () const { return _resetData; }
+

 /*
  * Interface for accessing the register's state, for use by the
@@ -817,7 +855,7 @@
 }

 // Reset our data to its initial value.
-void reset() override { get() = _resetData; }
+void reset() override { _resetter(*this); }
 };

   private:
diff --git a/src/dev/reg_bank.test.cc b/src/dev/reg_bank.test.cc
index b4bc969..4439526 100644
--- a/src/dev/reg_bank.test.cc
+++ b/src/dev/reg_bank.test.cc
@@ -868,6 +868,56 @@
 EXPECT_EQ(write_value, 0x0344);
 }

+// Use the default resetter for a register.
+TEST_F(TypedRegisterTest, DefaultResetter)
+{
+BackingType initial_value = reg.get();
+
+reg.get() = initial_value + 1;
+EXPECT_EQ(reg.get(), initial_value + 1);
+
+reg.reset();
+
+EXPECT_EQ(reg.get(), 

[gem5-dev] Build failed in Jenkins: nightly #483

[jenkins-no-reply--- via gem5-dev]

See 

Changes:

[vramadas] gpu-compute : Fix incorrect TLB stats when FunctionalTLB is used


--
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[gem5-dev] [S] Change in gem5/gem5[develop]: systemc: fix -Wno-free-nonheap-object for building scheduler.cc

[Earl Ou (Gerrit) via gem5-dev]

Earl Ou has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67237?usp=email )



Change subject: systemc: fix -Wno-free-nonheap-object for building  
scheduler.cc

..

systemc: fix -Wno-free-nonheap-object for building scheduler.cc

-Wno-free-nonheap-object need to be added into linker flag as
the this check is actually at link time. This change also removes
the global flags so other code is still checked with the flags.

Change-Id: I8f1e20197b25c90b5f439e2ecc474bd99e4f82ed
---
M SConstruct
M src/systemc/core/SConscript
2 files changed, 15 insertions(+), 8 deletions(-)



diff --git a/SConstruct b/SConstruct
index bd26e45..e08c2984 100755
--- a/SConstruct
+++ b/SConstruct
@@ -447,10 +447,6 @@
 error('gcc version 7 or newer required.\n'
   'Installed version:', env['CXXVERSION'])

-with gem5_scons.Configure(env) as conf:
-# This warning has a false positive in the systemc in g++ 11.1.
-conf.CheckCxxFlag('-Wno-free-nonheap-object')
-
 # Add the appropriate Link-Time Optimization (LTO) flags if
 # `--with-lto` is set.
 if GetOption('with_lto'):
diff --git a/src/systemc/core/SConscript b/src/systemc/core/SConscript
index 2b88111..c7c9dbb 100644
--- a/src/systemc/core/SConscript
+++ b/src/systemc/core/SConscript
@@ -40,6 +40,7 @@
 Source('port.cc')
 Source('process.cc')
 Source('sched_event.cc')
+Source('scheduler.cc')
 Source('sensitivity.cc')
 Source('time.cc')

@@ -75,7 +76,4 @@
 # Disable the false positive warning for the event members of the  
scheduler.

 with gem5_scons.Configure(env) as conf:
 flag = '-Wno-free-nonheap-object'
-append = {}
-if conf.CheckCxxFlag(flag, autoadd=False):
-append['CCFLAGS'] = [flag]
-Source('scheduler.cc', append=append)
+conf.CheckLinkFlag(flag)

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8f1e20197b25c90b5f439e2ecc474bd99e4f82ed
Gerrit-Change-Number: 67237
Gerrit-PatchSet: 1
Gerrit-Owner: Earl Ou 
Gerrit-MessageType: newchange
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