[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv,dev: Add HiFive Base Platform
Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/68199?usp=email ) Change subject: arch-riscv,dev: Add HiFive Base Platform .. arch-riscv,dev: Add HiFive Base Platform This is basic abstract platform and all of RISC-V system should use platform inherit from HiFiveBase, HiFiveBase declared the common way to handle interrupt. Change-Id: I52122e1c82c200d7e6012433c2535c07d427f637 --- M src/dev/riscv/HiFive.py M src/dev/riscv/SConscript M src/dev/riscv/hifive.cc M src/dev/riscv/hifive.hh 4 files changed, 118 insertions(+), 75 deletions(-) diff --git a/src/dev/riscv/HiFive.py b/src/dev/riscv/HiFive.py index 4669686..ae5c232 100755 --- a/src/dev/riscv/HiFive.py +++ b/src/dev/riscv/HiFive.py @@ -1,5 +1,6 @@ # Copyright (c) 2021 Huawei International # Copyright (c) 2022 EXAscale Performance SYStems (EXAPSYS) +# Copyright (c) 2023 Google LLC # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -63,24 +64,14 @@ _dma_coherent = True -class HiFive(Platform): -"""HiFive Platform +class HiFiveBase(Platform): +"""HiFive Base Abstract Platform Implementation: This is the base class for SiFive's HiFive board series. It contains the CLINT and PLIC interrupt controllers, Uart and Disk. -Implementation details are based on SiFive -FU540-C000. https://sifive.cdn.prismic.io/ -sifive/b5e7a29c-d3c2-44ea-85fb-acc1df282e2 -1_FU540-C000-v1p3.pdf - -Setup: -The following sections outline the required -setup for a RISC-V HiFive platform. See -configs/example/riscv/fs_linux.py for example. - Driving CLINT: CLINT has an interrupt pin which increments mtime. It can be connected to any interrupt @@ -99,60 +90,29 @@ by _off_chip_devices(). Calling attachPlic sets up the PLIC interrupt source count. -Uart: -The HiFive platform also has an uart_int_id. -This is because Uart8250 uses postConsoleInt -instead of postPciInt. In the future if a Uart -that inherits PlicIntDevice is implemented, -this can be removed. - -Disk: -See fs_linux.py for setup example. - -PMAChecker: -The PMAChecker will be attached to the MMU of -each CPU (which allows them to differ). See -fs_linux.py for setup example. """ -type = "HiFive" +type = "HiFiveBase" cxx_header = "dev/riscv/hifive.hh" -cxx_class = "gem5::HiFive" +cxx_class = "gem5::HiFiveBase" # CLINT -clint = Param.Clint(Clint(pio_addr=0x200), "CLINT") +clint = Param.Clint(NULL, "CLINT") # PLIC -plic = Param.Plic(Plic(pio_addr=0xC00), "PLIC") +plic = Param.PlicBase(NULL, "PLIC") -# PCI -pci_host = GenericRiscvPciHost( -conf_base=0x3000, -conf_size="256MB", -conf_device_bits=12, -pci_pio_base=0x2F00, -pci_mem_base=0x4000, -) - -# Uart -uart = RiscvUart8250(pio_addr=0x1000) # Int source ID to redirect console interrupts to # Set to 0 if using a pci interrupt for Uart instead -uart_int_id = Param.Int(0xA, "PLIC Uart interrupt ID") -terminal = Terminal() +uart_int_id = Param.Int(0, "PLIC Uart interrupt ID") def _on_chip_devices(self): """Returns a list of on-chip peripherals""" -return [self.clint, self.plic] +return [] def _off_chip_devices(self): """Returns a list of off-chip peripherals""" -devices = [self.uart] -if hasattr(self, "disk"): -devices.append(self.disk) -if hasattr(self, "rng"): -devices.append(self.rng) -return devices +return [] def _on_chip_ranges(self): """Returns a list of on-chip peripherals @@ -172,17 +132,6 @@ for dev in self._off_chip_devices() ] -def attachPlic(self): -"""Count number of PLIC interrupt sources""" -plic_srcs = [ -self.uart_int_id, -self.pci_host.int_base + self.pci_host.int_count, -] -for device in self._off_chip_devices(): -if hasattr(device, "interrupt_id"): -plic_srcs.append(device.interrupt_id) -self.plic.n_src = max(plic_srcs) + 1 - def attachOnChipIO(self, bus): """Attach on-chip IO devices, needs modification to support DMA @@ -197,6 +146,83 @@ for device in self._off_chip_devices(): device.pio = bus.mem_side_ports + +class HiFive(HiFiveBase): +"""HiFive Platform + +Implementation: +Implementation details are based on SiFive +FU540-C000. https://sifive.cdn.prismic.io/ +sifive/b5e7a29c-d3c2-44ea-85fb-acc1df282e2 +1_FU540-C000-v1p3.pdf + +Setup: +The following
[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv,dev: Fix reserved size between enable memory map and thres...
Roger Chang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/68198?usp=email )
Change subject: arch-riscv,dev: Fix reserved size between enable memory map
and threshold memory map
..
arch-riscv,dev: Fix reserved size between enable memory map and
threshold memory map
The number of enablePadding is depending on number of context in
PLIC
Change-Id: Ib4b7e5ecd183863e140c4f3382a75057902d446d
---
M src/dev/riscv/plic.cc
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/src/dev/riscv/plic.cc b/src/dev/riscv/plic.cc
index edf0e06..d221946 100644
--- a/src/dev/riscv/plic.cc
+++ b/src/dev/riscv/plic.cc
@@ -204,7 +204,7 @@
- plic->nSrc32 * 4;
reserved.emplace_back("reserved1", reserve1_size);
const size_t reserve2_size = thresholdStart - enableStart
-- plic->nSrc32 * plic->nContext * enablePadding;
+- plic->nContext * enablePadding;
reserved.emplace_back("reserved2", reserve2_size);
const size_t reserve3_size = plic->pioSize - thresholdStart
- plic->nContext * thresholdPadding;
--
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Gerrit-Change-Id: Ib4b7e5ecd183863e140c4f3382a75057902d446d
Gerrit-Change-Number: 68198
Gerrit-PatchSet: 1
Gerrit-Owner: Roger Chang
Gerrit-MessageType: newchange
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv,dev: Add PLIC abstract class to support multiple PLIC impl...
Roger Chang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/68197?usp=email )
Change subject: arch-riscv,dev: Add PLIC abstract class to support multiple
PLIC implementation
..
arch-riscv,dev: Add PLIC abstract class to support multiple PLIC
implementation
We should create PLIC abstract and have common interface to let
HiFive platform send and clear interrupt to variable PLIC
Change-Id: Ic3a2ffc2a2a002540b400c70c85c3495fa838f2a
---
M src/dev/riscv/Plic.py
M src/dev/riscv/SConscript
M src/dev/riscv/plic.cc
M src/dev/riscv/plic.hh
4 files changed, 53 insertions(+), 7 deletions(-)
diff --git a/src/dev/riscv/Plic.py b/src/dev/riscv/Plic.py
index 33b6940..3233e0d 100644
--- a/src/dev/riscv/Plic.py
+++ b/src/dev/riscv/Plic.py
@@ -1,4 +1,5 @@
# Copyright (c) 2021 Huawei International
+# Copyright (c) 2023 Google LLC
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -39,7 +40,21 @@
from m5.util.fdthelper import *
-class Plic(BasicPioDevice):
+class PlicBase(BasicPioDevice):
+ """
+ This is abstract class of PLIC and
+ define interface to handle received
+ interrupt singal from device
+ """
+ type = "PlicBase"
+ cxx_header = "dev/riscv/plic.hh"
+ cxx_class = "gem5::PlicBase"
+ abstract = True
+
+ pio_size = Param.Addr("PIO Size")
+
+
+class Plic(PlicBase):
"""
This implementation of PLIC is based on
the SiFive U54MC datasheet:
@@ -51,7 +66,7 @@
type = "Plic"
cxx_header = "dev/riscv/plic.hh"
cxx_class = "gem5::Plic"
-pio_size = Param.Addr(0x400, "PIO Size")
+pio_size = 0x400
n_src = Param.Int("Number of interrupt sources")
n_contexts = Param.Int(
"Number of interrupt contexts. Usually the number "
diff --git a/src/dev/riscv/SConscript b/src/dev/riscv/SConscript
index af0b96b..6e3376b 100755
--- a/src/dev/riscv/SConscript
+++ b/src/dev/riscv/SConscript
@@ -2,6 +2,7 @@
# Copyright (c) 2021 Huawei International
# Copyright (c) 2022 EXAscale Performance SYStems (EXAPSYS)
+# Copyright (c) 2023 Google LLC
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -34,7 +35,7 @@
SimObject('LupV.py', sim_objects=['LupV'], tags='riscv isa')
SimObject('Clint.py', sim_objects=['Clint'], tags='riscv isa')
SimObject('PlicDevice.py', sim_objects=['PlicIntDevice'], tags='riscv isa')
-SimObject('Plic.py', sim_objects=['Plic'], tags='riscv isa')
+SimObject('Plic.py', sim_objects=['PlicBase', 'Plic'], tags='riscv isa')
SimObject('RTC.py', sim_objects=['RiscvRTC'], tags='riscv isa')
SimObject('RiscvVirtIOMMIO.py', sim_objects=['RiscvMmioVirtIO'],
tags='riscv isa')
diff --git a/src/dev/riscv/plic.cc b/src/dev/riscv/plic.cc
index b8f765a..edf0e06 100644
--- a/src/dev/riscv/plic.cc
+++ b/src/dev/riscv/plic.cc
@@ -45,6 +45,7 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "params/Plic.hh"
+#include "params/PlicBase.hh"
#include "sim/system.hh"
namespace gem5
@@ -53,7 +54,7 @@
using namespace RiscvISA;
Plic::Plic(const Params ) :
-BasicPioDevice(params, params.pio_size),
+PlicBase(params),
system(params.system),
nSrc(params.n_src),
nContext(params.n_contexts),
diff --git a/src/dev/riscv/plic.hh b/src/dev/riscv/plic.hh
index d077e73..0b30813 100644
--- a/src/dev/riscv/plic.hh
+++ b/src/dev/riscv/plic.hh
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2021 Huawei International
+ * Copyright (c) 2023 Google LLC
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -47,6 +48,7 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "params/Plic.hh"
+#include "params/PlicBase.hh"
#include "sim/system.hh"
namespace gem5
@@ -94,7 +96,21 @@
std::vector maxPriority;
};
-class Plic : public BasicPioDevice
+class PlicBase : public BasicPioDevice
+{
+ public:
+typedef PlicBaseParams Params;
+PlicBase(const Params ) :
+ BasicPioDevice(params, params.pio_size)
+{}
+
+/** Interrupt interface to send signal to PLIC */
+virtual void post(int src_id) = 0;
+/** Interrupt interface to clear signal to PLIC */
+virtual void clear(int src_id) = 0;
+};
+
+class Plic : public PlicBase
{
// Params
protected:
@@ -125,8 +141,8 @@
/**
* Interrupt interface
*/
-void post(int src_id);
-void clear(int src_id);
+void post(int src_id) override;
+void clear(int src_id) override;
/**
* SimObject functions
--
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[gem5-dev] [S] Change in gem5/gem5[develop]: base: extensible: add example codes of extension
Yan Lee has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/68017?usp=email )
Change subject: base: extensible: add example codes of extension
..
base: extensible: add example codes of extension
Change-Id: Iaab1f2998a3f621b86d63bed7274373ba433d71c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68017
Maintainer: Jason Lowe-Power
Reviewed-by: Jason Lowe-Power
Tested-by: kokoro
---
M src/base/extensible.hh
1 file changed, 44 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/extensible.hh b/src/base/extensible.hh
index eb79c71..e80103c 100644
--- a/src/base/extensible.hh
+++ b/src/base/extensible.hh
@@ -27,6 +27,10 @@
/* @file
* Extensible Object Base Class Declaration
+ *
+ * This class can be used to add an "extension" field to packet/request
which
+ * will be passed along with the original packet/request pointer. This
allows
+ * developers to extend packet/request without modifying the original
class.
*/
#ifndef __BASE_EXTENSIBLE_HH__
@@ -69,6 +73,33 @@
* This is the extension for carrying additional information.
* Each type of extension will have a unique extensionID.
* This extensionID will assign to base class for comparsion.
+ *
+ * Example usage:
+ *
+ * class MyTarget : Extensible {};
+ *
+ * class MyExtension : public Extension
+ * {
+ * public:
+ * MyExtension();
+ * std::unique_ptr clone() const override;
+ * uint32_t getData();
+ *
+ * private:
+ * uint32_t data_;;
+ * };
+ *
+ * std::unique_ptr mytarget(new MyTarget);
+ * std::shared_ptr myext(new MyExtension);
+ * mytarget->setExtension(myext);
+ *
+ * std::shared_ptr ext =
mytarget->getExtension();
+ * uint32_t data = ext->getData();
+ * mytarget->removeExtension();
+ *
+ * In the example above, MyTarget can carry an extension named
MyExtension,
+ * which contains an additional data field. This could be applicated to
any
+ * debug information or any data field in any protocol.
*/
template
class Extension : public ExtensionBase
--
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Gerrit-Change-Id: Iaab1f2998a3f621b86d63bed7274373ba433d71c
Gerrit-Change-Number: 68017
Gerrit-PatchSet: 3
Gerrit-Owner: Yan Lee
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Yan Lee
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: mem: add extension mechanism into Request
Yan Lee has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67958?usp=email )
Change subject: mem: add extension mechanism into Request
..
mem: add extension mechanism into Request
Change-Id: Ie144e0cf243bab6d9ddbea79caf559c7e774a787
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67958
Maintainer: Jason Lowe-Power
Reviewed-by: Yu-hsin Wang
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
---
M src/mem/request.hh
1 file changed, 18 insertions(+), 2 deletions(-)
Approvals:
kokoro: Regressions pass
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
Yu-hsin Wang: Looks good to me, approved
diff --git a/src/mem/request.hh b/src/mem/request.hh
index be91c71..491aad0 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -58,6 +58,7 @@
#include "base/amo.hh"
#include "base/compiler.hh"
+#include "base/extensible.hh"
#include "base/flags.hh"
#include "base/types.hh"
#include "cpu/inst_seq.hh"
@@ -93,7 +94,7 @@
typedef std::shared_ptr RequestPtr;
typedef uint16_t RequestorID;
-class Request
+class Request : public Extensible
{
public:
typedef uint64_t FlagsType;
@@ -501,7 +502,8 @@
}
Request(const Request& other)
-: _paddr(other._paddr), _size(other._size),
+: Extensible(other),
+ _paddr(other._paddr), _size(other._size),
_byteEnable(other._byteEnable),
_requestorId(other._requestorId),
_flags(other._flags),
--
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Gerrit-Change-Id: Ie144e0cf243bab6d9ddbea79caf559c7e774a787
Gerrit-Change-Number: 67958
Gerrit-PatchSet: 4
Gerrit-Owner: Yan Lee
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: Yan Lee
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: mem: add extension mechanism into Packet
Yan Lee has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67957?usp=email )
Change subject: mem: add extension mechanism into Packet
..
mem: add extension mechanism into Packet
Change-Id: Ieda941f73078d98ad7896a376d95dd1573c938e6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67957
Reviewed-by: Yu-hsin Wang
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/packet.hh
1 file changed, 18 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
Yu-hsin Wang: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index 9d720fb..ed7a94f 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -55,6 +55,7 @@
#include "base/addr_range.hh"
#include "base/cast.hh"
#include "base/compiler.hh"
+#include "base/extensible.hh"
#include "base/flags.hh"
#include "base/logging.hh"
#include "base/printable.hh"
@@ -290,7 +291,7 @@
* ultimate destination and back, possibly being conveyed by several
* different Packets along the way.)
*/
-class Packet : public Printable
+class Packet : public Printable, public Extensible
{
public:
typedef uint32_t FlagsType;
@@ -941,7 +942,8 @@
* packet should allocate its own data.
*/
Packet(const PacketPtr pkt, bool clear_flags, bool alloc_data)
-: cmd(pkt->cmd), id(pkt->id), req(pkt->req),
+: Extensible(*pkt),
+ cmd(pkt->cmd), id(pkt->id), req(pkt->req),
data(nullptr),
addr(pkt->addr), _isSecure(pkt->_isSecure), size(pkt->size),
bytesValid(pkt->bytesValid),
--
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Gerrit-Change-Number: 67957
Gerrit-PatchSet: 4
Gerrit-Owner: Yan Lee
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: Yan Lee
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: fastmodel: Check early for license server issue
Nicolas Boichat has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/68177?usp=email )
Change subject: fastmodel: Check early for license server issue
..
fastmodel: Check early for license server issue
We have a setup that requires manual startup of an ssh proxy to
access license server, and without that, gem5 takes about a minute
until the license checkout times out (until then, it's unclear
why nothing is happening).
We filed a ticket with ARM to try to understand if we can reduce
the timeout or number of attempts on fastmodel side. But, for now,
we can just attempt to connect to license servers early on, and
fail quickly.
Change-Id: I37b84fd52cb7fb221a9e48dcb52a33a11f4d1580
---
M src/arch/arm/fastmodel/arm_fast_model.py
1 file changed, 73 insertions(+), 5 deletions(-)
diff --git a/src/arch/arm/fastmodel/arm_fast_model.py
b/src/arch/arm/fastmodel/arm_fast_model.py
index d2d911f..a1a0059 100644
--- a/src/arch/arm/fastmodel/arm_fast_model.py
+++ b/src/arch/arm/fastmodel/arm_fast_model.py
@@ -23,22 +23,68 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+import logging
import os
+import socket
from m5.defines import buildEnv
import _m5.arm_fast_model
+LICENSE_ENV = 'ARMLMD_LICENSE_FILE'
def set_armlmd_license_file(force=False):
"""Set the ARMLMD_LICENSE_FILE environment variable. If "force" is
False, then it will only be set if it wasn't already set in the
environment. The value it's set to is the one gem5 was built with.
"""
-key = "ARMLMD_LICENSE_FILE"
-license_file = buildEnv[key]
-if force or key not in os.environ:
-os.environ[key] = license_file
+license_file = buildEnv[LICENSE_ENV]
+if force or LICENSE_ENV not in os.environ:
+os.environ[LICENSE_ENV] = license_file
+def check_armlmd_license(timeout):
+"""Check if any of the provided license server can be reached, or
+if a license file is provided. This allows to fail early and fast,
+as fastmodel code makes multiple lengthy attempts to connect to
+license server. "timeout" is in seconds.
+"""
+reachable = False
+servers = os.environ[LICENSE_ENV].split(':')
+
+# Fastmodel appears to try these 2 extra server/file, regardless of
+# env variable.
+extras = ('27010@localhost', '/opt/arm/licenses/license.dat')
+for extra in extras:
+if extra not in servers:
+servers.append(extra)
+
+for server in servers:
+tuple = server.split('@')
+if len(tuple) != 2:
+# Probably a file, not a server.
+if os.path.exists(server):
+reachable = True
+logging.debug("License file %s exists." % server)
+break
+else:
+logging.debug('License file "%s" does not exist.' % server)
+continue
+try:
+# Try to connect to license server. This doesn't attempt to
+# communicate with it, just checking reachability.
+s = socket.create_connection(
+(tuple[1], int(tuple[0])), timeout=timeout)
+s.close()
+reachable = True
+logging.debug("License server %s is reachable." % server)
+break
+except Exception as e:
+logging.debug("Cannot connect to license server %s (%s: %s)." %
+(server, type(e).__name__, e))
+
+if not reachable:
+raise ConnectionError(
+"Cannot connect to any of the license servers (%s)." %
+', '.join(servers))
# These methods wrap much of the SystemC Export API described in section
# 7.6 of the Fast Models User Guide.
@@ -142,9 +188,12 @@
# This should be called once per simulation
def setup_simulation(
-sim_name, min_sync_latency=100.0 / 1, exit_on_dmi_warning=False
+sim_name, min_sync_latency=100.0 / 1,
exit_on_dmi_warning=False,
+check_license=True, check_license_timeout=1
):
set_armlmd_license_file()
+if check_license:
+check_armlmd_license(check_license_timeout)
scx_initialize(sim_name)
scx_set_min_sync_latency(min_sync_latency)
if exit_on_dmi_warning:
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I37b84fd52cb7fb221a9e48dcb52a33a11f4d1580
Gerrit-Change-Number: 68177
Gerrit-PatchSet: 1
Gerrit-Owner: Nicolas Boichat
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: python: Ensure that m5.internal.params is available
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67797?usp=email )
Change subject: python: Ensure that m5.internal.params is available
..
python: Ensure that m5.internal.params is available
Add an import to m5.internal.params which became necessary after:
95f9017c2e configs,python: Clean some cruft out of m5.objects.
This import is necessary but also causes problems when scons calls
build_tools/sim_object_param_struct_hh.py to generate
params/SimObject.hh. m5.internal.params itself imports _m5 and _m5 is
unavalailable resulting in an ImportError. This is bening and we can
safely ignore it.
Change-Id: I3809e81284e730fb9c9e0e7e91bd61b801d73f90
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67797
Maintainer: Giacomo Travaglini
Tested-by: kokoro
Reviewed-by: Giacomo Travaglini
---
M src/python/m5/SimObject.py
M src/python/m5/internal/params.py
2 files changed, 40 insertions(+), 4 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index b5dfca9..6caa532 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -445,6 +445,9 @@
return cls.__name__
def getCCClass(cls):
+# Ensure that m5.internal.params is available.
+import m5.internal.params
+
return getattr(m5.internal.params, cls.pybind_class)
# See ParamValue.cxx_predecls for description.
diff --git a/src/python/m5/internal/params.py
b/src/python/m5/internal/params.py
index 8762a69..8225d0b 100644
--- a/src/python/m5/internal/params.py
+++ b/src/python/m5/internal/params.py
@@ -37,8 +37,17 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import inspect
-import _m5
-for name, module in inspect.getmembers(_m5):
-if name.startswith("param_") or name.startswith("enum_"):
-exec("from _m5.%s import *" % name)
+try:
+# Avoid ImportErrors at build time when _m5 is not available
+import _m5
+
+in_gem5 = True
+except ImportError:
+# The import failed, we're being called from the build system
+in_gem5 = False
+
+if in_gem5:
+for name, module in inspect.getmembers(_m5):
+if name.startswith("param_") or name.startswith("enum_"):
+exec("from _m5.%s import *" % name)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3809e81284e730fb9c9e0e7e91bd61b801d73f90
Gerrit-Change-Number: 67797
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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