date:20230616

[gem5-dev] Re: [Important Announcement] gem5 Migration from Gerrit to GitHub

2023-06-16 Thread Bobby Bruce via gem5-dev

Dear all,

We’re still working on ensuring a smooth migration from Gerrit to Github. We 
had originally planned to have migration occur yesterday, on the 15th, but 
found we still need to update documentation and do some further checks to 
ensure the GitHub testing infrastructure meet our requirements. As such, we 
wish to re-schedule the transfer to June 27th.

Kind regards,
Bobby
--
Dr. Bobby R. Bruce
Room 3050,
Kemper Hall, UC Davis
Davis,
CA, 95616
 
web: https://www.bobbybruce.net

> On Jun 6, 2023, at 6:50 AM, Bobby Bruce  wrote:
> 
> Dear all,
> 
> We are excited to inform you that gem5 is migrating from Gerrit to GitHub for 
> code collaboration and version control. This migration is scheduled to take 
> place on June 15th. We believe that this move will provide a more streamlined 
> and efficient development process for our community.
> 
> The new gem5 repository will be hosted at the following URL: 
> https://github.com/gem5/gem5. We kindly request all contributors and 
> maintainers to update their references, links, and remote repo settings 
> accordingly. In order to complete this migration, on June 15th the Gerrit 
> Repository will be changed to a read-only state.
> 
> With this migration, we will be transitioning to a pull-request model for 
> code contributions. This means that contributors will need to undertake 
> following process:
> 
> 1. Fork the gem5 repository on GitHub.
> 2. Create a new branch in your forked repository for your feature or bug fix.
> 3. Commit your changes to the new branch.
> 4. Push the branch to your forked repository.
> 5. Open a pull request from your branch in your forked repository to the main 
> gem5 repository.
> 
> We will continue to use the “develop” branch for development, so please 
> ensure your pull requests are for the gem5 develop branch. Pull requests to 
> the stable branch will be blocked.
> 
> Each pull request will then be evaluated prior to being merged into develop. 
> The new process for merging code into gem5 requires that:
> 
> 1. Continuous Integration (CI) tests must pass. These will be run via GitHub 
> Actions when a PR is created or updated. They are equivalent to kokoro tests 
> today.
> 2. Each pull request must be reviewed and "approved" by at least one 
> reviewer. Like on Gerrit today, anyone can review any changeset.
> 3. A maintainer must merge the PR, which can only happen after the PR is 
> approved by a reviewer and the CI tests pass. We will give gem5 maintainers 
> these permissions over the next few days.
> 
> We understand that this transition may require some adjustments, but we 
> believe that it will provide a more collaborative and transparent environment 
> for our community. The GitHub platform offers robust features for code 
> reviews, discussions, and a familiar interface for many developers. The 
> https://github.com/gem5/gem5 repo is, at the time of writing, setup for 
> members of the community to play with and accustom themselves with the 
> process. We encourage developers to create dummy pull-requests and post 
> reviewers. Merging a pull to develop is currently blocked but will be enabled 
> in June 15th when Gerrit is turned read-only.
> 
> We encourage all community members to actively participate in the migration 
> process and provide feedback or suggestions to make this transition as smooth 
> as possible. As with all big changes we expect teething problems so encourage 
> you to highlight any issues, ask questions, or raise concerns regarding this 
> new model and setup.
> 
> In addition to the gem5 git repository will be making similar migrations for 
> our gem5-resources and gem5-website repositories. We are also enabling GitHub 
> Issues and GitHub Discussions. Please feel free to use these in place of 
> Jira, gem5-dev, gem5-users, and Slack. Depending on the community's 
> preferences, we may migrate to solely using these GitHub-based tools to 
> simplify the organization of the project.
> 
> Thank you for your continued support and dedication to the gem5 project. We 
> look forward to this new chapter in our development journey! We will keep 
> close eye on this thread for discussions about this move. We will work over 
> the coming week to update all the website and related documentation to 
> reflect this change and provide the documentation needed to the community.
> 
> Best regards,
> Bobby
> 
> --
> Dr. Bobby R. Bruce
> Room 3050,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
> 
> web: https://www.bobbybruce.net
> 
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[gem5-dev] Re: v23.0 staging branch to be created on May 24th

2023-06-16 Thread Bobby Bruce via gem5-dev

Dear all,

As you have probably noticed, we’re already over our original June 9th 
scheduled release of v23.0. The staging branch periods has been productive and 
allowed us to test and fix many parts of the project. We still require a little 
more time with this so are now aiming to have the release complete by the end 
of the month.

As always, you may push bug fixes and other minor improvements to the staging 
branch during this time.

Kind regards,
Bobby
--
Dr. Bobby R. Bruce
Room 3050,
Kemper Hall, UC Davis
Davis,
CA, 95616
 
web: https://www.bobbybruce.net

> On May 26, 2023, at 5:55 PM, Bobby Bruce  wrote:
> 
> Dear all,
> 
> As of this afternoon, the gem5 v23.0 staging branch has been created. This 
> branch will be intensely tested over the next couple of weeks to ensure it's 
> ready to be merged into the stable branch. The release of gem5 v23.0 (the 
> point at which the staging branch is merged into the stable branch) is now 
> scheduled for June 9th.
> 
> If you have any bug fixes you can submit them to the develop branch then 
> cherry-pick the changes onto the staging branch to ensure they make it into 
> the v23.0 release. 
> 
> More information on our release procedures can be found here: 
> https://www.gem5.org/documentation/general_docs/development/release_procedures/
>  
> 
> 
> 
> Kind regards,
> Bobby
> --
> Dr. Bobby R. Bruce
> Room 3050,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
> 
> web: https://www.bobbybruce.net 
> --
> Dr. Bobby R. Bruce
> Room 3050,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>  
> web: https://www.bobbybruce.net
> 
>> On May 9, 2023, at 2:09 PM, Bobby Bruce  wrote:
>> 
>> Dear all,
>> 
>> I am writing to inform the community that we are planning to create the 
>> staging branch for v23.0 on May 24th. This branch will be created from the 
>> develop branch and intensively tested prior to merging into the stable 
>> branch, thereby completing the release of v23.0. The staging branch will 
>> exist for no less than two weeks with the current goal to officially 
>> releasing on June 7th.  More information about this process can be found in 
>> our release procedures documentation: 
>> https://www.gem5.org/documentation/general_docs/development/release_procedures/
>> 
>> Any patches intended for v23.0 should be submitted over the next two weeks. 
>> We'll work hard to ensure those who have pushed patched to Gerrit are 
>> reviewed as soon as possible. If you feel your patch has been neglected 
>> please reach out. 
>> 
>> Please note that anything which doesn't make it into develop prior to 
>> creation of the staging branch can still make it to the gem5 v23.1 release 
>> later in the year. As always, bug fixes/stability improvements and minor, 
>> inoffensive changes will be permitted for submission to the staging branch 
>> for the time it exists prior to the release.
>> 
>> Kind regards,
>> Bobby
>> --
>> Dr. Bobby R. Bruce
>> Room 3050,
>> Kemper Hall, UC Davis
>> Davis,
>> CA, 95616
>> 
>> web: https://www.bobbybruce.net
>> 
> 

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[gem5-dev] [S] Change in gem5/gem5[release-staging-v23-0]: arch-riscv: fix load reserved store conditional

2023-06-16 Thread Bobby Bruce (Gerrit) via gem5-dev

Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71520?usp=email )


Change subject: arch-riscv: fix load reserved store conditional
..

arch-riscv: fix load reserved store conditional

  * According to the manual, load reservations must be cleared on a
failed or a successful SC attempt.
  * A load reservation can be arbitrarily large. The current
implementation was reserving something different than cacheBlockSize
which could lead to problems if snoop addresses are cache block
aligned. This patch implementation assumes a cacheBlock granularity.
  * Load reservations should also be cleared on faults

Change-Id: I64513534710b5f269260fcb204f717801913e2f5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71520
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Bobby Bruce 
---
M src/arch/generic/isa.hh
M src/arch/riscv/faults.cc
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
4 files changed, 34 insertions(+), 11 deletions(-)

Approvals:
  kokoro: Regressions pass
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved




diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh
index e9e4d95..58f66fc 100644
--- a/src/arch/generic/isa.hh
+++ b/src/arch/generic/isa.hh
@@ -70,6 +70,7 @@
   public:
 virtual PCStateBase *newPCState(Addr new_inst_addr=0) const = 0;
 virtual void clear() {}
+virtual void clearLoadReservation(ContextID cid) {}

 virtual RegVal readMiscRegNoEffect(RegIndex idx) const = 0;
 virtual RegVal readMiscReg(RegIndex idx) = 0;
diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index 940f710..8fb8f81 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -153,6 +153,9 @@
 tc->setMiscReg(MISCREG_NMIE, 0);
 }

+// Clear load reservation address
+tc->getIsaPtr()->clearLoadReservation(tc->contextId());
+
 // Set PC to fault handler address
 Addr addr = mbits(tc->readMiscReg(tvec), 63, 2);
 if (isInterrupt() && bits(tc->readMiscReg(tvec), 1, 0) == 1)
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index d744fe36..94a8239 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -672,11 +672,6 @@
 UNSERIALIZE_CONTAINER(miscRegFile);
 }

-const int WARN_FAILURE = 1;
-
-const Addr INVALID_RESERVATION_ADDR = (Addr) -1;
-std::unordered_map load_reservation_addrs;
-
 void
 ISA::handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask)
 {
@@ -696,9 +691,9 @@
 {
 Addr& load_reservation_addr = load_reservation_addrs[tc->contextId()];

-load_reservation_addr = req->getPaddr() & ~0xF;
+load_reservation_addr = req->getPaddr();
 DPRINTF(LLSC, "[cid:%d]: Reserved address %x.\n",
-req->contextId(), req->getPaddr() & ~0xF);
+req->contextId(), req->getPaddr());
 }

 bool
@@ -717,12 +712,13 @@
 lr_addr_empty ? "yes" : "no");
 if (!lr_addr_empty) {
 DPRINTF(LLSC, "[cid:%d]: addr = %x.\n", req->contextId(),
-req->getPaddr() & ~0xF);
+req->getPaddr() & cacheBlockMask);
 DPRINTF(LLSC, "[cid:%d]: last locked addr = %x.\n",  
req->contextId(),

-load_reservation_addr);
+load_reservation_addr & cacheBlockMask);
 }
-if (lr_addr_empty
-|| load_reservation_addr != ((req->getPaddr() & ~0xF))) {
+if (lr_addr_empty ||
+(load_reservation_addr & cacheBlockMask)
+!= ((req->getPaddr() & cacheBlockMask))) {
 req->setExtraData(0);
 int stCondFailures = tc->readStCondFailures();
 tc->setStCondFailures(++stCondFailures);
@@ -730,12 +726,21 @@
 warn("%i: context %d: %d consecutive SC failures.\n",
 curTick(), tc->contextId(), stCondFailures);
 }
+
+// Must clear any reservations
+load_reservation_addr = INVALID_RESERVATION_ADDR;
+
 return false;
 }
 if (req->isUncacheable()) {
 req->setExtraData(2);
 }

+// Must clear any reservations
+load_reservation_addr = INVALID_RESERVATION_ADDR;
+
+DPRINTF(LLSC, "[cid:%d]: SC success! Current locked addr = %x.\n",
+req->contextId(), load_reservation_addr & cacheBlockMask);
 return true;
 }

@@ -743,6 +748,8 @@
 ISA::globalClearExclusive()
 {
 tc->getCpuPtr()->wakeup(tc->threadId());
+Addr& load_reservation_addr = load_reservation_addrs[tc->contextId()];
+load_reservation_addr = INVALID_RESERVATION_ADDR;
 }

 void
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 5a2a610..7ef5c52 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -76,6 +76,11 @@

 bool hpmCounterEnabled(int counter) const;

+// Load reserve - store conditional monitor
+const int WARN_FAILURE = 1;
+const Addr INVALID_RESERVATION_ADDR = (Addr)-1;
+

[gem5-dev] [S] Change in gem5/gem5[develop]: python: Remove Python 'pipes' module

2023-06-16 Thread Bobby Bruce (Gerrit) via gem5-dev

Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71740?usp=email )


Change subject: python: Remove Python 'pipes' module
..

python: Remove Python 'pipes' module

This is scheduled for removal from Python in 3.13:
https://docs.python.org/3/library/pipes.html.

The 'shlex.quote' function can replace the 'pipes.quote' function used
in "main.py". A special wrapper has been made to account for the Windows
case which 'shlex.quote' doesn't handle.

Change-Id: I9c84605f0ccd8468b9cab6cece6248ef8c2107f0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71678
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
(cherry picked from commit a63d376ecd4debd60f89fa2e0592dac6f9addae2)
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71740
Maintainer: Bobby Bruce 
Reviewed-by: Bobby Bruce 
---
M src/python/m5/main.py
1 file changed, 16 insertions(+), 3 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/m5/main.py b/src/python/m5/main.py
index 4701dfa..ddcb024 100644
--- a/src/python/m5/main.py
+++ b/src/python/m5/main.py
@@ -496,10 +496,23 @@
 % (socket.gethostname(), os.getpid())
 )

-# in Python 3 pipes.quote() is moved to shlex.quote()
-import pipes
+def quote(arg: str) -> str:
+"""Quotes a string for printing in a shell. In addition to  
Unix,

+this is designed to handle the problematic Windows cases where
+'shlex.quote' doesn't work"""

-print("command line:", " ".join(map(pipes.quote, sys.argv)))
+if os.name == "nt" and os.sep == "\\":
+# If a Windows machine, we manually quote the string.
+arg = arg.replace('"', '\\"')
+if re.search("\s", args):
+# We quote args which have whitespace.
+arg = '"' + arg + '"'
+return arg
+import shlex
+
+return shlex.quote(arg)
+
+print("command line:", " ".join(map(quote, sys.argv)))
 print()

 # check to make sure we can find the listed script

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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9c84605f0ccd8468b9cab6cece6248ef8c2107f0
Gerrit-Change-Number: 71740
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby Bruce 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-CC: kokoro 
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[gem5-dev] [S] Change in gem5/gem5[develop]: scons,stdlib: Remove deprecated 'distutils' module

2023-06-16 Thread Bobby Bruce (Gerrit) via gem5-dev

Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71741?usp=email )


Change subject: scons,stdlib: Remove deprecated 'distutils' module
..

scons,stdlib: Remove deprecated 'distutils' module

The Python module 'distutils' will be removed in Python 3.12:
https://docs.python.org/3/library/distutils.html

This patch removed usage of 'distutils' in the gem5 code base.

Change-Id: I1e3a96149f3cd6cbf4211a1565b5f74c85a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71679
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
(cherry picked from commit b182b15f93621206c87c6c760cdfc1f5df1877cf)
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71741
Maintainer: Bobby Bruce 
Reviewed-by: Bobby Bruce 
---
M src/SConscript
M src/python/gem5/resources/client_api/client_wrapper.py
2 files changed, 22 insertions(+), 8 deletions(-)

Approvals:
  kokoro: Regressions pass
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved




diff --git a/src/SConscript b/src/SConscript
index d26bf49..1b44303 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -39,7 +39,7 @@

 import collections
 import copy
-import distutils.spawn
+from shutil import which
 import itertools
 import os
 import os.path
@@ -269,7 +269,7 @@
 '''Add a Protocol Buffer to build'''
 Source(source, tags, add_tags,  
append={'CXXFLAGS': '-Wno-array-bounds'})


-env['PROTOC_GRPC'] = distutils.spawn.find_executable('grpc_cpp_plugin')
+env['PROTOC_GRPC'] = which('grpc_cpp_plugin')
 if env['PROTOC_GRPC']:
 with Configure(env) as conf:
 if (not env['HAVE_PKG_CONFIG'] or
diff --git a/src/python/gem5/resources/client_api/client_wrapper.py  
b/src/python/gem5/resources/client_api/client_wrapper.py

index 74ee831..69787a0 100644
--- a/src/python/gem5/resources/client_api/client_wrapper.py
+++ b/src/python/gem5/resources/client_api/client_wrapper.py
@@ -27,8 +27,7 @@
 from .jsonclient import JSONClient
 from .atlasclient import AtlasClient
 from _m5 import core
-from typing import Optional, Dict, List
-from distutils.version import StrictVersion
+from typing import Optional, Dict, List, Tuple
 import itertools
 from m5.util import warn

@@ -191,12 +190,27 @@
 :param resources: A list of resources to sort.
 :return: A list of sorted resources.
 """
+
+def sort_tuple(resource: Dict) -> Tuple:
+"""This is used for sorting resources by ID and version. First
+the ID is sorted, then the version. In cases where the version
+contains periods, it's assumed this is to separate a
+"major.minor.hotfix" style versioning system. In which case,  
the
+value separated in the most-significant position is sorted  
before
+those less significant. If the value is a digit it is cast as  
an

+int, otherwise, it is cast as a string, to lower-case.
+"""
+to_return = (resource["id"].lower(),)
+for val in resource["resource_version"].split("."):
+if val.isdigit():
+to_return += (int(val),)
+else:
+to_return += (str(val).lower(),)
+return to_return
+
 return sorted(
 resources,
-key=lambda resource: (
-resource["id"].lower(),
-StrictVersion(resource["resource_version"]),
-),
+key=lambda resource: sort_tuple(resource),
 reverse=True,
 )


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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1e3a96149f3cd6cbf4211a1565b5f74c85a0
Gerrit-Change-Number: 71741
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby Bruce 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-CC: kokoro 
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[gem5-users] Request for Guidance: Extracting Detailed Information for Floating-Point Instructions

2023-06-16 Thread Alexandra-Nicoleta DAVID via gem5-users

Dear gem5 Community,

I am currently using the gem5 simulator for my research work and I find it
a powerful and insightful tool for studying and understanding the inner
workings of computer architectures.

I am particularly interested in exploring and understanding the behavior of
floating-point instructions within certain benchmarking suites. For my
study, I need to extract detailed information about each floating-point
instruction that is executed, such as the Program Counter (PC), source
register, and destination register.

Despite my efforts, I am having difficulty obtaining this data. I have been
trying to use the trace functionality, but it seems I may be missing some
key steps or perhaps there is a better approach.

Could anyone guide me on how to accomplish this task? Specifically, I would
appreciate it if you could share any scripts, changes in the source code,
configuration options, or any other method that would allow me to collect
the information I need.

Your assistance in this matter would be greatly appreciated. I look forward
to the possibility of learning from your collective experience and
expertise.

Thank you for your time and consideration.

Best regards,

David Alexandra
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: fix load reserved store conditional

2023-06-16 Thread Gerrit

Adrià Armejach has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71558?usp=email )


Change subject: arch-riscv: fix load reserved store conditional
..

arch-riscv: fix load reserved store conditional

  * According to the manual, load reservations must be cleared on a
failed or a successful SC attempt.
  * A load reservation can be arbitrarily large. The current
implementation was reserving something different than cacheBlockSize
which could lead to problems if snoop addresses are cache block
aligned. This patch implementation assumes a cacheBlock granularity.
  * Load reservations should also be cleared on faults

Change-Id: I64513534710b5f269260fcb204f717801913e2f5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71558
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Roger Chang 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/generic/isa.hh
M src/arch/riscv/faults.cc
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
4 files changed, 34 insertions(+), 11 deletions(-)

Approvals:
  Roger Chang: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  kokoro: Regressions pass




diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh
index e9e4d95..58f66fc 100644
--- a/src/arch/generic/isa.hh
+++ b/src/arch/generic/isa.hh
@@ -70,6 +70,7 @@
   public:
 virtual PCStateBase *newPCState(Addr new_inst_addr=0) const = 0;
 virtual void clear() {}
+virtual void clearLoadReservation(ContextID cid) {}

 virtual RegVal readMiscRegNoEffect(RegIndex idx) const = 0;
 virtual RegVal readMiscReg(RegIndex idx) = 0;
diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index 940f710..8fb8f81 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -153,6 +153,9 @@
 tc->setMiscReg(MISCREG_NMIE, 0);
 }

+// Clear load reservation address
+tc->getIsaPtr()->clearLoadReservation(tc->contextId());
+
 // Set PC to fault handler address
 Addr addr = mbits(tc->readMiscReg(tvec), 63, 2);
 if (isInterrupt() && bits(tc->readMiscReg(tvec), 1, 0) == 1)
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index d744fe36..94a8239 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -672,11 +672,6 @@
 UNSERIALIZE_CONTAINER(miscRegFile);
 }

-const int WARN_FAILURE = 1;
-
-const Addr INVALID_RESERVATION_ADDR = (Addr) -1;
-std::unordered_map load_reservation_addrs;
-
 void
 ISA::handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask)
 {
@@ -696,9 +691,9 @@
 {
 Addr& load_reservation_addr = load_reservation_addrs[tc->contextId()];

-load_reservation_addr = req->getPaddr() & ~0xF;
+load_reservation_addr = req->getPaddr();
 DPRINTF(LLSC, "[cid:%d]: Reserved address %x.\n",
-req->contextId(), req->getPaddr() & ~0xF);
+req->contextId(), req->getPaddr());
 }

 bool
@@ -717,12 +712,13 @@
 lr_addr_empty ? "yes" : "no");
 if (!lr_addr_empty) {
 DPRINTF(LLSC, "[cid:%d]: addr = %x.\n", req->contextId(),
-req->getPaddr() & ~0xF);
+req->getPaddr() & cacheBlockMask);
 DPRINTF(LLSC, "[cid:%d]: last locked addr = %x.\n",  
req->contextId(),

-load_reservation_addr);
+load_reservation_addr & cacheBlockMask);
 }
-if (lr_addr_empty
-|| load_reservation_addr != ((req->getPaddr() & ~0xF))) {
+if (lr_addr_empty ||
+(load_reservation_addr & cacheBlockMask)
+!= ((req->getPaddr() & cacheBlockMask))) {
 req->setExtraData(0);
 int stCondFailures = tc->readStCondFailures();
 tc->setStCondFailures(++stCondFailures);
@@ -730,12 +726,21 @@
 warn("%i: context %d: %d consecutive SC failures.\n",
 curTick(), tc->contextId(), stCondFailures);
 }
+
+// Must clear any reservations
+load_reservation_addr = INVALID_RESERVATION_ADDR;
+
 return false;
 }
 if (req->isUncacheable()) {
 req->setExtraData(2);
 }

+// Must clear any reservations
+load_reservation_addr = INVALID_RESERVATION_ADDR;
+
+DPRINTF(LLSC, "[cid:%d]: SC success! Current locked addr = %x.\n",
+req->contextId(), load_reservation_addr & cacheBlockMask);
 return true;
 }

@@ -743,6 +748,8 @@
 ISA::globalClearExclusive()
 {
 tc->getCpuPtr()->wakeup(tc->threadId());
+Addr& load_reservation_addr = load_reservation_addrs[tc->contextId()];
+load_reservation_addr = INVALID_RESERVATION_ADDR;
 }

 void
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 5a2a610..7ef5c52 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -76,6 +76,11 @@

 bool hpmCounterEnabled(int counter) const;

+// Load reserve - store conditional

[gem5-dev] Re: [Important Announcement] gem5 Migration from Gerrit to GitHub

[gem5-dev] Re: v23.0 staging branch to be created on May 24th

[gem5-dev] [S] Change in gem5/gem5[release-staging-v23-0]: arch-riscv: fix load reserved store conditional

[gem5-dev] [S] Change in gem5/gem5[develop]: python: Remove Python 'pipes' module

[gem5-dev] [S] Change in gem5/gem5[develop]: scons,stdlib: Remove deprecated 'distutils' module

[gem5-users] Request for Guidance: Extracting Detailed Information for Floating-Point Instructions

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: fix load reserved store conditional

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