[gem5-dev] Change in gem5/gem5[develop]: cpu: fixed unused variable on fast binary
Andrea Mondelli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/29252 )
Change subject: cpu: fixed unused variable on fast binary
..
cpu: fixed unused variable on fast binary
When gem5.fast is compiled, an error on a variable
used only for debug purposes is raised:
build/X86/cpu/o3/mem_dep_unit_impl.hh:262:19: error: unused
variable 'producing_store' [-Werror=unused-variable]
for (auto producing_store : producing_stores)
This patch remove the variable when *.fast is used.
Change-Id: Ib77c26073db39644e3525bc16edcb7d3bc871d76
---
M src/cpu/o3/mem_dep_unit_impl.hh
1 file changed, 2 insertions(+), 0 deletions(-)
diff --git a/src/cpu/o3/mem_dep_unit_impl.hh
b/src/cpu/o3/mem_dep_unit_impl.hh
index 9a50341..57e90d2 100644
--- a/src/cpu/o3/mem_dep_unit_impl.hh
+++ b/src/cpu/o3/mem_dep_unit_impl.hh
@@ -259,7 +259,9 @@
} else {
// Otherwise make the instruction dependent on the store/barrier.
DPRINTF(MemDepUnit, "Adding to dependency list\n");
+#if TRACING_ON==1
for (auto producing_store : producing_stores)
+#endif
DPRINTF(MemDepUnit, "\tinst PC %s is dependent on
[sn:%lli].\n",
inst->pcState(), producing_store);
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/29252
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib77c26073db39644e3525bc16edcb7d3bc871d76
Gerrit-Change-Number: 29252
Gerrit-PatchSet: 1
Gerrit-Owner: Andrea Mondelli
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: cpu: fixed unused variable on fast binary
Andrea Mondelli has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/29252 )
Change subject: cpu: fixed unused variable on fast binary
..
cpu: fixed unused variable on fast binary
When gem5.fast is compiled, an error on a variable
used only for debug purposes is raised:
build/X86/cpu/o3/mem_dep_unit_impl.hh:262:19: error: unused
variable 'producing_store' [-Werror=unused-variable]
for (auto producing_store : producing_stores)
This patch remove the variable when *.fast is used.
Change-Id: Ib77c26073db39644e3525bc16edcb7d3bc871d76
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29252
Tested-by: kokoro
Reviewed-by: Bobby R. Bruce
Maintainer: Bobby R. Bruce
---
M src/cpu/o3/mem_dep_unit_impl.hh
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/o3/mem_dep_unit_impl.hh
b/src/cpu/o3/mem_dep_unit_impl.hh
index 9a50341..d1eac29 100644
--- a/src/cpu/o3/mem_dep_unit_impl.hh
+++ b/src/cpu/o3/mem_dep_unit_impl.hh
@@ -259,7 +259,7 @@
} else {
// Otherwise make the instruction dependent on the store/barrier.
DPRINTF(MemDepUnit, "Adding to dependency list\n");
-for (auto producing_store : producing_stores)
+for (auto M5_VAR_USED producing_store : producing_stores)
DPRINTF(MemDepUnit, "\tinst PC %s is dependent on
[sn:%lli].\n",
inst->pcState(), producing_store);
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/29252
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib77c26073db39644e3525bc16edcb7d3bc871d76
Gerrit-Change-Number: 29252
Gerrit-PatchSet: 4
Gerrit-Owner: Andrea Mondelli
Gerrit-Reviewer: Andrea Mondelli
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem: model data array bank in classic cache - revisited
Hello Andrea Mondelli,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/30035
to review the following change.
Change subject: mem: model data array bank in classic cache - revisited
..
mem: model data array bank in classic cache - revisited
Recently, I dug up an old patch initially proposed by Xiangyu Dong and
never integrated into gem5.
I adapted it to the new basecode. I bring back the original changelog:
The classic cache does not model data array bank, i.e. if a read/write is
being
serviced by a cache bank, no other requests should be sent to this bank.
This patch models a multi-bank cache. Features include:
1. detect if the bank interleave granularity is larger than cache line size
2. add CacheBank debug flag
3. Differentiate read and write latency
3a. read latency is named as read_latency
3b. write latency is named as write_latency
4. Add write_latency, num_banks, bank_itlv_bit into the Python parser
5. Enabling bank model by --l1-bank-model, --l2-bank-model, --l3-bank-model
Not modeled in this patch:
Due to the lack of retry mechanism in the cache master port, the access form
the memory side will not be denied if the bank is in service. Instead, the
bank
service time will be extended. This is equivalent to an infinite write
buffer
for cache fill operations.
I remain available for any changes or improvements, it would be interesting
to integrate this feature in the cache model.
Change-Id: I8ae601df924aadcee29f87326517e3157b9cb93c
---
M configs/common/CacheConfig.py
M configs/common/Caches.py
M configs/common/Options.py
M src/mem/cache/Cache.py
M src/mem/cache/SConscript
M src/mem/cache/base.cc
M src/mem/cache/base.hh
7 files changed, 246 insertions(+), 6 deletions(-)
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index 05c38e0..040fe0e 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -99,7 +99,10 @@
# same clock as the CPUs.
system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
size=options.l2_size,
- assoc=options.l2_assoc)
+ assoc=options.l2_assoc,
+
enable_bank_model=options.l2_enable_bank,
+ num_banks=options.l2_num_banks,
+
bank_intlv_high_bit=options.l2_intlv_bit)
system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)
system.l2.cpu_side = system.tol2bus.master
@@ -119,9 +122,15 @@
for i in range(options.num_cpus):
if options.caches:
icache = icache_class(size=options.l1i_size,
- assoc=options.l1i_assoc)
+ assoc=options.l1i_assoc,
+ enable_bank_model=options.l1_enable_bank,
+ num_banks=options.l1_num_banks,
+ bank_intlv_high_bit=options.l1_intlv_bit)
dcache = dcache_class(size=options.l1d_size,
- assoc=options.l1d_assoc)
+ assoc=options.l1d_assoc,
+ enable_bank_model=options.l1_enable_bank,
+ num_banks=options.l1_num_banks,
+ bank_intlv_high_bit=options.l1_intlv_bit)
# If we have a walker cache specified, instantiate two
# instances here
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 77213e8..10ab6ff 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -56,6 +56,7 @@
response_latency = 2
mshrs = 4
tgts_per_mshr = 20
+enable_bank_model = False
class L1_ICache(L1Cache):
is_read_only = True
@@ -73,6 +74,7 @@
mshrs = 20
tgts_per_mshr = 12
write_buffers = 8
+enable_bank_model = False
class IOCache(Cache):
assoc = 8
@@ -82,6 +84,7 @@
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
+enable_bank_model = False
class PageTableWalkerCache(Cache):
assoc = 2
@@ -91,6 +94,7 @@
mshrs = 10
size = '1kB'
tgts_per_mshr = 12
+enable_bank_model = False
# the x86 table walker actually writes to the table-walker cache
if buildEnv['TARGET_ISA'] in ['x86', 'riscv']:
diff --git a/configs/common/Options.py b/configs/common/Options.py
index 3eff04b..d1dfeff 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -134,6 +134,24 @@
parser.add_option("--l1i_assoc", type="int", default=2)
parser.add_option("--l2_assoc", type="int", default=8)
parser.add_option("--l3_assoc", type="int", default=16)
+parser.add_option("--l1-enable-bank", action="store_true",
+ help="Enable
[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: arch-riscv: Fixed CPU switching and PLIC issue with MinorCPU
Andrea Mondelli has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41933 )
Change subject: arch-riscv: Fixed CPU switching and PLIC issue with MinorCPU
..
arch-riscv: Fixed CPU switching and PLIC issue with MinorCPU
Added takeover methods for PMA Checker and RiscvTLB to ensure
that checkpoint restoration works. Also added logic in PLIC
to prevent posting interrupts to a CPU that has yet to complete
the current interrupt. PLIC's behaviour when a CPU claims another
interrupt before completion is also changed. Now PLIC will return
the uncompleted interrupt ID instead of return 0. This behaviour
is not documented in the specs but is designed this way to avoid
issues from CPU side (especially MinorCPU).
Change-Id: I68eaaf56d2c4d76cc1e0a1e2160f5abe184c2cd5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41933
Maintainer: Bobby R. Bruce
Tested-by: kokoro
Reviewed-by: Ayaz Akram
---
M src/arch/generic/mmu.hh
M src/arch/riscv/RiscvMMU.py
M src/arch/riscv/RiscvTLB.py
M src/arch/riscv/mmu.hh
M src/arch/riscv/pma_checker.cc
M src/arch/riscv/pma_checker.hh
M src/arch/riscv/tlb.cc
M src/arch/riscv/tlb.hh
M src/dev/riscv/plic.cc
9 files changed, 67 insertions(+), 13 deletions(-)
Approvals:
Ayaz Akram: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/generic/mmu.hh b/src/arch/generic/mmu.hh
index 9765273..79e53dc 100644
--- a/src/arch/generic/mmu.hh
+++ b/src/arch/generic/mmu.hh
@@ -103,7 +103,7 @@
return getTlb(mode)->finalizePhysical(req, tc, mode);
}
-void takeOverFrom(BaseMMU *old_mmu);
+virtual void takeOverFrom(BaseMMU *old_mmu);
public:
BaseTLB* dtb;
diff --git a/src/arch/riscv/RiscvMMU.py b/src/arch/riscv/RiscvMMU.py
index 4ff477e..38f1da9 100644
--- a/src/arch/riscv/RiscvMMU.py
+++ b/src/arch/riscv/RiscvMMU.py
@@ -35,6 +35,8 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+from m5.params import *
+
from m5.objects.BaseMMU import BaseMMU
from m5.objects.RiscvTLB import RiscvTLB
from m5.objects.PMAChecker import PMAChecker
@@ -45,7 +47,7 @@
cxx_header = 'arch/riscv/mmu.hh'
itb = RiscvTLB()
dtb = RiscvTLB()
-pma_checker = PMAChecker()
+pma_checker = Param.PMAChecker(PMAChecker(), "PMA Checker")
@classmethod
def walkerPorts(cls):
diff --git a/src/arch/riscv/RiscvTLB.py b/src/arch/riscv/RiscvTLB.py
index b419262..05ff521 100644
--- a/src/arch/riscv/RiscvTLB.py
+++ b/src/arch/riscv/RiscvTLB.py
@@ -43,7 +43,7 @@
num_squash_per_cycle = Param.Unsigned(4,
"Number of outstanding walks that can be squashed per cycle")
# Grab the pma_checker from the MMU
-pma_checker = Param.PMAChecker(Parent.any, "PMA Chekcer")
+pma_checker = Param.PMAChecker(Parent.any, "PMA Checker")
class RiscvTLB(BaseTLB):
type = 'RiscvTLB'
@@ -53,4 +53,4 @@
walker = Param.RiscvPagetableWalker(\
RiscvPagetableWalker(), "page table walker")
# Grab the pma_checker from the MMU
-pma_checker = Param.PMAChecker(Parent.any, "PMA Chekcer")
+pma_checker = Param.PMAChecker(Parent.any, "PMA Checker")
diff --git a/src/arch/riscv/mmu.hh b/src/arch/riscv/mmu.hh
index 322f0af..ce3ce30 100644
--- a/src/arch/riscv/mmu.hh
+++ b/src/arch/riscv/mmu.hh
@@ -40,6 +40,7 @@
#include "arch/generic/mmu.hh"
#include "arch/riscv/isa.hh"
+#include "arch/riscv/pma_checker.hh"
#include "arch/riscv/tlb.hh"
#include "params/RiscvMMU.hh"
@@ -49,8 +50,10 @@
class MMU : public BaseMMU
{
public:
+PMAChecker *pma;
+
MMU(const RiscvMMUParams )
- : BaseMMU(p)
+ : BaseMMU(p), pma(p.pma_checker)
{}
PrivilegeMode
@@ -64,6 +67,14 @@
{
return static_cast(dtb)->getWalker();
}
+
+void
+takeOverFrom(BaseMMU *old_mmu) override
+{
+ MMU *ommu = dynamic_cast(old_mmu);
+ BaseMMU::takeOverFrom(ommu);
+ pma->takeOverFrom(ommu->pma);
+}
};
} // namespace RiscvISA
diff --git a/src/arch/riscv/pma_checker.cc b/src/arch/riscv/pma_checker.cc
index 32cb66d..d36dc1d 100644
--- a/src/arch/riscv/pma_checker.cc
+++ b/src/arch/riscv/pma_checker.cc
@@ -81,3 +81,9 @@
{
return isUncacheable(pkt->getAddrRange());
}
+
+void
+PMAChecker::takeOverFrom(PMAChecker *old)
+{
+uncacheable = old->uncacheable;
+}
diff --git a/src/arch/riscv/pma_checker.hh b/src/arch/riscv/pma_checker.hh
index 5833dbe..298d4a0 100644
--- a/src/arch/riscv/pma_checker.hh
+++ b/src/arch/riscv/pma_checker.hh
@@ -74,6 +74,8 @@
bool isUncacheable(const AddrRange );
bool isUncacheable(const Addr , const unsigned size);
bool isUncacheable(PacketPtr pkt);
+
+void takeOverFrom(PMAChecker *old);
};
#endif // __ARCH_RISCV_PMA_CHECKER_HH__
diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc
