[gem5-dev] [S] Change in gem5/gem5[release-staging-v23-0]: arch-arm: Apply FEAT_IDST to missing ID registers

-Change-Number: 71178 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Bobby Bruce Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro

[gem5-dev] [S] Change in gem5/gem5[develop]: dev-arm: Treat GICv3 reserved addresses as RES0

; break; } } -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/71138?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branc

[gem5-dev] [S] Change in gem5/gem5[release-staging-v23-0]: arch-arm: Apply FEAT_IDST to AArch32 state registers

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/71178?usp=email ) Change subject: arch-arm: Apply FEAT_IDST to AArch32 state registers .. arch-arm: Apply

[gem5-dev] [S] Change in gem5/gem5[develop]: dev-arm: Treat GICv3 reserved addresses as RES0

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/71138?usp=email ) Change subject: dev-arm: Treat GICv3 reserved addresses as RES0 .. dev-arm: Treat GICv3

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Add an ArmAllRelease containing every defined extension

05a5a9186d02aa99 Gerrit-Change-Number: 70958 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro __

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Add an ArmAllRelease containing every defined extension

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/70958?usp=email ) Change subject: arch-arm: Add an ArmAllRelease containing every defined extension ..

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_EVT

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/70938?usp=email ) Change subject: arch-arm: Implement FEAT_EVT .. arch-arm: Implement FEAT_EVT This extension is

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_HCX

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/70939?usp=email ) Change subject: arch-arm: Implement FEAT_HCX .. arch-arm: Implement FEAT_HCX This is just

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Fix printing of VecElemClass registers

: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Bobby Bruce Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro ___ gem5-dev

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Rename AdvSIMD instruction pool

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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Improve debugging of CC regs accesses

.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ib4b56a372b25e5bc2b6b762d2ef3ff2084097cce Gerrit-Change-Number: 70718 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-R

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Define a AA64ZFR0 data type

or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I6b0dcf0c1882f356783934f625c2bc3a25fbb885 Gerrit-Change-Number: 70725 Gerrit-PatchSet: 3 Gerrit-Owner: G

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Define remaining fields of the arm64 AT_HWCAP entry

t: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I4db4884d677f6d25417ae6edceb7f1e8dfad36cb Gerrit-Change-Number: 70758 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Ge

[gem5-dev] [L] Change in gem5/gem5[develop]: arch-arm: Split decodeDataProcReg into subfunctions

t: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ifa03a93cb73de0b2dc93d7784f9011e0e55dfc1e Gerrit-Change-Number: 70717 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Review

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Extend auxiliary vector with AT_HWCAP2 entry

armHwcapImpl2() const override; }; } // namespace gem5 -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70760?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project:

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Extend SCR to be 64-bit wide

rrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I9928de3db61957404269d189a15a951fd6707c8a Gerrit-Change-Number: 70720 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Re

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Enable FEAT_PAuth in SE mode

develop Gerrit-Change-Id: I6da5da0878dde56c22ffdba25eff15e36f5022fe Gerrit-Change-Number: 70759 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_FLAGM(2)

on::FEAT_TLBIOS) ? 0x1 : 0x0; + isar0_el1.ts = release->has(ArmExtension::FEAT_FLAGM2) ? + 0x2 : release->has(ArmExtension::FEAT_FLAGM) ? + 0x1 : 0x0; return isar0_el1; }()) .faultRead(EL1, HCR_TRAP(tid3)) -- To vi

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement trapping of SME registers

/gem5-review.googlesource.com/c/public/gem5/+/70722?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ic5bcc79a535c928265fb

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_IDST

lesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I3cabcfdb10f4eefaf2ab039376d840cc4c54609a Gerrit-Change-Number: 70723 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer:

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_RNG

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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Extend auxiliary vector with AT_HWCAP2 entry

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/70760?usp=email ) Change subject: arch-arm: Extend auxiliary vector with AT_HWCAP2 entry .. arch-arm: Extend

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Define remaining fields of the arm64 AT_HWCAP entry

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/70758?usp=email ) Change subject: arch-arm: Define remaining fields of the arm64 AT_HWCAP entry .. arch-arm:

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Enable FEAT_PAuth in SE mode

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/70759?usp=email ) Change subject: arch-arm: Enable FEAT_PAuth in SE mode .. arch-arm: Enable FEAT_PAuth in SE

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Re-factor Arm decoder for SVE mixed-sign DOT insts.

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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Declare support for Armv8.2-F64MM.

ltRead(EL0, faultIdst) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70729?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Ger

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Add support for Armv8.2-I8MM NEON extension.

om/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I6fb9318f67cc9d2737079283e1a095630c4d2ad9 Gerrit-Change-Number: 70737 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Declare support for Armv8.2-I8MM.

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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Fix too long lines in existing Arm NEON instructons.

t-Change-Id: I587fcb2d75c4ab9de47fa53b4ae96526a20afe3f Gerrit-Change-Number: 70735 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm, cpu, configs: Add new Op Classes for Matrix Multiply insts

atMultAcc; static const OpClass SimdShiftOp = enums::SimdShift; static const OpClass SimdShiftAccOp = enums::SimdShiftAcc; static const OpClass SimdDivOp = enums::SimdDiv; @@ -87,6 +88,7 @@ static const OpClass SimdFloatMiscOp = enums::SimdFloatMisc; st

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Add support for Arm SVE Integer Matrix instructions.

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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Added Armv8.2-I8MM SVE mixed-sign dot product instrs.

l Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I83841654cee74b940f967b3a37b99d87c01bd92c Gerrit-Change-Number: 70732 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Support Arm SVE Load-Broadcast Octaword instructions.

Segments=2) +# LD1RO{B,H,W,D} (scalar plus scalar) +emitSveLoadAndReplMulti(offsetIsImm=False, numQwordSegments=2) # LD{2,3,4}{B,H,W,D} (scalar plus immediate) # ST{2,3,4}{B,H,W,D} (scalar plus immediate) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/7

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Add support for Armv8.2-DotProd NEON extension.

esource.com/c/public/gem5/+/70736?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I4caa3b97a74c65f32421487c55c3e36427194e61 Gerrit-Change-Number: 70736 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [L] Change in gem5/gem5[develop]: arch-arm: Add support for Arm SVE fmmla instruction.

aultRead(EL1, HCR_TRAP(tid3)) .allPrivileges().exceptUserMode().writes(0); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70726?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: If3547378ffa48527fe540767399bcc37a5dab524 Gerrit-Change-Number: 70726 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Rename AdvSIMD instruction pool

lp writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I056da8f0c7808935d12a4b05490d30654178071f Gerrit-Change-Number: 70724 Gerrit-PatchSet: 1 Gerrit-Owner: Giaco

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_FLAGM(2)

IOS) ? 0x1 : 0x0; + isar0_el1.ts = release->has(ArmExtension::FEAT_FLAGM2) ? + 0x2 : release->has(ArmExtension::FEAT_FLAGM) ? + 0x1 : 0x0; return isar0_el1; }()) .faultRead(EL1, HCR_TRAP(tid3)) -- To view, visit https://gem5-review.goo

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Improve debugging of CC regs accesses

tps://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ib4b56a372b25e5bc2b6b762d2ef3ff2084097cce Gerrit-Change-Number: 70718 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement trapping of SME registers

rrit-Change-Id: Ic5bcc79a535c928265fbc1db1cd0c85ba1a1b152 Gerrit-Change-Number: 70722 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [L] Change in gem5/gem5[develop]: arch-arm: Split decodeDataProcReg into subfunctions

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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Define a AA64ZFR0 data type

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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_RNG

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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_IDST

ail Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I3cabcfdb10f4eefaf2ab039376d840cc4c54609a Gerrit-Change-Number: 70723 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Extend SCR to be 64-bit wide

e.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I9928de3db61957404269d189a15a951fd6707c8a Gerrit-Change-Number: 70720 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-A

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Fix printing of VecElemClass registers

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/70697?usp=email ) Change subject: arch-arm: Fix printing of VecElemClass registers .. arch-arm: Fix printing of

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_TLBIOS

", "tlbi_ipas2le1_xt", "tlbi_alle2", @@ -2370,8 +2399,11 @@ "tlbi_vale2_xt", "tlbi_vmalls12e1", "tlbi_alle3is", +"tlbi_alle3os", "tlbi_vae3is_xt", + "tlbi_

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Add UNSERIALIZE flag to address cpt compatibility

Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro ___ gem5-dev mailing list -- gem5-dev@g

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement RES0/RES1 with miscreg specifiers

mail Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ic2caea121e02f63f069f1576760c849bcbdac894 Gerrit-Change-Number: 70563 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Update MISCREG_DBGDIDR to point to Armv8 debug arch

lic/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I20691ecdaedde6740c706782635b1f9a4491dc51 Gerrit-Change-Number: 70561 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Implement RAZ/WI with raz specifier

ct: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I195f042fbeb10c0ca1f9095a0d26e6c213496ee5 Gerrit-Change-Number: 70560 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewe

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Provide default mask for raz/rao helpers

: I309e345fc8336df3a74474f8f9202bf7e2095b41 Gerrit-Change-Number: 70559 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Simplify FPSCR writes

lters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I59942bd98c074349307d27e3a99351ee25f4db95 Gerrit-Change-Number: 70565 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Review

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Extend SCTLR to be 64-bit wide

70566 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro ___ gem5-dev mailing list -- gem5-dev

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Move RO values from ISA::read to the reset field

Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I62270cdb59f39b8a143e9554c8beaa8cd15824aa Gerrit-Change-Number: 70558 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Rev

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Group self hosted debug writes in ISA switch

m/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: If9c0675743856b603e7b5ec1898f5cdd650f3ce6 Gerrit-Change-Number: 70562 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Review

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Remove unnecessary case in ISA::readMiscReg

//gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I8b95a75fbfec2626fbe8b455ae9b3f30acda538f Gerrit-Change-Number: 70564 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Re

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Fix position of AA64ISAR0.AES bitfield

chSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Fix position of AA64ISAR0.AES bitfield

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/70637?usp=email ) Change subject: arch-arm: Fix position of AA64ISAR0.AES bitfield .. arch-arm: Fix position of

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_TLBIOS

3is_xt", +"tlbi_vae3os_xt", "tlbi_vale3is_xt", +"tlbi_vale3os_xt", "tlbi_alle3", "tlbi_vae3_xt", "tlbi_vale3_xt", -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70567?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I2198e6155f1eea7c5f8083c6ffb178d3a3d163d3 Gerrit-Change-Number: 70567 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement RES0/RES1 with miscreg specifiers

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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Provide default mask for raz/rao helpers

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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Update MISCREG_DBGDIDR to point to Armv8 debug arch

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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Add UNSERIALIZE flag to address cpt compatibility

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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Extend SCTLR to be 64-bit wide

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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Move RO values from ISA::read to the reset field

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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Simplify FPSCR writes

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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Remove unnecessary case in ISA::readMiscReg

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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Implement RAZ/WI with raz specifier

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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Group self hosted debug writes in ISA switch

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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Remove clear32/64 methods

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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Remove ISA::initID64

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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Rewrite ISA::initID64 using BitUnions

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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: VMPIDR_EL2 can be used in secure mode as well

errit-Branch: develop Gerrit-Change-Id: Ie7e112a83e64f33a98885e88504c2d6bc5070218 Gerrit-Change-Number: 70471 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Ge

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Remove ISA::initID32

46e64c6ee55fa8cedf98ac6 Gerrit-Change-Number: 70467 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Make MISCREGs reset value configurable

: I536065a2de5faeb8ab64391f8ca2aa83fb2cc82f Gerrit-Change-Number: 70458 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Rewrite ISA::initID32 using BitUnions

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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Map CTR_EL0 to AArch32 version

/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ia3e0cafa1bd2a3054b286e79ac378c895d6910e8 Gerrit-Change-Number: 70463 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Replace 0ing of miscRegs with assignment of reset value

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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Fix read redirection for MIDR register

4 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro ___ gem5-dev mailing list -- gem5-dev@

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Map MIDR_EL1 to AArch32 version

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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Move MISCREG init logic from ISA to reset field

Mode(); InitReg(MISCREG_NMRR_S) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70465?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Map MPIDR_EL1 to AArch32 version

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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Generalize SCTLR_RST behaviour

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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Remove clear32/64 methods

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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Rewrite ISA::initID64 using BitUnions

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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: VMPIDR_EL2 can be used in secure mode as well

elop Gerrit-Change-Id: Ie7e112a83e64f33a98885e88504c2d6bc5070218 Gerrit-Change-Number: 70471 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Attention: Richard Cooper ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsu

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Remove ISA::initID64

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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Remove ISA::initID32

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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Map MIDR_EL1 to AArch32 version

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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Fix read redirection for MIDR register

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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Move MISCREG init logic from ISA to reset field

:2 +0) .privSecure(!aarch32EL3) .nonSecure().exceptUserMode(); InitReg(MISCREG_NMRR_S) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70465?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.c

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Map MPIDR_EL1 to AArch32 version

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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Map MVFR0_EL1/MVFR1_EL1 to AArch32 version

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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Map CTR_EL0 to AArch32 version

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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Generalize SCTLR_RST behaviour

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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Rewrite ISA::initID32 using BitUnions

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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Make MISCREGs reset value configurable

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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Replace 0ing of miscRegs with assignment of reset value

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[gem5-dev] [L] Change in gem5/gem5[develop]: arch-arm: Partial SVE2 Implementation

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/70277?usp=email ) Change subject: arch-arm: Partial SVE2 Implementation .. arch-arm: Partial SVE2 Implementation

[gem5-dev] [S] Change in gem5/gem5[develop]: mem: Fix SW prefetch asynchronous handling

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/70117?usp=email ) Change subject: mem: Fix SW prefetch asynchronous handling .. mem: Fix SW prefetch asynchronous

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