[gem5-dev] Change in public/gem5[master]: arch-arm: Change function name for banked miscregs

Hello Nikos Nikoleris, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/7982 to review the following change. Change subject: arch-arm: Change function name for banked miscregs ..

[gem5-dev] Change in public/gem5[master]: arch-arm: Fix AArch32 SETEND Instruction

Hello Nikos Nikoleris, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/7981 to review the following change. Change subject: arch-arm: Fix AArch32 SETEND Instruction .. arch-arm: Fix

[gem5-dev] Change in public/gem5[master]: arch-arm: Fix syntax error in TLB::getResultTe

Hello Nikos Nikoleris, Andreas Sandberg, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/7983 to review the following change. Change subject: arch-arm: Fix syntax error in TLB::getResultTe

[gem5-dev] Change in public/gem5[master]: arch-arm: isSecureBelow from armarm pseudocode

Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/7221 ) Change subject: arch-arm: isSecureBelow from armarm pseudocode .. arch-arm: isSecureBelow from armarm pseudocode

[gem5-dev] Change in public/gem5[master]: arch-arm: Fix incorrect assumptions in ELIs64

Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/7141 ) Change subject: arch-arm: Fix incorrect assumptions in ELIs64 .. arch-arm: Fix incorrect assumptions in ELIs64 The

[gem5-dev] Change in public/gem5[master]: arch-arm: Correct Illegal Exception Return detection

Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/7223 ) Change subject: arch-arm: Correct Illegal Exception Return detection .. arch-arm: Correct Illegal Exception Return

[gem5-dev] Change in public/gem5[master]: arch-arm: ELUsingAArch32K from armarm pseudocode

Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/7222 ) Change subject: arch-arm: ELUsingAArch32K from armarm pseudocode .. arch-arm: ELUsingAArch32K from armarm

[gem5-dev] Change in public/gem5[master]: arch-arm: Fix AArch32 SETEND Instruction

Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/7981 ) Change subject: arch-arm: Fix AArch32 SETEND Instruction .. arch-arm: Fix AArch32 SETEND Instruction This patch

[gem5-dev] Change in public/gem5[master]: arch-arm: Change function name for banked miscregs

Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/7982 ) Change subject: arch-arm: Change function name for banked miscregs .. arch-arm: Change function name for banked

[gem5-dev] Change in public/gem5[master]: arch-arm: Fixed error in choosing vector offset

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/8001 Change subject: arch-arm: Fixed error in choosing vector offset .. arch-arm: Fixed error in choosing vector offset The old

[gem5-dev] Change in public/gem5[master]: arch-arm: Change ArmFault cast from reinterpret to static

Giacomo Travaglini merged this change by Giacomo Travaglini. ( https://gem5-review.googlesource.com/8241 ) Change subject: arch-arm: Change ArmFault cast from reinterpret to static .. arch-arm: Change ArmFault cast from

[gem5-dev] Change in public/gem5[master]: arch-arm: Arch regs and pseudo regs distinction

Giacomo Travaglini merged this change by Giacomo Travaglini. ( https://gem5-review.googlesource.com/7921 ) Change subject: arch-arm: Arch regs and pseudo regs distinction .. arch-arm: Arch regs and pseudo regs distinction A

[gem5-dev] Change in public/gem5[master]: arch-arm: IMPLEMENTATION DEFINED register

Giacomo Travaglini merged this change by Giacomo Travaglini. ( https://gem5-review.googlesource.com/7922 ) Change subject: arch-arm: IMPLEMENTATION DEFINED register .. arch-arm: IMPLEMENTATION DEFINED register A new pseudo

[gem5-dev] Change in public/gem5[master]: arch-arm: Fix FSC generation in AbortFault

Hello Andreas Sandberg, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/8362 to review the following change. Change subject: arch-arm: Fix FSC generation in AbortFault .. arch-arm:

[gem5-dev] Change in public/gem5[master]: arch-arm: Fix syntax error in TLB::getResultTe

Giacomo Travaglini merged this change by Chuan Zhu. ( https://gem5-review.googlesource.com/7983 ) Change subject: arch-arm: Fix syntax error in TLB::getResultTe .. arch-arm: Fix syntax error in TLB::getResultTe The patch

[gem5-dev] Change in public/gem5[master]: arch-arm: Semihosting not available in syscall emulation

Hello Andreas Sandberg, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/8367 to review the following change. Change subject: arch-arm: Semihosting not available in syscall emulation ..

[gem5-dev] Change in public/gem5[master]: arch-arm: HLT using immediate when checking for semihosting

Hello Andreas Sandberg, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/8369 to review the following change. Change subject: arch-arm: HLT using immediate when checking for semihosting

[gem5-dev] Change in public/gem5[master]: arch-arm: Add AArch32 HLT Semihosting interface

Hello Andreas Sandberg, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/8372 to review the following change. Change subject: arch-arm: Add AArch32 HLT Semihosting interface ..

[gem5-dev] Change in public/gem5[master]: arch-arm: Make hlt64 a mem barrier with semihosting

Hello Andreas Sandberg, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/8373 to review the following change. Change subject: arch-arm: Make hlt64 a mem barrier with semihosting ..

[gem5-dev] Change in public/gem5[master]: arch-arm: Add AArch32 SVC Semihosting interface

Hello Andreas Sandberg, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/8371 to review the following change. Change subject: arch-arm: Add AArch32 SVC Semihosting interface ..

[gem5-dev] Change in public/gem5[master]: arch-arm: Adding isa templates for semihosting ops

Hello Andreas Sandberg, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/8370 to review the following change. Change subject: arch-arm: Adding isa templates for semihosting ops ..

[gem5-dev] Change in public/gem5[master]: arch-arm: Fix Hlt64, Svc64, Hvc64, Smc64, Brk64 disassembly

Hello Andreas Sandberg, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/8368 to review the following change. Change subject: arch-arm: Fix Hlt64,Svc64,Hvc64,Smc64,Brk64 disassembly ..

[gem5-dev] Change in public/gem5[master]: arch-arm: Make hlt64 a mem barrier with semihosting

Giacomo Travaglini merged this change by Giacomo Travaglini. ( https://gem5-review.googlesource.com/8373 ) Change subject: arch-arm: Make hlt64 a mem barrier with semihosting .. arch-arm: Make hlt64 a mem barrier with

[gem5-dev] Change in public/gem5[master]: arch-arm: Fix Hlt64, Svc64, Hvc64, Smc64, Brk64 disassembly

Giacomo Travaglini merged this change by Giacomo Travaglini. ( https://gem5-review.googlesource.com/8368 ) Change subject: arch-arm: Fix Hlt64,Svc64,Hvc64,Smc64,Brk64 disassembly .. arch-arm: Fix Hlt64,Svc64,Hvc64,Smc64,Brk64

[gem5-dev] Change in public/gem5[master]: cpu-o3: Don't add non-speculative mem barriers to the IQ twice

Giacomo Travaglini merged this change by Andreas Sandberg. ( https://gem5-review.googlesource.com/8374 ) Change subject: cpu-o3: Don't add non-speculative mem barriers to the IQ twice .. cpu-o3: Don't add non-speculative

[gem5-dev] Change in public/gem5[master]: arch-arm: HLT using immediate when checking for semihosting

Giacomo Travaglini merged this change by Giacomo Travaglini. ( https://gem5-review.googlesource.com/8369 ) Change subject: arch-arm: HLT using immediate when checking for semihosting .. arch-arm: HLT using immediate when

[gem5-dev] Change in public/gem5[master]: arch-arm: Add AArch32 SVC Semihosting interface

Giacomo Travaglini merged this change by Giacomo Travaglini. ( https://gem5-review.googlesource.com/8371 ) Change subject: arch-arm: Add AArch32 SVC Semihosting interface .. arch-arm: Add AArch32 SVC Semihosting interface

[gem5-dev] Change in public/gem5[master]: arch-arm: Add AArch32 HLT Semihosting interface

Giacomo Travaglini merged this change by Giacomo Travaglini. ( https://gem5-review.googlesource.com/8372 ) Change subject: arch-arm: Add AArch32 HLT Semihosting interface .. arch-arm: Add AArch32 HLT Semihosting interface

[gem5-dev] Change in public/gem5[master]: arch-arm: Adding isa templates for semihosting ops

Giacomo Travaglini merged this change by Giacomo Travaglini. ( https://gem5-review.googlesource.com/8370 ) Change subject: arch-arm: Adding isa templates for semihosting ops .. arch-arm: Adding isa templates for semihosting

[gem5-dev] Change in public/gem5[master]: arch-arm: Fix StaticInst encoding() method

Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/6881 ) Change subject: arch-arm: Fix StaticInst encoding() method .. arch-arm: Fix StaticInst encoding() method The

[gem5-dev] Change in public/gem5[master]: arch-arm: Hyp routed undef fault need to change its syndrome

Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/6621 ) Change subject: arch-arm: Hyp routed undef fault need to change its syndrome .. arch-arm: Hyp routed undef fault

[gem5-dev] Change in public/gem5[master]: arch-arm: Fixed WFE/WFI trapping behaviour

Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/6622 ) Change subject: arch-arm: Fixed WFE/WFI trapping behaviour .. arch-arm: Fixed WFE/WFI trapping behaviour This

[gem5-dev] Change in gem5/gem5[master]: base: Add an asymmetrical Coroutine class

https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I7bb673a954d4a456997afd45b696933534f3e239 Gerrit-Change-Number: 11195 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Gabe Black

[gem5-dev] Change in gem5/gem5[master]: cpu: Fix bug introduced by RequestPtr type change

nch: master Gerrit-Change-Id: Ifccb6df2427df8b0daac5ee6a99e5cca0b20825e Gerrit-Change-Number: 11469 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org h

[gem5-dev] Change in gem5/gem5[master]: cpu: Fix bug introduced by RequestPtr type change

469 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: mer

[gem5-dev] Change in gem5/gem5[master]: base: Add an asymmetrical Coroutine class

https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I7bb673a954d4a456997afd45b696933534f3e239 Gerrit-Change-Number: 11195 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Gabe Black

[gem5-dev] Change in gem5/gem5[master]: base: Add an asymmetrical Coroutine class

https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I7bb673a954d4a456997afd45b696933534f3e239 Gerrit-Change-Number: 11195 Gerrit-PatchSet: 4 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Gabe Black

[gem5-dev] Change in gem5/gem5[master]: arch-arm: BadMode checking if corresponding EL is implemented

lic/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ibfe385c5465b904acc0d2eb9647710891d72c9df Gerrit-Change-Number: 11196 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-MessageType: merged ___ gem5-dev

[gem5-dev] Change in gem5/gem5[master]: arch-arm: AArch32 execution triggering AArch64 SW Break

Gerrit-Branch: master Gerrit-Change-Id: I485852ed19429f9cd928a6447a95eb6f471f189c Gerrit-Change-Number: 11197 Gerrit-PatchSet: 4 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: base: Fix ucontext compilation error for macOS

7 Gerrit-Change-Number: 11729 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Matteo Andreozzi Gerrit-Reviewer: Matthias Jung Gerrit-MessageType

[gem5-dev] Change in gem5/gem5[master]: mem: Implement base QoS Policies.

Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-MessageType: newpatchset

[gem5-dev] Change in gem5/gem5[master]: mem: Add a QoS-aware Memory Controller type

it-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I0b611f13fce54dd1dd444eb806f8e98afd248bd5 Gerrit-Change-Number: 11970 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Gabe Black Gerrit-Reviewe

[gem5-dev] Change in gem5/gem5[master]: mem: Add a simple QoS-aware Memory Controller

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[gem5-dev] Change in gem5/gem5[master]: mem: Make DRAMCtrl a QoS-aware Memory Controller

stored seperately mostly to keep the code clean + * responses are stored separately mostly to keep the code clean * and help with events scheduling. For all logical purposes such * as sizing the read queue, this and the main read queue nee

[gem5-dev] Change in gem5/gem5[master]: mem: Add a simple QoS-aware Memory Controller

packet access latency in ticks + */ +Tick recvAtomic(PacketPtr pkt); + +/** + * Receive a Packet in Functional mode + * + * @param pkt pointer to memory packet + */ +void recvFunctional(PacketPtr pkt); + + /** +* Receive a Packet in Timing mode +* +* @pa

[gem5-dev] Change in gem5/gem5[master]: sim: Add System method for MasterID lookup

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[gem5-dev] Change in gem5/gem5[master]: mem: Implement base QoS Policies.

ate() override; +}; + +} // namespace QoS + +#endif /* __MEM_QOS_TURNAROUND_POLICY_IDEAL_HH_ */ -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/11972 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem

[gem5-dev] Change in gem5/gem5[master]: mem: Add a QoS-aware Memory Controller type

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/11970 Change subject: mem: Add a QoS-aware Memory Controller type .. mem: Add a QoS-aware Memory Controller type

[gem5-dev] Change in gem5/gem5[master]: mem: Implement base QoS Policies.

Gerrit-PatchSet: 5 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-MessageType: newpatchset

[gem5-dev] Change in gem5/gem5[master]: mem: Add a simple QoS-aware Memory Controller

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[gem5-dev] Change in gem5/gem5[master]: mem: Make DRAMCtrl a QoS-aware Memory Controller

iting mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I48163da8c8208498cf0398b07094cb840272507f Gerrit-Change-Number: 11973 Gerrit-PatchSet: 6 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Anthony Gutierr

[gem5-dev] Change in gem5/gem5[master]: mem: Add a QoS-aware Memory Controller type

it-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I0b611f13fce54dd1dd444eb806f8e98afd248bd5 Gerrit-Change-Number: 11970 Gerrit-PatchSet: 6 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Gabe Black Gerrit-Reviewe

[gem5-dev] Change in gem5/gem5[master]: mem: Make DRAMCtrl a QoS-aware Memory Controller

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[gem5-dev] Change in gem5/gem5[master]: mem: Add a QoS-aware Memory Controller type

it-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I0b611f13fce54dd1dd444eb806f8e98afd248bd5 Gerrit-Change-Number: 11970 Gerrit-PatchSet: 7 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Gabe Black Gerrit-Reviewe

[gem5-dev] Change in gem5/gem5[master]: mem: Add a QoS-aware Memory Controller type

it-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I0b611f13fce54dd1dd444eb806f8e98afd248bd5 Gerrit-Change-Number: 11970 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Gabe Black Gerrit-Reviewe

[gem5-dev] Change in gem5/gem5[master]: mem: Add a QoS-aware Memory Controller type

it-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I0b611f13fce54dd1dd444eb806f8e98afd248bd5 Gerrit-Change-Number: 11970 Gerrit-PatchSet: 4 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Gabe Black Gerrit-Reviewe

[gem5-dev] Change in gem5/gem5[master]: arm: Add support for RCpc load-acquire instructions (ARMv8.3)

, 1, flavor="acquire").emit() + class LoadImmU64(LoadImm64): decConstBase = 'LoadStoreImmU64' micro = True -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/11989 To unsubscribe, or for help writing mail filters, visit https://gem5-review.go

[gem5-dev] Change in gem5/gem5[master]: arm: Add support for RCpc load-acquire instructions (ARMv8.3)

= True -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/11989 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I04c786ad2941072bf28feba7d2ec6e142c8b74cb

[gem5-dev] Change in gem5/gem5[master]: mem: Add StreamID and SubstreamID

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[gem5-dev] Change in gem5/gem5[master]: cpu: Stream/SubstreamID support in TrafficGen

_GEN_HH__ -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/12188 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Iea068de581ae7125a9d49314124a08c045c75b49 Gerrit-Change-Number: 12188 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: cpu: Stream/SubstreamID support in TrafficGen

pick one of the preset Stream or Substream ID */ +uint32_t randomPick(const std::vector ); +}; + +#endif // __CPU_TRAFFIC_GEN_STREAM_GEN_HH__ -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/12188 To unsubscribe, or for help writing mail filters, visit https://gem5

[gem5-dev] Change in gem5/gem5[master]: cpu: Turn BaseTrafficGen numSuppressed into a stat

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[gem5-dev] Change in gem5/gem5[master]: cpu: Stream/SubstreamID support in TrafficGen

Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Iea068de581ae7125a9d49314124a08c045c75b49 Gerrit-Change-Number: 12188 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Anthony Gutierrez Gerrit-Reviewer: Giacomo Travaglini

[gem5-dev] Change in gem5/gem5[master]: mem: Add StreamID and SubstreamID

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[gem5-dev] Change in gem5/gem5[master]: base: Fix ucontext compilation error for macOS

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Introduce ARMv8.1 Virtual Timer System Registers

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Introduce RAS System Registers

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[gem5-dev] Change in gem5/gem5[master]: cpu: Allow creation of traffic gen from generic SimObjects

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[gem5-dev] Change in gem5/gem5[master]: cpu: Turn BaseTrafficGen numSuppressed into a stat

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[gem5-dev] Change in gem5/gem5[master]: cpu: Warn when (un)serializing a traffic generator

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[gem5-dev] Change in gem5/gem5[master]: cpu: Allow creation of traffic gen from generic SimObjects

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[gem5-dev] Change in gem5/gem5[master]: base: Fix ucontext compilation error for macOS

Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Matteo Andreozzi Gerrit-Reviewer: Matthias Jung Gerrit-MessageType: newpatchset ___ gem5-dev

[gem5-dev] Change in gem5/gem5[master]: cpu: Warn when (un)serializing a traffic generator

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[gem5-dev] Change in gem5/gem5[master]: dev-arm: Create a getter for ArmInterruptPin ID number

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[gem5-dev] Change in gem5/gem5[master]: mem: Add a QoS-aware Memory Controller type

m/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I0b611f13fce54dd1dd444eb806f8e98afd248bd5 Gerrit-Change-Number: 11970 Gerrit-PatchSet: 8 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Gabe Bla

[gem5-dev] Change in gem5/gem5[master]: mem: Implement base QoS Policies.

-Change-Number: 11972 Gerrit-PatchSet: 8 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Matthew Poremba Gerrit-MessageType

[gem5-dev] Change in gem5/gem5[master]: mem: Implement base QoS Policies.

rtual MemCtrl::BusState selectBusState() override; +}; + +} // namespace QoS + +#endif /* __MEM_QOS_TURNAROUND_POLICY_IDEAL_HH_ */ -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/11972 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesourc

[gem5-dev] Change in gem5/gem5[master]: mem: Add a simple QoS-aware Memory Controller

+ * @param pkt pointer to memory packet + * @return packet access latency in ticks + */ +Tick recvAtomic(PacketPtr pkt); + +/** + * Receive a Packet in Functional mode + * + * @param pkt pointer to memory packet + */ +void recvFunctional(PacketPtr pkt); + + /** + * Rece

[gem5-dev] Change in gem5/gem5[master]: sim: Add System method for MasterID lookup

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[gem5-dev] Change in gem5/gem5[master]: mem: Make DRAMCtrl a QoS-aware Memory Controller

onse yet. The - * responses are stored seperately mostly to keep the code clean + * responses are stored separately mostly to keep the code clean * and help with events scheduling. For all logical purposes such * as sizing the read queue, this and the main read queue need to

[gem5-dev] Change in gem5/gem5[master]: mem: Add a QoS-aware Memory Controller type

Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/11970 ) Change subject: mem: Add a QoS-aware Memory Controller type .. mem: Add a QoS-aware Memory

[gem5-dev] Change in gem5/gem5[master]: arch-arm: raise/clear IRQ when writing to PMOVSCLR/SET

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[gem5-dev] Change in gem5/gem5[master]: dev-arm: Create a getter for ArmInterruptPin ID number

: I095393d4d25efe13eb2a75a0b0b055d386c2c126 Gerrit-Change-Number: 12298 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Ciro Santilli Gerrit-Reviewer: Giacomo Travaglini Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev

[gem5-dev] Change in gem5/gem5[master]: arm: Add support for tracking TCs in ISA devices

hSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: dev, arm: Add misc reg tracing to the generic timer

rs, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ice9376b8eb42423679b0191910e8c980f8017f88 Gerrit-Change-Number: 12398 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Curtis

[gem5-dev] Change in gem5/gem5[master]: arm: Use the interrupt adaptor in the PMU

iting mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I2cbb99580c46d3e21a1335b897843b7b6e41f10c Gerrit-Change-Number: 12400 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerr

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Make GenericTimer use standard ArmInterruptPin

rqPhysS; -/// Physical timer interrupt (NS) -const unsigned irqPhysNS; - -/// Virtual timer interrupt -const unsigned irqVirt; - -/// Hypervisor timer interrupt -const unsigned irqHyp; }; class GenericTimerISA : public ArmISA::BaseISADevice -- To view, visit https://gem5-revi

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Factory SimObject for generating ArmInterruptPin

esource.com/c/public/gem5/+/12401 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I917d73a26168447221f5993c8ae975ee3771e3bf Gerrit-Change-Number: 12401 Gerrit-PatchSet: 3

[gem5-dev] Change in gem5/gem5[master]: mem: Implement QoS Proportional Fair policy

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[gem5-dev] Change in gem5/gem5[master]: mem: Make DRAMCtrl a QoS-aware Memory Controller

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[gem5-dev] Change in gem5/gem5[master]: mem: Implement QoS Round Robin policy

+ +} // namespace QoS + +#endif // __MEM_QOS_POLICY_ROUND_ROBIN_HH__ -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/12358 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: mast

[gem5-dev] Change in public/gem5[master]: arch-arm: Fix PCAlignmentFault routing to Hypervisor

Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/8841 ) Change subject: arch-arm: Fix PCAlignmentFault routing to Hypervisor .. arch-arm: Fix PCAlignmentFault routing to

[gem5-dev] Change in public/gem5[master]: arch-arm: Fix FSC generation in AbortFault

Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/8362 ) Change subject: arch-arm: Fix FSC generation in AbortFault .. arch-arm: Fix FSC generation in AbortFault The fault

[gem5-dev] Change in public/gem5[master]: arch-arm: Introduce update method in ArmFault class

Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/8361 ) Change subject: arch-arm: Introduce update method in ArmFault class .. arch-arm: Introduce update method in

[gem5-dev] Change in public/gem5[master]: arch-arm: Enable Debug IFSC when faulting to aarch64 mode

Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/8363 ) Change subject: arch-arm: Enable Debug IFSC when faulting to aarch64 mode .. arch-arm: Enable Debug IFSC when

[gem5-dev] Change in public/gem5[master]: arch-arm: Adding IPA-Based Invalidating instructions

Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/8822 ) Change subject: arch-arm: Adding IPA-Based Invalidating instructions .. arch-arm: Adding IPA-Based Invalidating

[gem5-dev] Change in public/gem5[master]: arch-arm: Implement missing aarch32 TLBI registers

Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/8821 ) Change subject: arch-arm: Implement missing aarch32 TLBI registers .. arch-arm: Implement missing aarch32 TLBI

[gem5-dev] Change in public/gem5[master]: arch, arm: Fix implicit-fallthrough GCC warnings

Giacomo Travaglini has uploaded a new patch set (#4) to the change originally created by Chun-Chen TK Hsu. ( https://gem5-review.googlesource.com/9101 ) Change subject: arch, arm: Fix implicit-fallthrough GCC warnings ..

[gem5-dev] Change in public/gem5[master]: arch, arm: Fix implicit-fallthrough GCC warnings

Giacomo Travaglini has uploaded a new patch set (#5) to the change originally created by Chun-Chen TK Hsu. ( https://gem5-review.googlesource.com/9101 ) Change subject: arch, arm: Fix implicit-fallthrough GCC warnings ..

[gem5-dev] Change in public/gem5[master]: arch-arm: ERET from AArch64 to AArch32 ignore MSBs

Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/8881 ) Change subject: arch-arm: ERET from AArch64 to AArch32 ignore MSBs .. arch-arm: ERET from AArch64 to AArch32 ignore

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