[gem5-dev] Change in gem5/gem5[master]: cpu-o3: fix atomic instructions non-speculative

lic/gem5/+/19815 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ia0c5fbb9dc44a9991337b57eb759b1ed08e4149e Gerrit-Change-Number: 19815 Gerrit-PatchSet: 1 Gerrit-Owner: Jordi Vaquero

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic func

IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result) + : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, + _dest, _base, _result) +{ +%(constructor)s; + +uint32_t d2 = RegId(IntRegClass, dest).index() + 1 ; +uint32_t r2 = RegId(IntRegClass, result).index() + 1 ; + +d2_src = _numSrcRegs ; +_srcRegIdx[_numSrcRegs++] = RegId(IntRegClass, d2); +r2_src = _numSrcRegs ; +_srcRegIdx[_numSrcRegs++] = RegId(IntRegClass, r2); +r2_dst = _numDestRegs ; +_destRegIdx[_numDestRegs++] = RegId(IntRegClass, r2); + +} +}}; + +def template AmoArithmeticOpDeclare {{ +class %(class_name)s : public %(base_class)s +{ + public: +bool isXZR ; +/// Constructor. +%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, + IntRegIndex _base, IntRegIndex _result); + +Fault execute(ExecContext *, Trace::InstRecord *) const override; +Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; +Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; + +void +annotateFault(ArmFault *fault) override +{ +%(fa_code)s +} +}; +}}; + +def template AmoArithmeticOpConstructor {{ +%(class_name)s::%(class_name)s(ExtMachInst machInst, +IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result) + : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, + _dest, _base, _result) +{ +%(constructor)s; +isXZR = false; +uint32_t r2 = RegId(IntRegClass, dest).index() ; +if (r2 == 31){ +flags[IsReadBarrier] = false; +isXZR = true; +} +} +}}; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19811 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I4a4acdec4ab1c8b888f10ef5dc1e896be8c432bf Gerrit-Change-Number: 19811 Gerrit-PatchSet: 1 Gerrit-Owner: Jordi Vaquero Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Added LD/ST atomic instruction family and SWP instrs

Jordi Vaquero has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/19812 ) Change subject: arch-arm: Added LD/ST atomic instruction family and SWP instrs .. arch-arm: Added LD/ST

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add TypeAtomicOp class to be used by new atomic instructions

/+/19810 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: If082b596fb37d7a1cb569a4320c23505591df6a5 Gerrit-Change-Number: 19810 Gerrit-PatchSet: 1 Gerrit-Owner: Jordi Vaquero

[gem5-dev] Change in gem5/gem5[master]: arch-arm: adding register control flags enabling LSE implementation

AN; } -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19809 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482d

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