[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fault on mstatus accesses from lower privilege modes.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: added fullsystem support.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/25647 ) Change subject: arch-riscv: added fullsystem support. .. arch-riscv: added fullsystem support. That is,

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: added (un)serialization of miscRegFile.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv, tests: merged changes from RISCV-test upstream repo.

ff12345678, 0 ); + TEST_RR_OP( 45, srlw, 0x01234567, 0x12345678, 4 ); + TEST_RR_OP( 46, srlw, 0x92345678, 0x92345678, 0 ); + TEST_RR_OP( 47, srlw, 0x09234567, 0x000092345678, 4 ); + #- # Sou

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: make accesses to CSRs SerializeAfter.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv, tests: added .gitignore.

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[gem5-dev] Change in gem5/gem5[develop]: tests: call sys.exit() on failure in Simulation::run.

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[gem5-dev] Change in gem5/gem5[develop]: base, sim: allow m5writeFile with stdout/stderr.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv, tests: run p tests.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: report that we don't have debugging support.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: added support for pseudo instructions.

scv/faults.hh" #include "arch/riscv/tlb.hh" @@ -90,6 +94,7 @@ #include "mem/request.hh" #include "sim/eventq.hh" #include "sim/full_system.hh" +#include "sim/pseudo_inst.hh" #include "sim/sim_events.hh" #include "sim/sim_exit.hh" #include "sim/system.hh" diff --git a/src/arch/riscv/isa/operands.isa b/src/arch/riscv/isa/operands.isa index 7c80b8a..41e0a4b 100644 --- a/src/arch/riscv/isa/operands.isa +++ b/src/arch/riscv/isa/operands.isa @@ -2,6 +2,7 @@ // Copyright (c) 2015 RISC-V Foundation // Copyright (c) 2016 The University of Virginia +// Copyright (c) 2020 Barkhausen Institut // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -53,6 +54,11 @@ 'ra': ('IntReg', 'ud', 'ReturnAddrReg', 'IsInteger', 1), 'sp': ('IntReg', 'ud', 'StackPointerReg', 'IsInteger', 2), +'a0': ('IntReg', 'ud', '10', 'IsInteger', 1), +'a1': ('IntReg', 'ud', '11', 'IsInteger', 2), +'a2': ('IntReg', 'ud', '12', 'IsInteger', 3), +'a3': ('IntReg', 'ud', '13', 'IsInteger', 4), + 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 1), 'Fd_bits': ('FloatReg', 'ud', 'FD', 'IsFloating', 1), 'Fs1': ('FloatReg', 'df', 'FS1', 'IsFloating', 2), -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/25645 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I4f73f8fcf62def8815e82555fc2a67f89efc09d1 Gerrit-Change-Number: 25645 Gerrit-PatchSet: 1 Gerrit-Owner: Nils Asmussen Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fault according to status.{TVM, TSK, TW}.

!= PrivilegeMode::PRV_M) { -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/25654 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Chan

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: show names of MiscRegs on accesses.

Params *p) : BaseISA(p) { +static_assert( +sizeof(MiscRegNames) / sizeof(MiscRegNames[0]) == NumMiscRegs, + "MiscRegNames not in sync with NumMiscRegs" +); + miscRegFile.resize(NumMiscRegs); clear(); } @@ -105,8 +237,8 @@ panic("Illegal CSR index %#x\n", misc_reg); return -1; } -DPRINTF(RiscvMisc, "Reading MiscReg %d: %#llx.\n", misc_reg, -miscRegFile[misc_reg]); +DPRINTF(RiscvMisc, "Reading MiscReg %s (%d): %#llx.\n", +MiscRegNames[misc_reg], misc_reg, miscRegFile[misc_reg]); return miscRegFile[misc_reg]; } @@ -180,7 +312,8 @@ // Illegal CSR panic("Illegal CSR index %#x\n", misc_reg); } -DPRINTF(RiscvMisc, "Setting MiscReg %d to %#x.\n", misc_reg, val); +DPRINTF(RiscvMisc, "Setting MiscReg %s (%d) to %#x.\n", +MiscRegNames[misc_reg], misc_reg, val); miscRegFile[misc_reg] = val; } -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/25649 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Icd53d5524a5d5daf3e50f253cdda56341663f26e Gerrit-Change-Number: 25649 Gerrit-PatchSet: 1 Gerrit-Owner: Nils Asmussen Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fixed read of {M, S, U}TVEC.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: ignore writes to SXL/UXL fields in status register.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: print information about faults.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: added dummy implementation of wfi instruction.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: respect IALIGN, influenced by toggling 'c' extension.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: make uret, sret, mret SerializeAfter, NonSpeculative.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv, arch-x86: moved common code into generic walker class.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/25660 ) Change subject: arch-riscv,arch-x86: moved common code into generic walker class. .. arch-riscv,arch-x86:

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv, tests: run v tests.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv, tests: improved run-tests.py.

uot;) + print(zip(job_names, job_outputs)) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/25703 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/g

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: let FPU instructions fault if status.FS = off.

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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: make SetPCCPRS microop SerializeAfter

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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: make MicroUopSetPCCPSR SerializeAfter

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: print information about faults.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: added support for pseudo instructions.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: implement RemoteGDB::acc for FS mode.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: make sure only supported modes can be set in SATP.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv, configs: add support for the walker cache.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: removed unused files.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fixed formatting.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: implement sfence.vma to flush TLBs.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv, configs: added bare metal FS support.

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[gem5-dev] Change in gem5/gem5[develop]: misc: added news on RISC-V to RELEASE-NOTES.md.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: be prepared for CSR changes during PT walk.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: be prepared for CSR changes during PT walk.

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[gem5-dev] Change in gem5/gem5[develop]: misc: added news on RISC-V to RELEASE-NOTES.md.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: report that we don't have debugging support.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: make accesses to CSRs SerializeAfter.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: let FPU instructions fault if status.FS = off.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: respect IALIGN, influenced by toggling 'c' extension.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: make sure only supported modes can be set in SATP.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fixed formatting.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: implement sfence.vma to flush TLBs.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: implement RemoteGDB::acc for FS mode.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: show names of MiscRegs on accesses.

= "UTVEC", +[MISCREG_USCRATCH] = "USCRATCH", +[MISCREG_UEPC] = "UEPC", +[MISCREG_UCAUSE]= "UCAUSE", +[MISCREG_UTVAL] = "UTVAL", +[MISCREG_FFLAGS]= "FFLAGS", + [MISCREG_FRM]

[gem5-dev] Change in gem5/gem5[develop]: configs: added bare metal FS support for RISC-V.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fixed read of {M,S,U}TVEC.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: ignore writes to SXL/UXL fields in status register.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: added dummy implementation of wfi instruction.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fault on mstatus accesses from lower privilege modes.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fault according to status.{TVM,TSK,TW}.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: added (un)serialization of miscRegFile.

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: added TLB and page table walker.

Nils Asmussen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/25647 ) Change subject: arch-riscv: added TLB and page table walker. .. arch-riscv: added TLB and page table walker. That is,

[gem5-dev] Change in gem5/gem5[develop]: cpu,configs: let RISC-V use the PT walker cache.

nge-Number: 26988 Gerrit-PatchSet: 10 Gerrit-Owner: Nils Asmussen Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Gem5 Cloud Project GCB service account <345032938...@cloudbuild.gserviceaccount.com> Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nils

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: make uret,sret,mret SerializeAfter,NonSpeculative.

for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: If3b5ba6ec3b4102d53c51cf723eba5d5da3eaa2f Gerrit-Change-Number: 25656 Gerrit-PatchSet: 11 Gerrit-Owner: Nils Asmussen Gerrit-Reviewer: Alec Ro

[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: arch-riscv,tests: merged changes from RISCV-test upstream repo.

Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/28729 ) Change subject: arch-riscv,tests: merged changes from RISCV-test upstream repo. .. arch-riscv,tests: merged

[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: base,sim: allow m5writeFile with stdout/stderr.

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[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: arch-riscv,tests: run p tests.

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[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: arch-riscv,tests: run v tests.

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[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: arch-riscv,tests: added .gitignore.

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[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: base,sim: allow m5writeFile with stdout/stderr.

t-Branch: release-staging-v20.0.0.0 Gerrit-Change-Id: I102f82dcd2c63420b6f3fe55d67f03c62349e69d Gerrit-Change-Number: 28727 Gerrit-PatchSet: 2 Gerrit-Owner: Nils Asmussen Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nils Asmussen Gerrit-Reviewer: