[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Fix debug prints for regular Stores
Pouya Fotouhi has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/32514 )
Change subject: mem-ruby: Fix debug prints for regular Stores
..
mem-ruby: Fix debug prints for regular Stores
In the updated implementation of LL/SC (27103) the default value
of success was changed, which results in printing "SC_Failed" for
any regular stores.
Change-Id: I4f2e0b26233ce0cbdf948aadd19c9d81bf18bec0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32514
Reviewed-by: Jason Lowe-Power
Reviewed-by: Giacomo Travaglini
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/system/Sequencer.cc
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/system/Sequencer.cc
b/src/mem/ruby/system/Sequencer.cc
index aa134f4..42398e2 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -368,7 +368,7 @@
(seq_req.m_type != RubyRequestType_Load_Linked) &&
(seq_req.m_type != RubyRequestType_IFETCH)) {
// LL/SC support (tested with ARMv8)
-bool success = false;
+bool success = true;
if (seq_req.m_type != RubyRequestType_Store_Conditional) {
// Regular stores to addresses being monitored
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4f2e0b26233ce0cbdf948aadd19c9d81bf18bec0
Gerrit-Change-Number: 32514
Gerrit-PatchSet: 2
Gerrit-Owner: Pouya Fotouhi
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Pouya Fotouhi
Gerrit-Reviewer: Timothy Hayes
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Fix debug prints for regular Stores
Pouya Fotouhi has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/32514 )
Change subject: mem-ruby: Fix debug prints for regular Stores
..
mem-ruby: Fix debug prints for regular Stores
In the updated implementation of LL/SC (27103) the default value
of success was changed, which results in printing "SC_Failed" for
any regular stores.
Change-Id: I4f2e0b26233ce0cbdf948aadd19c9d81bf18bec0
---
M src/mem/ruby/system/Sequencer.cc
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mem/ruby/system/Sequencer.cc
b/src/mem/ruby/system/Sequencer.cc
index aa134f4..42398e2 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -368,7 +368,7 @@
(seq_req.m_type != RubyRequestType_Load_Linked) &&
(seq_req.m_type != RubyRequestType_IFETCH)) {
// LL/SC support (tested with ARMv8)
-bool success = false;
+bool success = true;
if (seq_req.m_type != RubyRequestType_Store_Conditional) {
// Regular stores to addresses being monitored
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I4f2e0b26233ce0cbdf948aadd19c9d81bf18bec0
Gerrit-Change-Number: 32514
Gerrit-PatchSet: 1
Gerrit-Owner: Pouya Fotouhi
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Adding FS support for MOESI_AMD_Base
Pouya Fotouhi has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/32317 )
Change subject: mem-ruby: Adding FS support for MOESI_AMD_Base
..
mem-ruby: Adding FS support for MOESI_AMD_Base
WIP
Change-Id: Ic424cc6e78399e9cd73d6419ea0ad6f8c9397673
---
M configs/ruby/MOESI_AMD_Base.py
M src/mem/ruby/protocol/MOESI_AMD_Base.slicc
2 files changed, 56 insertions(+), 3 deletions(-)
diff --git a/configs/ruby/MOESI_AMD_Base.py b/configs/ruby/MOESI_AMD_Base.py
index 91ff4d2..ae17031 100644
--- a/configs/ruby/MOESI_AMD_Base.py
+++ b/configs/ruby/MOESI_AMD_Base.py
@@ -260,6 +260,12 @@
dir_cntrl.create(options, dir_ranges, ruby_system, system)
# Connect the Directory controller to the ruby network
+dir_cntrl.requestFromDMA = MessageBuffer(ordered = True)
+dir_cntrl.requestFromDMA.slave = ruby_system.network.master
+
+dir_cntrl.responseToDMA = MessageBuffer()
+dir_cntrl.responseToDMA.master = ruby_system.network.slave
+
dir_cntrl.requestFromCores = MessageBuffer(ordered = True)
dir_cntrl.requestFromCores.slave = ruby_system.network.master
@@ -290,7 +296,7 @@
# level config files, such as the ruby_random_tester, will get
confused if
# the number of cpus does not equal the number of sequencers. Thus
make
# sure that an even number of cpus is specified.
-assert((options.num_cpus % 2) == 0)
+#assert((options.num_cpus % 2) == 0)
# For an odd number of CPUs, still create the right number of
controllers
cpuCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s
@@ -378,8 +384,54 @@
cpus = [n for n in
range(options.num_cpus)])
-# Assuming no DMA devices
-assert(len(dma_devices) == 0)
+### Assuming no DMA devices
+##assert(len(dma_devices) == 0)
+##dma_cntrl_nodes = []
+
+for i, dma_port in enumerate(dma_devices):
+# Create the Ruby objects associated with the dma controller
+dma_seq = DMASequencer(version = i, ruby_system = ruby_system,
+ slave = dma_port)
+
+dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq,
+ transitions_per_cycle = options.ports,
+ ruby_system = ruby_system)
+
+exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
+#dma_cntrl_nodes.append(dma_cntrl)
+
+# Connect the dma controller to the network
+dma_cntrl.mandatoryQueue = MessageBuffer()
+dma_cntrl.responseFromDir = MessageBuffer(ordered = True)
+dma_cntrl.responseFromDir.slave = ruby_system.network.master
+dma_cntrl.requestToDir = MessageBuffer()
+dma_cntrl.requestToDir.master = ruby_system.network.slave
+
+mainCluster.add(dma_cntrl)
+
+# Create the io controller and the sequencer
+if full_system:
+io_seq = DMASequencer(version = len(dma_devices),
+ ruby_system = ruby_system)
+ruby_system._io_port = io_seq
+io_controller = DMA_Controller(version = len(dma_devices),
+ dma_sequencer = io_seq,
+ ruby_system = ruby_system)
+ruby_system.io_controller = io_controller
+
+# Connect the dma controller to the network
+io_controller.mandatoryQueue = MessageBuffer()
+io_controller.responseFromDir = MessageBuffer(ordered = True)
+io_controller.responseFromDir.slave = ruby_system.network.master
+io_controller.requestToDir = MessageBuffer()
+io_controller.requestToDir.master = ruby_system.network.slave
+
+#dma_cntrl_nodes.append(io_controller)
+mainCluster.add(io_controller)
+
+
+#mainCluster.add(dma_cntrl_nodes)
+
# Add cpu/gpu clusters to main cluster
mainCluster.add(cpuCluster)
diff --git a/src/mem/ruby/protocol/MOESI_AMD_Base.slicc
b/src/mem/ruby/protocol/MOESI_AMD_Base.slicc
index b381452..dd4b0fc 100644
--- a/src/mem/ruby/protocol/MOESI_AMD_Base.slicc
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base.slicc
@@ -4,3 +4,4 @@
include "MOESI_AMD_Base-CorePair.sm";
include "MOESI_AMD_Base-L3cache.sm";
include "MOESI_AMD_Base-dir.sm";
+include "MOESI_AMD_Base-dma.sm";
--
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Gerrit-Branch: develop
Gerrit-Change-Id: Ic424cc6e78399e9cd73d6419ea0ad6f8c9397673
Gerrit-Change-Number: 32317
Gerrit-PatchSet: 1
Gerrit-Owner: Pouya Fotouhi
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: MESI_Three_level prefetcher page crossing
Pouya Fotouhi has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28048 )
Change subject: mem-ruby: MESI_Three_level prefetcher page crossing
..
mem-ruby: MESI_Three_level prefetcher page crossing
This patch allows MESI_Three_level using the Ruby prefetcher to
safely cross page boundaries by determining if an address is bad
and cannot be mapped to a memory controller.
Change-Id: I675a13dfa6deb5b6a9f986ced5a3130436db911d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28048
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M configs/ruby/MESI_Three_Level.py
M src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
2 files changed, 16 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/ruby/MESI_Three_Level.py
b/configs/ruby/MESI_Three_Level.py
index 0e9ef09..61d6c52 100644
--- a/configs/ruby/MESI_Three_Level.py
+++ b/configs/ruby/MESI_Three_Level.py
@@ -127,7 +127,7 @@
nonunit_filter = 256,
train_misses = 5,
num_startup_pfs = 4,
-cross_page = False
+cross_page = True
)
l0_cntrl = L0Cache_Controller(
diff --git a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
index da89bf5..3639ef2 100644
--- a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
@@ -140,6 +140,7 @@
PF_Load, desc="Load request from prefetcher";
PF_Ifetch, desc="Instruction fetch request from prefetcher";
PF_Store,desc="Exclusive load request from prefetcher";
+PF_Bad_Addr, desc="Throw away prefetch request due to bad address
generation";
}
// TYPES
@@ -323,7 +324,16 @@
in_port(optionalQueue_in, RubyRequest, prefetchQueue, desc="...", rank =
2) {
if (optionalQueue_in.isReady(clockEdge())) {
peek(optionalQueue_in, RubyRequest) {
-if (in_msg.Type == RubyRequestType:IFETCH) {
+// first check for valid address
+MachineID mid := mapAddressToMachine(in_msg.LineAddress,
MachineType:Directory);
+NodeID nid := machineIDToNodeID(mid);
+int nidint := IDToInt(nid);
+int numDirs := machineCount(MachineType:Directory);
+if (nidint >= numDirs) {
+ Entry cache_entry := static_cast(Entry, "pointer",
Dcache.getNullEntry());
+ TBE tbe := TBEs.getNullEntry();
+ trigger(Event:PF_Bad_Addr, in_msg.LineAddress, cache_entry, tbe);
+} else if (in_msg.Type == RubyRequestType:IFETCH) {
// Instruction Prefetch
Entry icache_entry := getICacheEntry(in_msg.LineAddress);
if (is_valid(icache_entry)) {
@@ -1164,4 +1174,8 @@
o_popIncomingResponseQueue;
kd_wakeUpDependents;
}
+
+ transition(I, PF_Bad_Addr) {
+pq_popPrefetchQueue;
+ }
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28048
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I675a13dfa6deb5b6a9f986ced5a3130436db911d
Gerrit-Change-Number: 28048
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Pouya Fotouhi
Gerrit-Reviewer: Timothy Hayes
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: MESI_Three_level prefetcher support
Pouya Fotouhi has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27715 )
Change subject: mem-ruby: MESI_Three_level prefetcher support
..
mem-ruby: MESI_Three_level prefetcher support
Add support for the Ruby stride prefetcher to MESI_Three_Level.
Change-Id: Id68935e2a7d3ccd0e22a59f43a15f167410632a2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27715
Reviewed-by: Bradford Beckmann
Maintainer: Bradford Beckmann
Tested-by: kokoro
---
M configs/ruby/MESI_Three_Level.py
M src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
M src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
M src/mem/ruby/protocol/MESI_Three_Level-msg.sm
M src/mem/ruby/protocol/MESI_Two_Level-L2cache.sm
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/structures/CacheMemory.hh
M src/mem/ruby/structures/TBETable.hh
8 files changed, 386 insertions(+), 3 deletions(-)
Approvals:
Bradford Beckmann: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/ruby/MESI_Three_Level.py
b/configs/ruby/MESI_Three_Level.py
index fdebea4..0e9ef09 100644
--- a/configs/ruby/MESI_Three_Level.py
+++ b/configs/ruby/MESI_Three_Level.py
@@ -53,6 +53,8 @@
parser.add_option("--l0_transitions_per_cycle", type="int", default=32)
parser.add_option("--l1_transitions_per_cycle", type="int", default=32)
parser.add_option("--l2_transitions_per_cycle", type="int", default=4)
+parser.add_option("--enable-prefetch", action="store_true",
default=False,\
+help="Enable Ruby hardware prefetcher")
return
def create_system(options, full_system, system, dma_ports, bootmem,
@@ -118,10 +120,22 @@
else:
clk_domain = system.cpu[i].clk_domain
+# Ruby prefetcher
+prefetcher = RubyPrefetcher.Prefetcher(
+num_streams=16,
+unit_filter = 256,
+nonunit_filter = 256,
+train_misses = 5,
+num_startup_pfs = 4,
+cross_page = False
+)
+
l0_cntrl = L0Cache_Controller(
version = i * num_cpus_per_cluster + j,
Icache = l0i_cache, Dcache = l0d_cache,
transitions_per_cycle =
options.l0_transitions_per_cycle,
+ prefetcher = prefetcher,
+ enable_prefetch = options.enable_prefetch,
send_evictions = send_evicts(options),
clk_domain = clk_domain,
ruby_system = ruby_system)
@@ -159,6 +173,7 @@
l1_cntrl_nodes.append(l1_cntrl)
# Connect the L0 and L1 controllers
+l0_cntrl.prefetchQueue = MessageBuffer()
l0_cntrl.mandatoryQueue = MessageBuffer()
l0_cntrl.bufferToL1 = MessageBuffer(ordered = True)
l1_cntrl.bufferFromL0 = l0_cntrl.bufferToL1
diff --git a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
index 14fb07a..da89bf5 100644
--- a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
@@ -46,6 +46,9 @@
Cycles response_latency := 2;
bool send_evictions;
+ Prefetcher * prefetcher;
+ bool enable_prefetch := "False";
+
// From this node's L0 cache to the network
MessageBuffer * bufferToL1, network="To";
@@ -54,6 +57,9 @@
// Message queue between this controller and the processor
MessageBuffer * mandatoryQueue;
+
+ // Request Buffer for prefetches
+ MessageBuffer * prefetchQueue;
{
// STATES
state_declaration(State, desc="Cache states", default="L0Cache_State_I")
{
@@ -92,6 +98,11 @@
// processor needs to write to it. So, the controller has requested for
// write permission.
SM, AccessPermission:Read_Only, desc="Issued GETX, have not seen
response yet";
+
+// Transient states in which block is being prefetched
+PF_Inst_IS, AccessPermission:Busy, desc="Issued GETS, have not seen
response yet";
+PF_IS, AccessPermission:Busy, desc="Issued GETS, have not seen
response yet";
+PF_IE, AccessPermission:Busy, desc="Issued GETX, have not seen
response yet";
}
// EVENTS
@@ -123,6 +134,12 @@
WB_Ack,desc="Ack for replacement";
Failed_SC,desc="Store conditional request that will fail";
+
+// Prefetch events (generated by prefetcher)
+PF_L0_Replacement, desc="L0 Replacement caused by pretcher",
format="!pr";
+PF_Load, desc="Load request from prefetcher";
+PF_Ifetch, desc="Instruction fetch request from prefetcher";
+PF_Store,desc="Exclusive load request from prefetcher";
}
// TYPES
@@ -132,6 +149,7 @@
State CacheState,desc="cache state";
DataBlock DataBlk, desc="data for the block";
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: MESI_Three_Level LL/SC improvements
Pouya Fotouhi has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28328 )
Change subject: mem-ruby: MESI_Three_Level LL/SC improvements
..
mem-ruby: MESI_Three_Level LL/SC improvements
This patch fixes the MESI_Three_Level protocols so that it correctly
informers the Ruby sequencer when a line eviction occurs. Furthermore,
the patch allows the protocol to recognize the 'Store_Conditional'
RubyRequestType and shortcuts this operation if the monitored line
has been cleared from the address monitor. This prevents certain
livelock behaviour in which a line could ping-pong between competing
cores.
The patch establishes a new C/C++ preprocessor definition which allows
the Sequencer to send the 'Store_Conditional' RubyRequestType to
MESI_Three_Level instead of 'ST'. This is a temporary measure until
the other protocols explicitely recognize 'Store_Conditional'.
Change-Id: I27ae041ab0e015a4f54f20df666f9c4873c7583d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28328
Reviewed-by: Daniel Carvalho
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
M src/mem/ruby/system/SConscript
M src/mem/ruby/system/Sequencer.cc
3 files changed, 77 insertions(+), 23 deletions(-)
Approvals:
Daniel Carvalho: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
index b74a727..14fb07a 100644
--- a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
@@ -121,6 +121,8 @@
Ack,desc="Ack for processor";
WB_Ack,desc="Ack for replacement";
+
+Failed_SC,desc="Store conditional request that will fail";
}
// TYPES
@@ -257,7 +259,8 @@
return Event:Load;
} else if (type == RubyRequestType:IFETCH) {
return Event:Ifetch;
-} else if ((type == RubyRequestType:ST) || (type ==
RubyRequestType:ATOMIC)) {
+} else if ((type == RubyRequestType:ST) || (type ==
RubyRequestType:ATOMIC)
+ || (type == RubyRequestType:Store_Conditional)) {
return Event:Store;
} else {
error("Invalid RubyRequestType");
@@ -349,36 +352,51 @@
}
}
} else {
-
// *** DATA ACCESS ***
Entry Dcache_entry := getDCacheEntry(in_msg.LineAddress);
+
+ // early out for failed store conditionals
+
+ if (in_msg.Type == RubyRequestType:Store_Conditional) {
+ if (!sequencer.llscCheckMonitor(in_msg.LineAddress)) {
+trigger(Event:Failed_SC, in_msg.LineAddress,
+Dcache_entry, TBEs[in_msg.LineAddress]);
+}
+ }
+
if (is_valid(Dcache_entry)) {
// The tag matches for the L0, so the L0 ask the L1 for it
trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress,
Dcache_entry, TBEs[in_msg.LineAddress]);
} else {
-
-// Check to see if it is in the OTHER L0
-Entry Icache_entry := getICacheEntry(in_msg.LineAddress);
-if (is_valid(Icache_entry)) {
- // The block is in the wrong L0, put the request on the
queue to the private L1
- trigger(Event:L0_Replacement, in_msg.LineAddress,
- Icache_entry, TBEs[in_msg.LineAddress]);
-}
-
-if (Dcache.cacheAvail(in_msg.LineAddress)) {
- // L1 does't have the line, but we have space for it
- // in the L0 let's see if the L1 has it
- trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress,
- Dcache_entry, TBEs[in_msg.LineAddress]);
+// if the request is not valid, the store conditional will fail
+if (in_msg.Type == RubyRequestType:Store_Conditional) {
+// if the line is not valid, it can't be locked
+trigger(Event:Failed_SC, in_msg.LineAddress,
+Dcache_entry, TBEs[in_msg.LineAddress]);
} else {
- // No room in the L1, so we need to make room in the L0
- // Check if the line we want to evict is not locked
- Addr addr := Dcache.cacheProbe(in_msg.LineAddress);
- check_on_cache_probe(mandatoryQueue_in, addr);
- trigger(Event:L0_Replacement, addr,
- getDCacheEntry(addr),
- TBEs[addr]);
+ // Check to see if it is in the OTHER L0
+ Entry Icache_entry := getICacheEntry(in_msg.LineAddress);
+ if (is_valid(Icache_entry)) {
+// The block is in the wrong L0, put the request on the
queue to the private L1
+
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: LL/SC fixes
Pouya Fotouhi has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27103 )
Change subject: mem-ruby: LL/SC fixes
..
mem-ruby: LL/SC fixes
The implementation for load-linked/store-conditional did not work
correctly for multi-core simulations. Since load-links were treated as
stores, it was not possible for a line to have multiple readers which
often resulted in livelock when using these instructions to implemented
mutexes. This improved implementation treats load-linked instructions
similarly to loads but locks the line after a copy has been fetched
locally. Writes to a monitored address ensure the 'linked' property is
blown away and any subsequent store-conditional will fail.
Change-Id: I19bd74459e26732c92c8b594901936e6439fb073
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27103
Reviewed-by: Daniel Carvalho
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/system/Sequencer.cc
M src/mem/ruby/system/Sequencer.hh
3 files changed, 155 insertions(+), 73 deletions(-)
Approvals:
Daniel Carvalho: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index fd76289..f8de9ed 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved.
@@ -112,6 +124,10 @@
void writeCallback(Addr, DataBlock, bool, MachineType,
Cycles, Cycles, Cycles);
+ // ll/sc support
+ void writeCallbackScFail(Addr, DataBlock);
+ bool llscCheckMonitor(Addr);
+
void checkCoherence(Addr);
void evictionCallback(Addr);
void recordRequestType(SequencerRequestType);
diff --git a/src/mem/ruby/system/Sequencer.cc
b/src/mem/ruby/system/Sequencer.cc
index 1f538c3..0287e13 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 ARM Limited
+ * Copyright (c) 2019-2020 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -45,6 +45,7 @@
#include "base/logging.hh"
#include "base/str.hh"
#include "cpu/testers/rubytest/RubyTester.hh"
+#include "debug/LLSC.hh"
#include "debug/MemoryAccess.hh"
#include "debug/ProtocolTrace.hh"
#include "debug/RubySequencer.hh"
@@ -90,6 +91,64 @@
}
void
+Sequencer::llscLoadLinked(const Addr claddr)
+{
+AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr);
+if (line) {
+line->setLocked(m_version);
+DPRINTF(LLSC, "LLSC Monitor - inserting load linked - "
+ "addr=0x%lx - cpu=%u\n", claddr, m_version);
+}
+}
+
+void
+Sequencer::llscClearMonitor(const Addr claddr)
+{
+AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr);
+if (line && line->isLocked(m_version)) {
+line->clearLocked();
+DPRINTF(LLSC, "LLSC Monitor - clearing due to store - "
+ "addr=0x%lx - cpu=%u\n", claddr, m_version);
+}
+}
+
+bool
+Sequencer::llscStoreConditional(const Addr claddr)
+{
+AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr);
+if (!line)
+return false;
+
+DPRINTF(LLSC, "LLSC Monitor - clearing due to "
+ "store conditional - "
+ "addr=0x%lx - cpu=%u\n",
+ claddr, m_version);
+
+if (line->isLocked(m_version)) {
+line->clearLocked();
+return true;
+} else {
+line->clearLocked();
+return false;
+}
+}
+
+bool
+Sequencer::llscCheckMonitor(const Addr address)
+{
+const Addr claddr = makeLineAddress(address);
+AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr);
+if (!line)
+return false;
+
+if (line->isLocked(m_version)) {
+return true;
+} else {
+return false;
+}
+}
+
+void
Sequencer::wakeup()
{
assert(drainState() != DrainState::Draining);
@@ -203,62 +262,6 @@
}
void
-Sequencer::invalidateSC(Addr address)
-{
-AbstractCacheEntry *e =
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: fix MESI_Three_Level erroneous transition
Pouya Fotouhi has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28047 )
Change subject: mem-ruby: fix MESI_Three_Level erroneous transition
..
mem-ruby: fix MESI_Three_Level erroneous transition
The MESI_Three_Level protocol includes a transition in its L1
definition to invalidate an SM state but this transition does
not notify the L0 cache. The unintended side effect of this
allows stale values to be read by the L0 cache. This can cause
incorrect behaviour when executing LL/SC based mutexes. This
patch ensures that all invalidates to SM states are exposed to
the L0 cache.
Change-Id: I7fefabdaa8027fdfa4c9c362abd7e467493196aa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28047
Reviewed-by: John Alsop
Reviewed-by: Pouya Fotouhi
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
1 file changed, 3 insertions(+), 2 deletions(-)
Approvals:
Pouya Fotouhi: Looks good to me, approved
John Alsop: Looks good to me, but someone else must approve
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
b/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
index 00d897a..1890bcc 100644
--- a/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
+++ b/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
@@ -262,7 +262,8 @@
}
bool inL0Cache(State state) {
-if (state == State:S || state == State:E || state == State:M ||
+if (state == State:S || state == State:E ||
+state == State:M || state == State:SM ||
state == State:S_IL0 || state == State:E_IL0 ||
state == State:M_IL0 || state == State:SM_IL0) {
return true;
@@ -996,7 +997,7 @@
}
// Transitions from IM
- transition({IM,SM}, Inv, IM) {
+ transition(IM, Inv, IM) {
fi_sendInvAck;
l_popL2RequestQueue;
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28047
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7fefabdaa8027fdfa4c9c362abd7e467493196aa
Gerrit-Change-Number: 28047
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: John Alsop
Gerrit-Reviewer: Marjan Fariborz
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: Pouya Fotouhi
Gerrit-Reviewer: Timothy Hayes
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: GCN3 and VIPER integration
Hello Tuan Ta,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28413
to review the following change.
Change subject: mem-ruby: GCN3 and VIPER integration
..
mem-ruby: GCN3 and VIPER integration
This patch modifies the Coalescer and VIPER protocol to support memory
synchronization requests and write-completion responses that are
required by upcoming GCN3 implementation.
VIPER protocol is simplified to be a solely write-through protocol.
Change-Id: Icc3a5beda8550f55f3fb673216056f79e093e25f
---
M src/mem/ruby/protocol/GPU_VIPER-TCC.sm
M src/mem/ruby/protocol/GPU_VIPER-TCP.sm
M src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
M src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/slicc_interface/RubyRequest.hh
M src/mem/ruby/system/GPUCoalescer.cc
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/ruby/system/RubyPort.cc
M src/mem/ruby/system/VIPERCoalescer.cc
M src/mem/ruby/system/VIPERCoalescer.hh
11 files changed, 320 insertions(+), 466 deletions(-)
diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
index f8da4ab..5f05a60 100644
--- a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
@@ -392,14 +392,15 @@
action(w_sendResponseWBAck, "w", desc="send WB Ack") {
peek(responseFromNB_in, ResponseMsg) {
-enqueue(responseToCore_out, ResponseMsg, l2_response_latency) {
- out_msg.addr := address;
- out_msg.Type := CoherenceResponseType:TDSysWBAck;
- out_msg.Destination.clear();
- out_msg.Destination.add(in_msg.WTRequestor);
- out_msg.Sender := machineID;
- out_msg.MessageSize := MessageSizeType:Writeback_Control;
-}
+ enqueue(responseToCore_out, ResponseMsg, l2_response_latency) {
+out_msg.addr := address;
+out_msg.Type := CoherenceResponseType:TDSysWBAck;
+out_msg.Destination.clear();
+out_msg.Destination.add(in_msg.WTRequestor);
+out_msg.Sender := machineID;
+out_msg.MessageSize := MessageSizeType:Writeback_Control;
+out_msg.instSeqNum := in_msg.instSeqNum;
+ }
}
}
@@ -412,6 +413,7 @@
out_msg.Destination.add(in_msg.Requestor);
out_msg.Sender := machineID;
out_msg.MessageSize := MessageSizeType:Writeback_Control;
+out_msg.instSeqNum := in_msg.instSeqNum;
}
}
}
@@ -486,6 +488,7 @@
out_msg.Dirty := true;
out_msg.DataBlk := in_msg.DataBlk;
out_msg.writeMask.orMask(in_msg.writeMask);
+out_msg.instSeqNum := in_msg.instSeqNum;
}
}
}
diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
index 4047dc6..3f61791 100644
--- a/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
@@ -56,9 +56,6 @@
state_declaration(State, desc="TCP Cache States", default="TCP_State_I")
{
I, AccessPermission:Invalid, desc="Invalid";
V, AccessPermission:Read_Only, desc="Valid";
-W, AccessPermission:Read_Write, desc="Written";
-M, AccessPermission:Read_Write, desc="Written and Valid";
-L, AccessPermission:Read_Write, desc="Local access is modifable";
A, AccessPermission:Invalid, desc="Waiting on Atomic";
}
@@ -67,7 +64,6 @@
Load, desc="Load";
Store, desc="Store to L1 (L1 is dirty)";
StoreThrough, desc="Store directly to L2(L1 is clean)";
-StoreLocal, desc="Store to L1 but L1 is clean";
Atomic, desc="Atomic";
Flush, desc="Flush if dirty(wbL1 for Store Release)";
Evict, desc="Evict if clean(invL1 for Load Acquire)";
@@ -264,7 +260,7 @@
if (in_msg.Type == CoherenceResponseType:TDSysResp) {
// disable L1 cache
if (disableL1) {
- trigger(Event:Bypass, in_msg.addr, cache_entry, tbe);
+ trigger(Event:Bypass, in_msg.addr, cache_entry, tbe);
} else {
if (is_valid(cache_entry) || L1cache.cacheAvail(in_msg.addr)) {
trigger(Event:TCC_Ack, in_msg.addr, cache_entry, tbe);
@@ -291,18 +287,16 @@
DPRINTF(RubySlicc, "%s\n", in_msg);
if (in_msg.Type == RubyRequestType:LD) {
trigger(Event:Load, in_msg.LineAddress, cache_entry, tbe);
-} else if (in_msg.Type == RubyRequestType:ATOMIC) {
+} else if (in_msg.Type == RubyRequestType:ATOMIC ||
+ in_msg.Type == RubyRequestType:ATOMIC_RETURN ||
+ in_msg.Type == RubyRequestType:ATOMIC_NO_RETURN) {
trigger(Event:Atomic, in_msg.LineAddress, cache_entry, tbe);
} else if (in_msg.Type == RubyRequestType:ST) {
if(disableL1) {
trigger(Event:StoreThrough, in_msg.LineAddress, cache_entry,
tbe);
} else {
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Add DMA support to MOESI_AMD_Base-dir.sm
Hello Tony Gutierrez,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28414
to review the following change.
Change subject: mem-ruby: Add DMA support to MOESI_AMD_Base-dir.sm
..
mem-ruby: Add DMA support to MOESI_AMD_Base-dir.sm
This change adds DMA support to the MOESI_AMD_Base-dir.sm,
which is needed to support ROCm apps/GCN3 ISA in the VIPER
ptl. The DMA controller is copied from the MOESI_hammer-dma.sm
with few modifications.
Change-Id: I0cb53abedb7817c88a57c66614e37d1f90603906
---
M src/mem/ruby/protocol/GPU_VIPER.slicc
M src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
A src/mem/ruby/protocol/MOESI_AMD_Base-dma.sm
M src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
4 files changed, 499 insertions(+), 6 deletions(-)
diff --git a/src/mem/ruby/protocol/GPU_VIPER.slicc
b/src/mem/ruby/protocol/GPU_VIPER.slicc
index 45f7f34..0b37ce6 100644
--- a/src/mem/ruby/protocol/GPU_VIPER.slicc
+++ b/src/mem/ruby/protocol/GPU_VIPER.slicc
@@ -2,6 +2,7 @@
include "RubySlicc_interfaces.slicc";
include "MOESI_AMD_Base-msg.sm";
include "MOESI_AMD_Base-dir.sm";
+include "MOESI_AMD_Base-dma.sm";
include "MOESI_AMD_Base-CorePair.sm";
include "GPU_VIPER-TCP.sm";
include "GPU_VIPER-SQC.sm";
diff --git a/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
b/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
index 6112ec2..e2c5ff5 100644
--- a/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
@@ -44,6 +44,10 @@
bool useL3OnWT := "False";
Cycles to_memory_controller_latency := 1;
+ // DMA
+ MessageBuffer * requestFromDMA, network="From", virtual_network="1",
vnet_type="request";
+ MessageBuffer * responseToDMA, network="To", virtual_network="3",
vnet_type="request";
+
// From the Cores
MessageBuffer * requestFromCores, network="From", virtual_network="0",
vnet_type="request";
MessageBuffer * responseFromCores, network="From", virtual_network="2",
vnet_type="response";
@@ -63,13 +67,17 @@
// BL is Busy because it's possible for the data only to be in the
network
// in the WB, L3 has sent it and gone on with its business in possibly
I
// state.
+BDR_M, AccessPermission:Backing_Store, desc="DMA read, blocked
waiting for memory";
BS_M, AccessPermission:Backing_Store, desc="blocked
waiting for memory";
BM_M, AccessPermission:Backing_Store, desc="blocked
waiting for memory";
B_M, AccessPermission:Backing_Store, desc="blocked
waiting for memory";
BP, AccessPermission:Backing_Store, desc="blocked
waiting for probes, no need for memory";
+BDR_PM, AccessPermission:Backing_Store, desc="DMA read, blocked
waiting for probes and memory";
BS_PM, AccessPermission:Backing_Store,desc="blocked
waiting for probes and Memory";
BM_PM, AccessPermission:Backing_Store,desc="blocked
waiting for probes and Memory";
B_PM, AccessPermission:Backing_Store,desc="blocked
waiting for probes and Memory";
+BDW_P, AccessPermission:Backing_Store, desc="DMA write, blocked
waiting for probes, no need for memory";
+BDR_Pm, AccessPermission:Backing_Store, desc="DMA read, blocked
waiting for probes, already got memory";
BS_Pm, AccessPermission:Backing_Store,desc="blocked
waiting for probes, already got memory";
BM_Pm, AccessPermission:Backing_Store,desc="blocked
waiting for probes, already got memory";
B_Pm, AccessPermission:Backing_Store,desc="blocked
waiting for probes, already got memory";
@@ -107,6 +115,10 @@
UnblockWriteThrough,desc="Unblock because of writethrough request
finishing";
StaleVicDirty,desc="Core invalidated before VicDirty
processed";
+
+// DMA
+DmaRead,desc="DMA read";
+DmaWrite, desc="DMA write";
}
enumeration(RequestType, desc="To communicate stats from transitions to
recordStats") {
@@ -148,6 +160,7 @@
bool L3Hit, default="false", desc="Was this an L3 hit?";
uint64_t probe_id,desc="probe id for lifetime profiling";
WriteMask writeMask,desc="outstanding write through mask";
+int Len,desc="Length of memory request for DMA";
}
structure(TBETable, external="yes") {
@@ -266,6 +279,8 @@
}
// ** OUT_PORTS **
+ out_port(dmaResponseQueue_out, DMAResponseMsg, responseToDMA);
+
out_port(probeNetwork_out, NBProbeRequestMsg, probeToCore);
out_port(responseNetwork_out, ResponseMsg, responseToCore);
@@ -274,6 +289,23 @@
// ** IN_PORTS **
+ // DMA Ports
+ in_port(dmaRequestQueue_in, DMARequestMsg, requestFromDMA, rank=6) {
+if (dmaRequestQueue_in.isReady(clockEdge())) {
+ peek(dmaRequestQueue_in, DMARequestMsg) {
+TBE tbe :=
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Getting rid of HSA segment and scope
Pouya Fotouhi has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28411 )
Change subject: mem-ruby: Getting rid of HSA segment and scope
..
mem-ruby: Getting rid of HSA segment and scope
This is protocol and sequencer parts of the bigger GCN3 change.
Author: Tony Gutierrez
Change-Id: I803b4cbb46eeab8462d9af80dd003940a9968b60
---
M src/mem/ruby/protocol/GPU_VIPER-TCP.sm
M src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
M src/mem/ruby/protocol/RubySlicc_Exports.sm
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/system/GPUCoalescer.cc
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/ruby/system/GPUCoalescer.py
M src/mem/ruby/system/VIPERCoalescer.py
8 files changed, 285 insertions(+), 399 deletions(-)
diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
index 9dffe0f..4047dc6 100644
--- a/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
@@ -298,9 +298,7 @@
trigger(Event:StoreThrough, in_msg.LineAddress, cache_entry,
tbe);
} else {
if (is_valid(cache_entry) ||
L1cache.cacheAvail(in_msg.LineAddress)) {
- if (in_msg.segment == HSASegment:SPILL) {
-trigger(Event:StoreLocal, in_msg.LineAddress, cache_entry,
tbe);
- } else if (WB) {
+ if (WB) {
trigger(Event:Store, in_msg.LineAddress, cache_entry, tbe);
} else {
trigger(Event:StoreThrough, in_msg.LineAddress,
cache_entry, tbe);
diff --git a/src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
b/src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
index a66939c..6d04c76 100644
--- a/src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
@@ -137,7 +137,6 @@
CoherenceRequestType OriginalType, default="CoherenceRequestType_NA",
desc="Type of request from core fwded through region buffer";
WriteMask writeMask, desc="Write Through Data";
MachineID WTRequestor,desc="Node who initiated the write
through";
- HSAScope scope, default="HSAScope_SYSTEM",
desc="Request Scope";
int wfid, default="0", desc="wavefront id";
bool NoWriteConflict, default="true", desc="write collided
with CAB entry";
int ProgramCounter, desc="PC that accesses to this block";
diff --git a/src/mem/ruby/protocol/RubySlicc_Exports.sm
b/src/mem/ruby/protocol/RubySlicc_Exports.sm
index 8e17f98..fe2c83b 100644
--- a/src/mem/ruby/protocol/RubySlicc_Exports.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Exports.sm
@@ -91,26 +91,6 @@
NotPresent, desc="block is NotPresent";
Busy, desc="block is in a transient state, currently invalid";
}
-//HSA scopes
-enumeration(HSAScope, desc="...", default="HSAScope_UNSPECIFIED") {
- UNSPECIFIED, desc="Unspecified scope";
- NOSCOPE, desc="Explictly unscoped";
- WAVEFRONT, desc="Wavefront scope";
- WORKGROUP, desc="Workgroup scope";
- DEVICE, desc="Device scope";
- SYSTEM, desc="System scope";
-}
-
-// HSA segment types
-enumeration(HSASegment, desc="...", default="HSASegment_GLOBAL") {
- GLOBAL, desc="Global segment";
- GROUP,desc="Group segment";
- PRIVATE, desc="Private segment";
- KERNARG, desc="Kernarg segment";
- READONLY, desc="Readonly segment";
- SPILL,desc="Spill segment";
- ARG, desc="Arg segment";
-}
// TesterStatus
enumeration(TesterStatus, desc="...") {
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index fd76289..95a093a 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -169,8 +169,6 @@
WriteMask writeMask, desc="Writethrough mask";
DataBlock WTData, desc="Writethrough data block";
int wfid, desc="Writethrough wavefront";
- HSAScope scope,desc="HSA scope";
- HSASegment segment,desc="HSA segment";
PacketPtr pkt, desc="Packet associated with this request";
}
diff --git a/src/mem/ruby/system/GPUCoalescer.cc
b/src/mem/ruby/system/GPUCoalescer.cc
index 4cea30f..19b50ea 100644
--- a/src/mem/ruby/system/GPUCoalescer.cc
+++ b/src/mem/ruby/system/GPUCoalescer.cc
@@ -63,58 +63,6 @@
using namespace std;
-GPUCoalescer *
-RubyGPUCoalescerParams::create()
-{
-return new GPUCoalescer(this);
-}
-
-HSAScope
-reqScopeToHSAScope(const RequestPtr )
-{
-HSAScope accessScope = HSAScope_UNSPECIFIED;
-if (req->isScoped()) {
-if (req->isWavefrontScope()) {
-accessScope = HSAScope_WAVEFRONT;
-} else if (req->isWorkgroupScope()) {
-accessScope = HSAScope_WORKGROUP;
-} else if (req->isDeviceScope()) {
-accessScope = HSAScope_DEVICE;
-} else if (req->isSystemScope()) {
-
[gem5-dev] Change in gem5/gem5[develop]: gpu-compute, configs: Add GCN3 ISA support to GPU model
Hello Tony Gutierrez, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/28412 to review the following change. Change subject: gpu-compute, configs: Add GCN3 ISA support to GPU model .. gpu-compute, configs: Add GCN3 ISA support to GPU model Change-Id: I0ead5bcab6fa014e37294c22243831e08dbc5656 --- M configs/common/GPUTLBConfig.py M src/gpu-compute/GPU.py M src/gpu-compute/GPUStaticInstFlags.py M src/gpu-compute/SConscript M src/gpu-compute/compute_unit.cc M src/gpu-compute/compute_unit.hh M src/gpu-compute/dispatcher.cc M src/gpu-compute/dispatcher.hh M src/gpu-compute/exec_stage.cc M src/gpu-compute/exec_stage.hh M src/gpu-compute/fetch_stage.cc M src/gpu-compute/fetch_stage.hh M src/gpu-compute/fetch_unit.cc M src/gpu-compute/fetch_unit.hh M src/gpu-compute/global_memory_pipeline.cc M src/gpu-compute/global_memory_pipeline.hh A src/gpu-compute/gpu_command_processor.cc A src/gpu-compute/gpu_command_processor.hh A src/gpu-compute/gpu_compute_driver.cc A src/gpu-compute/gpu_compute_driver.hh M src/gpu-compute/gpu_dyn_inst.cc M src/gpu-compute/gpu_dyn_inst.hh M src/gpu-compute/gpu_exec_context.cc M src/gpu-compute/gpu_exec_context.hh M src/gpu-compute/gpu_static_inst.cc M src/gpu-compute/gpu_static_inst.hh M src/gpu-compute/gpu_tlb.cc M src/gpu-compute/gpu_tlb.hh A src/gpu-compute/hsa_queue_entry.hh A src/gpu-compute/kernel_code.hh M src/gpu-compute/lds_state.cc M src/gpu-compute/lds_state.hh M src/gpu-compute/local_memory_pipeline.cc M src/gpu-compute/local_memory_pipeline.hh M src/gpu-compute/misc.hh M src/gpu-compute/pool_manager.cc M src/gpu-compute/pool_manager.hh A src/gpu-compute/register_file.cc A src/gpu-compute/register_file.hh A src/gpu-compute/register_manager.cc A src/gpu-compute/register_manager.hh A src/gpu-compute/register_manager_policy.hh M src/gpu-compute/rr_scheduling_policy.hh A src/gpu-compute/scalar_memory_pipeline.cc A src/gpu-compute/scalar_memory_pipeline.hh A src/gpu-compute/scalar_register_file.cc A src/gpu-compute/scalar_register_file.hh M src/gpu-compute/schedule_stage.cc M src/gpu-compute/schedule_stage.hh M src/gpu-compute/scoreboard_check_stage.cc M src/gpu-compute/scoreboard_check_stage.hh M src/gpu-compute/shader.cc M src/gpu-compute/shader.hh M src/gpu-compute/simple_pool_manager.cc M src/gpu-compute/simple_pool_manager.hh A src/gpu-compute/static_register_manager_policy.cc A src/gpu-compute/static_register_manager_policy.hh M src/gpu-compute/tlb_coalescer.cc M src/gpu-compute/tlb_coalescer.hh M src/gpu-compute/vector_register_file.cc M src/gpu-compute/vector_register_file.hh M src/gpu-compute/wavefront.cc M src/gpu-compute/wavefront.hh 63 files changed, 9,892 insertions(+), 3,278 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28412 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I0ead5bcab6fa014e37294c22243831e08dbc5656 Gerrit-Change-Number: 28412 Gerrit-PatchSet: 1 Gerrit-Owner: Pouya Fotouhi Gerrit-Reviewer: Tony Gutierrez Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
