[gem5-dev] Change in gem5/gem5[develop]: arch: Delete a few unused vector register types/constants.

2021-02-26 Thread Gabe Black (Gerrit) via gem5-dev
eBytes = ::DummyVecRegSizeBytes;

 // Not applicable to SPARC
-using VecPredReg = ::DummyVecPredReg;
-using ConstVecPredReg = ::DummyConstVecPredReg;
 using VecPredRegContainer = ::DummyVecPredRegContainer;
-constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;

 // semantically meaningful register indices
 enum {
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index 867ad9a..cc30a93 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -85,13 +85,9 @@
 using VecElem = ::DummyVecElem;
 using VecRegContainer = ::DummyVecRegContainer;
 constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
-constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes;

 // Not applicable to x86
-using VecPredReg = ::DummyVecPredReg;
-using ConstVecPredReg = ::DummyConstVecPredReg;
 using VecPredRegContainer = ::DummyVecPredRegContainer;
-constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;

 } // namespace X86ISA


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[gem5-dev] Change in gem5/gem5[develop]: arch,cpu,gpu-compute: Further simplify VecRegContainer.

2021-02-26 Thread Gabe Black (Gerrit) via gem5-dev
rc/arch/null/registers.hh
@@ -49,8 +49,6 @@

 // Not applicable to null
 using VecElem = ::DummyVecElem;
-using VecReg = ::DummyVecReg;
-using ConstVecReg = ::DummyConstVecReg;
 using VecRegContainer = ::DummyVecRegContainer;
 constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
 constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes;
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index 2a1aea5..5fc2200 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -39,8 +39,6 @@

 // Not applicable to Power
 using VecElem = ::DummyVecElem;
-using VecReg = ::DummyVecReg;
-using ConstVecReg = ::DummyConstVecReg;
 using VecRegContainer = ::DummyVecRegContainer;
 constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
 constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes;
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index 862259f..e7f3e11 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -93,8 +93,6 @@

 // Not applicable to RISC-V
 using VecElem = ::DummyVecElem;
-using VecReg = ::DummyVecReg;
-using ConstVecReg = ::DummyConstVecReg;
 using VecRegContainer = ::DummyVecRegContainer;
 constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
 constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes;
diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index 0602176..aa263a9 100644
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -40,8 +40,6 @@

 // Not applicable to SPARC
 using VecElem = ::DummyVecElem;
-using VecReg = ::DummyVecReg;
-using ConstVecReg = ::DummyConstVecReg;
 using VecRegContainer = ::DummyVecRegContainer;
 constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
 constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes;
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index a29f1b8..769f6da 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -83,8 +83,6 @@

 // Not applicable to x86
 using VecElem = ::DummyVecElem;
-using VecReg = ::DummyVecReg;
-using ConstVecReg = ::DummyConstVecReg;
 using VecRegContainer = ::DummyVecRegContainer;
 constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
 constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes;
diff --git a/src/cpu/o3/rename_map.cc b/src/cpu/o3/rename_map.cc
index cda9924..0edafcf 100644
--- a/src/cpu/o3/rename_map.cc
+++ b/src/cpu/o3/rename_map.cc
@@ -200,7 +200,7 @@
  */
 TheISA::VecRegContainer new_RF[TheISA::NumVecRegs];
 for (uint32_t i = 0; i < TheISA::NumVecRegs; i++) {
-TheISA::VecReg dst = new_RF[i].as();
+TheISA::VecElem *dst = new_RF[i].as();
 for (uint32_t l = 0; l < TheISA::NumVecElemPerVecReg; l++) {
 RegId s_rid(VecElemClass, i, l);
 PhysRegIdPtr s_prid = vecElemMap.lookup(s_rid);
diff --git a/src/gpu-compute/wavefront.cc b/src/gpu-compute/wavefront.cc
index e442e2a..c5a6d24 100644
--- a/src/gpu-compute/wavefront.cc
+++ b/src/gpu-compute/wavefront.cc
@@ -453,7 +453,7 @@
 {
 physVgprIdx = computeUnit->registerManager
 ->mapVgpr(this, regInitIdx);
-TheGpuISA::VecRegU32 vgpr_x
+TheGpuISA::VecElemU32 *vgpr_x
 = raw_vgpr.as();

 for (int lane = 0; lane < workItemId[0].size();  
++lane) {

@@ -469,7 +469,7 @@
 {
 physVgprIdx = computeUnit->registerManager
 ->mapVgpr(this, regInitIdx);
-TheGpuISA::VecRegU32 vgpr_y
+TheGpuISA::VecElemU32 *vgpr_y
 = raw_vgpr.as();

 for (int lane = 0; lane < workItemId[1].size();  
++lane) {

@@ -485,7 +485,7 @@
 {
 physVgprIdx = computeUnit->registerManager->
 mapVgpr(this, regInitIdx);
-TheGpuISA::VecRegU32 vgpr_z
+TheGpuISA::VecElemU32 *vgpr_z
 = raw_vgpr.as();

         for (int lane = 0; lane < workItemId[2].size();  
++lane) {


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[gem5-dev] Change in gem5/gem5[develop]: cpu: Use the built in << for VecReg and VecPredReg in ExeTrace.

2021-02-26 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42001 )



Change subject: cpu: Use the built in << for VecReg and VecPredReg in  
ExeTrace.

..

cpu: Use the built in << for VecReg and VecPredReg in ExeTrace.

There's no reason to reimplement printing code when VecReg and
VecPredReg types already know how to print themselves.

Change-Id: I092c28143de286d765312122b81ce865a5184091
---
M src/cpu/exetrace.cc
1 file changed, 2 insertions(+), 23 deletions(-)



diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 76db4d7..cf4a734 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -116,31 +116,10 @@
 if (Debug::ExecResult && data_status != DataInvalid) {
 switch (data_status) {
   case DataVec:
-{
-ccprintf(outs, " D=0x[");
-auto dv = data.as_vec->as();
-for (int i = TheISA::VecRegSizeBytes / 4 - 1; i >= 0;
- i--) {
-ccprintf(outs, "%08x", dv[i]);
-if (i != 0) {
-ccprintf(outs, "_");
-}
-}
-ccprintf(outs, "]");
-}
+ccprintf(outs, " D=%s", *data.as_vec);
 break;
   case DataVecPred:
-{
-ccprintf(outs, " D=0b[");
-auto pv = data.as_pred->as();
-for (int i = TheISA::VecPredRegSizeBits - 1; i >= 0;  
i--) {

-ccprintf(outs, pv[i] ? "1" : "0");
-if (i != 0 && i % 4 == 0) {
-ccprintf(outs, "_");
-}
-}
-ccprintf(outs, "]");
-}
+ccprintf(outs, " D=%s", *data.as_pred);
 break;
   default:
 ccprintf(outs, " D=%#018x", data.as_int);

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[gem5-dev] Change in gem5/gem5[develop]: sim: Don't needlessly recreate ISA types in InstRecord.

2021-02-26 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42002 )



Change subject: sim: Don't needlessly recreate ISA types in InstRecord.
..

sim: Don't needlessly recreate ISA types in InstRecord.

The ISAs already define fully realized types. We don't need to
separately track what parameters they used and then feed them into the
same templates again elsewhere.

Change-Id: Iac18bb9374ff684259c6aa00036eac4d1026dcfc
---
M src/sim/insttracer.hh
1 file changed, 6 insertions(+), 7 deletions(-)



diff --git a/src/sim/insttracer.hh b/src/sim/insttracer.hh
index 636bf76..a2ecad4 100644
--- a/src/sim/insttracer.hh
+++ b/src/sim/insttracer.hh
@@ -94,8 +94,8 @@
 union {
 uint64_t as_int;
 double as_double;
-::VecRegContainer* as_vec;
-::VecPredRegContainer* as_pred;
+TheISA::VecRegContainer* as_vec;
+TheISA::VecPredRegContainer* as_pred;
 } data;

 /** @defgroup fetch_seq
@@ -201,17 +201,16 @@
 void setData(double d) { data.as_double = d; data_status = DataDouble;  
}


 void
-setData(::VecRegContainer& d)
+setData(TheISA::VecRegContainer& d)
 {
-data.as_vec = new ::VecRegContainer(d);
+data.as_vec = new TheISA::VecRegContainer(d);
 data_status = DataVec;
 }

 void
-setData(::VecPredRegContainer& d)
+setData(TheISA::VecPredRegContainer& d)
 {
-data.as_pred =
-new ::VecPredRegContainer(d);
+data.as_pred = new TheISA::VecPredRegContainer(d);
 data_status = DataVecPred;
 }


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[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Separate printing and serialization of VecPredReg.

2021-02-26 Thread Gabe Black (Gerrit) via gem5-dev
7 +343,7 @@
 getWritableVecPredRegFlat(flatIndex);
 DPRINTF(VecPredRegs,
 "Reading predicate reg %d (%d) as %s for modify.\n",
-reg.index(), flatIndex, regVal.print());
+reg.index(), flatIndex, regVal);
 return regVal;
 }

@@ -410,7 +410,7 @@
 assert(flatIndex < TheISA::NumVecPredRegs);
 setVecPredRegFlat(flatIndex, val);
 DPRINTF(VecPredRegs, "Setting predicate reg %d (%d) to %s.\n",
-reg.index(), flatIndex, val.print());
+reg.index(), flatIndex, val);
 }

 void

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[gem5-dev] Change in gem5/gem5[develop]: arch: Remove unnecessary "typename"s from VecPredRegT.

2021-02-26 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41998 )



Change subject: arch: Remove unnecessary "typename"s from VecPredRegT.
..

arch: Remove unnecessary "typename"s from VecPredRegT.

Change-Id: If38e71ac79105b111d68df1e572f9a8e32a131ad
---
M src/arch/generic/vec_pred_reg.hh
1 file changed, 5 insertions(+), 5 deletions(-)



diff --git a/src/arch/generic/vec_pred_reg.hh  
b/src/arch/generic/vec_pred_reg.hh

index e932418..6db0e1e 100644
--- a/src/arch/generic/vec_pred_reg.hh
+++ b/src/arch/generic/vec_pred_reg.hh
@@ -83,14 +83,14 @@

 /// Reset the register to an all-false value.
 template
-typename std::enable_if_t reset() {  
container.reset(); }

+std::enable_if_t reset() { container.reset(); }

 /// Reset the register to an all-true value.
 template
-typename std::enable_if_t set() { container.set(); }
+std::enable_if_t set() { container.set(); }

 template
-typename std::enable_if_t
+std::enable_if_t
 operator=(const MyClass& that)
 {
 container = that.container;
@@ -104,7 +104,7 @@
 }

 template
-typename std::enable_if_t
+std::enable_if_t
 operator[](size_t idx)
 {
 return container[idx * sizeof(VecElem)];
@@ -120,7 +120,7 @@

 /// Write a raw value in an element of the predicate register
 template
-typename std::enable_if_t
+std::enable_if_t
 set_raw(size_t idx, uint8_t val)
 {
 container.set_bits(idx * sizeof(VecElem), sizeof(VecElem), val);

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[gem5-dev] Change in gem5/gem5[develop]: arch,sim: Get rid of unused "Packed" vector predicate registers.

2021-02-26 Thread Gabe Black (Gerrit) via gem5-dev
ol
-to_number(const std::string& value, VecPredRegContainer&  
p)

+to_number(const std::string& value, VecPredRegContainer& p)
 {
 int i = 0;
 for (const auto& c: value) {
@@ -388,12 +372,11 @@
 /// Dummy type aliases and constants for architectures that do not  
implement

 /// vector predicate registers.
 /// @{
-constexpr bool DummyVecPredRegHasPackedRepr = false;
 using DummyVecPredReg = VecPredRegT;
+false>;
 using DummyConstVecPredReg = VecPredRegT- DummyVecPredRegHasPackedRepr,  
true>;

+ true>;
 using DummyVecPredRegContainer = DummyVecPredReg::Container;
 constexpr size_t DummyVecPredRegSizeBits = 8;
 /// @}
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index 18c0d58..4ca73d8 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -279,7 +279,6 @@
 using ConstVecPredReg = ::DummyConstVecPredReg;
 using VecPredRegContainer = ::DummyVecPredRegContainer;
 constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
-constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;

 } // namespace MipsISA

diff --git a/src/arch/null/registers.hh b/src/arch/null/registers.hh
index d56a6a7..aa01945 100644
--- a/src/arch/null/registers.hh
+++ b/src/arch/null/registers.hh
@@ -58,7 +58,6 @@
 using ConstVecPredReg = ::DummyConstVecPredReg;
 using VecPredRegContainer = ::DummyVecPredRegContainer;
 constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
-constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;

 }

diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index 5fc2200..5f5f67b 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -48,7 +48,6 @@
 using ConstVecPredReg = ::DummyConstVecPredReg;
 using VecPredRegContainer = ::DummyVecPredRegContainer;
 constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
-constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;

 // Constants Related to the number of registers
 const int NumIntArchRegs = 32;
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index e7f3e11..126132f 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -102,7 +102,6 @@
 using ConstVecPredReg = ::DummyConstVecPredReg;
 using VecPredRegContainer = ::DummyVecPredRegContainer;
 constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
-constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;

 const int NumIntArchRegs = 32;
 const int NumMicroIntRegs = 1;
diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index aa263a9..bf92f02 100644
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -49,7 +49,6 @@
 using ConstVecPredReg = ::DummyConstVecPredReg;
 using VecPredRegContainer = ::DummyVecPredRegContainer;
 constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
-constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;

 // semantically meaningful register indices
 enum {
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index 769f6da..867ad9a 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -92,7 +92,6 @@
 using ConstVecPredReg = ::DummyConstVecPredReg;
 using VecPredRegContainer = ::DummyVecPredRegContainer;
 constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
-constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;

 } // namespace X86ISA

diff --git a/src/sim/insttracer.hh b/src/sim/insttracer.hh
index 22e2489..636bf76 100644
--- a/src/sim/insttracer.hh
+++ b/src/sim/insttracer.hh
@@ -95,8 +95,7 @@
 uint64_t as_int;
 double as_double;
 ::VecRegContainer* as_vec;
-::VecPredRegContainer* as_pred;
+::VecPredRegContainer* as_pred;
 } data;

 /** @defgroup fetch_seq
@@ -209,11 +208,10 @@
 }

 void
-setData(::VecPredRegContainer& d)
+setData(::VecPredRegContainer& d)
 {
-data.as_pred = new ::VecPredRegContainer<
-TheISA::VecPredRegSizeBits,  
TheISA::VecPredRegHasPackedRepr>(d);

+data.as_pred =
+new ::VecPredRegContainer(d);
 data_status = DataVecPred;
 }


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[gem5-dev] Change in gem5/gem5[develop]: arch: Collapse unused size parameter from "as" VecPredReg method.

2021-02-26 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42000 )



Change subject: arch: Collapse unused size parameter from "as" VecPredReg  
method.

..

arch: Collapse unused size parameter from "as" VecPredReg method.

Change-Id: Ibdaf38b2e2d8f37ef76d6b8874ac3620982e78a2
---
M src/arch/generic/vec_pred_reg.hh
1 file changed, 6 insertions(+), 12 deletions(-)



diff --git a/src/arch/generic/vec_pred_reg.hh  
b/src/arch/generic/vec_pred_reg.hh

index cdf5eb5..86e3b83 100644
--- a/src/arch/generic/vec_pred_reg.hh
+++ b/src/arch/generic/vec_pred_reg.hh
@@ -333,24 +333,18 @@
 /// @tparam VecElem Type of the vector elements.
 /// @tparam NumElems Number of vector elements making up the view.
 /// @{
-template sizeof(VecElem)>

-VecPredRegT
+template 
+VecPredRegT
 as() const
 {
-static_assert(NumBits % sizeof(VecElem) == 0 &&
-  sizeof(VecElem) * NumElems <= NumBits,
-  "Container size incompatible with view size");
-return VecPredRegT(*this);
+return VecPredRegTtrue>(*this);

 }

-template sizeof(VecElem)>

-VecPredRegT
+template 
+VecPredRegT
 as()
 {
-static_assert(NumBits % sizeof(VecElem) == 0 &&
-  sizeof(VecElem) * NumElems <= NumBits,
-  "Container size incompatible with view size");
-return VecPredRegT(*this);
+return VecPredRegTfalse>(*this);

 }
 /// @}
 };

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[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Stop using << and to_number for VecReg serialization.

2021-02-26 Thread Gabe Black (Gerrit) via gem5-dev
g->index()]);

 return vectorRegFile[phys_reg->index()];
 }
@@ -296,7 +296,7 @@
 assert(phys_reg->isVectorPhysReg());

 DPRINTF(IEW, "RegFile: Setting vector register %i to %s\n",
-int(phys_reg->index()), val.print());
+int(phys_reg->index()), val);

 vectorRegFile[phys_reg->index()] = val;
 }
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index b2321c4..8f65ea3 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -295,7 +295,7 @@
 assert(flatIndex < TheISA::NumVecRegs);
 const TheISA::VecRegContainer& regVal = readVecRegFlat(flatIndex);
 DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s.\n",
-reg.index(), flatIndex, regVal.print());
+reg.index(), flatIndex, regVal);
 return regVal;
 }

@@ -306,7 +306,7 @@
 assert(flatIndex < TheISA::NumVecRegs);
 TheISA::VecRegContainer& regVal = getWritableVecRegFlat(flatIndex);
 DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s for modify.\n",
-reg.index(), flatIndex, regVal.print());
+reg.index(), flatIndex, regVal);
 return regVal;
 }

@@ -389,7 +389,7 @@
 assert(flatIndex < TheISA::NumVecRegs);
 setVecRegFlat(flatIndex, val);
 DPRINTF(VecRegs, "Setting vector reg %d (%d) to %s.\n",
-reg.index(), flatIndex, val.print());
+reg.index(), flatIndex, val);
 }

 void

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[gem5-dev] Change in gem5/gem5[develop]: arch: Break the dependence between (non)-predicate vector regs.

2021-02-26 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41997 )



Change subject: arch: Break the dependence between (non)-predicate vector  
regs.

..

arch: Break the dependence between (non)-predicate vector regs.

Change-Id: I6c3cd7c1ce9c5d509c332be9bfc107a329f1
---
M src/arch/generic/vec_pred_reg.hh
1 file changed, 5 insertions(+), 6 deletions(-)



diff --git a/src/arch/generic/vec_pred_reg.hh  
b/src/arch/generic/vec_pred_reg.hh

index 67ee9e5..e932418 100644
--- a/src/arch/generic/vec_pred_reg.hh
+++ b/src/arch/generic/vec_pred_reg.hh
@@ -38,9 +38,11 @@

 #include 
 #include 
+#include 
+#include 
+#include 
 #include 

-#include "arch/generic/vec_reg.hh"
 #include "base/cprintf.hh"

 template 
@@ -372,11 +374,8 @@
 /// Dummy type aliases and constants for architectures that do not  
implement

 /// vector predicate registers.
 /// @{
-using DummyVecPredReg = VecPredRegT;
-using DummyConstVecPredReg = VecPredRegT;
+using DummyVecPredReg = VecPredRegT;
+using DummyConstVecPredReg = VecPredRegT;
 using DummyVecPredRegContainer = DummyVecPredReg::Container;
 constexpr size_t DummyVecPredRegSizeBits = 8;
 /// @}

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[gem5-dev] Change in gem5/gem5[develop]: arch: Simplify and correct style of VecReg types.

2021-02-26 Thread Gabe Black (Gerrit) via gem5-dev
nd std::ostream& operator<<(std::ostream& os, const MyClass& v)
+friend std::ostream&
+operator<<(std::ostream& os, const MyClass& v)
 {
 for (auto& b: v.container) {
 os << csprintf("%02x", b);

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[gem5-dev] Change in gem5/gem5[develop]: arch: Eliminate the "Lane" view of vector registers.

2021-02-25 Thread Gabe Black (Gerrit) via gem5-dev
Elem. */
-template 
-template 
-VecLaneT
-VecRegContainer::laneView() const
-{
-return VecLaneT(as()[LaneIdx]);
-}
-
-/** View as the Nth lane of type VecElem. */
-template 
-template 
-VecLaneT
-VecRegContainer::laneView(int laneIdx)
-{
-return VecLaneT(as()[laneIdx]);
-}
-
-/** View as the const Nth lane of type VecElem. */
-template 
-template 
-VecLaneT
-VecRegContainer::laneView(int laneIdx) const
-{
-return VecLaneT(as()[laneIdx]);
-}
-
-using VecLane8 = VecLaneT;
-using VecLane16 = VecLaneT;
-using VecLane32 = VecLaneT;
-using VecLane64 = VecLaneT;
-
-using ConstVecLane8 = VecLaneT;
-using ConstVecLane16 = VecLaneT;
-using ConstVecLane32 = VecLaneT;
-using ConstVecLane64 = VecLaneT;
-
 /**
  * Calls required for serialization/deserialization
  */

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[gem5-dev] Change in gem5/gem5[develop]: cpu: Eliminate the unused "lane" interface from the ThreadContext.

2021-02-25 Thread Gabe Black (Gerrit) via gem5-dev
   readVec32BitLaneReg(const RegId ) const override
-{
-return readVecLane(reg);
-}
-
-/** Reads source vector 64bit operand. */
-virtual ConstVecLane64
-readVec64BitLaneReg(const RegId ) const override
-{
-return readVecLane(reg);
-}
-
-/** Write a lane of the destination vector register. */
-template 
-void
-setVecLaneT(const RegId , const LD )
-{
-int flatIndex = isa->flattenVecIndex(reg.index());
-assert(flatIndex < TheISA::NumVecRegs);
-setVecLaneFlat(flatIndex, reg.elemIndex(), val);
-DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] to %lx.\n",
-reg.index(), flatIndex, reg.elemIndex(), val);
-}
-virtual void
-setVecLane(const RegId , const LaneData )  
override

-{
-return setVecLaneT(reg, val);
-}
-virtual void
-setVecLane(const RegId ,
-   const LaneData ) override
-{
-return setVecLaneT(reg, val);
-}
-virtual void
-setVecLane(const RegId ,
-   const LaneData ) override
-{
-return setVecLaneT(reg, val);
-}
-virtual void
-setVecLane(const RegId ,
-   const LaneData ) override
-{
-return setVecLaneT(reg, val);
-}
-/** @} */
-
 const TheISA::VecElem &
 readVecElem(const RegId ) const override
 {
@@ -609,20 +530,6 @@
 vecRegs[reg] = val;
 }

-template 
-VecLaneT
-readVecLaneFlat(RegIndex reg, int lId) const
-{
-return vecRegs[reg].laneView(lId);
-}
-
-template 
-void
-setVecLaneFlat(RegIndex reg, int lId, const LD )
-{
-vecRegs[reg].laneView(lId) = val;
-}
-
 const TheISA::VecElem &
 readVecElemFlat(RegIndex reg, const ElemIndex ) const  
override

 {
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 874146a..75f6f5a 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -205,35 +205,6 @@
 readVecReg(const RegId& reg) const = 0;
 virtual TheISA::VecRegContainer& getWritableVecReg(const RegId& reg) =  
0;


-/** Vector Register Lane Interfaces. */
-/** @{ */
-/** Reads source vector 8bit operand. */
-virtual ConstVecLane8
-readVec8BitLaneReg(const RegId& reg) const = 0;
-
-/** Reads source vector 16bit operand. */
-virtual ConstVecLane16
-readVec16BitLaneReg(const RegId& reg) const = 0;
-
-/** Reads source vector 32bit operand. */
-virtual ConstVecLane32
-readVec32BitLaneReg(const RegId& reg) const = 0;
-
-/** Reads source vector 64bit operand. */
-virtual ConstVecLane64
-readVec64BitLaneReg(const RegId& reg) const = 0;
-
-/** Write a lane of the destination vector register. */
-virtual void setVecLane(const RegId& reg,
-const LaneData& val) = 0;
-virtual void setVecLane(const RegId& reg,
-const LaneData& val) = 0;
-virtual void setVecLane(const RegId& reg,
-const LaneData& val) = 0;
-virtual void setVecLane(const RegId& reg,
-const LaneData& val) = 0;
-/** @} */
-
 virtual const TheISA::VecElem& readVecElem(const RegId& reg) const = 0;

 virtual const TheISA::VecPredRegContainer& readVecPredReg(

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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Switch the AAPCS ABIs to .as<>() instead of .laneView<>().

2021-02-25 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41898 )



Change subject: arch-arm: Switch the AAPCS ABIs to .as<>() instead  
of .laneView<>().

..

arch-arm: Switch the AAPCS ABIs to .as<>() instead of .laneView<>().

Change-Id: I9e9c7163db4c061af00111b8dc959c364c6b7ae6
---
M src/arch/arm/aapcs32.hh
M src/arch/arm/aapcs64.hh
2 files changed, 6 insertions(+), 6 deletions(-)



diff --git a/src/arch/arm/aapcs32.hh b/src/arch/arm/aapcs32.hh
index a1345bd..c450237 100644
--- a/src/arch/arm/aapcs32.hh
+++ b/src/arch/arm/aapcs32.hh
@@ -463,7 +463,7 @@

 RegId id(VecRegClass, 0);
 auto reg = tc->readVecReg(id);
-reg.laneView() = f;
+reg.as()[0] = f;
 tc->setVecReg(id, reg);
 };
 };
@@ -487,7 +487,7 @@

 RegId id(VecRegClass, reg);
 auto val = tc->readVecReg(id);
-return val.laneView(lane);
+return val.as()[lane];
 }

 return loadFromStack(tc, state);
@@ -558,7 +558,7 @@

 RegId id(VecRegClass, reg);
 auto val = tc->readVecReg(id);
-ha[i] = val.laneView(lane);
+ha[i] = val.as()[lane];
 }
 return ha;
 }
@@ -605,7 +605,7 @@

 RegId id(VecRegClass, reg);
 auto val = tc->readVecReg(id);
-val.laneView(lane) = ha[i];
+val.as()[lane] = ha[i];
 tc->setVecReg(id, val);
 }
 }
diff --git a/src/arch/arm/aapcs64.hh b/src/arch/arm/aapcs64.hh
index fb7b8f8..ddd5606 100644
--- a/src/arch/arm/aapcs64.hh
+++ b/src/arch/arm/aapcs64.hh
@@ -186,7 +186,7 @@
 {
 if (state.nsrn <= state.MAX_SRN) {
 RegId id(VecRegClass, state.nsrn++);
-return tc->readVecReg(id).laneView();
+return tc->readVecReg(id).as()[0];
 }

 return loadFromStack(tc, state);
@@ -203,7 +203,7 @@
 {
 RegId id(VecRegClass, 0);
 auto reg = tc->readVecReg(id);
-reg.laneView() = f;
+reg.as()[0] = f;
 tc->setVecReg(id, reg);
 }
 };

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[gem5-dev] Change in gem5/gem5[develop]: arch,arch-arm: Eliminate the "zeroing" field of vec reg elements.

2021-02-25 Thread Gabe Black (Gerrit) via gem5-dev
  'AA64FpOffsetQ':  vectorRegElem('0', 'tud')
 }),

 'AA64FpUreg0': vectorReg('VECREG_UREG0',
@@ -619,9 +619,9 @@
 'AA64FpUreg0P1': vectorRegElem('1'),
 'AA64FpUreg0P2': vectorRegElem('2'),
 'AA64FpUreg0P3': vectorRegElem('3'),
-'AA64FpUreg0S':  vectorRegElem('0', 'sf', zeroing = True),
-'AA64FpUreg0D':  vectorRegElem('0', 'df', zeroing = True),
-'AA64FpUreg0Q':  vectorRegElem('0', 'tud', zeroing = True)
+'AA64FpUreg0S':  vectorRegElem('0', 'sf'),
+'AA64FpUreg0D':  vectorRegElem('0', 'df'),
+'AA64FpUreg0Q':  vectorRegElem('0', 'tud')
 }),

 # Predicate register operands
diff --git a/src/arch/isa_parser/operand_types.py  
b/src/arch/isa_parser/operand_types.py

index 6c3549f..10e763b 100755
--- a/src/arch/isa_parser/operand_types.py
+++ b/src/arch/isa_parser/operand_types.py
@@ -319,7 +319,7 @@

 def makeDeclElem(self, elem_op):
 (elem_name, elem_ext) = elem_op
-(elem_spec, dflt_elem_ext, zeroing) = self.elems[elem_name]
+(elem_spec, dflt_elem_ext) = self.elems[elem_name]
 if elem_ext:
 ext = elem_ext
 else:
@@ -356,7 +356,7 @@
 # Read destination register to write
 def makeReadWElem(self, elem_op):
 (elem_name, elem_ext) = elem_op
-(elem_spec, dflt_elem_ext, zeroing) = self.elems[elem_name]
+(elem_spec, dflt_elem_ext) = self.elems[elem_name]
 if elem_ext:
 ext = elem_ext
 else:
@@ -393,7 +393,7 @@
 # Normal source operand read
 def makeReadElem(self, elem_op, name):
 (elem_name, elem_ext) = elem_op
-(elem_spec, dflt_elem_ext, zeroing) = self.elems[elem_name]
+(elem_spec, dflt_elem_ext) = self.elems[elem_name]

 if elem_ext:
 ext = elem_ext

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[gem5-dev] Change in gem5/gem5[develop]: cpu: Remove "lane" accessors from the ExecContext classes.

2021-02-25 Thread Gabe Black (Gerrit) via gem5-dev
{
-return setVecLaneOperandT(si, idx, val);
-}
-/** @} */
-
 TheISA::VecElem
 readVecElemOperand(const StaticInst *si, int idx) const override
 {
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index 235c703..218f350 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -344,75 +344,6 @@
 thread->setVecReg(reg, val);
 }

-/** Vector Register Lane Interfaces. */
-/** @{ */
-/** Reads source vector lane. */
-template 
-VecLaneT
-readVecLaneOperand(const StaticInst *si, int idx) const
-{
-execContextStats.numVecRegReads++;
-const RegId& reg = si->srcRegIdx(idx);
-assert(reg.isVecReg());
-return thread->readVecLane(reg);
-}
-/** Reads source vector 8bit operand. */
-virtual ConstVecLane8
-readVec8BitLaneOperand(const StaticInst *si, int idx) const
-override
-{ return readVecLaneOperand(si, idx); }
-
-/** Reads source vector 16bit operand. */
-virtual ConstVecLane16
-readVec16BitLaneOperand(const StaticInst *si, int idx) const
-override
-{ return readVecLaneOperand(si, idx); }
-
-/** Reads source vector 32bit operand. */
-virtual ConstVecLane32
-readVec32BitLaneOperand(const StaticInst *si, int idx) const
-override
-{ return readVecLaneOperand(si, idx); }
-
-/** Reads source vector 64bit operand. */
-virtual ConstVecLane64
-readVec64BitLaneOperand(const StaticInst *si, int idx) const
-override
-{ return readVecLaneOperand(si, idx); }
-
-/** Write a lane of the destination vector operand. */
-template 
-void
-setVecLaneOperandT(const StaticInst *si, int idx,
-const LD& val)
-{
-execContextStats.numVecRegWrites++;
-const RegId& reg = si->destRegIdx(idx);
-assert(reg.isVecReg());
-return thread->setVecLane(reg, val);
-}
-/** Write a lane of the destination vector operand. */
-virtual void
-setVecLaneOperand(const StaticInst *si, int idx,
-const LaneData& val) override
-{ return setVecLaneOperandT(si, idx, val); }
-/** Write a lane of the destination vector operand. */
-virtual void
-setVecLaneOperand(const StaticInst *si, int idx,
-const LaneData& val) override
-{ return setVecLaneOperandT(si, idx, val); }
-/** Write a lane of the destination vector operand. */
-virtual void
-setVecLaneOperand(const StaticInst *si, int idx,
-const LaneData& val) override
-{ return setVecLaneOperandT(si, idx, val); }
-/** Write a lane of the destination vector operand. */
-virtual void
-setVecLaneOperand(const StaticInst *si, int idx,
-const LaneData& val) override
-{ return setVecLaneOperandT(si, idx, val); }
-/** @} */
-
 /** Reads an element of a vector register. */
 TheISA::VecElem
 readVecElemOperand(const StaticInst *si, int idx) const override

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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Consolidate defintions of vectorReg operands.

2021-02-25 Thread Gabe Black (Gerrit) via gem5-dev
',
-{
-'AA64IntrlvReg0P0': vectorRegElem('0'),
-'AA64IntrlvReg0P1': vectorRegElem('1'),
-'AA64IntrlvReg0P2': vectorRegElem('2'),
-'AA64IntrlvReg0P3': vectorRegElem('3'),
-'AA64IntrlvReg0S':  vectorRegElem('0', 'sf'),
-'AA64IntrlvReg0D':  vectorRegElem('0', 'df'),
-'AA64IntrlvReg0Q':  vectorRegElem('0', 'tud')
-}),
-
-'AA64IntrlvReg1': vectorReg('INTRLVREG1',
-{
-'AA64IntrlvReg1P0': vectorRegElem('0'),
-'AA64IntrlvReg1P1': vectorRegElem('1'),
-'AA64IntrlvReg1P2': vectorRegElem('2'),
-'AA64IntrlvReg1P3': vectorRegElem('3'),
-'AA64IntrlvReg1S':  vectorRegElem('0', 'sf'),
-'AA64IntrlvReg1D':  vectorRegElem('0', 'df'),
-'AA64IntrlvReg1Q':  vectorRegElem('0', 'tud')
-}),
-
-'AA64IntrlvReg2': vectorReg('INTRLVREG2',
-{
-'AA64IntrlvReg2P0': vectorRegElem('0'),
-'AA64IntrlvReg2P1': vectorRegElem('1'),
-'AA64IntrlvReg2P2': vectorRegElem('2'),
-'AA64IntrlvReg2P3': vectorRegElem('3'),
-'AA64IntrlvReg2S':  vectorRegElem('0', 'sf'),
-'AA64IntrlvReg2D':  vectorRegElem('0', 'df'),
-'AA64IntrlvReg2Q':  vectorRegElem('0', 'tud')
-}),
-
-'AA64IntrlvReg3': vectorReg('INTRLVREG3',
-{
-'AA64IntrlvReg3P0': vectorRegElem('0'),
-'AA64IntrlvReg3P1': vectorRegElem('1'),
-'AA64IntrlvReg3P2': vectorRegElem('2'),
-'AA64IntrlvReg3P3': vectorRegElem('3'),
-'AA64IntrlvReg3S':  vectorRegElem('0', 'sf'),
-'AA64IntrlvReg3D':  vectorRegElem('0', 'df'),
-'AA64IntrlvReg3Q':  vectorRegElem('0', 'tud')
-}),
-
-'AA64FpDestMerge':   vectorReg('dest',
-{
-'AA64FpDestMergeP0': vectorRegElem('0'),
-'AA64FpDestMergeP1': vectorRegElem('1'),
-'AA64FpDestMergeP2': vectorRegElem('2'),
-'AA64FpDestMergeP3': vectorRegElem('3'),
-'AA64FpDestMergeS':  vectorRegElem('0', 'sf'),
-'AA64FpDestMergeD':  vectorRegElem('0', 'df'),
-'AA64FpDestMergeQ':  vectorRegElem('0', 'tud')
-}),
-
-'AA64FpBase': vectorReg('base',
-{
-'AA64FpBaseP0': vectorRegElem('0'),
-'AA64FpBaseP1': vectorRegElem('1'),
-'AA64FpBaseP2': vectorRegElem('2'),
-'AA64FpBaseP3': vectorRegElem('3'),
-'AA64FpBaseS':  vectorRegElem('0', 'sf'),
-'AA64FpBaseD':  vectorRegElem('0', 'df'),
-'AA64FpBaseQ':  vectorRegElem('0', 'tud')
-}),
-
-'AA64FpOffset': vectorReg('offset',
-{
-'AA64FpOffsetP0': vectorRegElem('0'),
-'AA64FpOffsetP1': vectorRegElem('1'),
-'AA64FpOffsetP2': vectorRegElem('2'),
-'AA64FpOffsetP3': vectorRegElem('3'),
-'AA64FpOffsetS':  vectorRegElem('0', 'sf'),
-'AA64FpOffsetD':  vectorRegElem('0', 'df'),
-'AA64FpOffsetQ':  vectorRegElem('0', 'tud')
-}),
-
-'AA64FpUreg0': vectorReg('VECREG_UREG0',
-{
-'AA64FpUreg0P0': vectorRegElem('0'),
-'AA64FpUreg0P1': vectorRegElem('1'),
-'AA64FpUreg0P2': vectorRegElem('2'),
-'AA64FpUreg0P3': vectorRegElem('3'),
-'AA64FpUreg0S':  vectorRegElem('0', 'sf'),
-'AA64FpUreg0D':  vectorRegElem('0', 'df'),
-'AA64FpUreg0Q':  vectorRegElem('0', 'tud')
-}),
+'AA64IntrlvReg0': vectorReg('INTRLVREG0', 'AA64FpIntrlvReg0'),
+'AA64IntrlvReg1': vectorReg('INTRLVREG1', 'AA64FpIntrlvReg1'),
+'AA64IntrlvReg2': vectorReg('INTRLVREG2', 'AA64FpIntrlvReg2'),
+'AA64IntrlvReg3': vectorReg('INTRLVREG3', 'AA64FpIntrlvReg3'),
+'AA64FpDestMerge': vectorReg('dest', 'AA64FpDestMerge'),
+'AA64FpBase': vectorReg('base', 'AA64FpBase'),
+'AA64FpOffset': vectorReg('offset', 'AA64FpOffset'),
+'AA64FpUreg0': vectorReg('VECREG_UREG0', 'AA64FpUreg0'),

 # Predicate register operands
 'GpOp': vecPredReg('gp'),

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[gem5-dev] Change in gem5/gem5[develop]: WIP

2021-02-24 Thread Gabe Black (Gerrit) via gem5-dev
SIMPLE_THREAD_HH__

-#include 
-
 #include "arch/decoder.hh"
 #include "arch/generic/htm.hh"
 #include "arch/generic/mmu.hh"
@@ -94,7 +92,7 @@

   protected:
 std::array floatRegs;
-std::array intRegs;
+std::vector intRegs;
 std::array vecRegs;
 std::array
 vecPredRegs;
@@ -270,8 +268,8 @@
 readIntReg(RegIndex reg_idx) const override
 {
 int flatIndex = isa->flattenIntIndex(reg_idx);
-assert(flatIndex < TheISA::NumIntRegs);
-uint64_t regVal(readIntRegFlat(flatIndex));
+assert(flatIndex < intRegs.size());
+uint64_t regVal = readIntRegFlat(flatIndex);
 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
 reg_idx, flatIndex, regVal);
 return regVal;
@@ -442,7 +440,7 @@
 setIntReg(RegIndex reg_idx, RegVal val) override
 {
 int flatIndex = isa->flattenIntIndex(reg_idx);
-assert(flatIndex < TheISA::NumIntRegs);
+assert(flatIndex < intRegs.size());
 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
 reg_idx, flatIndex, val);
 setIntRegFlat(flatIndex, val);
diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index 16db818..9983c9f 100644
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -57,7 +57,7 @@
 DPRINTF(Context, "Comparing thread contexts\n");

 // First loop through the integer registers.
-for (int i = 0; i < TheISA::NumIntRegs; ++i) {
+for (int i = 0; i < registerClassInfo(IntRegClass).size(); ++i) {
 RegVal t1 = one->readIntReg(i);
 RegVal t2 = two->readIntReg(i);
 if (t1 != t2)
@@ -161,10 +161,11 @@
 }
 SERIALIZE_CONTAINER(vecPredRegs);

-RegVal intRegs[TheISA::NumIntRegs];
-for (int i = 0; i < TheISA::NumIntRegs; ++i)
+const size_t numIntRegs = registerClassInfo(IntRegClass).size();
+RegVal intRegs[numIntRegs];
+for (int i = 0; i < numIntRegs; ++i)
 intRegs[i] = tc.readIntRegFlat(i);
-SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
+SERIALIZE_ARRAY(intRegs, numIntRegs);

 if (TheISA::NumCCRegs) {
 RegVal ccRegs[TheISA::NumCCRegs];
@@ -201,9 +202,10 @@
 tc.setVecPredRegFlat(i, vecPredRegs[i]);
 }

-RegVal intRegs[TheISA::NumIntRegs];
-UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
-for (int i = 0; i < TheISA::NumIntRegs; ++i)
+const size_t numIntRegs = registerClassInfo(IntRegClass).size();
+RegVal intRegs[numIntRegs];
+UNSERIALIZE_ARRAY(intRegs, numIntRegs);
+for (int i = 0; i < numIntRegs; ++i)
 tc.setIntRegFlat(i, intRegs[i]);

 if (TheISA::NumCCRegs) {
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index c1c951d..ba49390 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -296,6 +296,12 @@
 // Same with st cond failures.
 virtual Counter readFuncExeInst() const = 0;

+const RegisterClassInfo &
+registerClassInfo(RegClass reg_class)
+{
+return getIsaPtr()->registerClassInfo(reg_class);
+}
+
 // This function exits the thread context in the CPU and returns
 // 1 if the CPU has no more active threads (meaning it's OK to exit);
 // Used in syscall-emulation mode when a  thread calls the exit  
syscall.


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[gem5-dev] Change in gem5/gem5[develop]: x86: Minor cleanup of the ISA class.

2021-02-24 Thread Gabe Black (Gerrit) via gem5-dev
kpointOut ) const override;
+void unserialize(CheckpointIn ) override;

-void setThreadContext(ThreadContext *_tc) override;
+void setThreadContext(ThreadContext *_tc) override;

-std::string getVendorString() const;
+std::string getVendorString() const;
+};

-  private:
-std::string vendorString;
-};
 }

 #endif

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[gem5-dev] Change in gem5/gem5[develop]: scons: Create a small helper function for disecting a build target path.

2021-02-23 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40970 )


Change subject: scons: Create a small helper function for disecting a build  
target path.

..

scons: Create a small helper function for disecting a build target path.

This function does about half of the work of the loop which determines
the build root and the list of variants.

Change-Id: I4f44d1e2643244a4be889c677b25b83d41a39b19
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40970
Tested-by: kokoro 
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
---
M SConstruct
M site_scons/gem5_scons/__init__.py
2 files changed, 28 insertions(+), 16 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index b63e2cc..beaf9ae 100755
--- a/SConstruct
+++ b/SConstruct
@@ -124,7 +124,7 @@
   help='Build systemc tests')

 from gem5_scons import Transform, error, warning, summarize_warnings
-from gem5_scons import TempFileSpawn
+from gem5_scons import TempFileSpawn, parse_build_path
 import gem5_scons

 
@@ -182,24 +182,20 @@

 # Generate a list of the unique build roots and configs that the
 # collected targets reference.
-variant_paths = []
+variant_paths = set()
 build_root = None
 for t in BUILD_TARGETS:
-path_dirs = t.split('/')
-try:
-build_top = rfind(path_dirs, 'build', -2)
-except:
-error("No non-leaf 'build' dir found on target path.", t)
-this_build_root = joinpath('/',*path_dirs[:build_top+1])
+this_build_root, variant = parse_build_path(t)
+
+# Make sure all targets use the same build root.
 if not build_root:
 build_root = this_build_root
-else:
-if this_build_root != build_root:
-error("build targets not under same build root\n"
-  "  %s\n  %s" % (build_root, this_build_root))
-variant_path = joinpath('/',*path_dirs[:build_top+2])
-if variant_path not in variant_paths:
-variant_paths.append(variant_path)
+elif this_build_root != build_root:
+error("build targets not under same build root\n  %s\n  %s" %
+(build_root, this_build_root))
+
+# Collect all the variants into a set.
+variant_paths.add(os.path.join('/', build_root, variant))

 # Make sure build_root exists (might not if this is the first build there)
 if not isdir(build_root):
diff --git a/site_scons/gem5_scons/__init__.py  
b/site_scons/gem5_scons/__init__.py

index 5b5777c..6b167af 100644
--- a/site_scons/gem5_scons/__init__.py
+++ b/site_scons/gem5_scons/__init__.py
@@ -221,4 +221,20 @@
 print_message('Error: ', termcap.Red, message, **kwargs)
 SCons.Script.Exit(1)

-__all__ = ['Configure', 'Transform', 'warning', 'error']
+def parse_build_path(target):
+path_dirs = target.split('/')
+
+# Pop off the target file.
+path_dirs.pop()
+
+# Search backwards for the "build" directory. Whatever was just before  
it

+# was the name of the variant.
+variant_dir = path_dirs.pop()
+while path_dirs and path_dirs[-1] != 'build':
+variant_dir = path_dirs.pop()
+if not path_dirs:
+error("No non-leaf 'build' dir found on target path.", t)
+
+return os.path.join('/', *path_dirs), variant_dir
+
+__all__ = ['Configure', 'Transform', 'warning', 'error', 'parse_build_dir']



8 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

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Gerrit-Change-Number: 40970
Gerrit-PatchSet: 12
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
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Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: scons: Eliminate CXX_V and main_dict_keys in SConstruct.

2021-02-23 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40963 )


Change subject: scons: Eliminate CXX_V and main_dict_keys in SConstruct.
..

scons: Eliminate CXX_V and main_dict_keys in SConstruct.

CXX_V isn't used by anything, and main_dict_keys is unnecessary because
using "in" with the whole main environment (which acts like a dict)
checks against the keys without needing a temporary variable.

Change-Id: Iab07246c00b1969858659043cead1dd657b1707b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40963
Tested-by: kokoro 
Maintainer: Gabe Black 
Reviewed-by: Andreas Sandberg 
---
M SConstruct
1 file changed, 2 insertions(+), 5 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index 915c112..b63e2cc 100755
--- a/SConstruct
+++ b/SConstruct
@@ -141,10 +141,8 @@
 from gem5_scons.util import get_termcap
 termcap = get_termcap()

-main_dict_keys = main.Dictionary().keys()
-
 # Check that we have a C/C++ compiler
-if not ('CC' in main_dict_keys and 'CXX' in main_dict_keys):
+if not ('CC' in main and 'CXX' in main):
 error("No C++ compiler installed (package g++ on Ubuntu and RedHat)")

 ###
@@ -302,8 +300,7 @@
 # builds under a given build root run on the same host platform.
 conf = gem5_scons.Configure(main)

-CXX_version = readCommand([main['CXX'],'--version'], exception=False)
-CXX_V = readCommand([main['CXX'],'-V'], exception=False)
+CXX_version = readCommand([main['CXX'], '--version'], exception=False)

 main['GCC'] = CXX_version and CXX_version.find('g++') >= 0
 main['CLANG'] = CXX_version and CXX_version.find('clang') >= 0



7 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

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Gerrit-Change-Number: 40963
Gerrit-PatchSet: 12
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: scons: Remove an extraneous Exit().

2021-02-23 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40961 )


Change subject: scons: Remove an extraneous Exit().
..

scons: Remove an extraneous Exit().

This isn't necessary after error() which exits on its own.

Change-Id: Icad08c1badc73fa8f41013cc69d6cc5a96ff8fdb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40961
Tested-by: kokoro 
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
---
M SConstruct
1 file changed, 0 insertions(+), 1 deletion(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index ed27e58..915c112 100755
--- a/SConstruct
+++ b/SConstruct
@@ -353,7 +353,6 @@
 if compareVersions(main['CXXVERSION'], "5") < 0:
 error('gcc version 5 or newer required.\n'
   'Installed version:', main['CXXVERSION'])
-Exit(1)

 # Add the appropriate Link-Time Optimization (LTO) flags
 # unless LTO is explicitly turned off.



10 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

--
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Gerrit-Change-Number: 40961
Gerrit-PatchSet: 12
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Enable the clang++ and clang tools.

2021-02-23 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41673 )


Change subject: scons: Enable the clang++ and clang tools.
..

scons: Enable the clang++ and clang tools.

If these tools aren't enabled and CXX isn't set, scons will look for
generically named compiler aliases like cc and c++. These will generally
work, but if scons knows that the compiler is specifically clang, it
will set the CXXCONFIG variable we can use to do compiler version
checking.

Because scons blindly forces a tool into use if you specify it, we need
to use the FindTool method which will check a list of tools and add the
first one that it actually finds.

Change-Id: Ie6bebb8eab531989575c878bee07189541756d2c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41673
Reviewed-by: Earl Ou 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M SConstruct
1 file changed, 4 insertions(+), 0 deletions(-)

Approvals:
  Earl Ou: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index 19a5da9..c5dac00 100755
--- a/SConstruct
+++ b/SConstruct
@@ -94,6 +94,7 @@
 import SCons
 import SCons.Node
 import SCons.Node.FS
+import SCons.Tool

 from m5.util import compareVersions, readCommand, readCommandWithReturn

@@ -137,6 +138,9 @@

 main = Environment(tools=['default', 'git', TempFileSpawn])

+main.Tool(SCons.Tool.FindTool(['gcc', 'clang'], main))
+main.Tool(SCons.Tool.FindTool(['g++', 'clang++'], main))
+
 from gem5_scons.util import get_termcap
 termcap = get_termcap()


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie6bebb8eab531989575c878bee07189541756d2c
Gerrit-Change-Number: 41673
Gerrit-PatchSet: 4
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Use SCons' built in CXXVERSION instead of detecting our own.

2021-02-23 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41596 )


Change subject: scons: Use SCons' built in CXXVERSION instead of detecting  
our own.

..

scons: Use SCons' built in CXXVERSION instead of detecting our own.

It's not guaranteed that every compiler will set CXXVERSION, but both
gcc and clang do, and for any check of CXXVERSION to be meaningful, we
have to first check which compiler we're talking about.

Change-Id: Icd15e12832920fec6fa8634bc0fde16cc48e3f41
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41596
Tested-by: kokoro 
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
---
M SConstruct
M src/systemc/dt/int/SConscript
2 files changed, 6 insertions(+), 18 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index c5dac00..ed27e58 100755
--- a/SConstruct
+++ b/SConstruct
@@ -79,9 +79,6 @@
 import atexit
 import itertools
 import os
-import re
-import shutil
-import subprocess
 import sys

 from os import mkdir, environ
@@ -353,14 +350,11 @@
   "src/SConscript to support that compiler.")))

 if main['GCC']:
-gcc_version = readCommand([main['CXX'], '-dumpversion'],  
exception=False)

-if compareVersions(gcc_version, "5") < 0:
+if compareVersions(main['CXXVERSION'], "5") < 0:
 error('gcc version 5 or newer required.\n'
-  'Installed version:', gcc_version)
+  'Installed version:', main['CXXVERSION'])
 Exit(1)

-main['GCC_VERSION'] = gcc_version
-
 # Add the appropriate Link-Time Optimization (LTO) flags
 # unless LTO is explicitly turned off.
 if not GetOption('no_lto'):
@@ -387,15 +381,9 @@
   '-fno-builtin-realloc', '-fno-builtin-free'])

 elif main['CLANG']:
-clang_version_re = re.compile(".* version (\d+\.\d+)")
-clang_version_match = clang_version_re.search(CXX_version)
-if (clang_version_match):
-clang_version = clang_version_match.groups()[0]
-if compareVersions(clang_version, "3.9") < 0:
-error('clang version 3.9 or newer required.\n'
-  'Installed version:', clang_version)
-else:
-error('Unable to determine clang version.')
+if compareVersions(main['CXXVERSION'], "3.9") < 0:
+error('clang version 3.9 or newer required.\n'
+  'Installed version:', main['CXXVERSION'])

 # clang has a few additional warnings that we disable, extraneous
 # parantheses are allowed due to Ruby's printing of the AST,
diff --git a/src/systemc/dt/int/SConscript b/src/systemc/dt/int/SConscript
index 92c0f07..b052f04 100644
--- a/src/systemc/dt/int/SConscript
+++ b/src/systemc/dt/int/SConscript
@@ -28,7 +28,7 @@
 from m5.util import compareVersions

 if env['USE_SYSTEMC']:
-if main['GCC'] and compareVersions(main['GCC_VERSION'], '10.0') >= 0:
+if main['GCC'] and compareVersions(main['CXXVERSION'], '10.0') >= 0:
 disable_false_positives = {
 "CCFLAGS": [ "-Wno-array-bounds",
  "-Wno-stringop-overflow" ]



5 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

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Gerrit-Change-Id: Icd15e12832920fec6fa8634bc0fde16cc48e3f41
Gerrit-Change-Number: 41596
Gerrit-PatchSet: 7
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
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Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: scons: Check for "make" when using LTO with gcc.

2021-02-22 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41773 )


Change subject: scons: Check for "make" when using LTO with gcc.
..

scons: Check for "make" when using LTO with gcc.

gcc uses "make" to parallelize LTO. If we're using gcc and make isn't
found, we have to use single threaded LTO instead. A warning will let
the user know what's happening and that they might want to correct the
situation.

Technically gcc can use the MAKE environment variable to override the
program it uses, although I assume it still has to be "make" compatible.
Given the fairly low likelihood that someone will need that override and
the fact that scons won't pipe that variable through unless we plumb it
up, we'll just ignore that for now.

Change-Id: I891b213ece2a75bd8a915ee91f4130458dab397b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41773
Reviewed-by: Earl Ou 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M SConstruct
1 file changed, 12 insertions(+), 2 deletions(-)

Approvals:
  Earl Ou: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index cc3af90..19a5da9 100755
--- a/SConstruct
+++ b/SConstruct
@@ -360,14 +360,24 @@
 # Add the appropriate Link-Time Optimization (LTO) flags
 # unless LTO is explicitly turned off.
 if not GetOption('no_lto'):
+# g++ uses "make" to parallelize LTO. The program can be overriden  
with
+# the environment variable "MAKE", but we currently make no  
attempt to

+# plumb that variable through.
+parallelism = ''
+if main.Detect('make'):
+parallelism = '=%d' % GetOption('num_jobs')
+else:
+warning('"make" not found, link time optimization will be '
+'single threaded.')
+
 # Pass the LTO flag when compiling to produce GIMPLE
 # output, we merely create the flags here and only append
 # them later
-main['LTO_CCFLAGS'] = ['-flto=%d' % GetOption('num_jobs')]
+main['LTO_CCFLAGS'] = ['-flto%s' % parallelism]

 # Use the same amount of jobs for LTO as we are running
 # scons with
-main['LTO_LDFLAGS'] = ['-flto=%d' % GetOption('num_jobs')]
+main['LTO_LDFLAGS'] = ['-flto%s' % parallelism]

  
main.Append(TCMALLOC_CCFLAGS=['-fno-builtin-malloc', '-fno-builtin-calloc',

   '-fno-builtin-realloc', '-fno-builtin-free'])

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I891b213ece2a75bd8a915ee91f4130458dab397b
Gerrit-Change-Number: 41773
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Jui-min Lee 
Gerrit-CC: Yu-hsin Wang 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Check for "make" when using LTO with gcc.

2021-02-22 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41773 )



Change subject: scons: Check for "make" when using LTO with gcc.
..

scons: Check for "make" when using LTO with gcc.

gcc uses "make" to parallelize LTO. If we're using gcc and make isn't
found, we have to use single threaded LTO instead. A warning will let
the user know what's happening and that they might want to correct the
situation.

Technically gcc can use the MAKE environment variable to override the
program it uses, although I assume it still has to be "make" compatible.
Given the fairly low likelihood that someone will need that override and
the fact that scons won't pipe that variable through unless we plumb it
up, we'll just ignore that for now.

Change-Id: I891b213ece2a75bd8a915ee91f4130458dab397b
---
M SConstruct
1 file changed, 12 insertions(+), 2 deletions(-)



diff --git a/SConstruct b/SConstruct
index cc3af90..19a5da9 100755
--- a/SConstruct
+++ b/SConstruct
@@ -360,14 +360,24 @@
 # Add the appropriate Link-Time Optimization (LTO) flags
 # unless LTO is explicitly turned off.
 if not GetOption('no_lto'):
+# g++ uses "make" to parallelize LTO. The program can be overriden  
with
+# the environment variable "MAKE", but we currently make no  
attempt to

+# plumb that variable through.
+parallelism = ''
+if main.Detect('make'):
+parallelism = '=%d' % GetOption('num_jobs')
+else:
+warning('"make" not found, link time optimization will be '
+'single threaded.')
+
 # Pass the LTO flag when compiling to produce GIMPLE
 # output, we merely create the flags here and only append
 # them later
-main['LTO_CCFLAGS'] = ['-flto=%d' % GetOption('num_jobs')]
+main['LTO_CCFLAGS'] = ['-flto%s' % parallelism]

 # Use the same amount of jobs for LTO as we are running
 # scons with
-main['LTO_LDFLAGS'] = ['-flto=%d' % GetOption('num_jobs')]
+main['LTO_LDFLAGS'] = ['-flto%s' % parallelism]

  
main.Append(TCMALLOC_CCFLAGS=['-fno-builtin-malloc', '-fno-builtin-calloc',

   '-fno-builtin-realloc', '-fno-builtin-free'])

--
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Gerrit-Change-Id: I891b213ece2a75bd8a915ee91f4130458dab397b
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Gerrit-Owner: Gabe Black 
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[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Create register class descriptors.

2021-02-22 Thread Gabe Black (Gerrit) via gem5-dev
   const TheISA::VecPredRegContainer& t2 = two->readVecPredReg(rid);
@@ -94,7 +96,7 @@
   i, t1, t2);
 }

-for (int i = 0; i < TheISA::NumMiscRegs; ++i) {
+for (int i = 0; i < regClasses.at(MiscRegClass).size(); ++i) {
 RegVal t1 = one->readMiscRegNoEffect(i);
 RegVal t2 = two->readMiscRegNoEffect(i);
 if (t1 != t2)
@@ -103,7 +105,7 @@
 }

 // loop through the Condition Code registers.
-for (int i = 0; i < TheISA::NumCCRegs; ++i) {
+for (int i = 0; i < regClasses.at(CCRegClass).size(); ++i) {
 RegVal t1 = one->readCCReg(i);
 RegVal t2 = two->readCCReg(i);
 if (t1 != t2)
@@ -141,36 +143,45 @@
 void
 serialize(const ThreadContext , CheckpointOut )
 {
-RegVal floatRegs[TheISA::NumFloatRegs];
-for (int i = 0; i < TheISA::NumFloatRegs; ++i)
+// Cast away the const so we can get the non-const ISA ptr, which we  
then

+// use to get the const register classes.
+auto _tc = const_cast(tc);
+const auto  = nc_tc.getIsaPtr()->regClasses();
+
+const size_t numFloats = regClasses.at(FloatRegClass).size();
+RegVal floatRegs[numFloats];
+for (int i = 0; i < numFloats; ++i)
 floatRegs[i] = tc.readFloatRegFlat(i);
 // This is a bit ugly, but needed to maintain backwards
 // compatibility.
-arrayParamOut(cp, "floatRegs.i", floatRegs, TheISA::NumFloatRegs);
+arrayParamOut(cp, "floatRegs.i", floatRegs, numFloats);

-std::vector vecRegs(TheISA::NumVecRegs);
-for (int i = 0; i < TheISA::NumVecRegs; ++i) {
+const size_t numVecs = regClasses.at(VecRegClass).size();
+std::vector vecRegs(numVecs);
+for (int i = 0; i < numVecs; ++i) {
 vecRegs[i] = tc.readVecRegFlat(i);
 }
 SERIALIZE_CONTAINER(vecRegs);

-std::vector
-vecPredRegs(TheISA::NumVecPredRegs);
-for (int i = 0; i < TheISA::NumVecPredRegs; ++i) {
+const size_t numPreds = regClasses.at(VecPredRegClass).size();
+std::vector vecPredRegs(numPreds);
+for (int i = 0; i < numPreds; ++i) {
 vecPredRegs[i] = tc.readVecPredRegFlat(i);
 }
 SERIALIZE_CONTAINER(vecPredRegs);

-RegVal intRegs[TheISA::NumIntRegs];
-for (int i = 0; i < TheISA::NumIntRegs; ++i)
+const size_t numInts = regClasses.at(IntRegClass).size();
+RegVal intRegs[numInts];
+for (int i = 0; i < numInts; ++i)
 intRegs[i] = tc.readIntRegFlat(i);
-SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
+SERIALIZE_ARRAY(intRegs, numInts);

-if (TheISA::NumCCRegs) {
-RegVal ccRegs[TheISA::NumCCRegs];
-for (int i = 0; i < TheISA::NumCCRegs; ++i)
+const size_t numCcs = regClasses.at(CCRegClass).size();
+if (numCcs) {
+RegVal ccRegs[numCcs];
+for (int i = 0; i < numCcs; ++i)
 ccRegs[i] = tc.readCCRegFlat(i);
-SERIALIZE_ARRAY(ccRegs, TheISA::NumCCRegs);
+SERIALIZE_ARRAY(ccRegs, numCcs);
 }

 tc.pcState().serialize(cp);
@@ -181,35 +192,41 @@
 void
 unserialize(ThreadContext , CheckpointIn )
 {
-RegVal floatRegs[TheISA::NumFloatRegs];
+const auto  = tc.getIsaPtr()->regClasses();
+
+const size_t numFloats = regClasses.at(FloatRegClass).size();
+RegVal floatRegs[numFloats];
 // This is a bit ugly, but needed to maintain backwards
 // compatibility.
-arrayParamIn(cp, "floatRegs.i", floatRegs, TheISA::NumFloatRegs);
-for (int i = 0; i < TheISA::NumFloatRegs; ++i)
+arrayParamIn(cp, "floatRegs.i", floatRegs, numFloats);
+for (int i = 0; i < numFloats; ++i)
 tc.setFloatRegFlat(i, floatRegs[i]);

-std::vector vecRegs(TheISA::NumVecRegs);
+const size_t numVecs = regClasses.at(VecRegClass).size();
+std::vector vecRegs(numVecs);
 UNSERIALIZE_CONTAINER(vecRegs);
-for (int i = 0; i < TheISA::NumVecRegs; ++i) {
+for (int i = 0; i < numVecs; ++i) {
 tc.setVecRegFlat(i, vecRegs[i]);
 }

-std::vector
-vecPredRegs(TheISA::NumVecPredRegs);
+const size_t numPreds = regClasses.at(VecPredRegClass).size();
+std::vector vecPredRegs(numPreds);
 UNSERIALIZE_CONTAINER(vecPredRegs);
-for (int i = 0; i < TheISA::NumVecPredRegs; ++i) {
+for (int i = 0; i < numPreds; ++i) {
     tc.setVecPredRegFlat(i, vecPredRegs[i]);
 }

-RegVal intRegs[TheISA::NumIntRegs];
-UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
-for (int i = 0; i < TheISA::NumIntRegs; ++i)
+const size_t numInts = regClasses.at(IntRegClass).size();
+RegVal intRegs[numInts];
+UNSERIALIZE_ARRAY(intRegs, numInts);
+for (int i = 0; i < numInts; ++i)
 tc.setIntRegFlat(i, intRegs[i]);

-if (TheISA::NumCCRegs) {
-RegVal ccRegs[TheISA::NumCCRegs];
-UNSERIALIZE_ARRAY(ccRegs, TheISA::NumCCRegs);
-for (int i = 0; i < TheISA::NumCCRegs; ++i)
+const size_t numCcs = regClasses.at(CCRegClass).size();
+if (numCcs) {
+RegVal ccRegs[numCcs];
+UNSERIALIZE_ARRAY(ccRegs, numCcs);
+for (int i = 0; i < numCcs; ++i)
 tc.setCCRegFlat(i, ccRegs[i]);
 }


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Gerrit-Change-Id: I6d6d1256288f880391246b71045482a4a03c4198
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Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
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[gem5-dev] Change in gem5/gem5[develop]: arch: Move setting up RegClassInfos into the arches.

2021-02-22 Thread Gabe Black (Gerrit) via gem5-dev
sters.hh
@@ -31,7 +31,6 @@

 #include "arch/generic/vec_pred_reg.hh"
 #include "arch/generic/vec_reg.hh"
-#include "arch/sparc/miscregs.hh"
 #include "arch/sparc/sparc_traits.hh"
 #include "base/types.hh"

@@ -94,17 +93,10 @@
 const int SyscallPseudoReturnReg = INTREG_O1;

 const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs;
-const int NumVecRegs = 1;  // Not applicable to SPARC
-   // (1 to prevent warnings)
-const int NumVecPredRegs = 1;  // Not applicable to SPARC
-   // (1 to prevent warnings)
-const int NumCCRegs = 0;

 const int NumFloatRegs = 64;
 const int NumFloatArchRegs = NumFloatRegs;

-const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
-
 } // namespace SparcISA

 #endif
diff --git a/src/arch/sparc/remote_gdb.cc b/src/arch/sparc/remote_gdb.cc
index a2988c6..10c5c1f 100644
--- a/src/arch/sparc/remote_gdb.cc
+++ b/src/arch/sparc/remote_gdb.cc
@@ -124,6 +124,7 @@
 #include 
 #include 

+#include "arch/sparc/miscregs.hh"
 #include "base/intmath.hh"
 #include "base/remote_gdb.hh"
 #include "base/socket.hh"
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 46e03e3..4fc25b6 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -33,6 +33,7 @@
 #include "arch/sparc/asi.hh"
 #include "arch/sparc/faults.hh"
 #include "arch/sparc/interrupts.hh"
+#include "arch/sparc/miscregs.hh"
 #include "arch/sparc/mmu.hh"
 #include "arch/sparc/registers.hh"
 #include "base/bitfield.hh"
diff --git a/src/arch/sparc/utility.cc b/src/arch/sparc/utility.cc
index a0c0f8b..e606d16 100644
--- a/src/arch/sparc/utility.cc
+++ b/src/arch/sparc/utility.cc
@@ -205,9 +205,6 @@
 dest->setFloatReg(i, src->readFloatReg(i));
 }

-// Would need to add condition-code regs if implemented
-assert(NumCCRegs == 0);
-
 // Copy misc. registers
 copyMiscRegs(src, dest);

diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index 8ec3e10..053258f 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -30,7 +30,7 @@
 #define __ARCH_SPARC_UTILITY_HH__

 #include "arch/sparc/isa_traits.hh"
-#include "arch/sparc/registers.hh"
+#include "arch/sparc/miscregs.hh"
 #include "arch/sparc/tlb.hh"
 #include "base/bitfield.hh"
 #include "base/logging.hh"
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index f568f01..640422d 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -30,6 +30,10 @@

 #include "arch/x86/decoder.hh"
 #include "arch/x86/mmu.hh"
+#include "arch/x86/registers.hh"
+#include "arch/x86/regs/ccr.hh"
+#include "arch/x86/regs/int.hh"
+#include "arch/x86/regs/misc.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "params/X86ISA.hh"
@@ -104,7 +108,7 @@
 {
 // Blank everything. 0 might not be an appropriate value for some  
things,

 // but it is for most.
-memset(regVal, 0, NumMiscRegs * sizeof(RegVal));
+memset(regVal, 0, NUM_MISCREGS * sizeof(RegVal));

 // If some state should be non-zero after a reset, set those values  
here.

 regVal[MISCREG_CR0] = 0x6010ULL;
@@ -134,6 +138,17 @@
 {
 fatal_if(vendorString.size() != 12,
  "CPUID vendor string must be 12 characters\n");
+
+_regClasses.insert(_regClasses.end(), {
+{ NumIntRegs },
+{ NumFloatRegs },
+    { 1 }, // Not applicable to X86
+{ 2 }, // Not applicable to X86
+{ 1 }, // Not applicable to X86
+{ NUM_CCREGS },
+{ NUM_MISCREGS },
+});
+
 clear();
 }

@@ -409,13 +424,13 @@
 void
 ISA::serialize(CheckpointOut ) const
 {
-SERIALIZE_ARRAY(regVal, NumMiscRegs);
+SERIALIZE_ARRAY(regVal, NUM_MISCREGS);
 }

 void
 ISA::unserialize(CheckpointIn )
 {
-UNSERIALIZE_ARRAY(regVal, NumMiscRegs);
+UNSERIALIZE_ARRAY(regVal, NUM_MISCREGS);
 updateHandyM5Reg(regVal[MISCREG_EFER],
  regVal[MISCREG_CR0],
  regVal[MISCREG_CS_ATTR],
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index a29f1b8..572fa3d 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -49,8 +49,6 @@
 namespace X86ISA
 {

-const int NumMiscRegs = NUM_MISCREGS;
-
 const int NumIntArchRegs = NUM_INTREGS;
 const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs +  
NumImplicitIntRegs;

 const int NumCCRegs = NUM_CCREGS;
@@ -68,14 +66,9 @@
 FP_Reg_Base = 128,
 CC_Reg_Base = FP_Reg_Base + NumFloatRegs,
 Misc_Reg_Base = CC_Reg_Base + NumCCRegs,
-Max_Reg_Index = Misc_Reg_Base + NumMiscRegs
+Max_Reg_Index = Misc_Reg_Base + NUM_MISCREGS
 };

-const int NumVecRegs = 1;  // Not applicable to x86
-   // (1 to prevent warnings)
-const int NumVecPredRegs = 1;  // Not applicable to x86
-   // (1 to prevent warnings)
-
 // semantically meaningful register indices
 //There is no such register in X86
 const int ZeroReg = NUM_INTREGS;

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[gem5-dev] Change in gem5/gem5[develop]: arch-sparc: Move non-public values out of registers.hh.

2021-02-22 Thread Gabe Black (Gerrit) via gem5-dev
h/sparc/process.hh"
-#include "arch/sparc/registers.hh"
+#include "arch/sparc/regs/int.hh"
+#include "arch/sparc/regs/misc.hh"
 #include "arch/sparc/types.hh"
 #include "base/logging.hh"
 #include "cpu/thread_context.hh"
diff --git a/src/arch/sparc/se_workload.hh b/src/arch/sparc/se_workload.hh
index 7303010..0ad572a 100644
--- a/src/arch/sparc/se_workload.hh
+++ b/src/arch/sparc/se_workload.hh
@@ -30,7 +30,8 @@

 #include 

-#include "arch/sparc/miscregs.hh"
+#include "arch/sparc/regs/int.hh"
+#include "arch/sparc/regs/misc.hh"
 #include "base/loader/object_file.hh"
 #include "cpu/thread_context.hh"
 #include "sim/se_workload.hh"
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 4fc25b6..f89019b 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -33,9 +33,8 @@
 #include "arch/sparc/asi.hh"
 #include "arch/sparc/faults.hh"
 #include "arch/sparc/interrupts.hh"
-#include "arch/sparc/miscregs.hh"
 #include "arch/sparc/mmu.hh"
-#include "arch/sparc/registers.hh"
+#include "arch/sparc/regs/misc.hh"
 #include "base/bitfield.hh"
 #include "base/compiler.hh"
 #include "base/trace.hh"
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 3f33816..0fec710 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -28,7 +28,7 @@

 #include "arch/sparc/interrupts.hh"
 #include "arch/sparc/isa.hh"
-#include "arch/sparc/registers.hh"
+#include "arch/sparc/regs/misc.hh"
 #include "base/bitfield.hh"
 #include "base/trace.hh"
 #include "cpu/base.hh"
diff --git a/src/arch/sparc/utility.cc b/src/arch/sparc/utility.cc
index e606d16..324bf2d 100644
--- a/src/arch/sparc/utility.cc
+++ b/src/arch/sparc/utility.cc
@@ -29,6 +29,10 @@
 #include "arch/sparc/utility.hh"

 #include "arch/sparc/faults.hh"
+#include "arch/sparc/regs/float.hh"
+#include "arch/sparc/regs/int.hh"
+#include "arch/sparc/regs/misc.hh"
+#include "arch/sparc/sparc_traits.hh"
 #include "mem/port_proxy.hh"

 namespace SparcISA
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index 053258f..3bafb4e 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -30,7 +30,7 @@
 #define __ARCH_SPARC_UTILITY_HH__

 #include "arch/sparc/isa_traits.hh"
-#include "arch/sparc/miscregs.hh"
+#include "arch/sparc/regs/misc.hh"
 #include "arch/sparc/tlb.hh"
 #include "base/bitfield.hh"
 #include "base/logging.hh"

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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Pull everything not purely public out of registers.hh.

2021-02-22 Thread Gabe Black (Gerrit) via gem5-dev
 to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2007-2008 The Florida State University
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_ARM_REGS_VEC_HH__
+#define __ARCH_ARM_REGS_VEC_HH__
+
+#include "arch/generic/vec_pred_reg.hh"
+#include "arch/generic/vec_reg.hh"
+
+namespace ArmISA
+{
+
+// Number of VecElem per Vector Register considering only pre-SVE
+// Advanced SIMD registers.
+constexpr unsigned NumVecElemPerNeonVecReg = 4;
+// Number of VecElem per Vector Register, computed based on the vector  
length

+constexpr unsigned NumVecElemPerVecReg = MaxSveVecLenInWords;
+
+using VecElem = uint32_t;
+using VecReg = ::VecRegT;
+using ConstVecReg = ::VecRegT;
+using VecRegContainer = VecReg::Container;
+
+using VecPredReg = ::VecPredRegT;
+using ConstVecPredReg = ::VecPredRegT;
+using VecPredRegContainer = VecPredReg::Container;
+
+// Vec, PredVec
+// NumFloatV7ArchRegs: This in theory should be 32.
+// However in A32 gem5 is splitting double register accesses in two
+// subsequent single register ones. This means we would use a index
+// bigger than 31 when accessing D16-D31.
+const int NumFloatV7ArchRegs = 64; // S0-S31, D0-D31
+const int NumVecV7ArchRegs  = 16; // Q0-Q15
+const int NumVecV8ArchRegs  = 32; // V0-V31
+const int NumVecSpecialRegs = 8;
+const int NumVecIntrlvRegs = 4;
+const int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs +  
NumVecIntrlvRegs;

+const int NumVecPredRegs = 18;  // P0-P15, FFR, UREG0
+
+// Vec, PredVec indices
+const int VecSpecialElem = NumVecV8ArchRegs * NumVecElemPerNeonVecReg;
+const int INTRLVREG0 = NumVecV8ArchRegs + NumVecSpecialRegs;
+const int INTRLVREG1 = INTRLVREG0 + 1;
+const int INTRLVREG2 = INTRLVREG0 + 2;
+const int INTRLVREG3 = INTRLVREG0 + 3;
+const int VECREG_UREG0 = 32;
+const int PREDREG_FFR = 16;
+const int PREDREG_UREG0 = 17;
+
+} // namespace ArmISA
+
+#endif

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Clean up new FP code in arch/registers.hh.

2021-02-22 Thread Gabe Black (Gerrit) via gem5-dev
(Fs1_bits)), rm,
+  true));
 }}, FloatCvtOp);
 0x2: fcvt_l_d({{
 RM_REQUIRED;
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index bd29bb2..38636f4 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -62,34 +62,32 @@
 namespace RiscvISA
 {

-/* Convenience wrappers to simplify softfloat code sequences */
-#define isBoxedF32(r) ((uint32_t)((r.v >> 32) + 1) == 0)
-#define unboxF32(r) (isBoxedF32(r) ? (uint32_t)r.v : defaultNaNF32UI)
-#define unboxF64(r) (r.v)
+/* Conversion functions for working with softfloat. */

-typedef int64_t sreg_t;
-typedef uint64_t reg_t;
-typedef float64_t freg_t;
-inline float32_t f32(uint32_t v) { return { v }; }
-inline float64_t f64(uint64_t v) { return { v }; }
-inline float32_t f32(freg_t r) { return f32(unboxF32(r)); }
-inline float64_t f64(freg_t r) { return f64(unboxF64(r)); }
-inline freg_t freg(float32_t f) { return {((uint64_t)-1 << 32) | f.v}; }
-inline freg_t freg(float64_t f) { return {f}; }
-inline freg_t freg(uint_fast16_t f) { return {f}; }
-#define F32_SIGN ((uint32_t)1 << 31)
-#define F64_SIGN ((uint64_t)1 << 63)
-#define fsgnj32(a, b, n, x) \
-  f32((f32(a).v & ~F32_SIGN) | \
-  x) ? f32(a).v : (n) ? F32_SIGN : 0) ^ f32(b).v) & F32_SIGN))
-#define fsgnj64(a, b, n, x) \
-  f64((f64(a).v & ~F64_SIGN) | \
-  x) ? f64(a).v : (n) ? F64_SIGN : 0) ^ f64(b).v) & F64_SIGN))
+// Generic floating point value type.
+using freg_t = float64_t;

-#define sext32(x) ((sreg_t)(int32_t)(x))
-#define zext32(x) ((reg_t)(uint32_t)(x))
-#define sext_xlen(x) (((sreg_t)(x) << (64-xlen)) >> (64-xlen))
-#define zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen))
+// Extract a 32 bit float packed into a 64 bit value.
+static constexpr uint32_t
+unboxF32(float64_t r)
+{
+// The upper 32 bits should all be ones.
+if (bits(r.v, 63, 32) == mask(32))
+return bits(r.v, 31, 0);
+else
+return defaultNaNF32UI;
+}
+
+// Create fixed size floats from raw bytes or generic floating point  
values.

+static constexpr float32_t f32(uint32_t v) { return {v}; }
+static constexpr float64_t f64(uint64_t v) { return {v}; }
+static constexpr float32_t f32(freg_t r) { return {unboxF32(r)}; }
+static constexpr float64_t f64(freg_t r) { return r; }
+
+// Create generic floating point values from fixed size floats.
+static constexpr freg_t freg(float32_t f) { return {mask(63, 32) | f.v}; }
+static constexpr freg_t freg(float64_t f) { return f; }
+static constexpr freg_t freg(uint_fast16_t f) { return {f}; }

 // Not applicable to RISC-V
 using VecElem = ::DummyVecElem;

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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Move (most) non-public values out of registers.hh.

2021-02-22 Thread Gabe Black (Gerrit) via gem5-dev
atRegs; ++i)
  dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
 //copy condition-code regs
-for (int i = 0; i < NumCCRegs; ++i)
+for (int i = 0; i < NUM_CCREGS; ++i)
  dest->setCCRegFlat(i, src->readCCRegFlat(i));
 copyMiscRegs(src, dest);
 dest->pcState(src->pcState());

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[gem5-dev] Change in gem5/gem5[develop]: arch-mips: Pull non-public values out of registers.hh.

2021-02-22 Thread Gabe Black (Gerrit) via gem5-dev
14: 112-119
+
+MISCREG_PRID = 120,  //Bank 15: 120-127,
+MISCREG_EBASE,
+
+MISCREG_CONFIG = 128,//Bank 16: 128-135
+MISCREG_CONFIG1,
+MISCREG_CONFIG2,
+MISCREG_CONFIG3,
+MISCREG_CONFIG4,
+MISCREG_CONFIG5,
+MISCREG_CONFIG6,
+MISCREG_CONFIG7,
+
+
+MISCREG_LLADDR = 136,//Bank 17: 136-143
+
+MISCREG_WATCHLO0 = 144,  //Bank 18: 144-151
+MISCREG_WATCHLO1,
+MISCREG_WATCHLO2,
+MISCREG_WATCHLO3,
+MISCREG_WATCHLO4,
+MISCREG_WATCHLO5,
+MISCREG_WATCHLO6,
+MISCREG_WATCHLO7,
+
+MISCREG_WATCHHI0 = 152, //Bank 19: 152-159
+MISCREG_WATCHHI1,
+MISCREG_WATCHHI2,
+MISCREG_WATCHHI3,
+MISCREG_WATCHHI4,
+MISCREG_WATCHHI5,
+MISCREG_WATCHHI6,
+MISCREG_WATCHHI7,
+
+MISCREG_XCCONTEXT64 = 160, //Bank 20: 160-167
+
+   //Bank 21: 168-175
+
+   //Bank 22: 176-183
+
+MISCREG_DEBUG = 184,   //Bank 23: 184-191
+MISCREG_TRACE_CONTROL1,
+MISCREG_TRACE_CONTROL2,
+MISCREG_USER_TRACE_DATA,
+MISCREG_TRACE_BPC,
+
+MISCREG_DEPC = 192,//Bank 24: 192-199
+
+MISCREG_PERFCNT0 = 200,//Bank 25: 200-207
+MISCREG_PERFCNT1,
+MISCREG_PERFCNT2,
+MISCREG_PERFCNT3,
+MISCREG_PERFCNT4,
+MISCREG_PERFCNT5,
+MISCREG_PERFCNT6,
+MISCREG_PERFCNT7,
+
+MISCREG_ERRCTL = 208,  //Bank 26: 208-215
+
+MISCREG_CACHEERR0 = 216,   //Bank 27: 216-223
+MISCREG_CACHEERR1,
+MISCREG_CACHEERR2,
+MISCREG_CACHEERR3,
+
+MISCREG_TAGLO0 = 224,  //Bank 28: 224-231
+MISCREG_DATALO1,
+MISCREG_TAGLO2,
+MISCREG_DATALO3,
+MISCREG_TAGLO4,
+MISCREG_DATALO5,
+MISCREG_TAGLO6,
+MISCREG_DATALO7,
+
+MISCREG_TAGHI0 = 232,  //Bank 29: 232-239
+MISCREG_DATAHI1,
+MISCREG_TAGHI2,
+MISCREG_DATAHI3,
+MISCREG_TAGHI4,
+MISCREG_DATAHI5,
+MISCREG_TAGHI6,
+MISCREG_DATAHI7,
+
+
+MISCREG_ERROR_EPC = 240,//Bank 30: 240-247
+
+MISCREG_DESAVE = 248,   //Bank 31: 248-256
+
+MISCREG_LLFLAG = 257,
+MISCREG_TP_VALUE,
+
+MISCREG_NUMREGS
+};
+
+} // namespace MipsISA
+
+#endif
diff --git a/src/arch/mips/remote_gdb.cc b/src/arch/mips/remote_gdb.cc
index 9d71792..30efb36 100644
--- a/src/arch/mips/remote_gdb.cc
+++ b/src/arch/mips/remote_gdb.cc
@@ -136,6 +136,9 @@
 #include 

 #include "arch/mips/decoder.hh"
+#include "arch/mips/regs/float.hh"
+#include "arch/mips/regs/int.hh"
+#include "arch/mips/regs/misc.hh"
 #include "blobs/gdb_xml_mips.hh"
 #include "cpu/thread_state.hh"
 #include "debug/GDBAcc.hh"
diff --git a/src/arch/mips/remote_gdb.hh b/src/arch/mips/remote_gdb.hh
index 2119d8e..2084ec8 100644
--- a/src/arch/mips/remote_gdb.hh
+++ b/src/arch/mips/remote_gdb.hh
@@ -31,7 +31,6 @@
 #ifndef __ARCH_MIPS_REMOTE_GDB_HH__
 #define __ARCH_MIPS_REMOTE_GDB_HH__

-#include "arch/mips/registers.hh"
 #include "base/bitfield.hh"
 #include "base/remote_gdb.hh"

diff --git a/src/arch/mips/se_workload.hh b/src/arch/mips/se_workload.hh
index 55c605d..63eba3c 100644
--- a/src/arch/mips/se_workload.hh
+++ b/src/arch/mips/se_workload.hh
@@ -28,7 +28,7 @@
 #ifndef __ARCH_MIPS_SE_WORKLOAD_HH__
 #define __ARCH_MIPS_SE_WORKLOAD_HH__

-#include "arch/mips/registers.hh"
+#include "arch/mips/regs/int.hh"
 #include "params/MipsSEWorkload.hh"
 #include "sim/se_workload.hh"
 #include "sim/syscall_abi.hh"
diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index 911756f..596c4d1 100644
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -31,7 +31,9 @@
 #include 

 #include "arch/mips/isa_traits.hh"
-#include "arch/mips/registers.hh"
+#include "arch/mips/regs/float.hh"
+#include "arch/mips/regs/int.hh"
+#include "arch/mips/regs/misc.hh"
 #include "base/bitfield.hh"
 #include "base/logging.hh"
 #include "cpu/static_inst.hh"
diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index 6fb211d..54bcd08 100644
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -29,7 +29,9 @@

 #ifndef __ARCH_MIPS_UTILITY_HH__
 #define __ARCH_MIPS_UTILITY_HH__
+
 #include "arch/mips/isa_traits.hh"
+#include "arch/mips/regs/misc.hh"
 #include "arch/mips/types.hh"
 #include "base/logging.hh"
 #include "base/types.hh"

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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Consolidate register related files into a directory.

2021-02-22 Thread Gabe Black (Gerrit) via gem5-dev
ch/arm/tracers/tarmac_record.hh  
b/src/arch/arm/tracers/tarmac_record.hh

index 870a3fd..b02f780 100644
--- a/src/arch/arm/tracers/tarmac_record.hh
+++ b/src/arch/arm/tracers/tarmac_record.hh
@@ -45,7 +45,7 @@

 #include 

-#include "arch/arm/miscregs.hh"
+#include "arch/arm/regs/misc.hh"
 #include "arch/arm/tracers/tarmac_base.hh"
 #include "base/printable.hh"
 #include "config/the_isa.hh"
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 533b339..5372b59 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -39,12 +39,12 @@

 #include 

-#include "arch/arm/ccregs.hh"
 #include "arch/arm/faults.hh"
 #include "arch/arm/interrupts.hh"
-#include "arch/arm/intregs.hh"
 #include "arch/arm/isa_traits.hh"
 #include "arch/arm/mmu.hh"
+#include "arch/arm/regs/cc.hh"
+#include "arch/arm/regs/int.hh"
 #include "arch/arm/system.hh"
 #include "cpu/base.hh"
 #include "cpu/checker/cpu.hh"
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 1a12b6a..d7a1270 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -42,9 +42,9 @@
 #ifndef __ARCH_ARM_UTILITY_HH__
 #define __ARCH_ARM_UTILITY_HH__

-#include "arch/arm/ccregs.hh"
 #include "arch/arm/isa_traits.hh"
-#include "arch/arm/miscregs.hh"
+#include "arch/arm/regs/cc.hh"
+#include "arch/arm/regs/misc.hh"
 #include "arch/arm/types.hh"
 #include "base/logging.hh"
 #include "base/trace.hh"

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[gem5-dev] Change in gem5/gem5[develop]: arch-power: Pull non-public information out of registers.hh.

2021-02-22 Thread Gabe Black (Gerrit) via gem5-dev
BUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_POWER_REGS_FLOAT_HH__
+#define __ARCH_POWER_REGS_FLOAT_HH__
+
+namespace PowerISA
+{
+
+const int NumFloatArchRegs = 32;
+const int NumFloatRegs = NumFloatArchRegs;
+
+} // namespace PowerISA
+
+#endif // __ARCH_POWER_REGS_FLOAT_HH__
diff --git a/src/arch/power/regs/int.hh b/src/arch/power/regs/int.hh
new file mode 100644
index 000..823b256
--- /dev/null
+++ b/src/arch/power/regs/int.hh
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2009 The University of Edinburgh
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_POWER_REGS_INT_HH__
+#define __ARCH_POWER_REGS_INT_HH__
+
+namespace PowerISA
+{
+
+// Constants Related to the number of registers
+const int NumIntArchRegs = 32;
+
+// CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR
+// and zero register, which doesn't actually exist but needs a number
+const int NumIntSpecialRegs = 9;
+
+const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
+
+// Semantically meaningful register indices
+const int ReturnValueReg = 3;
+const int StackPointerReg = 1;
+
+enum MiscIntRegNums {
+INTREG_CR = NumIntArchRegs,
+INTREG_XER,
+INTREG_LR,
+INTREG_CTR,
+INTREG_FPSCR,
+INTREG_RSV,
+INTREG_RSV_LEN,
+INTREG_RSV_ADDR
+};
+
+} // namespace PowerISA
+
+#endif // __ARCH_POWER_REGS_INT_HH__
diff --git a/src/arch/power/miscregs.hh b/src/arch/power/regs/misc.hh
similarity index 100%
rename from src/arch/power/miscregs.hh
rename to src/arch/power/regs/misc.hh
diff --git a/src/arch/power/remote_gdb.hh b/src/arch/power/remote_gdb.hh
index 3bb726e..660ddb4 100644
--- a/src/arch/power/remote_gdb.hh
+++ b/src/arch/power/remote_gdb.hh
@@ -32,7 +32,8 @@
 #ifndef __ARCH_POWER_REMOTE_GDB_HH__
 #define __ARCH_POWER_REMOTE_GDB_HH__

-#include "arch/power/registers.hh"
+#include "arch/power/regs/float.hh"
+#include "arch/power/regs/int.hh"
 #include "arch/power/remote_gdb.hh"
 #include "base/remote_gdb.hh"

diff --git a/src/arch/power/se_workload.hh b/src/arch/power/se_workload.hh
index 910a271..ac79151 100644
--- a/src/arch/power/se_workload.hh
+++ b/src/arch/power/se_workload.hh
@@ -28,8 +28,8 @@
 #ifndef __ARCH_POWER_SE_WORKLOAD_HH__
 #define __ARCH_POWER_SE_WORKLOAD_HH__

-#include "arch/power/miscregs.hh"
-#include "arch/power/registers.hh"
+#include "arch/power/regs/int.hh"
+#include "arch/power/regs/misc.hh"
 #include "params/PowerSEWorkload.hh"
 #include "sim/se_workload.hh"
 #include "sim/syscall_abi.hh"
diff --git a/src/arch/power/utility.cc b/src/arch/power/utility.cc
index 1c68cd9..c4111d3 100644
--- a/src/arch/power/utility.cc
+++ b/src/arch/power/utility.cc
@@ -30,6 +30,8 @@

 #include "arch/power/utility.hh"

+#include "arch/power/regs/float.hh"
+#include "arch/power/regs/int.hh"
 #include "base/logging.hh"

 namespace PowerISA {

--
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[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Move the inUserMode function to the ISA object.

2021-02-21 Thread Gabe Black (Gerrit) via gem5-dev
ader::SymbolTable::const_iterator it;
 ccprintf(outs, "%#x", cur_pc);
-if (Debug::ExecSymbol && (!FullSystem || !TheISA::inUserMode(thread))  
&&

+if (Debug::ExecSymbol && (!FullSystem || !in_user_mode) &&
 (it = Loader::debugSymbolTable.findNearest(cur_pc)) !=
 Loader::debugSymbolTable.end()) {
 Addr delta = cur_pc - it->address;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I624f9365124679343e988cabfb4e1929225b439a
Gerrit-Change-Number: 39323
Gerrit-PatchSet: 7
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch: Eliminate the getArgument function.

2021-02-19 Thread Gabe Black (Gerrit) via gem5-dev
 int , uint16_t size, bool fp)
-{
-panic("getArgument not implemented for POWER.\n");
-return 0;
-}
-
 } // namespace PowerISA
diff --git a/src/arch/power/utility.hh b/src/arch/power/utility.hh
index 3a4b16c..9092a23 100644
--- a/src/arch/power/utility.hh
+++ b/src/arch/power/utility.hh
@@ -58,8 +58,6 @@
 pc.advance();
 }

-uint64_t getArgument(ThreadContext *tc, int , uint16_t size, bool  
fp);

-
 static inline bool
 inUserMode(ThreadContext *tc)
 {
diff --git a/src/arch/riscv/utility.hh b/src/arch/riscv/utility.hh
index 816d36c..c2f4ac8 100644
--- a/src/arch/riscv/utility.hh
+++ b/src/arch/riscv/utility.hh
@@ -107,19 +107,6 @@
 return retPC;
 }

-inline uint64_t
-getArgument(ThreadContext *tc, int , uint16_t size, bool fp)
-{
-panic_if(fp, "getArgument(): Floating point arguments not  
implemented");
-panic_if(size != 8, "getArgument(): Can only handle 64-bit  
arguments.");

-panic_if(number >= ArgumentRegs.size(),
- "getArgument(): Don't know how to handle stack arguments");
-
-// The first 8 integer arguments are passed in registers, the rest
-// are passed on the stack.
-return tc->readIntReg(ArgumentRegs[number]);
-}
-
 inline void
 copyRegs(ThreadContext *src, ThreadContext *dest)
 {
diff --git a/src/arch/sparc/utility.cc b/src/arch/sparc/utility.cc
index 66fabd1..a0c0f8b 100644
--- a/src/arch/sparc/utility.cc
+++ b/src/arch/sparc/utility.cc
@@ -31,31 +31,8 @@
 #include "arch/sparc/faults.hh"
 #include "mem/port_proxy.hh"

-namespace SparcISA {
-
-
-// The caller uses %o0-%05 for the first 6 arguments even if their floating
-// point. Double precision floating point values take two registers/args.
-// Quads, structs, and unions are passed as pointers. All arguments beyond
-// the sixth are passed on the stack past the 16 word window save area,
-// space for the struct/union return pointer, and space reserved for the
-// first 6 arguments which the caller may use but doesn't have to.
-uint64_t
-getArgument(ThreadContext *tc, int , uint16_t size, bool fp)
+namespace SparcISA
 {
-panic_if(!FullSystem, "getArgument() only implemented for full  
system");

-
-const int NumArgumentRegs = 6;
-if (number < NumArgumentRegs) {
-return tc->readIntReg(8 + number);
-} else {
-Addr sp = tc->readIntReg(StackPointerReg);
-PortProxy  = tc->getVirtProxy();
-uint64_t arg = vp.read(sp + 92 +
-(number-NumArgumentRegs) * sizeof(uint64_t));
-return arg;
-}
-}

 void
 copyMiscRegs(ThreadContext *src, ThreadContext *dest)
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index 3f36f03..18b5164 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -50,8 +50,6 @@
 return ret;
 }

-uint64_t getArgument(ThreadContext *tc, int , uint16_t size, bool  
fp);

-
 static inline bool
 inUserMode(ThreadContext *tc)
 {
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index 7d891af..c664620 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -46,29 +46,8 @@
 #include "fputils/fp80.h"
 #include "sim/full_system.hh"

-namespace X86ISA {
-
-uint64_t
-getArgument(ThreadContext *tc, int , uint16_t size, bool fp)
+namespace X86ISA
 {
-if (fp) {
-panic("getArgument(): Floating point arguments not implemented\n");
-} else if (size != 8) {
-panic("getArgument(): Can only handle 64-bit arguments.\n");
-}
-
-// The first 6 integer arguments are passed in registers, the rest
-// are passed on the stack.
-const int int_reg_map[] = {
-INTREG_RDI, INTREG_RSI, INTREG_RDX,
-INTREG_RCX, INTREG_R8, INTREG_R9
-};
-if (number < sizeof(int_reg_map) / sizeof(*int_reg_map)) {
-return tc->readIntReg(int_reg_map[number]);
-} else {
-panic("getArgument(): Don't know how to handle stack  
arguments.\n");

-}
-}

 void
 copyMiscRegs(ThreadContext *src, ThreadContext *dest)
diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index 50f65ef..1ff7b16 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -53,9 +53,6 @@
 return retPC;
 }

-uint64_t
-getArgument(ThreadContext *tc, int , uint16_t size, bool fp);
-
 static inline bool
 inUserMode(ThreadContext *tc)
 {

--
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Gerrit-Project: public/gem5
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Gerrit-Change-Id: Ic6020c5fa6d976d9dbf1e9f517809acf9b0b7cd8
Gerrit-Change-Number: 39321
Gerrit-PatchSet: 5
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Boris Shingarov 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: arm,kern: Stop using the getArgument function for kernel events.

2021-02-19 Thread Gabe Black (Gerrit) via gem5-dev
 time in native size
-uint64_t time = TheISA::getArgument(tc, arg_num,  (uint16_t)-1, false);
-
 // convert parameter to ns
 if (div)
 time /= div;
diff --git a/src/kern/freebsd/events.hh b/src/kern/freebsd/events.hh
index 79894b6..ebf6128 100644
--- a/src/kern/freebsd/events.hh
+++ b/src/kern/freebsd/events.hh
@@ -34,18 +34,19 @@
 #define __KERN_FREEBSD_EVENTS_HH__

 #include "kern/system_events.hh"
+#include "sim/guest_abi.hh"

 namespace FreeBSD
 {

-void onUDelay(ThreadContext *tc, uint64_t div, uint64_t mul);
+void onUDelay(ThreadContext *tc, uint64_t div, uint64_t mul, uint64_t  
time);


 /** A class to skip udelay() and related calls in the kernel.
- * This class has two additional parameters that take the argument to  
udelay and

- * manipulated it to come up with ns and eventually ticks to quiesce for.
+ * This class has two additional parameters that take the argument to  
udelay
+ * and manipulated it to come up with ns and eventually ticks to quiesce  
for.

  * See descriptions of argDivToNs and argMultToNs below.
  */
-template 
+template 
 class SkipUDelay : public Base
 {
   private:
@@ -69,7 +70,13 @@
 void
 process(ThreadContext *tc) override
 {
-onUDelay(tc, argDivToNs, argMultToNs);
+// Use Addr since it's handled specially and will act as a natively
+// sized data type.
+std::function call_udelay =
+[this](ThreadContext *tc, Addr time) {
+onUDelay(tc, argDivToNs, argMultToNs, time);
+};
+invokeSimcall(tc, call_udelay);
 Base::process(tc);
 }
 };
diff --git a/src/kern/linux/events.cc b/src/kern/linux/events.cc
index db487e8..8ae76b3 100644
--- a/src/kern/linux/events.cc
+++ b/src/kern/linux/events.cc
@@ -78,13 +78,8 @@
 }

 void
-onUDelay(ThreadContext *tc, uint64_t div, uint64_t mul)
+onUDelay(ThreadContext *tc, uint64_t div, uint64_t mul, uint64_t time)
 {
-int arg_num = 0;
-
-// Get the time in native size
-uint64_t time = TheISA::getArgument(tc, arg_num, (uint16_t)-1, false);
-
 // convert parameter to ns
 if (div)
 time /= div;
diff --git a/src/kern/linux/events.hh b/src/kern/linux/events.hh
index 2ca97a4..8785345 100644
--- a/src/kern/linux/events.hh
+++ b/src/kern/linux/events.hh
@@ -56,7 +56,7 @@
 namespace Linux
 {

-template 
+template 
 class DebugPrintk : public Base
 {
   public:
@@ -71,7 +71,7 @@
 PrintkVarArgs args) -> int {
 return printk(str, tc, format_ptr, args);
 };
-invokeSimcall(tc, func);
+invokeSimcall(tc, func);
 DPRINTFN("%s", str);
 }
 Base::process(tc);
@@ -120,7 +120,7 @@
 void process(ThreadContext *tc) override;
 };

-void onUDelay(ThreadContext *tc, uint64_t div, uint64_t mul);
+void onUDelay(ThreadContext *tc, uint64_t div, uint64_t mul, uint64_t  
time);


 /**
  * A class to skip udelay() and related calls in the kernel.
@@ -128,7 +128,7 @@
  * and manipulated it to come up with ns and eventually ticks to quiesce  
for.

  * See descriptions of argDivToNs and argMultToNs below.
  */
-template 
+template 
 class SkipUDelay : public Base
 {
   private:
@@ -156,7 +156,13 @@
 void
 process(ThreadContext *tc) override
 {
-onUDelay(tc, argDivToNs, argMultToNs);
+// Use Addr since it's handled specially and will act as a natively
+// sized data type.
+std::function call_udelay =
+[this](ThreadContext *tc, Addr time) {
+onUDelay(tc, argDivToNs, argMultToNs, time);
+};
+invokeSimcall(tc, call_udelay);
 Base::process(tc);
 }
 };

--
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Gerrit-Change-Id: I0d394dcfd7ad6fa745b6ef2aa62973167108f0c3
Gerrit-Change-Number: 39320
Gerrit-PatchSet: 5
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
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Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Move getExecutingAsid to the ISA class.

2021-02-19 Thread Gabe Black (Gerrit) via gem5-dev
<<
+thread->getIsaPtr()->getExecutingAsid() << " ";
+}

 if (Debug::ExecThread)
 outs << "T" << thread->threadId() << " : ";



4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

--
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Gerrit-Change-Id: I70c274cb76fb229d0e2bc606ba41f458ed18ab81
Gerrit-Change-Number: 39322
Gerrit-PatchSet: 7
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[develop]: scons: Enable the clang++ and clang tools.

2021-02-19 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41673 )



Change subject: scons: Enable the clang++ and clang tools.
..

scons: Enable the clang++ and clang tools.

If these tools aren't enabled and CXX isn't set, scons will look for
generically named compiler aliases like cc and c++. These will generally
work, but if scons knows that the compiler is specifically clang, it
will set the CXXCONFIG variable we can use to do compiler version
checking.

Change-Id: Ie6bebb8eab531989575c878bee07189541756d2c
---
M SConstruct
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/SConstruct b/SConstruct
index cc3af90..150e068 100755
--- a/SConstruct
+++ b/SConstruct
@@ -135,7 +135,7 @@
 #
 

-main = Environment(tools=['default', 'git', TempFileSpawn])
+main = Environment(tools=['default', 'git',  
TempFileSpawn, 'clang', 'clang++'])


 from gem5_scons.util import get_termcap
 termcap = get_termcap()

--
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Gerrit-Branch: develop
Gerrit-Change-Id: Ie6bebb8eab531989575c878bee07189541756d2c
Gerrit-Change-Number: 41673
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: misc: Fix mismatched struct/class "tags" and reenable that warning.

2021-02-19 Thread Gabe Black (Gerrit) via gem5-dev
 RealView;

 class NoMaliGpu : public PioDevice
diff --git a/src/dev/arm/watchdog_generic.hh  
b/src/dev/arm/watchdog_generic.hh

index 24d3999..177df93 100644
--- a/src/dev/arm/watchdog_generic.hh
+++ b/src/dev/arm/watchdog_generic.hh
@@ -42,7 +42,7 @@
 #include "dev/io_device.hh"

 class ArmInterruptPin;
-class GenericWatchdogParams;
+struct GenericWatchdogParams;

 /**
  * @file
diff --git a/src/dev/arm/watchdog_sp805.hh b/src/dev/arm/watchdog_sp805.hh
index a64e4c9..5a6e962 100644
--- a/src/dev/arm/watchdog_sp805.hh
+++ b/src/dev/arm/watchdog_sp805.hh
@@ -40,7 +40,7 @@

 #include "dev/arm/amba_device.hh"

-class Sp805Params;
+struct Sp805Params;

 /**
  * @file
diff --git a/src/gpu-compute/scheduler.hh b/src/gpu-compute/scheduler.hh
index 1acf643..fbf7206 100644
--- a/src/gpu-compute/scheduler.hh
+++ b/src/gpu-compute/scheduler.hh
@@ -38,7 +38,7 @@

 #include "gpu-compute/scheduling_policy.hh"

-class ComputeUnitParams;
+struct ComputeUnitParams;

 class Scheduler
 {
diff --git a/src/mem/qos/mem_sink.hh b/src/mem/qos/mem_sink.hh
index 8a9708d..27eded5 100644
--- a/src/mem/qos/mem_sink.hh
+++ b/src/mem/qos/mem_sink.hh
@@ -46,7 +46,7 @@
 #include "mem/qport.hh"
 #include "params/QoSMemSinkCtrl.hh"

-class QoSMemSinkInterfaceParams;
+struct QoSMemSinkInterfaceParams;
 class QoSMemSinkInterface;

 namespace QoS {
diff --git a/src/mem/ruby/system/GPUCoalescer.hh  
b/src/mem/ruby/system/GPUCoalescer.hh

index 05d5269..01ad1d2 100644
--- a/src/mem/ruby/system/GPUCoalescer.hh
+++ b/src/mem/ruby/system/GPUCoalescer.hh
@@ -52,10 +52,10 @@

 class DataBlock;
 class CacheMsg;
-class MachineID;
+struct MachineID;
 class CacheMemory;

-class RubyGPUCoalescerParams;
+struct RubyGPUCoalescerParams;

 // List of packets that belongs to a specific instruction.
 typedef std::list PerInstPackets;
diff --git a/src/mem/ruby/system/VIPERCoalescer.hh  
b/src/mem/ruby/system/VIPERCoalescer.hh

index 213a675..40b32cc 100644
--- a/src/mem/ruby/system/VIPERCoalescer.hh
+++ b/src/mem/ruby/system/VIPERCoalescer.hh
@@ -46,10 +46,10 @@

 class DataBlock;
 class CacheMsg;
-class MachineID;
+struct MachineID;
 class CacheMemory;

-class VIPERCoalescerParams;
+struct VIPERCoalescerParams;

 class VIPERCoalescer : public GPUCoalescer
 {
diff --git a/src/sim/mem_state.hh b/src/sim/mem_state.hh
index c052389..d0fa9bd 100644
--- a/src/sim/mem_state.hh
+++ b/src/sim/mem_state.hh
@@ -42,7 +42,7 @@
 #include "sim/vma.hh"

 class Process;
-class ProcessParams;
+struct ProcessParams;
 class System;

 /**
diff --git a/src/sim/probe/probe.hh b/src/sim/probe/probe.hh
index 5becc26..eb0e445 100644
--- a/src/sim/probe/probe.hh
+++ b/src/sim/probe/probe.hh
@@ -69,7 +69,7 @@
 /** Forward declare the ProbeManager. */
 class ProbeManager;
 class ProbeListener;
-class ProbeListenerObjectParams;
+struct ProbeListenerObjectParams;

 /**
  * Name space containing shared probe point declarations.
diff --git a/src/sim/ticked_object.hh b/src/sim/ticked_object.hh
index 3991618..abfa801 100644
--- a/src/sim/ticked_object.hh
+++ b/src/sim/ticked_object.hh
@@ -48,7 +48,7 @@

 #include "sim/clocked_object.hh"

-class TickedObjectParams;
+struct TickedObjectParams;

 /** Ticked attaches gem5's event queue/scheduler to evaluate
  *  calls and provides a start/stop interface to ticking.

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Gerrit-Change-Number: 40953
Gerrit-PatchSet: 9
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
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[gem5-dev] Change in gem5/gem5[develop]: cpu,mem: Add or remove parenthesis to make the compiler happy.

2021-02-18 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40956 )


Change subject: cpu,mem: Add or remove parenthesis to make the compiler  
happy.

..

cpu,mem: Add or remove parenthesis to make the compiler happy.

Remove extraneous parenthesis in an if condition, and add some
parenthesis where an assignment was being used as a condition in a while
loop.

Change-Id: Ie12c74ac681ef042138e3b41f257ea1bb2ce4267
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40956
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/pred/tage_base.cc
2 files changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 8472597..0f8716b 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -773,12 +773,12 @@
 IssueStruct *i2e_info = issueToExecuteQueue->access(0);

 DynInstPtr mem_inst;
-while (mem_inst = std::move(getDeferredMemInstToExecute())) {
+while ((mem_inst = std::move(getDeferredMemInstToExecute( {
 addReadyMemInst(mem_inst);
 }

 // See if any cache blocked instructions are able to be executed
-while (mem_inst = std::move(getBlockedMemInstToExecute())) {
+while ((mem_inst = std::move(getBlockedMemInstToExecute( {
 addReadyMemInst(mem_inst);
 }

diff --git a/src/cpu/pred/tage_base.cc b/src/cpu/pred/tage_base.cc
index 108f6a2..791f5d4 100644
--- a/src/cpu/pred/tage_base.cc
+++ b/src/cpu/pred/tage_base.cc
@@ -467,7 +467,7 @@
 //Allocate entries
 unsigned numAllocated = 0;
 for (int i = X; i <= nHistoryTables; i++) {
-if ((gtable[i][bi->tableIndices[i]].u == 0)) {
+if (gtable[i][bi->tableIndices[i]].u == 0) {
 gtable[i][bi->tableIndices[i]].tag = bi->tableTags[i];
 gtable[i][bi->tableIndices[i]].ctr = (taken) ? 0 : -1;
 ++numAllocated;



7 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

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Gerrit-Change-Number: 40956
Gerrit-PatchSet: 10
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[develop]: base: Introduce a version of reverseBits for 8 bit types.

2021-02-18 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41593 )


Change subject: base: Introduce a version of reverseBits for 8 bit types.
..

base: Introduce a version of reverseBits for 8 bit types.

These types shouldn't be shifted by 8, since shifting a type by its
width is technically undefined behavior. We never actually use the
result from this shift, but it still upsets certain versions of clang.

Change-Id: I425431473fa44a6e0de2edf780c265ff4e3f440e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41593
Reviewed-by: Gabe Black 
Reviewed-by: Jason Lowe-Power 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/base/bitfield.hh
1 file changed, 9 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/bitfield.hh b/src/base/bitfield.hh
index 1ec684f..470941a 100644
--- a/src/base/bitfield.hh
+++ b/src/base/bitfield.hh
@@ -209,7 +209,7 @@
  * @ingroup api_bitfield
  */
 template 
-std::enable_if_t::value, T>
+std::enable_if_t::value && sizeof(T) != 1, T>
 reverseBits(T val, size_t size=sizeof(T))
 {
 assert(size <= sizeof(T));
@@ -223,6 +223,14 @@
 return output;
 }

+template 
+std::enable_if_t::value && sizeof(T) == 1, T>
+reverseBits(T val, size_t size=sizeof(T))
+{
+assert(size == 1);
+return reverseBitsLookUpTable[val];
+}
+
 /**
  * Returns the bit position of the MSB that is set in the input
  *

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Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
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[gem5-dev] Change in gem5/gem5[develop]: scons: Move imports below version checks in site_init.py.

2021-02-18 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40966 )


Change subject: scons: Move imports below version checks in site_init.py.
..

scons: Move imports below version checks in site_init.py.

Without knowing for sure we're using python 3, it's dangerous to start
pulling in code which may make that assumption.

Change-Id: Ic13af74a686ee0fb8f36bb672beadea4334b431c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40966
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Andreas Sandberg 
---
M site_scons/site_init.py
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/site_scons/site_init.py b/site_scons/site_init.py
index 2f7cbf1..3507373 100644
--- a/site_scons/site_init.py
+++ b/site_scons/site_init.py
@@ -39,7 +39,6 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 from __future__ import print_function
-from gem5_python_paths import extra_python_paths

 # Check for recent-enough Python and SCons versions.
 try:
@@ -85,4 +84,6 @@
 """)
 raise

+from gem5_python_paths import extra_python_paths
+
 sys.path[1:1] = extra_python_paths



7 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

--
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Gerrit-Change-Number: 40966
Gerrit-PatchSet: 9
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Use std::abs() in traffic_gen.cc.

2021-02-18 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41597 )


Change subject: cpu: Use std::abs() in traffic_gen.cc.
..

cpu: Use std::abs() in traffic_gen.cc.

When building with clang with the --without-tcmalloc flag set, the
-fno-builtin flag is not used, and clang can then detect that the
integer version of abs(), apparently the C version, is being used on a
floating point value in traffic_gen.cc.

This change takes clang's suggestion to use std::abs instead, and also
includes a header file which will provide it.

Change-Id: Ic28ed7454b2ac00c89328d9d0314aed74e946643
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41597
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/cpu/testers/traffic_gen/traffic_gen.cc
1 file changed, 3 insertions(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/testers/traffic_gen/traffic_gen.cc  
b/src/cpu/testers/traffic_gen/traffic_gen.cc

index 1ea4d5e..6e1a00a 100644
--- a/src/cpu/testers/traffic_gen/traffic_gen.cc
+++ b/src/cpu/testers/traffic_gen/traffic_gen.cc
@@ -39,6 +39,7 @@
 #include 
 #include 

+#include 
 #include 
 #include 

@@ -331,9 +332,10 @@
 }

 // avoid comparing floating point numbers
-if (abs(sum - 1.0) > 0.001)
+if (std::fabs(sum - 1.0) > 0.001) {
 fatal("%s has transition probability != 1 for state %d\n",
   name(), i);
+}
 }

 // close input file

--
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Gerrit-Change-Number: 41597
Gerrit-PatchSet: 4
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[develop]: scons,systemc: Drop the check for gcc version when building systemc.

2021-02-18 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41595 )


Change subject: scons,systemc: Drop the check for gcc version when building  
systemc.

..

scons,systemc: Drop the check for gcc version when building systemc.

The minimum version of gcc is 5, and the check would only fail if gcc
was older than that.

Change-Id: I20f4f42661baf415b7cbe80ec0ace4e427666348
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41595
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Andreas Sandberg 
---
M src/systemc/SConsopts
1 file changed, 1 insertion(+), 8 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/systemc/SConsopts b/src/systemc/SConsopts
index bd9f1da..26a15dd 100644
--- a/src/systemc/SConsopts
+++ b/src/systemc/SConsopts
@@ -25,17 +25,10 @@

 Import('*')

-from m5.util import compareVersions
-
 from gem5_scons import warning

 def use_systemc_check(env, warn=False):
-if ('GCC_VERSION' in env and
-compareVersions(env['GCC_VERSION'], '5.0') < 0):
-if warn:
-warning('Systemc may not work on gcc versions less than 5.0.')
-return False
-elif env['PLATFORM'] == 'darwin':
+if env['PLATFORM'] == 'darwin':
 if warn:
 warning('Warning: Systemc may not work on Mac OS.')
 return False



2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

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Gerrit-Change-Number: 41595
Gerrit-PatchSet: 4
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
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[gem5-dev] Change in gem5/gem5[develop]: sim: Simplify some code in the guest ABI mechanism.

2021-02-18 Thread Gabe Black (Gerrit) via gem5-dev
 return target(_tc, next, args...);
-};
-
-// Recursively handle any remaining arguments.
-return callFrom(tc, state, partial);
-}
-
-// Recursively gather arguments for target from tc until we get to the base
-// case above. This version is for functions that don't return anything.
-template 
-static void
-callFrom(ThreadContext *tc, typename ABI::State ,
-std::function target)
-{
-// Extract the next argument from the thread context.
-NextArg next = getArgument(tc, state);
-
-// Build a partial function which adds the next argument to the call.
-std::function partial =
-[target,next](ThreadContext *_tc, Args... args) {
-target(_tc, next, args...);
-};
-
-// Recursively handle any remaining arguments.
-callFrom(tc, state, partial);
-}
-
-

 /*
- * These functions are like the ones above, except they print the arguments
+ * This function is like the ones above, except it prints the arguments
  * a target function would be called with instead of actually calling it.
  */

-// With no arguments to print, add the closing parenthesis and return.
-template 
+template 
 static void
-dumpArgsFrom(int count, std::ostream , ThreadContext *tc,
- typename ABI::State )
+dumpArgsFrom(std::ostream , M5_VAR_USED ThreadContext *tc,
+typename ABI::State )
 {
+int count = 0;
+// Extract all the arguments from the thread context and print them,
+// prefixed with either a ( or a , as appropriate. Braced initializers
+// are evaluated from left to right.
+M5_VAR_USED int dummy[] = {
+(os << (count++ ? ", " : "(") <<
+getArgument(tc, state), 0)...};
+// Close off the parenthesis.
 os << ")";
 }

-// Recursively gather arguments for target from tc until we get to the base
-// case above, and append those arguments to the string stream being
-// constructed.
-template 
-static void
-dumpArgsFrom(int count, std::ostream , ThreadContext *tc,
- typename ABI::State )
-{
-// Either open the parenthesis or add a comma, depending on where we  
are

-// in the argument list.
-os << (count ? ", " : "(");
-
-// Extract the next argument from the thread context.
-NextArg next = getArgument(tc, state);
-
-// Add this argument to the list.
-os << next;
-
-// Recursively handle any remaining arguments.
-dumpArgsFrom(count + 1, os, tc, state);
-}
-
 } // namespace GuestABI

 #endif // __SIM_GUEST_ABI_DISPATCH_HH__
diff --git a/src/sim/guest_abi/layout.hh b/src/sim/guest_abi/layout.hh
index bb46d62..8145bf3 100644
--- a/src/sim/guest_abi/layout.hh
+++ b/src/sim/guest_abi/layout.hh
@@ -100,29 +100,22 @@
 };

 template 
-static void
+static inline void
 prepareForResult(ThreadContext *tc, typename ABI::State )
 {
 Preparer::prepare(tc, state);
 }

-template 
-static void
-prepareForArguments(ThreadContext *tc, typename ABI::State )
+template 
+static inline void
+prepareForArguments(M5_VAR_USED ThreadContext *tc, typename ABI::State  
)

 {
-return;
-}
-
-template 
-static void
-prepareForArguments(ThreadContext *tc, typename ABI::State )
-{
-Preparer::prepare(tc, state);
-prepareForArguments(tc, state);
+M5_VAR_USED int dummy[] = {
+(Preparer::prepare(tc, state), 0)...};
 }

 template 
-static void
+static inline void
 prepareForFunction(ThreadContext *tc, typename ABI::State )
 {
 prepareForResult(tc, state);
@@ -144,12 +137,6 @@
 }
 };

-template 
-std::true_type foo(void (*)(ThreadContext *, const Ret , State  
));

-
-template 
-std::false_type foo(void (*)(ThreadContext *, const Ret ));
-
 template 
 struct ResultStorer std::is_sameABI::State &),


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Gerrit-Change-Id: If7c9234cc1014101211474c2ec20362702cf78c2
Gerrit-Change-Number: 41600
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[gem5-dev] Change in gem5/gem5[develop]: python,scons: Move readCommand and compareVersions into site_scons.

2021-02-18 Thread Gabe Black (Gerrit) via gem5-dev
###
 # Code for adding source files of various types
diff --git a/src/proto/SConsopts b/src/proto/SConsopts
index a7cb86f..ea8b9bd 100644
--- a/src/proto/SConsopts
+++ b/src/proto/SConsopts
@@ -26,7 +26,7 @@
 Import('*')

 from gem5_scons import warning
-from m5.util import readCommand, compareVersions
+from gem5_scons.util import readCommand, compareVersions

 import gem5_scons

diff --git a/src/python/m5/util/__init__.py b/src/python/m5/util/__init__.py
index a0fe63d..3f9d76e 100644
--- a/src/python/m5/util/__init__.py
+++ b/src/python/m5/util/__init__.py
@@ -41,8 +41,6 @@
 import re
 import sys

-from itertools import zip_longest
-
 from . import convert
 from . import jobfile

@@ -112,31 +110,6 @@
 else:
 return [applyMethod(o, meth, *args, **kwargs) for o in objOrSeq]

-def compareVersions(v1, v2):
-"""helper function: compare arrays or strings of version numbers.
-E.g., compare_version((1,3,25), (1,4,1)')
-returns -1, 0, 1 if v1 is <, ==, > v2
-"""
-def make_version_list(v):
-if isinstance(v, (list,tuple)):
-return v
-elif isinstance(v, str):
-return list(map(lambda x: int(re.match('\d+', x).group()),
-v.split('.')))
-else:
-raise TypeError()
-
-v1 = make_version_list(v1)
-v2 = make_version_list(v2)
-
-# Compare corresponding elements of lists
-# The shorter list is filled with 0 till the lists have the same length
-for n1,n2 in zip_longest(v1, v2, fillvalue=0):
-if n1 < n2: return -1
-if n1 > n2: return  1
-
-return 0
-
 def crossproduct(items):
 if len(items) == 1:
 for i in items[0]:
@@ -173,38 +146,6 @@
 line += item
 print(line)

-def readCommand(cmd, **kwargs):
-"""
-run the command cmd, read the results and return them
-this is sorta like `cmd` in shell
-
-:param cmd: command to run with Popen
-:type cmd: string, list
-:returns: command stdout
-:rtype: string
-"""
-from subprocess import Popen, PIPE, STDOUT
-
-if isinstance(cmd, str):
-cmd = cmd.split()
-
-no_exception = 'exception' in kwargs
-exception = kwargs.pop('exception', None)
-
-kwargs.setdefault('shell', False)
-kwargs.setdefault('stdout', PIPE)
-kwargs.setdefault('stderr', STDOUT)
-kwargs.setdefault('close_fds', True)
-try:
-subp = Popen(cmd, **kwargs)
-except Exception as e:
-if no_exception:
-return -1, exception
-raise
-
-output = subp.communicate()[0].decode('utf-8')
-return output
-
 def makeDir(path):
 """Make a directory if it doesn't exist.  If the path does exist,
 ensure that it is a directory"""
diff --git a/src/systemc/dt/int/SConscript b/src/systemc/dt/int/SConscript
index b052f04..159eb6f 100644
--- a/src/systemc/dt/int/SConscript
+++ b/src/systemc/dt/int/SConscript
@@ -25,7 +25,7 @@

 Import('*')

-from m5.util import compareVersions
+from gem5_scons.util import compareVersions

 if env['USE_SYSTEMC']:
 if main['GCC'] and compareVersions(main['CXXVERSION'], '10.0') >= 0:

--
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[gem5-dev] Change in gem5/gem5[develop]: python: Collapse away the now unused readCommandWithReturn function.

2021-02-18 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41598 )



Change subject: python: Collapse away the now unused readCommandWithReturn  
function.

..

python: Collapse away the now unused readCommandWithReturn function.

This had been used when detecting python versions, but can now be
absorbed into readCommand.

Change-Id: I4385357c3ce33a0f1b58e741067aa7ae3a7daa3b
---
M src/python/m5/util/__init__.py
1 file changed, 4 insertions(+), 16 deletions(-)



diff --git a/src/python/m5/util/__init__.py b/src/python/m5/util/__init__.py
index 74c0ec0..a0fe63d 100644
--- a/src/python/m5/util/__init__.py
+++ b/src/python/m5/util/__init__.py
@@ -173,15 +173,15 @@
 line += item
 print(line)

-def readCommandWithReturn(cmd, **kwargs):
+def readCommand(cmd, **kwargs):
 """
 run the command cmd, read the results and return them
 this is sorta like `cmd` in shell

 :param cmd: command to run with Popen
 :type cmd: string, list
-:returns: pair consisting on Popen retcode and the command stdout
-:rtype: (int, string)
+:returns: command stdout
+:rtype: string
 """
 from subprocess import Popen, PIPE, STDOUT

@@ -203,19 +203,7 @@
 raise

 output = subp.communicate()[0].decode('utf-8')
-return subp.returncode, output
-
-def readCommand(cmd, **kwargs):
-"""
-run the command cmd, read the results and return them
-this is sorta like `cmd` in shell
-
-:param cmd: command to run with Popen
-:type cmd: string, list
-:returns: command stdout
-:rtype: string
-"""
-return readCommandWithReturn(cmd, **kwargs)[1]
+return output

 def makeDir(path):
 """Make a directory if it doesn't exist.  If the path does exist,

--
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Use std::abs() in traffic_gen.cc.

2021-02-18 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41597 )



Change subject: cpu: Use std::abs() in traffic_gen.cc.
..

cpu: Use std::abs() in traffic_gen.cc.

When building with clang with the --without-tcmalloc flag set, the
-fno-builtin flag is not used, and clang can then detect that the
integer version of abs(), apparently the C version, is being used on a
floating point value in traffic_gen.cc.

This change takes clang's suggestion to use std::abs instead, and also
includes a header file which will provide it.

Change-Id: Ic28ed7454b2ac00c89328d9d0314aed74e946643
---
M src/cpu/testers/traffic_gen/traffic_gen.cc
1 file changed, 3 insertions(+), 1 deletion(-)



diff --git a/src/cpu/testers/traffic_gen/traffic_gen.cc  
b/src/cpu/testers/traffic_gen/traffic_gen.cc

index 1ea4d5e..97b6e65 100644
--- a/src/cpu/testers/traffic_gen/traffic_gen.cc
+++ b/src/cpu/testers/traffic_gen/traffic_gen.cc
@@ -39,6 +39,7 @@
 #include 
 #include 

+#include 
 #include 
 #include 

@@ -331,9 +332,10 @@
 }

 // avoid comparing floating point numbers
-if (abs(sum - 1.0) > 0.001)
+if (std::abs(sum - 1.0) > 0.001) {
 fatal("%s has transition probability != 1 for state %d\n",
   name(), i);
+}
 }

 // close input file

--
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[gem5-dev] Change in gem5/gem5[develop]: scons,systemc: Drop the check for gcc version when building systemc.

2021-02-18 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41595 )



Change subject: scons,systemc: Drop the check for gcc version when building  
systemc.

..

scons,systemc: Drop the check for gcc version when building systemc.

The minimum version of gcc is 5, and the check would only fail if gcc
was older than that.

Change-Id: I20f4f42661baf415b7cbe80ec0ace4e427666348
---
M src/systemc/SConsopts
1 file changed, 1 insertion(+), 6 deletions(-)



diff --git a/src/systemc/SConsopts b/src/systemc/SConsopts
index 13636cd..4864944 100644
--- a/src/systemc/SConsopts
+++ b/src/systemc/SConsopts
@@ -30,12 +30,7 @@
 from gem5_scons import warning

 def use_systemc_check(env, warn=False):
-if ('GCC_VERSION' in env and
-compareVersions(env['GCC_VERSION'], '5.0') < 0):
-if warn:
-warning('Systemc may not work on gcc versions less than 5.0.')
-return False
-elif env['PLATFORM'] == 'darwin':
+if env['PLATFORM'] == 'darwin':
 if warn:
 warning('Warning: Systemc may not work on Mac OS.')
 return False

--
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[gem5-dev] Change in gem5/gem5[develop]: scons: Use SCons' built in CXXVERSION instead of detecting our own.

2021-02-18 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41596 )



Change subject: scons: Use SCons' built in CXXVERSION instead of detecting  
our own.

..

scons: Use SCons' built in CXXVERSION instead of detecting our own.

It's not guaranteed that every compiler will set CXXVERSION, but both
gcc and clang do, and for any check of CXXVERSION to be meaningful, we
have to first check which compiler we're talking about.

Change-Id: Icd15e12832920fec6fa8634bc0fde16cc48e3f41
---
M SConstruct
M src/systemc/dt/int/SConscript
2 files changed, 5 insertions(+), 9 deletions(-)



diff --git a/SConstruct b/SConstruct
index 4752d9e..f2fbafb 100755
--- a/SConstruct
+++ b/SConstruct
@@ -345,12 +345,9 @@
   "src/SConscript to support that compiler.")))

 if main['GCC']:
-gcc_version = readCommand([main['CXX'], '-dumpversion'],  
exception=False)

-if compareVersions(gcc_version, "5") < 0:
+if compareVersions(main['CXXVERSION'], "5") < 0:
 error('gcc version 5 or newer required.\n'
-  'Installed version:', gcc_version)
-
-main['GCC_VERSION'] = gcc_version
+  'Installed version:', main['CXXVERSION'])

 # If not disabled, set the Link-Time Optimization (LTO) flags.
 if not GetOption('no_lto'):
@@ -362,10 +359,9 @@
   '-fno-builtin-realloc', '-fno-builtin-free'])

 elif main['CLANG']:
-clang_version = readCommand([main['CXX'], '-dumpversion'],  
exception=False)

-if compareVersions(clang_version, "3.9") < 0:
+if compareVersions(main['CXXVERSION'], "3.9") < 0:
 error('clang version 3.9 or newer required.\n'
-  'Installed version:', clang_version)
+  'Installed version:', main['CXXVERSION'])

 # If not disabled, set the Link-Time Optimization (LTO) flags.
 if not GetOption('no_lto'):
diff --git a/src/systemc/dt/int/SConscript b/src/systemc/dt/int/SConscript
index 92c0f07..b052f04 100644
--- a/src/systemc/dt/int/SConscript
+++ b/src/systemc/dt/int/SConscript
@@ -28,7 +28,7 @@
 from m5.util import compareVersions

 if env['USE_SYSTEMC']:
-if main['GCC'] and compareVersions(main['GCC_VERSION'], '10.0') >= 0:
+if main['GCC'] and compareVersions(main['CXXVERSION'], '10.0') >= 0:
 disable_false_positives = {
 "CCFLAGS": [ "-Wno-array-bounds",
  "-Wno-stringop-overflow" ]

--
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[gem5-dev] Change in gem5/gem5[develop]: scons: Introduce a version of reverseBits for 8 bit types.

2021-02-17 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41593 )



Change subject: scons: Introduce a version of reverseBits for 8 bit types.
..

scons: Introduce a version of reverseBits for 8 bit types.

These types shouldn't be shifted by 8, since shifting a type by its
width is technically undefined behavior. We never actually use the
result from this shift, but it still upsets certain versions of clang.

Change-Id: I425431473fa44a6e0de2edf780c265ff4e3f440e
---
M src/base/bitfield.hh
1 file changed, 9 insertions(+), 1 deletion(-)



diff --git a/src/base/bitfield.hh b/src/base/bitfield.hh
index 1ec684f..470941a 100644
--- a/src/base/bitfield.hh
+++ b/src/base/bitfield.hh
@@ -209,7 +209,7 @@
  * @ingroup api_bitfield
  */
 template 
-std::enable_if_t::value, T>
+std::enable_if_t::value && sizeof(T) != 1, T>
 reverseBits(T val, size_t size=sizeof(T))
 {
 assert(size <= sizeof(T));
@@ -223,6 +223,14 @@
 return output;
 }

+template 
+std::enable_if_t::value && sizeof(T) == 1, T>
+reverseBits(T val, size_t size=sizeof(T))
+{
+assert(size == 1);
+return reverseBitsLookUpTable[val];
+}
+
 /**
  * Returns the bit position of the MSB that is set in the input
  *

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[gem5-dev] Change in gem5/gem5[develop]: scons: Enable LTO for opt, perf and prof builds.

2021-02-17 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40815 )


Change subject: scons: Enable LTO for opt, perf and prof builds.
..

scons: Enable LTO for opt, perf and prof builds.

The name of the build is opt, so it should be fully optomized. Also, the
fast build, the only one with LTO historically, is dangerous to use
since it disables many error checks. I personally run gem5 many times
while developing, iterating and trying to fix bugs, and so want it to
run quickly then too, not just the final time when collecting results.

Also, since they mirror the opt build, the perf and prof builds also
have LTO options added.

This has the nice side effect of speeding up the build time of build/X86
significantly (6:20 -> 4:27) due to parallelization of the link, and
reduces the size of the build/X86 directory (with debug compression
enabled) from 3.4GB to 2.8GB.

The size of build/X86/python/_m5 is still 1.6GB, so still more than half
of the total size of build/X86.

Change-Id: I8feabf99454693fdd100d9e1a64fdeae53362f75
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40815
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
Reviewed-by: Earl Ou 
---
M SConstruct
M src/SConscript
2 files changed, 3 insertions(+), 7 deletions(-)

Approvals:
  Earl Ou: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index e9dfae5..e1814c3 100755
--- a/SConstruct
+++ b/SConstruct
@@ -358,8 +358,7 @@
 main['GCC_VERSION'] = gcc_version

 # Add the appropriate Link-Time Optimization (LTO) flags
-# unless LTO is explicitly turned off. Note that these flags
-# are only used by the fast target.
+# unless LTO is explicitly turned off.
 if not GetOption('no_lto'):
 # Pass the LTO flag when compiling to produce GIMPLE
 # output, we merely create the flags here and only append
diff --git a/src/SConscript b/src/SConscript
index aeb7038..5fe0ab2 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -1341,11 +1341,8 @@
 # the optimization to the ldflags as LTO defers the optimization
 # to link time
 for target in ['opt', 'fast', 'prof', 'perf']:
-ccflags[target] += ['-O3']
-ldflags[target] += ['-O3']
-
-ccflags['fast'] += env['LTO_CCFLAGS']
-ldflags['fast'] += env['LTO_LDFLAGS']
+ccflags[target] += ['-O3'] + env['LTO_CCFLAGS']
+ldflags[target] += ['-O3'] + env['LTO_LDFLAGS']
 elif env['CLANG']:
 ccflags['debug'] += ['-g', '-O0']
 # opt, fast, prof and perf all share the same cc flags

--
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Gerrit-Change-Id: I8feabf99454693fdd100d9e1a64fdeae53362f75
Gerrit-Change-Number: 40815
Gerrit-PatchSet: 10
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Andreas Sandberg 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base: Add some operators to the BitUnion types.

2021-02-17 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41515 )


Change subject: base: Add some operators to the BitUnion types.
..

base: Add some operators to the BitUnion types.

The operators it seems to need are ones which modify the BitUnion being
operated on, vs ones which just use it to produce a new value. The later
kind can be handled by converting the BitUnion into its underlying type
and then applying the built in operators.

Change-Id: I8aa08bf74d8ad88f4dfbb0031610c52ad412d03b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41515
Reviewed-by: Gabe Black 
Reviewed-by: Daniel Carvalho 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/base/bitunion.hh
1 file changed, 102 insertions(+), 11 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/bitunion.hh b/src/base/bitunion.hh
index aef6f6e..3b6ca16 100644
--- a/src/base/bitunion.hh
+++ b/src/base/bitunion.hh
@@ -260,35 +260,126 @@

 BitUnionOperators() {}

+//Conversion operators.
 operator const typename Base::__StorageType () const
 {
 return Base::__storage;
 }

-typename Base::__StorageType
+//Basic assignment operators.
+BitUnionOperators &
 operator=(typename Base::__StorageType const )
 {
 Base::__storage = val;
-return val;
+return *this;
 }

-typename Base::__StorageType
+BitUnionOperators &
 operator=(BitUnionOperators const )
 {
-Base::__storage = other;
-return Base::__storage;
+return operator=(other.__storage);
 }

-bool
-operator<(Base const ) const
+//Increment and decrement operators.
+BitUnionOperators &
+operator++()
 {
-return Base::__storage < base.__storage;
+Base::__storage++;
+return *this;
 }

-bool
-operator==(Base const ) const
+BitUnionOperators
+operator++(int)
 {
-return Base::__storage == base.__storage;
+BitUnionOperators ret = *this;
+operator++();
+return ret;
+}
+
+BitUnionOperators &
+operator--()
+{
+Base::__storage--;
+return *this;
+}
+
+BitUnionOperators
+operator--(int)
+{
+BitUnionOperators ret = *this;
+operator--();
+return ret;
+}
+
+//Operation and assignment operators
+BitUnionOperators &
+operator+=(typename Base::__StorageType const )
+{
+Base::__storage += val;
+return *this;
+}
+
+BitUnionOperators &
+operator-=(typename Base::__StorageType const )
+{
+Base::__storage -= val;
+return *this;
+}
+
+BitUnionOperators &
+operator*=(typename Base::__StorageType const )
+{
+Base::__storage *= val;
+return *this;
+}
+
+BitUnionOperators &
+operator/=(typename Base::__StorageType const )
+{
+Base::__storage /= val;
+return *this;
+}
+
+BitUnionOperators &
+operator%=(typename Base::__StorageType const )
+{
+Base::__storage %= val;
+return *this;
+}
+
+BitUnionOperators &
+operator&=(typename Base::__StorageType const )
+{
+Base::__storage &= val;
+return *this;
+}
+
+BitUnionOperators &
+operator|=(typename Base::__StorageType const )
+{
+Base::__storage |= val;
+return *this;
+}
+
+BitUnionOperators &
+operator^=(typename Base::__StorageType const )
+{
+Base::__storage ^= val;
+return *this;
+}
+
+BitUnionOperators &
+operator<<=(typename Base::__StorageType const )
+{
+Base::__storage <<= val;
+return *this;
+}
+
+BitUnionOperators &
+operator>>=(typename Base::__StorageType const )
+{
+Base::__storage >>= val;
+return *this;
 }
 };
 }

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[gem5-dev] Change in gem5/gem5[develop]: base: Clean up style in bitfield.(hh|cc|test.cc).

2021-02-17 Thread Gabe Black (Gerrit) via gem5-dev
13,7 +345,8 @@
  *
  * @ingroup api_bitfield
  */
-inline uint64_t alignToPowerOfTwo(uint64_t val)
+constexpr inline uint64_t
+alignToPowerOfTwo(uint64_t val)
 {
 val--;
 val |= val >> 1;
@@ -335,7 +368,8 @@
  *
  * @ingroup api_bitfield
  */
-inline int ctz32(uint32_t value)
+constexpr inline int
+ctz32(uint32_t value)
 {
 return value ? __builtin_ctzl(value) : 32;
 }
@@ -348,7 +382,8 @@
  *
  * @ingroup api_bitfield
  */
-inline int ctz64(uint64_t value)
+constexpr inline int
+ctz64(uint64_t value)
 {
 return value ? __builtin_ctzll(value) : 64;
 }
diff --git a/src/base/bitfield.test.cc b/src/base/bitfield.test.cc
index 3d07e69..51c316e 100644
--- a/src/base/bitfield.test.cc
+++ b/src/base/bitfield.test.cc
@@ -87,22 +87,22 @@
  */
 TEST(BitfieldTest, MaskOneBit)
 {
-EXPECT_EQ(1, mask(0,0));
+EXPECT_EQ(1, mask(0, 0));
 }

 TEST(BitfieldTest, MaskTwoBits)
 {
-EXPECT_EQ((1 << 1) + 1, mask(1,0));
+EXPECT_EQ((1 << 1) + 1, mask(1, 0));
 }

 TEST(BitfieldTest, MaskThreeBits)
 {
-EXPECT_EQ((1 << 5) + (1 << 4) + (1 << 3), mask(5,3));
+EXPECT_EQ((1 << 5) + (1 << 4) + (1 << 3), mask(5, 3));
 }

 TEST(BitfieldTest, MaskEntireRange)
 {
-EXPECT_EQ(0x, mask(63,0));
+EXPECT_EQ(0xFFFF, mask(63, 0));
 }

 TEST(BitfieldTest, MaskOutsideOfRange)

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Gerrit-Change-Id: Ic98a8ff451ca13f0872411ba5b8b27fc42de8093
Gerrit-Change-Number: 41434
Gerrit-PatchSet: 5
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Matt Sinclair 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: util: Delete the build_cross_gcc utility.

2021-02-17 Thread Gabe Black (Gerrit) via gem5-dev
  print('Don\'t know what to do with "{:s}"'.format(steps))
-
-def print_settings():
-print()
-print('Settings:')
-for setting in all_settings.values():
-print('{}{} = {}'.format(
-' ' if setting.valid else 'X', setting.key, setting.value))
-
-def save_settings():
-settings = {}
-for setting in all_settings.values():
-if setting.valid:
-settings[setting.key] = setting.get()
-with open(SETTINGS_FILE, 'wb') as settings_file:
-pickle.dump(settings, settings_file)
-
-def load_settings():
-if os.path.exists(SETTINGS_FILE):
-with open(SETTINGS_FILE, 'rb') as settings_file:
-settings = pickle.load(settings_file)
-else:
-settings = {}
-
-for setting in all_settings.values():
-if setting.key in settings:
-setting.set(settings[setting.key])
-
-def load_settings_file(path):
-with open(path, 'r') as settings:
-for line in settings.readlines():
-if not line:
-continue
-try:
-key, val = line.split('=')
-except:
-print('Malformated line "{}" in settings  
file "{}".'.format(

-line, path))
-return False
-key = key.strip()
-val = val.strip()
-if key not in all_settings:
-print('Unknown setting "{}" found in settings '
-  'file "{}".'.format(key, path))
-return False
-setting = all_settings[key]
-if not setting.set(val):
-print('Failed to set "{}" to "{}" from '
-  'settings file "{}".'.format(key, val, path))
-return False
-return True
-
-
-
-argparser.add_argument('--settings-file',
-help='A file with name=value settings to load.')
-
-def main():
-# Install command line options for each setting.
-for setting in all_settings.values():
-setting.add_to_argparser(argparser)
-
-args = argparser.parse_args()
-
-# Load settings from the last time we ran. Lowest priority.
-load_settings()
-
-# If requested, read in a settings file. Medium priority.
-if args.settings_file:
-if not load_settings_file(args.settings_file):
-return
-
-# Set settings based on command line options. Highest priority.
-for setting in all_settings.values():
-setting.set_from_args(args)
-
-# If a setting is still not valid, try setting it to its default.
-for setting in all_settings.values():
-if not setting.valid:
-setting.set_default()
-
-# Print out the resulting settings.
-print_settings()
-
-while True:
-steps = get_steps()
-if not steps:
-return
-for step in steps:
-print()
-print('Step {:d}: {:s}'.format(step.number, step.describe()))
-print()
-if not step.run():
-print()
-print('Step failed, aborting.')
-break
-
-if __name__ == "__main__":
-main()
diff --git a/util/build_cross_gcc/settings.aarch64  
b/util/build_cross_gcc/settings.aarch64

deleted file mode 100644
index d2b21f6..000
--- a/util/build_cross_gcc/settings.aarch64
+++ /dev/null
@@ -1,2 +0,0 @@
-TARGET=aarch64-linux-gnu
-LINUX_ARCH=arm64
diff --git a/util/build_cross_gcc/settings.arm  
b/util/build_cross_gcc/settings.arm

deleted file mode 100644
index 7f3eff3..000
--- a/util/build_cross_gcc/settings.arm
+++ /dev/null
@@ -1,2 +0,0 @@
-TARGET=arm-linux-gnueabihf
-LINUX_ARCH=arm
diff --git a/util/build_cross_gcc/settings.mips  
b/util/build_cross_gcc/settings.mips

deleted file mode 100644
index c29e4ad..000
--- a/util/build_cross_gcc/settings.mips
+++ /dev/null
@@ -1,2 +0,0 @@
-TARGET=mipsel-linux-gnu
-LINUX_ARCH=mips
diff --git a/util/build_cross_gcc/settings.power  
b/util/build_cross_gcc/settings.power

deleted file mode 100644
index 998a2bc..000
--- a/util/build_cross_gcc/settings.power
+++ /dev/null
@@ -1,2 +0,0 @@
-TARGET=powerpc-linux-gnu
-LINUX_ARCH=powerpc
diff --git a/util/build_cross_gcc/settings.riscv  
b/util/build_cross_gcc/settings.riscv

deleted file mode 100644
index d1910e8..000
--- a/util/build_cross_gcc/settings.riscv
+++ /dev/null
@@ -1,2 +0,0 @@
-TARGET=riscv64-linux-gnu
-LINUX_ARCH=riscv
diff --git a/util/build_cross_gcc/settings.sparc  
b/util/build_cross_gcc/settings.sparc

deleted file mode 100644
index cc96530..000
--- a/util/build_cross_gcc/settings.sparc
+++ /dev/null
@@ -1,2 +0,0 @@
-TARGET=sparc64-linux-gnu
-LINUX_ARCH=sparc

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Gerrit-Change

[gem5-dev] Change in gem5/gem5[develop]: util: Add a crosstool-ng defconfig for RISCV.

2021-02-17 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41453 )


Change subject: util: Add a crosstool-ng defconfig for RISCV.
..

util: Add a crosstool-ng defconfig for RISCV.

This may have been available before as well, but it was hidden behind an
"experimental" flag which needed to be enabled before riscv was
selectable.

Change-Id: I76239d826163e54d0b8a48c3492930bb787bea02
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41453
Tested-by: kokoro 
Maintainer: Gabe Black 
Maintainer: Bobby R. Bruce 
Reviewed-by: Bobby R. Bruce 
---
A util/crosstool-ng/riscv-linux-gnu.defconfig
1 file changed, 12 insertions(+), 0 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/crosstool-ng/riscv-linux-gnu.defconfig  
b/util/crosstool-ng/riscv-linux-gnu.defconfig

new file mode 100644
index 000..f458630
--- /dev/null
+++ b/util/crosstool-ng/riscv-linux-gnu.defconfig
@@ -0,0 +1,12 @@
+CT_CONFIG_VERSION="3"
+CT_EXPERIMENTAL=y
+CT_ARCH_RISCV=y
+CT_OMIT_TARGET_VENDOR=y
+CT_ARCH_USE_MMU=y
+CT_ARCH_64=y
+CT_KERNEL_LINUX=y
+CT_BINUTILS_PLUGINS=y
+CT_CC_LANG_CXX=y
+CT_DEBUG_GDB=y
+# CT_GDB_CROSS_PYTHON is not set
+# CT_GDB_GDBSERVER is not set

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I76239d826163e54d0b8a48c3492930bb787bea02
Gerrit-Change-Number: 41453
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Boris Shingarov 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Work around very long command lines and arg size limits.

2021-02-17 Thread Gabe Black (Gerrit) via gem5-dev
  return wrapper(old_pspawn, sh, esc, cmd, args, sh_env, stdout,  
stderr)

+def new_spawn(sh, esc, cmd, args, sh_env):
+return wrapper(old_spawn, sh, esc, cmd, args, sh_env)
+
+scons_env['PSPAWN'] = new_pspawn
+scons_env['SPAWN'] = new_spawn
+
 # Generate a string of the form:
 #   common/path/prefix/src1, src2 -> tgt1, tgt2
 # to print while building.

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Gerrit-Branch: develop
Gerrit-Change-Id: I0a5288aed745a432ed72ffd990ceded2b9422585
Gerrit-Change-Number: 41273
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Jui-min Lee 
Gerrit-CC: Yu-hsin Wang 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base: Add some operators to the BitUnion types.

2021-02-16 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41515 )



Change subject: base: Add some operators to the BitUnion types.
..

base: Add some operators to the BitUnion types.

The operators it seems to need are ones which modify the BitUnion being
operated on, vs ones which just use it to produce a new value. The later
kind can be handled by converting the BitUnion into its underlying type
and then applying the built in operators.

Change-Id: I8aa08bf74d8ad88f4dfbb0031610c52ad412d03b
---
M src/base/bitunion.hh
1 file changed, 102 insertions(+), 11 deletions(-)



diff --git a/src/base/bitunion.hh b/src/base/bitunion.hh
index aef6f6e..feb94b0 100644
--- a/src/base/bitunion.hh
+++ b/src/base/bitunion.hh
@@ -260,35 +260,126 @@

 BitUnionOperators() {}

+//Conversion operators.
 operator const typename Base::__StorageType () const
 {
 return Base::__storage;
 }

-typename Base::__StorageType
+//Basic assignment operators.
+BitUnionOperators &
 operator=(typename Base::__StorageType const )
 {
 Base::__storage = val;
-return val;
+return *this;
 }

-typename Base::__StorageType
+BitUnionOperators &
 operator=(BitUnionOperators const )
 {
-Base::__storage = other;
-return Base::__storage;
+return operator=(other.__storage);
 }

-bool
-operator<(Base const ) const
+//Increment and decrement operators.
+BitUnionOperators &
+operator++()
 {
-return Base::__storage < base.__storage;
+Base::__storage++;
+return *this;
 }

-bool
-operator==(Base const ) const
+BitUnionOperators
+operator++(int)
 {
-return Base::__storage == base.__storage;
+BitUnionOperators ret = *this;
+operator++();
+return ret;
+}
+
+BitUnionOperators &
+operator--()
+{
+Base::__storage--;
+return *this;
+}
+
+BitUnionOperators
+operator--(int)
+{
+BitUnionOperators ret = *this;
+operator--;
+return ret;
+}
+
+//Operation and assignment operators
+BitUnionOperators &
+operator+=(typename Base::__StorageType const )
+{
+Base::__storage += val;
+return *this;
+}
+
+BitUnionOperators &
+operator-=(typename Base::__StorageType const )
+{
+Base::__storage -= val;
+return *this;
+}
+
+BitUnionOperators &
+operator*=(typename Base::__StorageType const )
+{
+Base::__storage *= val;
+return *this;
+}
+
+BitUnionOperators &
+operator/=(typename Base::__StorageType const )
+{
+Base::__storage /= val;
+return *this;
+}
+
+BitUnionOperators &
+operator%=(typename Base::__StorageType const )
+{
+Base::__storage %= val;
+return *this;
+}
+
+BitUnionOperators &
+operator&=(typename Base::__StorageType const )
+{
+Base::__storage &= val;
+return *this;
+}
+
+BitUnionOperators &
+operator|=(typename Base::__StorageType const )
+{
+Base::__storage |= val;
+return *this;
+}
+
+BitUnionOperators &
+operator^=(typename Base::__StorageType const )
+{
+Base::__storage ^= val;
+return *this;
+}
+
+BitUnionOperators &
+operator<<=(typename Base::__StorageType const )
+{
+Base::__storage <<= val;
+return *this;
+}
+
+BitUnionOperators &
+operator>>=(typename Base::__StorageType const )
+{
+Base::__storage >>= val;
+return *this;
 }
 };
 }

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Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: util: Delete the ccdrv kernel module.

2021-02-16 Thread Gabe Black (Gerrit) via gem5-dev
XXX and count=X
-
-will read a long at addr dataAddr count times and return.
-
-Between runs you need to rmmod the module from the kernel.
-
-



The change was submitted with unreviewed changes in the following files:

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Gerrit-Change-Id: I3b1f44d718d7e6ee23695e3117bb169268f2157a
Gerrit-Change-Number: 41473
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
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Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: util: Delete the very obsolete "compile" script.

2021-02-16 Thread Gabe Black (Gerrit) via gem5-dev
path(m5_base, version)
-if not isdir(m5_dir):
-sys.exit('source directory %s not found' % m5_dir)
-
-# support M5 1.x
-oldstyle = isfile(joinpath(m5_dir, 'SConscript'))
-if oldstyle:
-ext_dir = joinpath(m5_base, 'ext')
-test_dir = joinpath(m5_base, 'test.' + version)
-
-if not isdir(ext_dir):
-sys.exit('ext directory not found at %s' % ext_dir)
-
-if not isdir(test_dir):
-sys.exit('test directory not found at %s' % test_dir)
-
-build_dir = joinpath(build_base, version)
-if not isdir(build_dir):
-os.mkdir(build_dir)
-# need some symlinks for m5 1.x
-if oldstyle:
-os.symlink(m5_dir, joinpath(build_dir, 'm5'))
-os.symlink(ext_dir, joinpath(build_dir, 'ext'))
-os.symlink(test_dir, joinpath(build_dir, 'test'))
-os.symlink(joinpath(m5_dir, 'build', 'SConstruct'),
-   joinpath(build_dir, 'SConstruct'))
-os.symlink(joinpath(m5_dir, 'build', 'default_options'),
-   joinpath(build_dir, 'default_options'))
-
-sys.argv = [ progname ]
-if oldstyle:
-os.chdir(build_dir)
-sys.argv.extend(args)
-else:
-os.chdir(m5_dir)
-for arg in args:
-if not arg.startswith('-') and '=' not in arg:
-arg = joinpath(build_dir, 'build', arg)
-sys.argv.append(arg)
-
-if options.no_compile or options.verbose:
-for arg in sys.argv[1:]:
-print arg
-
-if not options.no_compile:
-do_compile()



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Gerrit-Change-Number: 41455
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Gabe Black 
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[gem5-dev] Change in gem5/gem5[develop]: util: Delete the ccdrv kernel module.

2021-02-16 Thread Gabe Black (Gerrit) via gem5-dev
-#ifdef __alpha__
-static int memTest = 0;
-#endif
-
-static inline uint32_t cycleCounter(uint32_t dep);
-
-static int __init devtime_start(void)
-{
-uint64_t addr;
-uint32_t t1, t2;
-uint32_t trash;
-int x;
-uint32_t *times;
-uint32_t num = 0;
-struct net_device *dev;
-
-printk("Devtime Driver Version %s Loaded...\n", DRIVER_VER);
-
-#ifdef __alpha__
-if (memTest) {
-   addr = 0xfc00;
-// addr += 16*1024*1024;
-
-printk("Preparing memory test.\n");
-
-t1 = cycleCounter(trash);
-for (x = 0; x < count; x++) {
-trash = readl(addr);
-t2 = cycleCounter(trash);
-times[num++] = t2 - t1;
-t1 = t2;
-   addr += 4096;
-}
-
-printk("Measurements:\n");
-for (x = 0; x < count; x++) {
-printk("%d ", times[x]);
-if (((x + 1) % 10) == 0)
-printk("\n");
-}
-printk("\nDone.\n");
-} else
-#endif
-if (dataAddr != 0 && count != 0) {
-addr = simple_strtoull(dataAddr, NULL, 0);
-
-addr = ioremap(addr, PAGE_SIZE);
-/**
- * Make sure that the remapping actually worked. On alpha we have
- * linear addressing, so its not a problem. But it can fail in x86
- * if physical memory is mapped to this address.
- */
-times = kmalloc(sizeof(uint32_t) * count, GFP_USER);
-if (!times) {
-printk("Could not allocate memory... Try again later.\n");
-return -1;
-}
-
-if (addr) {
-printk("Preparing to read %#llx %d times.\n", addr, count);
-
-t1 = cycleCounter(trash);
-for (x = 0; x < count; x++) {
-trash = readl(addr);
-t2 = cycleCounter(trash);
-times[num++] = t2 - t1;
-t1 = t2;
-}
-
-/**
- * Unmap the address.
- */
-iounmap(addr);
-
-printk("Measurements:\n");
-for (x = 0; x < count; x++) {
-printk("%d ", times[x]);
-if (((x + 1) % 10) == 0)
-printk("\n");
-}
-printk("\nDone.\n");
-} else {
-printk("Unable to remap address. Please try again later.\n");
-}
-} else {
-dev = dev_get_by_name("eth0");
-if (dev) {
-printk("Eth0: MemStart: %#lx MemEnd: %#lx I/O Addr: %#lx\n",
-   dev->mem_start, dev->mem_end, dev->base_addr);
-dev_put(dev);
-}
-dev = 0;
-dev = dev_get_by_name("eth1");
-if (dev) {
-printk("Eth1: MemStart: %#lx MemEnd: %#lx I/O Addr: %#lx\n",
-   dev->mem_start, dev->mem_end, dev->base_addr);
-dev_put(dev);
-}
-
-printk("Required information not supplied.\n");
-}
-
-return 0;
-}
-
-#ifdef __i386__
-
-static inline uint32_t cycleCounter(uint32_t dep)
-{
-uint32_t time;
-cpuid_eax(0);
-rdtscl(time);
-cpuid_eax(0);
-return time;
-}
-
-#elif __alpha__
-
-inline uint32_t cycleCounter(uint32_t dep)
-{
-uint32_t res;
-asm volatile ("rpcc %0, %1" : "=r"(res) : "r" (dep) : "memory");
-return res;
-}
-#else
-#error Architecture NOT SUPPORTED
-#endif
-
-static void __exit devtime_end(void)
-{
-printk("Devtime Driver Version %s Unloaded...\n", DRIVER_VER);
-}
-
-
-module_init(devtime_start);
-module_exit(devtime_end);
-
-MODULE_LICENSE("Dual BSD/GPL");
-MODULE_AUTHOR(DRIVER_AUTHOR);
-MODULE_DESCRIPTION(DRIVER_DESC);
-module_param(dataAddr, charp, 0);
-module_param(count, int, 0);
-#ifdef __alpha__
-module_param(memTest, int, 0);
-#endif
diff --git a/util/ccdrv/readme.txt b/util/ccdrv/readme.txt
deleted file mode 100644
index 4b9892f..000
--- a/util/ccdrv/readme.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-This driver will read the address you point it to [count] times and
-print the results to the systemlog.
-
-To build the driver (Linux 2.6.X only) execute:
-make -C /path/to/linux-2.6.X/ SUBDIRS=$PWD modules
-
-
-Insmodding the kernel module without options will print
-the device addresses of eth0 and eth1 if they exist.
-
-Insmodding the kernel module with the options:
-dataAddr=0xX and count=X
-
-will read a long at addr dataAddr count times and return.
-
-Between runs you need to rmmod the module from the kernel.
-
-

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[gem5-dev] Change in gem5/gem5[develop]: util: Delete the build_cross_gcc utility.

2021-02-16 Thread Gabe Black (Gerrit) via gem5-dev
id:
-settings[setting.key] = setting.get()
-with open(SETTINGS_FILE, 'wb') as settings_file:
-pickle.dump(settings, settings_file)
-
-def load_settings():
-if os.path.exists(SETTINGS_FILE):
-with open(SETTINGS_FILE, 'rb') as settings_file:
-settings = pickle.load(settings_file)
-else:
-settings = {}
-
-for setting in all_settings.values():
-if setting.key in settings:
-setting.set(settings[setting.key])
-
-def load_settings_file(path):
-with open(path, 'r') as settings:
-for line in settings.readlines():
-if not line:
-continue
-try:
-key, val = line.split('=')
-except:
-print('Malformated line "{}" in settings  
file "{}".'.format(

-line, path))
-return False
-key = key.strip()
-val = val.strip()
-if key not in all_settings:
-print('Unknown setting "{}" found in settings '
-  'file "{}".'.format(key, path))
-return False
-setting = all_settings[key]
-if not setting.set(val):
-print('Failed to set "{}" to "{}" from '
-  'settings file "{}".'.format(key, val, path))
-return False
-return True
-
-
-
-argparser.add_argument('--settings-file',
-help='A file with name=value settings to load.')
-
-def main():
-# Install command line options for each setting.
-for setting in all_settings.values():
-setting.add_to_argparser(argparser)
-
-args = argparser.parse_args()
-
-# Load settings from the last time we ran. Lowest priority.
-load_settings()
-
-# If requested, read in a settings file. Medium priority.
-if args.settings_file:
-if not load_settings_file(args.settings_file):
-return
-
-# Set settings based on command line options. Highest priority.
-for setting in all_settings.values():
-setting.set_from_args(args)
-
-# If a setting is still not valid, try setting it to its default.
-for setting in all_settings.values():
-if not setting.valid:
-setting.set_default()
-
-# Print out the resulting settings.
-print_settings()
-
-while True:
-steps = get_steps()
-if not steps:
-return
-for step in steps:
-print()
-print('Step {:d}: {:s}'.format(step.number, step.describe()))
-print()
-if not step.run():
-print()
-print('Step failed, aborting.')
-break
-
-if __name__ == "__main__":
-main()
diff --git a/util/build_cross_gcc/settings.aarch64  
b/util/build_cross_gcc/settings.aarch64

deleted file mode 100644
index d2b21f6..000
--- a/util/build_cross_gcc/settings.aarch64
+++ /dev/null
@@ -1,2 +0,0 @@
-TARGET=aarch64-linux-gnu
-LINUX_ARCH=arm64
diff --git a/util/build_cross_gcc/settings.arm  
b/util/build_cross_gcc/settings.arm

deleted file mode 100644
index 7f3eff3..000
--- a/util/build_cross_gcc/settings.arm
+++ /dev/null
@@ -1,2 +0,0 @@
-TARGET=arm-linux-gnueabihf
-LINUX_ARCH=arm
diff --git a/util/build_cross_gcc/settings.mips  
b/util/build_cross_gcc/settings.mips

deleted file mode 100644
index c29e4ad..000
--- a/util/build_cross_gcc/settings.mips
+++ /dev/null
@@ -1,2 +0,0 @@
-TARGET=mipsel-linux-gnu
-LINUX_ARCH=mips
diff --git a/util/build_cross_gcc/settings.power  
b/util/build_cross_gcc/settings.power

deleted file mode 100644
index 998a2bc..000
--- a/util/build_cross_gcc/settings.power
+++ /dev/null
@@ -1,2 +0,0 @@
-TARGET=powerpc-linux-gnu
-LINUX_ARCH=powerpc
diff --git a/util/build_cross_gcc/settings.riscv  
b/util/build_cross_gcc/settings.riscv

deleted file mode 100644
index d1910e8..000
--- a/util/build_cross_gcc/settings.riscv
+++ /dev/null
@@ -1,2 +0,0 @@
-TARGET=riscv64-linux-gnu
-LINUX_ARCH=riscv
diff --git a/util/build_cross_gcc/settings.sparc  
b/util/build_cross_gcc/settings.sparc

deleted file mode 100644
index cc96530..000
--- a/util/build_cross_gcc/settings.sparc
+++ /dev/null
@@ -1,2 +0,0 @@
-TARGET=sparc64-linux-gnu
-LINUX_ARCH=sparc

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[gem5-dev] Change in gem5/gem5[develop]: util: Add a crosstool-ng defconfig for RISCV.

2021-02-16 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41453 )



Change subject: util: Add a crosstool-ng defconfig for RISCV.
..

util: Add a crosstool-ng defconfig for RISCV.

This may have been available before as well, but it was hidden behind an
"experimental" flag which needed to be enabled before riscv was
selectable.

Change-Id: I76239d826163e54d0b8a48c3492930bb787bea02
---
A util/crosstool-ng/riscv-linux-gnu.defconfig
1 file changed, 12 insertions(+), 0 deletions(-)



diff --git a/util/crosstool-ng/riscv-linux-gnu.defconfig  
b/util/crosstool-ng/riscv-linux-gnu.defconfig

new file mode 100644
index 000..f458630
--- /dev/null
+++ b/util/crosstool-ng/riscv-linux-gnu.defconfig
@@ -0,0 +1,12 @@
+CT_CONFIG_VERSION="3"
+CT_EXPERIMENTAL=y
+CT_ARCH_RISCV=y
+CT_OMIT_TARGET_VENDOR=y
+CT_ARCH_USE_MMU=y
+CT_ARCH_64=y
+CT_KERNEL_LINUX=y
+CT_BINUTILS_PLUGINS=y
+CT_CC_LANG_CXX=y
+CT_DEBUG_GDB=y
+# CT_GDB_CROSS_PYTHON is not set
+# CT_GDB_GDBSERVER is not set

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Gerrit-Branch: develop
Gerrit-Change-Id: I76239d826163e54d0b8a48c3492930bb787bea02
Gerrit-Change-Number: 41453
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: util: Delete the very obsolete "compile" script.

2021-02-16 Thread Gabe Black (Gerrit) via gem5-dev
est.' + version)
-
-if not isdir(ext_dir):
-sys.exit('ext directory not found at %s' % ext_dir)
-
-if not isdir(test_dir):
-sys.exit('test directory not found at %s' % test_dir)
-
-build_dir = joinpath(build_base, version)
-if not isdir(build_dir):
-os.mkdir(build_dir)
-# need some symlinks for m5 1.x
-if oldstyle:
-os.symlink(m5_dir, joinpath(build_dir, 'm5'))
-os.symlink(ext_dir, joinpath(build_dir, 'ext'))
-os.symlink(test_dir, joinpath(build_dir, 'test'))
-os.symlink(joinpath(m5_dir, 'build', 'SConstruct'),
-   joinpath(build_dir, 'SConstruct'))
-os.symlink(joinpath(m5_dir, 'build', 'default_options'),
-   joinpath(build_dir, 'default_options'))
-
-sys.argv = [ progname ]
-if oldstyle:
-os.chdir(build_dir)
-sys.argv.extend(args)
-else:
-os.chdir(m5_dir)
-for arg in args:
-if not arg.startswith('-') and '=' not in arg:
-arg = joinpath(build_dir, 'build', arg)
-sys.argv.append(arg)
-
-if options.no_compile or options.verbose:
-for arg in sys.argv[1:]:
-print arg
-
-if not options.no_compile:
-do_compile()

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Gerrit-Change-Id: I0e9fefaa5b3c2d092f70ad01b904eb7e64e5361e
Gerrit-Change-Number: 41455
Gerrit-PatchSet: 1
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[gem5-dev] Change in gem5/gem5[develop]: base: Clean up style in bitfield.(hh|cc|test.cc).

2021-02-15 Thread Gabe Black (Gerrit) via gem5-dev
__builtin_ctzll(value) : 64;
 }
diff --git a/src/base/bitfield.test.cc b/src/base/bitfield.test.cc
index 3d07e69..51c316e 100644
--- a/src/base/bitfield.test.cc
+++ b/src/base/bitfield.test.cc
@@ -87,22 +87,22 @@
  */
 TEST(BitfieldTest, MaskOneBit)
 {
-EXPECT_EQ(1, mask(0,0));
+EXPECT_EQ(1, mask(0, 0));
 }

 TEST(BitfieldTest, MaskTwoBits)
 {
-EXPECT_EQ((1 << 1) + 1, mask(1,0));
+EXPECT_EQ((1 << 1) + 1, mask(1, 0));
 }

 TEST(BitfieldTest, MaskThreeBits)
 {
-EXPECT_EQ((1 << 5) + (1 << 4) + (1 << 3), mask(5,3));
+EXPECT_EQ((1 << 5) + (1 << 4) + (1 << 3), mask(5, 3));
 }

 TEST(BitfieldTest, MaskEntireRange)
 {
-EXPECT_EQ(0x, mask(63,0));
+EXPECT_EQ(0xFFFF, mask(63, 0));
 }

 TEST(BitfieldTest, MaskOutsideOfRange)

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Gerrit-Change-Number: 41434
Gerrit-PatchSet: 1
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[gem5-dev] Change in gem5/gem5[develop]: base: Minor optimization in the bits() function.

2021-02-15 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41433 )



Change subject: base: Minor optimization in the bits() function.
..

base: Minor optimization in the bits() function.

This small optimization masks off the bits above the range of interest
and then shifts, where the old code shifted and then masked. The
difference is that in the new version, the size of the mask only depends
on the "first" bit index, not the difference between it and "last".

To ensure the shifting doesn't bring in any sign bits or right shift a
signed value which is undefined behvior, this change also converts "val"
into a uint64_t before operating on it.

Change-Id: Idb38a82702a57586253fd611312bd4c72f2f726a
---
M src/base/bitfield.hh
1 file changed, 3 insertions(+), 2 deletions(-)



diff --git a/src/base/bitfield.hh b/src/base/bitfield.hh
index 98a93d4..e7ed229 100644
--- a/src/base/bitfield.hh
+++ b/src/base/bitfield.hh
@@ -74,9 +74,10 @@
 T
 bits(T val, int first, int last)
 {
-int nbits = first - last + 1;
 assert((first - last) >= 0);
-return (val >> last) & mask(nbits);
+uint64_t u_val = val;
+u_val &= mask(first + 1);
+return u_val >> last;
 }

 /**

--
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Gerrit-Branch: develop
Gerrit-Change-Id: Idb38a82702a57586253fd611312bd4c72f2f726a
Gerrit-Change-Number: 41433
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
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[gem5-dev] Change in gem5/gem5[develop]: arch: Get rid of global maximums for numbers of source/dest/misc regs.

2021-02-15 Thread Gabe Black (Gerrit) via gem5-dev
gisters.hh
@@ -31,18 +31,11 @@

 #include "arch/generic/vec_pred_reg.hh"
 #include "arch/generic/vec_reg.hh"
-#include "arch/power/generated/max_inst_regs.hh"
 #include "arch/power/miscregs.hh"
 #include "base/types.hh"

-namespace PowerISA {
-
-using PowerISAInst::MaxInstSrcRegs;
-using PowerISAInst::MaxInstDestRegs;
-
-// Power writes a misc register outside of the isa parser, so it can't
-// be detected by it. Manually add it here.
-const int MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1;
+namespace PowerISA
+{

 // Not applicable to Power
 using VecElem = ::DummyVecElem;
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index 9721635..692f73d 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -52,15 +52,11 @@
 #include "arch/generic/types.hh"
 #include "arch/generic/vec_pred_reg.hh"
 #include "arch/generic/vec_reg.hh"
-#include "arch/riscv/generated/max_inst_regs.hh"
 #include "base/bitunion.hh"
 #include "base/types.hh"

-namespace RiscvISA {
-
-using RiscvISAInst::MaxInstSrcRegs;
-using RiscvISAInst::MaxInstDestRegs;
-const int MaxMiscDestRegs = 2;
+namespace RiscvISA
+{

 // Not applicable to RISC-V
 using VecElem = ::DummyVecElem;
diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index 6fd6577..0602176 100644
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -31,7 +31,6 @@

 #include "arch/generic/vec_pred_reg.hh"
 #include "arch/generic/vec_reg.hh"
-#include "arch/sparc/generated/max_inst_regs.hh"
 #include "arch/sparc/miscregs.hh"
 #include "arch/sparc/sparc_traits.hh"
 #include "base/types.hh"
@@ -39,10 +38,6 @@
 namespace SparcISA
 {

-using SparcISAInst::MaxInstSrcRegs;
-using SparcISAInst::MaxInstDestRegs;
-using SparcISAInst::MaxMiscDestRegs;
-
 // Not applicable to SPARC
 using VecElem = ::DummyVecElem;
 using VecReg = ::DummyVecReg;
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index fdd6d6b..a29f1b8 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -41,7 +41,6 @@

 #include "arch/generic/vec_pred_reg.hh"
 #include "arch/generic/vec_reg.hh"
-#include "arch/x86/generated/max_inst_regs.hh"
 #include "arch/x86/regs/int.hh"
 #include "arch/x86/regs/ccr.hh"
 #include "arch/x86/regs/misc.hh"
@@ -49,9 +48,7 @@

 namespace X86ISA
 {
-using X86ISAInst::MaxInstSrcRegs;
-using X86ISAInst::MaxInstDestRegs;
-using X86ISAInst::MaxMiscDestRegs;
+
 const int NumMiscRegs = NUM_MISCREGS;

 const int NumIntArchRegs = NUM_INTREGS;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6881572daedf0f0e9ff6aee4f174671d02ef743d
Gerrit-Change-Number: 38389
Gerrit-PatchSet: 9
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Boris Shingarov 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Work around a scons bug when calling TryCompile.

2021-02-13 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41213 )


Change subject: scons: Work around a scons bug when calling TryCompile.
..

scons: Work around a scons bug when calling TryCompile.

When calling TryCompile with an empty string for the source, useful
when just testing a build flag, some versions of SCons will apparently
create some sort of equivalence between Value('') and Value(0). That
shows itself when creating config file headers, where Value(0) is
switched with Value(''), and the header defines a macro with which
expands to nothing rather than a macro which expands to 0. Later uses
of the macro of the form:

 #if CONFIG_VARIABLE

fail because CONFIG_VARIABLE expands to nothing. If it expanded to 0
like it's supposed to, then the guarded block of code would be excluded
correctly.

Change-Id: Ie324ec5f8dd307c65745b9326a11230e10caa0bd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41213
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
Reviewed-by: Gabe Black 
---
M site_scons/gem5_scons/configure.py
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Gabe Black: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/site_scons/gem5_scons/configure.py  
b/site_scons/gem5_scons/configure.py

index 7bf97b2..35aa1a9 100644
--- a/site_scons/gem5_scons/configure.py
+++ b/site_scons/gem5_scons/configure.py
@@ -47,7 +47,7 @@
 context.Message("Checking for compiler %s support... " % flag)
 last_cxxflags = context.env['CXXFLAGS']
 context.env.Append(CXXFLAGS=[flag])
-ret = context.TryCompile('', '.cc')
+ret = context.TryCompile('// CheckCxxFlag DO NOTHING', '.cc')
 if not (ret and autoadd):
 context.env['CXXFLAGS'] = last_cxxflags
 context.Result(ret)

--
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Gerrit-Change-Id: Ie324ec5f8dd307c65745b9326a11230e10caa0bd
Gerrit-Change-Number: 41213
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Use popCount from bitfields.hh.

2021-02-13 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41354 )


Change subject: arch-x86: Use popCount from bitfields.hh.
..

arch-x86: Use popCount from bitfields.hh.

Use popCount from bitfields.hh rather than call __builtin_popcountl
directly. That will ensure the instruction works whether or not that
builtin is available.

Change-Id: I947b35bb832b768936b489a58ee324adb8a90b5e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41354
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/x86/isa/microops/regop.isa
1 file changed, 1 insertion(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/x86/isa/microops/regop.isa  
b/src/arch/x86/isa/microops/regop.isa

index 570c084..63a1683 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -1766,10 +1766,7 @@
 '''

 class Popcnt(RegOp):
-code = '''
-DestReg =
-merge(DestReg, __builtin_popcountl(psrc1), dataSize);
-'''
+code = 'DestReg = merge(DestReg, popCount(psrc1), dataSize);'
 flag_code = '''
 ccFlagBits = ccFlagBits & ~(SFBit | AFBit | ZFBit | PFBit);
 if (findZero(dataSize * 8, SrcReg1)) {

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I947b35bb832b768936b489a58ee324adb8a90b5e
Gerrit-Change-Number: 41354
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch: Stop including unnecessary FP headers.

2021-02-13 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41353 )


Change subject: arch: Stop including unnecessary FP headers.
..

arch: Stop including unnecessary FP headers.

Nothing is used from them. They're probably there as copy/paste from
other ISAs, or old code that's been replaced. This also gets rid of some
 #if guarded includes which is a nice cleanup.

Change-Id: Icd84300fb7531ec203ce4acbdae1d311e56cc873
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41353
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/mips/isa/includes.isa
M src/arch/power/isa/includes.isa
M src/arch/x86/isa/includes.isa
3 files changed, 9 insertions(+), 32 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index 34922e4..d17bcf6 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -41,6 +41,7 @@
 #include "arch/mips/pra_constants.hh"
 #include "cpu/static_inst.hh"
 #include "mem/packet.hh"
+
 }};

 output decoder {{
@@ -56,14 +57,11 @@
 #include "arch/mips/pra_constants.hh"
 #include "arch/mips/tlb.hh"
 #include "arch/mips/utility.hh"
-#include "base/loader/symtab.hh"
 #include "base/cprintf.hh"
+#include "base/loader/symtab.hh"
 #include "cpu/thread_context.hh"
 #include "mem/packet.hh"
 #include "sim/full_system.hh"
-#if defined(linux)
-#include 
-#endif

 using namespace MipsISA;
 }};
@@ -83,10 +81,6 @@
 #include "arch/mips/pra_constants.hh"
 #include "arch/mips/tlb.hh"
 #include "arch/mips/utility.hh"
-#if defined(linux)
-#include 
-#endif
-
 #include "base/condcodes.hh"
 #include "cpu/base.hh"
 #include "cpu/exetrace.hh"
diff --git a/src/arch/power/isa/includes.isa  
b/src/arch/power/isa/includes.isa

index ac7756c..c97aba9 100644
--- a/src/arch/power/isa/includes.isa
+++ b/src/arch/power/isa/includes.isa
@@ -52,9 +52,6 @@

 output decoder {{
 #include 
-#if defined(linux)
-#include 
-#endif

 #include "arch/power/decoder.hh"
 #include "arch/power/faults.hh"
@@ -69,9 +66,6 @@

 output exec {{
 #include 
-#if defined(linux)
-#include 
-#endif

 #include "arch/generic/memhelpers.hh"
 #include "arch/power/faults.hh"
diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index 3bd7872..27ef988 100644
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -53,13 +53,13 @@
 #include 

 #include "arch/generic/debugfaults.hh"
+#include "arch/x86/emulenv.hh"
 #include "arch/x86/insts/macroop.hh"
 #include "arch/x86/insts/microfpop.hh"
 #include "arch/x86/insts/microldstop.hh"
 #include "arch/x86/insts/micromediaop.hh"
 #include "arch/x86/insts/microregop.hh"
 #include "arch/x86/insts/static_inst.hh"
-#include "arch/x86/emulenv.hh"
 #include "arch/x86/isa_traits.hh"
 #include "arch/x86/registers.hh"
 #include "arch/x86/types.hh"
@@ -73,46 +73,35 @@
 }};

 output decoder {{
+#include 
+
 #include "arch/x86/decoder.hh"
+#include "arch/x86/faults.hh"
+#include "arch/x86/microcode_rom.hh"
 #include "arch/x86/regs/float.hh"
 #include "arch/x86/regs/misc.hh"
 #include "arch/x86/regs/segment.hh"
-#include "arch/x86/faults.hh"
-#include "arch/x86/microcode_rom.hh"
 #include "arch/x86/tlb.hh"
-#include "base/loader/symtab.hh"
 #include "base/cprintf.hh"
+#include "base/loader/symtab.hh"
 #include "base/logging.hh"
 #include "cpu/thread_context.hh"  // for Jump::branchTarget()
 #include "mem/packet.hh"
 #include "sim/full_system.hh"

-#if defined(linux) || defined(__APPLE__)
-#include 
-#endif
-#include 
-
 using namespace X86ISA;
 }};

 output exec {{
-#if defined(linux) || defined(__APPLE__)
-#include 
-#endif
-
-#if defined(__sun) || defined (__OpenBSD__)
-#include 
-#endif
-
 #include 
 #include 

 #include "arch/generic/debugfaults.hh"
-#include "arch/x86/regs/misc.hh"
 #include "arch/x86/cpuid.hh"
 #include "arch/x86/faults.hh"
 #include "arch/x86/memhelpers.hh"
 #include "arch/x86/pseudo_inst_abi.hh"
+#include "arch/x86/regs/misc.hh"
 #include "arch/x86/tlb.hh"
 #include "base/compiler.hh"
 #include "base/condcodes.hh"

--
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[gem5-dev] Change in gem5/gem5[develop]: arch: Stop including unnecessary FP headers.

2021-02-12 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41353 )



Change subject: arch: Stop including unnecessary FP headers.
..

arch: Stop including unnecessary FP headers.

Nothing is used from them. They're probably there as copy/paste from
other ISAs, or old code that's been replaced. This also gets rid of some
 #if guarded includes which is a nice cleanup.

Change-Id: Icd84300fb7531ec203ce4acbdae1d311e56cc873
---
M src/arch/mips/isa/includes.isa
M src/arch/power/isa/includes.isa
M src/arch/x86/isa/includes.isa
3 files changed, 9 insertions(+), 32 deletions(-)



diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index 34922e4..d17bcf6 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -41,6 +41,7 @@
 #include "arch/mips/pra_constants.hh"
 #include "cpu/static_inst.hh"
 #include "mem/packet.hh"
+
 }};

 output decoder {{
@@ -56,14 +57,11 @@
 #include "arch/mips/pra_constants.hh"
 #include "arch/mips/tlb.hh"
 #include "arch/mips/utility.hh"
-#include "base/loader/symtab.hh"
 #include "base/cprintf.hh"
+#include "base/loader/symtab.hh"
 #include "cpu/thread_context.hh"
 #include "mem/packet.hh"
 #include "sim/full_system.hh"
-#if defined(linux)
-#include 
-#endif

 using namespace MipsISA;
 }};
@@ -83,10 +81,6 @@
 #include "arch/mips/pra_constants.hh"
 #include "arch/mips/tlb.hh"
 #include "arch/mips/utility.hh"
-#if defined(linux)
-#include 
-#endif
-
 #include "base/condcodes.hh"
 #include "cpu/base.hh"
 #include "cpu/exetrace.hh"
diff --git a/src/arch/power/isa/includes.isa  
b/src/arch/power/isa/includes.isa

index ac7756c..c97aba9 100644
--- a/src/arch/power/isa/includes.isa
+++ b/src/arch/power/isa/includes.isa
@@ -52,9 +52,6 @@

 output decoder {{
 #include 
-#if defined(linux)
-#include 
-#endif

 #include "arch/power/decoder.hh"
 #include "arch/power/faults.hh"
@@ -69,9 +66,6 @@

 output exec {{
 #include 
-#if defined(linux)
-#include 
-#endif

 #include "arch/generic/memhelpers.hh"
 #include "arch/power/faults.hh"
diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index 3bd7872..27ef988 100644
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -53,13 +53,13 @@
 #include 

 #include "arch/generic/debugfaults.hh"
+#include "arch/x86/emulenv.hh"
 #include "arch/x86/insts/macroop.hh"
 #include "arch/x86/insts/microfpop.hh"
 #include "arch/x86/insts/microldstop.hh"
 #include "arch/x86/insts/micromediaop.hh"
 #include "arch/x86/insts/microregop.hh"
 #include "arch/x86/insts/static_inst.hh"
-#include "arch/x86/emulenv.hh"
 #include "arch/x86/isa_traits.hh"
 #include "arch/x86/registers.hh"
 #include "arch/x86/types.hh"
@@ -73,46 +73,35 @@
 }};

 output decoder {{
+#include 
+
 #include "arch/x86/decoder.hh"
+#include "arch/x86/faults.hh"
+#include "arch/x86/microcode_rom.hh"
 #include "arch/x86/regs/float.hh"
 #include "arch/x86/regs/misc.hh"
 #include "arch/x86/regs/segment.hh"
-#include "arch/x86/faults.hh"
-#include "arch/x86/microcode_rom.hh"
 #include "arch/x86/tlb.hh"
-#include "base/loader/symtab.hh"
 #include "base/cprintf.hh"
+#include "base/loader/symtab.hh"
 #include "base/logging.hh"
 #include "cpu/thread_context.hh"  // for Jump::branchTarget()
 #include "mem/packet.hh"
 #include "sim/full_system.hh"

-#if defined(linux) || defined(__APPLE__)
-#include 
-#endif
-#include 
-
 using namespace X86ISA;
 }};

 output exec {{
-#if defined(linux) || defined(__APPLE__)
-#include 
-#endif
-
-#if defined(__sun) || defined (__OpenBSD__)
-#include 
-#endif
-
 #include 
 #include 

 #include "arch/generic/debugfaults.hh"
-#include "arch/x86/regs/misc.hh"
 #include "arch/x86/cpuid.hh"
 #include "arch/x86/faults.hh"
 #include "arch/x86/memhelpers.hh"
 #include "arch/x86/pseudo_inst_abi.hh"
+#include "arch/x86/regs/misc.hh"
 #include "arch/x86/tlb.hh"
 #include "base/compiler.hh"
 #include "base/condcodes.hh"

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Gerrit-Change-Id: Icd84300fb7531ec203ce4acbdae1d311e56cc873
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Use popCount from bitfields.hh.

2021-02-12 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41354 )



Change subject: arch-x86: Use popCount from bitfields.hh.
..

arch-x86: Use popCount from bitfields.hh.

Use popCount from bitfields.hh rather than call __builtin_popcountl
directly. That will ensure the instruction works whether or not that
builtin is available.

Change-Id: I947b35bb832b768936b489a58ee324adb8a90b5e
---
M src/arch/x86/isa/microops/regop.isa
1 file changed, 1 insertion(+), 4 deletions(-)



diff --git a/src/arch/x86/isa/microops/regop.isa  
b/src/arch/x86/isa/microops/regop.isa

index 570c084..63a1683 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -1766,10 +1766,7 @@
 '''

 class Popcnt(RegOp):
-code = '''
-DestReg =
-merge(DestReg, __builtin_popcountl(psrc1), dataSize);
-'''
+code = 'DestReg = merge(DestReg, popCount(psrc1), dataSize);'
 flag_code = '''
 ccFlagBits = ccFlagBits & ~(SFBit | AFBit | ZFBit | PFBit);
 if (findZero(dataSize * 8, SrcReg1)) {

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[gem5-dev] Change in gem5/gem5[develop]: scons: Work around very long command lines and arg size limits.

2021-02-12 Thread Gabe Black (Gerrit) via gem5-dev
'SPAWN'] = new_spawn
+
 # Generate a string of the form:
 #   common/path/prefix/src1, src2 -> tgt1, tgt2
 # to print while building.

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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Use src/base/fenv.hh instead of raw fenv.h.

2021-02-11 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41214 )



Change subject: arch-arm: Use src/base/fenv.hh instead of raw fenv.h.
..

arch-arm: Use src/base/fenv.hh instead of raw fenv.h.

This provides a layer of indirection where the rounding mode
setting/getting code will do nothing if fenv.h isn't available. At build
time, if fenv.h can't be found, a warning is printed.

Also, the include for fenv.h was guarded in the includes in the ISA
header, but the functions from it weren't guarded in the actual code.

Finally, the code was setting the rounding mode, but not setting it
back. That would mean running these instructions would set the rounding
mode in gem5 as a whole, affecting its other behaviors and any other
instructions that might expect the default rounding mode.

Change-Id: Ic5cc32773652f423e66d78f31b80c6604f2c4a49
---
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa/insts/fp.isa
2 files changed, 14 insertions(+), 11 deletions(-)



diff --git a/src/arch/arm/isa/includes.isa b/src/arch/arm/isa/includes.isa
index 6af382a..7d9a3f0 100644
--- a/src/arch/arm/isa/includes.isa
+++ b/src/arch/arm/isa/includes.isa
@@ -111,17 +111,12 @@
 #include "arch/generic/memhelpers.hh"
 #include "base/condcodes.hh"
 #include "base/crc.hh"
+#include "base/fenv.hh"
 #include "cpu/base.hh"
-#include "sim/pseudo_inst.hh"
-
-#if defined(linux)
-#include 
-
-#endif
-
 #include "debug/Arm.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
+#include "sim/pseudo_inst.hh"
 #include "sim/sim_exit.hh"

 using namespace ArmISA;
diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa
index 7f530c2..99040b0 100644
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@@ -1106,11 +1106,13 @@
 FPSCR fpscr = (FPSCR) FpscrExc;
 vfpFlushToZero(fpscr, FpOp1);
 VfpSavedState state = prepFpState(fpscr.rMode);
-fesetround(FeRoundZero);
+Gem5::RoundingMode old_rm = Gem5::getFpRound();
+Gem5::setFpRound(Gem5::RoundingMode::TowardZero);
 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
 FpDest_uw = vfpFpToFixed(
 FpOp1, false, 32, 0, true, {round_mode});
 __asm__ __volatile__("" :: "m" (FpDest_uw));
+Gem5::setFpRound(old_rm);
 finishVfp(fpscr, state, fpscr.fz);
 FpscrExc = fpscr;
 '''
@@ -1122,11 +1124,13 @@
 double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw);
 vfpFlushToZero(fpscr, cOp1);
 VfpSavedState state = prepFpState(fpscr.rMode);
-fesetround(FeRoundZero);
+Gem5::RoundingMode old_rm = Gem5::getFpRound();
+Gem5::setFpRound(Gem5::RoundingMode::TowardZero);
 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
 uint64_t result = vfpFpToFixed(
 cOp1, false, 32, 0, true, {round_mode});
 __asm__ __volatile__("" :: "m" (result));
+Gem5::setFpRound(old_rm);
 finishVfp(fpscr, state, fpscr.fz);
 FpDestP0_uw = result;
 FpscrExc = fpscr;
@@ -1138,11 +1142,13 @@
 FPSCR fpscr = (FPSCR) FpscrExc;
 vfpFlushToZero(fpscr, FpOp1);
 VfpSavedState state = prepFpState(fpscr.rMode);
-fesetround(FeRoundZero);
+Gem5::RoundingMode old_rm = Gem5::getFpRound();
+Gem5::setFpRound(Gem5::RoundingMode::TowardZero);
 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
 FpDest_sw = vfpFpToFixed(
 FpOp1, true, 32, 0, true, {round_mode});
 __asm__ __volatile__("" :: "m" (FpDest_sw));
+Gem5::setFpRound(old_rm);
 finishVfp(fpscr, state, fpscr.fz);
 FpscrExc = fpscr;
 '''
@@ -1154,11 +1160,13 @@
 double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw);
 vfpFlushToZero(fpscr, cOp1);
 VfpSavedState state = prepFpState(fpscr.rMode);
-fesetround(FeRoundZero);
+Gem5::RoundingMode old_rm = Gem5::getFpRound();
+Gem5::setFpRound(Gem5::RoundingMode::TowardZero);
 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
 int64_t result = vfpFpToFixed(
 cOp1, true, 32, 0, true, {round_mode});
 __asm__ __volatile__("" :: "m" (result));
+Gem5::setFpRound(old_rm);
 finishVfp(fpscr, state, fpscr.fz);
 FpDestP0_uw = result;
 FpscrExc = fpscr;

--
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[gem5-dev] Change in gem5/gem5[develop]: scons: Work around a scons bug when calling TryCompile.

2021-02-11 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41213 )



Change subject: scons: Work around a scons bug when calling TryCompile.
..

scons: Work around a scons bug when calling TryCompile.

When calling TryCompile with an empty string for the source, useful
when just testing a build flag, some versions of SCons will apparently
create some sort of equivalence between Value('') and Value(0). That
shows itself when creating config file headers, where Value(0) is
switched with Value(''), and the header defines a macro with which
expands to nothing rather than a macro which expands to 0. Later uses
of the macro of the form:

 #if CONFIG_VARIABLE

fail because CONFIG_VARIABLE expands to nothing. If it expanded to 0
like it's supposed to, then the guarded block of code would be excluded
correctly.

Change-Id: Ie324ec5f8dd307c65745b9326a11230e10caa0bd
---
M site_scons/gem5_scons/configure.py
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/site_scons/gem5_scons/configure.py  
b/site_scons/gem5_scons/configure.py

index 7bf97b2..35aa1a9 100644
--- a/site_scons/gem5_scons/configure.py
+++ b/site_scons/gem5_scons/configure.py
@@ -47,7 +47,7 @@
 context.Message("Checking for compiler %s support... " % flag)
 last_cxxflags = context.env['CXXFLAGS']
 context.env.Append(CXXFLAGS=[flag])
-ret = context.TryCompile('', '.cc')
+ret = context.TryCompile('// CheckCxxFlag DO NOTHING', '.cc')
 if not (ret and autoadd):
 context.env['CXXFLAGS'] = last_cxxflags
 context.Result(ret)

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Gerrit-Change-Number: 41213
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[gem5-dev] Change in gem5/gem5[develop]: scons: Use conf to determine if some flags are supported.

2021-02-11 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40861 )


Change subject: scons: Use conf to determine if some flags are supported.
..

scons: Use conf to determine if some flags are supported.

Use conf rather than checking for particular combinations of OS and/or
compiler versions. This *should* be just as correct, and not require
keeping track of what versions of the tools particular flags were added.

Change-Id: Icaa4c273fe89801e2808e6a814ce476700fd6956
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40861
Tested-by: kokoro 
Maintainer: Gabe Black 
Reviewed-by: Andreas Sandberg 
---
M SConstruct
1 file changed, 3 insertions(+), 10 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index d648424..214aa48 100755
--- a/SConstruct
+++ b/SConstruct
@@ -323,10 +323,7 @@
 main.Append(CCFLAGS=['-I/usr/local/include'])
 main.Append(CXXFLAGS=['-I/usr/local/include'])

-# On Mac OS X/Darwin the default linker doesn't support the
-# option --as-needed
-if sys.platform != "darwin":
-main.Append(LINKFLAGS='-Wl,--as-needed')
+conf.CheckLinkFlag('-Wl,--as-needed')
 if GetOption('gold_linker'):
 main.Append(LINKFLAGS='-fuse-ld=gold')

@@ -397,12 +394,8 @@
  # interchangeably.
  '-Wno-mismatched-tags',
  ])
-if sys.platform != "darwin" and \
-   compareVersions(clang_version, "10.0") >= 0:
-main.Append(CCFLAGS=['-Wno-c99-designator'])
-
-if compareVersions(clang_version, "8.0") >= 0:
-main.Append(CCFLAGS=['-Wno-defaulted-function-deleted'])
+conf.CheckCxxFlag('-Wno-c99-designator')
+conf.CheckCxxFlag('-Wno-defaulted-function-deleted')

 main.Append(TCMALLOC_CCFLAGS=['-fno-builtin'])




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--
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Gerrit-Branch: develop
Gerrit-Change-Id: Icaa4c273fe89801e2808e6a814ce476700fd6956
Gerrit-Change-Number: 40861
Gerrit-PatchSet: 8
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Simplify kvm architecture compatibility check.

2021-02-11 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40870 )


Change subject: scons: Simplify kvm architecture compatibility check.
..

scons: Simplify kvm architecture compatibility check.

The original implementation had a function we'd call back into later
which checked if a given ISA has KVM support on the current host.
Instead, this change reverse that and statically figures out which
single target ISA could possibly run under KVM on this host. Then later,
we can just check if the ISA we're trying to build is that one.

Change-Id: I3e7e06180983dfcc4611181718eb5d6210844d36
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40870
Tested-by: kokoro 
Maintainer: Gabe Black 
Reviewed-by: Andreas Sandberg 
---
M SConstruct
1 file changed, 21 insertions(+), 34 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index 09029f6..210f813 100755
--- a/SConstruct
+++ b/SConstruct
@@ -674,39 +674,26 @@
 if not have_tuntap:
 print("Info: Compatible header file  not found.")

-# x86 needs support for xsave. We test for the structure here since we
-# won't be able to run new tests by the time we know which ISA we're
-# targeting.
-have_kvm_xsave = conf.CheckTypeSize('struct kvm_xsave',
-'#include ') != 0
+# Determine what ISA KVM can support on this host.
+kvm_isa = None
+host_isa = None
+try:
+import platform
+host_isa = platform.machine()
+except:
+pass

-# Check if the requested target ISA is compatible with the host
-def is_isa_kvm_compatible(isa):
-try:
-import platform
-host_isa = platform.machine()
-except:
-warning("Failed to determine host ISA.")
-return False
-
-if not have_posix_timers:
-warning("Can not enable KVM, host seems to lack support "
-"for POSIX timers")
-return False
-
-if isa == "arm":
-return host_isa in ( "armv7l", "aarch64" )
-elif isa == "x86":
-if host_isa != "x86_64":
-return False
-
-if not have_kvm_xsave:
-warning("KVM on x86 requires xsave support in kernel headers.")
-return False
-
-return True
+if not host_isa:
+warning("Failed to determine host ISA.")
+elif not have_posix_timers:
+warning("Cannot enable KVM, host seems to lack support for POSIX  
timers")

+elif host_isa in ('armv7l', 'aarch64'):
+kvm_isa = 'arm'
+elif host_isa == 'x86_64':
+if conf.CheckTypeSize('struct kvm_xsave', '#include ') !=  
0:

+kvm_isa = 'x86'
 else:
-return False
+warning("KVM on x86 requires xsave support in kernel headers.")


 # Check if the exclude_host attribute is available. We want this to
@@ -1044,9 +1031,9 @@
 if not have_kvm:
 warning("Can not enable KVM, host seems to lack KVM support")
 env['USE_KVM'] = False
-elif not is_isa_kvm_compatible(env['TARGET_ISA']):
-print("Info: KVM support disabled due to unsupported host and "
-  "target ISA combination")
+elif kvm_isa != env['TARGET_ISA']:
+print("Info: KVM for %s not supported on %s host." %
+  (env['TARGET_ISA'], kvm_isa))
 env['USE_KVM'] = False

 if env['USE_TUNTAP']:



The change was submitted with unreviewed changes in the following files:

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3e7e06180983dfcc4611181718eb5d6210844d36
Gerrit-Change-Number: 40870
Gerrit-PatchSet: 8
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Simplify the check for hdf5 support.

2021-02-11 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40865 )


Change subject: scons: Simplify the check for hdf5 support.
..

scons: Simplify the check for hdf5 support.

Collapse the check_hdf5 to the only place it was called, to set a simple
flag variable. Pull the invariant have_pkg_config check out of
check_hdf5_pkg, since if we don't have pkg-config there's no reason to
even try to use to set up hdf5. Turn the one-off, non-standard "Warning"
print into an actual warning().

Change-Id: I04793ae862aeaf1605467d205837b9dd744f93cb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40865
Tested-by: kokoro 
Maintainer: Gabe Black 
Reviewed-by: Andreas Sandberg 
---
M SConstruct
1 file changed, 11 insertions(+), 18 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index a3c330f..9e3af37 100755
--- a/SConstruct
+++ b/SConstruct
@@ -724,42 +724,35 @@
 main['HAVE_PERF_ATTR_EXCLUDE_HOST'] = conf.CheckMember(
 'linux/perf_event.h', 'struct perf_event_attr', 'exclude_host')

-def check_hdf5():
-return \
-conf.CheckLibWithHeader('hdf5', 'hdf5.h', 'C',
-'H5Fcreate("", 0, 0, 0);') and \
-conf.CheckLibWithHeader('hdf5_cpp', 'H5Cpp.h', 'C++',
-'H5::H5File("", 0);')
-
 def check_hdf5_pkg(name):
 print("Checking for %s using pkg-config..." % name, end="")
-if not have_pkg_config:
-print(" pkg-config not found")
-return False
-
 try:
 main.ParseConfig('pkg-config --cflags-only-I --libs-only-L %s' %  
name)

-print(" yes")
-return True
 except:
 print(" no")
 return False
+print(" yes")
+return True

 # Check if there is a pkg-config configuration for hdf5. If we find
 # it, setup the environment to enable linking and header inclusion. We
 # don't actually try to include any headers or link with hdf5 at this
 # stage.
-if not check_hdf5_pkg('hdf5-serial'):
-check_hdf5_pkg('hdf5')
+if have_pkg_config:
+if not check_hdf5_pkg('hdf5-serial'):
+check_hdf5_pkg('hdf5')

 # Check if the HDF5 libraries can be found. This check respects the
 # include path and library path provided by pkg-config. We perform
 # this check even if there isn't a pkg-config configuration for hdf5
 # since some installations don't use pkg-config.
-have_hdf5 = check_hdf5()
+have_hdf5 = \
+conf.CheckLibWithHeader('hdf5', 'hdf5.h', 'C',
+'H5Fcreate("", 0, 0, 0);') and \
+conf.CheckLibWithHeader('hdf5_cpp', 'H5Cpp.h', 'C++',
+'H5::H5File("", 0);')
 if not have_hdf5:
-print("Warning: Couldn't find any HDF5 C++ libraries. Disabling")
-print(" HDF5 support.")
+warning("Couldn't find any HDF5 C++ libraries. Disabling HDF5  
support.")


 ##
 #



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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I04793ae862aeaf1605467d205837b9dd744f93cb
Gerrit-Change-Number: 40865
Gerrit-PatchSet: 8
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: scons: Simplify check for have_posix_clock.

2021-02-11 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40863 )


Change subject: scons: Simplify check for have_posix_clock.
..

scons: Simplify check for have_posix_clock.

The "library" argument can actually be a list, in which case each
element of the list is checked, one after the other. Use that rather
than calling the CheckLibWithHeader method multiple times and manually
oring the results.

Change-Id: I5c774be15eaa9a7e52ec3ee5a1bbcc5ef1fa0f41
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40863
Tested-by: kokoro 
Maintainer: Gabe Black 
Reviewed-by: Andreas Sandberg 
---
M SConstruct
1 file changed, 1 insertion(+), 3 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index 45a0df6..d4acd19 100755
--- a/SConstruct
+++ b/SConstruct
@@ -629,9 +629,7 @@

 # Check for librt.
 have_posix_clock = \
-conf.CheckLibWithHeader(None, 'time.h', 'C',
-'clock_nanosleep(0,0,NULL,NULL);') or \
-conf.CheckLibWithHeader('rt', 'time.h', 'C',
+conf.CheckLibWithHeader([None, 'rt'], 'time.h', 'C',
 'clock_nanosleep(0,0,NULL,NULL);')
 if not have_posix_clock:
 warning("Can't find library for POSIX clocks.")



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--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5c774be15eaa9a7e52ec3ee5a1bbcc5ef1fa0f41
Gerrit-Change-Number: 40863
Gerrit-PatchSet: 8
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Create a Configure checker for pkg-config.

2021-02-11 Thread Gabe Black (Gerrit) via gem5-dev
-Id: I1495e5370b60dcebb1c9ce38517e84d727abc2fd
Gerrit-Change-Number: 40866
Gerrit-PatchSet: 8
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Simplify backtrace implementation detection.

2021-02-11 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40864 )


Change subject: scons: Simplify backtrace implementation detection.
..

scons: Simplify backtrace implementation detection.

There are really only two options current, glibc or none. If there's a
working implementation there's no real reason to select none, and if
there isn't there's no other option but to select none.

Instead of building up a list, having a default, and making what option
on the list is selected configurable, boil it down to either using glibc
if that implementation is detected, or warning and using none. Also
merge the "normal" and *BSD versions of the checks to reduce redundancy.

The complexity can be added back in if/when there are other
implementations to choose from.

Change-Id: I27c77996a00018302f4daea40924cf059d5a4323
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40864
Tested-by: kokoro 
Maintainer: Gabe Black 
Reviewed-by: Andreas Sandberg 
---
M SConstruct
1 file changed, 5 insertions(+), 18 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index d4acd19..a3c330f 100755
--- a/SConstruct
+++ b/SConstruct
@@ -649,22 +649,11 @@
 "on Ubuntu or RedHat).")


-# Detect back trace implementations. The last implementation in the
-# list will be used by default.
-backtrace_impls = [ "none" ]
-
-backtrace_checker = 'char temp;' + \
-' backtrace_symbols_fd((void*), 0, 0);'
-if conf.CheckLibWithHeader(None, 'execinfo.h', 'C', backtrace_checker):
-backtrace_impls.append("glibc")
-elif conf.CheckLibWithHeader('execinfo', 'execinfo.h', 'C',
- backtrace_checker):
-# NetBSD and FreeBSD need libexecinfo.
-backtrace_impls.append("glibc")
-main.Append(LIBS=['execinfo'])
-
-if backtrace_impls[-1] == "none":
-default_backtrace_impl = "none"
+if conf.CheckLibWithHeader([None, 'execinfo'], 'execinfo.h', 'C',
+'char temp; backtrace_symbols_fd((void *), 0, 0);'):
+main['BACKTRACE_IMPL'] = 'glibc'
+else:
+main['BACKTRACE_IMPL'] = 'none'
 warning("No suitable back trace implementation found.")

 # Check for  (C99 FP environment control)
@@ -866,8 +855,6 @@
 BoolVariable('BUILD_GPU', 'Build the compute-GPU model', False),
 EnumVariable('PROTOCOL', 'Coherence protocol for Ruby', 'None',
   all_protocols),
-EnumVariable('BACKTRACE_IMPL', 'Post-mortem dump implementation',
- backtrace_impls[-1], backtrace_impls),
 ('NUMBER_BITS_PER_SET', 'Max elements in set (default 64)',
  64),
 BoolVariable('USE_HDF5', 'Enable the HDF5 support', have_hdf5),



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--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I27c77996a00018302f4daea40924cf059d5a4323
Gerrit-Change-Number: 40864
Gerrit-PatchSet: 8
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Merge redundant checks for the socket library.

2021-02-11 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40869 )


Change subject: scons: Merge redundant checks for the socket library.
..

scons: Merge redundant checks for the socket library.

scons can accept more than one library at a time, so lets check for both
at once instead of writing out almost the same check twice.

Change-Id: I82f9bdf59a349e28ca75a615d711051256ec73a4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40869
Tested-by: kokoro 
Maintainer: Gabe Black 
Reviewed-by: Andreas Sandberg 
---
M SConstruct
1 file changed, 3 insertions(+), 4 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index d0fd852..09029f6 100755
--- a/SConstruct
+++ b/SConstruct
@@ -588,10 +588,9 @@
 warning('Python version too new. Python 3 expected.')

 # On Solaris you need to use libsocket for socket ops
-if not  
conf.CheckLibWithHeader(None, 'sys/socket.h', 'C++', 'accept(0,0,0);'):

-   if not conf.CheckLibWithHeader('socket', 'sys/socket.h',
-  'C++', 'accept(0,0,0);'):
-   error("Can't find library with socket calls (e.g. accept()).")
+if not conf.CheckLibWithHeader(
+[None, 'socket'], 'sys/socket.h', 'C++', 'accept(0,0,0);'):
+   error("Can't find library with socket calls (e.g. accept()).")

 # Check for zlib.  If the check passes, libz will be automatically
 # added to the LIBS environment variable.



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--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I82f9bdf59a349e28ca75a615d711051256ec73a4
Gerrit-Change-Number: 40869
Gerrit-PatchSet: 8
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Simplify the check for protoc.

2021-02-11 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40867 )


Change subject: scons: Simplify the check for protoc.
..

scons: Simplify the check for protoc.

Collapse nesting, and constrain the try/except to only the line in that
section which might actually be expected to throw an exception when
things are working normally.

This makes the code easier to read, and won't absorb and discard
exceptions which are thrown for unexpected reasons.

Change-Id: Id3ac417ab5545bef35ed8a87d05211c8ef2f5a50
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40867
Tested-by: kokoro 
Maintainer: Gabe Black 
Reviewed-by: Andreas Sandberg 
---
M SConstruct
1 file changed, 25 insertions(+), 27 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index 27816bf..d0fd852 100755
--- a/SConstruct
+++ b/SConstruct
@@ -455,39 +455,37 @@
 main.Append(CCFLAGS=["-Wno-uninitialized"])


-have_pkg_config = readCommand(['pkg-config', '--version'], exception='')
+have_pkg_config = main.Detect('pkg-config')

 # Check for the protobuf compiler
+main['HAVE_PROTOC'] = False
+protoc_version = []
 try:
-main['HAVE_PROTOC'] = True
 protoc_version = readCommand([main['PROTOC'], '--version']).split()
-
-# First two words should be "libprotoc x.y.z"
-if len(protoc_version) < 2 or protoc_version[0] != 'libprotoc':
-warning('Protocol buffer compiler (protoc) not found.\n'
-'Please install protobuf-compiler for tracing support.')
-main['HAVE_PROTOC'] = False
-else:
-# Based on the availability of the compress stream wrappers,
-# require 2.1.0
-min_protoc_version = '2.1.0'
-if compareVersions(protoc_version[1], min_protoc_version) < 0:
-warning('protoc version', min_protoc_version,
-'or newer required.\n'
-'Installed version:', protoc_version[1])
-main['HAVE_PROTOC'] = False
-else:
-# Attempt to determine the appropriate include path and
-# library path using pkg-config, that means we also need to
-# check for pkg-config. Note that it is possible to use
-# protobuf without the involvement of pkg-config. Later on we
-# check go a library config check and at that point the test
-# will fail if libprotobuf cannot be found.
-if have_pkg_config:
- 
conf.CheckPkgConfig('protobuf', '--cflags', '--libs-only-L')

 except Exception as e:
 warning('While checking protoc version:', str(e))
-main['HAVE_PROTOC'] = False
+
+# Based on the availability of the compress stream wrappers, require 2.1.0.
+min_protoc_version = '2.1.0'
+
+# First two words should be "libprotoc x.y.z"
+if len(protoc_version) < 2 or protoc_version[0] != 'libprotoc':
+warning('Protocol buffer compiler (protoc) not found.\n'
+'Please install protobuf-compiler for tracing support.')
+elif compareVersions(protoc_version[1], min_protoc_version) < 0:
+warning('protoc version', min_protoc_version, 'or newer required.\n'
+'Installed version:', protoc_version[1])
+else:
+# Attempt to determine the appropriate include path and
+# library path using pkg-config, that means we also need to
+# check for pkg-config. Note that it is possible to use
+# protobuf without the involvement of pkg-config. Later on we
+# check go a library config check and at that point the test
+# will fail if libprotobuf cannot be found.
+if have_pkg_config:
+conf.CheckPkgConfig('protobuf', '--cflags', '--libs-only-L')
+main['HAVE_PROTOC'] = True
+


 # Cache build files in the supplied directory.



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--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id3ac417ab5545bef35ed8a87d05211c8ef2f5a50
Gerrit-Change-Number: 40867
Gerrit-PatchSet: 8
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Move a displaced have_posix_clock check back where it goes.

2021-02-11 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40862 )


Change subject: scons: Move a displaced have_posix_clock check back where  
it goes.

..

scons: Move a displaced have_posix_clock check back where it goes.

This check had been separated from the code handling have_posix_clock by
some intervening code doing something else. Bring the check back
alongside the code setting that variable.

Change-Id: I6acb54fddbb5c41d6c38d4b93e649835a4775fa0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40862
Tested-by: kokoro 
Maintainer: Gabe Black 
Reviewed-by: Andreas Sandberg 
---
M SConstruct
1 file changed, 2 insertions(+), 3 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index 214aa48..45a0df6 100755
--- a/SConstruct
+++ b/SConstruct
@@ -633,6 +633,8 @@
 'clock_nanosleep(0,0,NULL,NULL);') or \
 conf.CheckLibWithHeader('rt', 'time.h', 'C',
 'clock_nanosleep(0,0,NULL,NULL);')
+if not have_posix_clock:
+warning("Can't find library for POSIX clocks.")

 have_posix_timers = \
 conf.CheckLibWithHeader([None, 'rt'], [ 'time.h', 'signal.h' ], 'C',
@@ -667,9 +669,6 @@
 default_backtrace_impl = "none"
 warning("No suitable back trace implementation found.")

-if not have_posix_clock:
-warning("Can't find library for POSIX clocks.")
-
 # Check for  (C99 FP environment control)
 have_fenv = conf.CheckHeader('fenv.h', '<>')
 if not have_fenv:



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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6acb54fddbb5c41d6c38d4b93e649835a4775fa0
Gerrit-Change-Number: 40862
Gerrit-PatchSet: 8
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: In Check(Cxx|Link)Flag, only install the flag if it exists.

2021-02-11 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41159 )


Change subject: scons: In Check(Cxx|Link)Flag, only install the flag if it  
exists.

..

scons: In Check(Cxx|Link)Flag, only install the flag if it exists.

These functions where correctly returning whether a flag had existed,
and also correctly not installing it if asked not to. Unfortunately if
they *were* asked to install the flag, they ignored whether or not it
had actually existed to begin with.

Change-Id: I2dca0e1a0ddbc182576d48237aeea5452a02c51b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41159
Maintainer: Gabe Black 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
M site_scons/gem5_scons/configure.py
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/site_scons/gem5_scons/configure.py  
b/site_scons/gem5_scons/configure.py

index e539c73..cebbb12 100644
--- a/site_scons/gem5_scons/configure.py
+++ b/site_scons/gem5_scons/configure.py
@@ -47,7 +47,7 @@
 last_cxxflags = context.env['CXXFLAGS']
 context.env.Append(CXXFLAGS=[flag])
 ret = context.TryCompile('', '.cc')
-if not autoadd:
+if not (ret and autoadd):
 context.env['CXXFLAGS'] = last_cxxflags
 context.Result(ret)
 return ret
@@ -57,7 +57,7 @@
 last_linkflags = context.env['LINKFLAGS']
 context.env.Append(LINKFLAGS=[flag])
 ret = context.TryLink('int main(int, char *[]) { return 0; }', '.cc')
-if not autoadd:
+if not (ret and autoadd):
 context.env['LINKFLAGS'] = last_linkflags
 if set_for_shared:
 assert(autoadd)

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2dca0e1a0ddbc182576d48237aeea5452a02c51b
Gerrit-Change-Number: 41159
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: In Check(Cxx|Link)Flag, only install the flag if it exists.

2021-02-10 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41159 )



Change subject: scons: In Check(Cxx|Link)Flag, only install the flag if it  
exists.

..

scons: In Check(Cxx|Link)Flag, only install the flag if it exists.

These functions where correctly returning whether a flag had existed,
and also correctly not installing it if asked not to. Unfortunately if
they *were* asked to install the flag, they ignored whether or not it
had actually existed to begin with.

Change-Id: I2dca0e1a0ddbc182576d48237aeea5452a02c51b
---
M site_scons/gem5_scons/configure.py
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/site_scons/gem5_scons/configure.py  
b/site_scons/gem5_scons/configure.py

index e539c73..cebbb12 100644
--- a/site_scons/gem5_scons/configure.py
+++ b/site_scons/gem5_scons/configure.py
@@ -47,7 +47,7 @@
 last_cxxflags = context.env['CXXFLAGS']
 context.env.Append(CXXFLAGS=[flag])
 ret = context.TryCompile('', '.cc')
-if not autoadd:
+if not (ret and autoadd):
 context.env['CXXFLAGS'] = last_cxxflags
 context.Result(ret)
 return ret
@@ -57,7 +57,7 @@
 last_linkflags = context.env['LINKFLAGS']
 context.env.Append(LINKFLAGS=[flag])
 ret = context.TryLink('int main(int, char *[]) { return 0; }', '.cc')
-if not autoadd:
+if not (ret and autoadd):
 context.env['LINKFLAGS'] = last_linkflags
 if set_for_shared:
 assert(autoadd)

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Gerrit-Change-Id: I2dca0e1a0ddbc182576d48237aeea5452a02c51b
Gerrit-Change-Number: 41159
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[gem5-dev] Change in gem5/gem5[develop]: scons: Pull Configure() to earlier in SConstruct so we can use it more.

2021-02-10 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40860 )


Change subject: scons: Pull Configure() to earlier in SConstruct so we can  
use it more.

..

scons: Pull Configure() to earlier in SConstruct so we can use it more.

This mechanism lets us check if headers are available, flags are
supported, etc. We should use that more often, rather than checking for
specific versions of tools where problematic new warnings were added, etc.

Change-Id: I5b1a6499147f27cc8944fcb8c61eb69e9fa8fb7a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40860
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M SConstruct
1 file changed, 4 insertions(+), 3 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index 1485a36..d648424 100755
--- a/SConstruct
+++ b/SConstruct
@@ -296,6 +296,10 @@
 # compiler we're using.
 main['TCMALLOC_CCFLAGS'] = []

+# Platform-specific configuration.  Note again that we assume that all
+# builds under a given build root run on the same host platform.
+conf = gem5_scons.Configure(main)
+
 CXX_version = readCommand([main['CXX'],'--version'], exception=False)
 CXX_V = readCommand([main['CXX'],'-V'], exception=False)

@@ -499,9 +503,6 @@
 warning('While checking protoc version:', str(e))
 main['HAVE_PROTOC'] = False

-# Platform-specific configuration.  Note again that we assume that all
-# builds under a given build root run on the same host platform.
-conf = gem5_scons.Configure(main)

 # Cache build files in the supplied directory.
 if main['M5_BUILD_CACHE']:

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Gerrit-Change-Id: I5b1a6499147f27cc8944fcb8c61eb69e9fa8fb7a
Gerrit-Change-Number: 40860
Gerrit-PatchSet: 7
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: scons: Extract the gem5 specific Configure call to its own file.

2021-02-10 Thread Gabe Black (Gerrit) via gem5-dev
sult(ret[1] if ret[0] == 1 else 0)
+if ret[0] == 0:
+return None
+else:
+return tuple(map(int, ret[1].split(".")))
+
+def Configure(env, *args, **kwargs):
+kwargs.setdefault('conf_dir',
+os.path.join(env['BUILDROOT'], '.scons_config'))
+kwargs.setdefault('log_file',
+os.path.join(env['BUILDROOT'], 'scons_config.log'))
+kwargs.setdefault('custom_tests', {})
+kwargs['custom_tests'].update({
+'CheckMember' : CheckMember,
+'CheckPythonLib' : CheckPythonLib,
+'CheckCxxFlag' : CheckCxxFlag,
+'CheckLinkFlag' : CheckLinkFlag,
+})
+conf = SCons.Script.Configure(env, *args, **kwargs)
+
+# Recent versions of scons substitute a "Null" object for Configure()
+# when configuration isn't necessary, e.g., if the "--help" option is
+# present.  Unfortuantely this Null object always returns false,
+# breaking all our configuration checks.  We replace it with our own
+# more optimistic null object that returns True instead.
+if not conf:
+def NullCheck(*args, **kwargs):
+return True
+
+class NullConf:
+def __init__(self, env):
+self.env = env
+def Finish(self):
+return self.env
+def __getattr__(self, mname):
+return NullCheck
+
+conf = NullConf(main)
+
+return conf



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--
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Gerrit-Branch: develop
Gerrit-Change-Id: I5f5edc866af43753b4e0a9cc63774ded0fffe06b
Gerrit-Change-Number: 40858
Gerrit-PatchSet: 8
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Trim down a check for mac OS and arch setting flags.

2021-02-10 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40857 )


Change subject: scons: Trim down a check for mac OS and arch setting flags.
..

scons: Trim down a check for mac OS and arch setting flags.

This check used uname to determine if scons was running on macos, and
then a fairly elaborate check to see if the version was above 9, and if
the hardware supported 64 bit. I think at this point it's safe to assume
both that we're at least at macos 10 which is 19 years old, and that Mac
hardware supports 64 bit.

Change-Id: Ice66df2530bbcc929d3a37e7679634b75ba7b860
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40857
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Andreas Sandberg 
---
M SConstruct
1 file changed, 0 insertions(+), 13 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index 3e892cd..3f55730 100755
--- a/SConstruct
+++ b/SConstruct
@@ -574,19 +574,6 @@
 'CheckLinkFlag' : CheckLinkFlag,
 })

-# Check if we should compile a 64 bit binary on Mac OS X/Darwin
-try:
-import platform
-uname = platform.uname()
-if uname[0] == 'Darwin' and compareVersions(uname[2], '9.0.0') >= 0:
-if int(readCommand('sysctl -n hw.cpu64bit_capable')[0]):
-main.Append(CCFLAGS=['-arch', 'x86_64'])
-main.Append(CFLAGS=['-arch', 'x86_64'])
-main.Append(LINKFLAGS=['-arch', 'x86_64'])
-main.Append(ASFLAGS=['-arch', 'x86_64'])
-except:
-pass
-
 # Recent versions of scons substitute a "Null" object for Configure()
 # when configuration isn't necessary, e.g., if the "--help" option is
 # present.  Unfortuantely this Null object always returns false,



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--
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Gerrit-Branch: develop
Gerrit-Change-Id: Ice66df2530bbcc929d3a37e7679634b75ba7b860
Gerrit-Change-Number: 40857
Gerrit-PatchSet: 7
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Remove "TIMEOUT" variable and checks.

2021-02-10 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40856 )


Change subject: scons: Remove "TIMEOUT" variable and checks.
..

scons: Remove "TIMEOUT" variable and checks.

This was used when regression tests were run from scons. Since that
hasn't been done for a while, these checks and this setting have no
purpose and can be removed.

Change-Id: Ibe383944f1427571061fd25ed6e97d9acfbbc7f1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40856
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Andreas Sandberg 
---
M SConstruct
1 file changed, 0 insertions(+), 14 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index 6b028ee..3e892cd 100755
--- a/SConstruct
+++ b/SConstruct
@@ -498,20 +498,6 @@
 warning('While checking protoc version:', str(e))
 main['HAVE_PROTOC'] = False

-# Check for 'timeout' from GNU coreutils. If present, regressions will
-# be run with a time limit. We require version 8.13 since we rely on
-# support for the '--foreground' option.
-if sys.platform.startswith('freebsd'):
-timeout_lines = readCommand(['gtimeout', '--version'],
-exception='').splitlines()
-else:
-timeout_lines = readCommand(['timeout', '--version'],
-exception='').splitlines()
-# Get the first line and tokenize it
-timeout_version = timeout_lines[0].split() if timeout_lines else []
-main['TIMEOUT'] =  timeout_version and \
-compareVersions(timeout_version[-1], '8.13') >= 0
-
 def CheckCxxFlag(context, flag, autoadd=True):
 context.Message("Checking for compiler %s support... " % flag)
 last_cxxflags = context.env['CXXFLAGS']



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--
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Gerrit-Branch: develop
Gerrit-Change-Id: Ibe383944f1427571061fd25ed6e97d9acfbbc7f1
Gerrit-Change-Number: 40856
Gerrit-PatchSet: 6
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: scons: Update the Check(Cxx|Link)Flag checks to set their vars.

2021-02-10 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40855 )


Change subject: scons: Update the Check(Cxx|Link)Flag checks to set their  
vars.

..

scons: Update the Check(Cxx|Link)Flag checks to set their vars.

This avoids boilerplate where we check to see if flag X is supported,
and if so then set flag X. Since there are shared and static versions of
the linker flags but we only explicitly check the static ones, this
change also adds a parameter to CheckLinkFlag to set both flavors. This
defaults to true since I assume most of the time linking flags will
apply to both.

Change-Id: I983222169e9835aeb98570362f7004e2ef0240d0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40855
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M SConstruct
1 file changed, 11 insertions(+), 10 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index 2e83aa2..6b028ee 100755
--- a/SConstruct
+++ b/SConstruct
@@ -512,21 +512,26 @@
 main['TIMEOUT'] =  timeout_version and \
 compareVersions(timeout_version[-1], '8.13') >= 0

-def CheckCxxFlag(context, flag):
+def CheckCxxFlag(context, flag, autoadd=True):
 context.Message("Checking for compiler %s support... " % flag)
 last_cxxflags = context.env['CXXFLAGS']
 context.env.Append(CXXFLAGS=[flag])
 ret = context.TryCompile('', '.cc')
-context.env['CXXFLAGS'] = last_cxxflags
+if not autoadd:
+context.env['CXXFLAGS'] = last_cxxflags
 context.Result(ret)
 return ret

-def CheckLinkFlag(context, flag):
+def CheckLinkFlag(context, flag, autoadd=True, set_for_shared=True):
 context.Message("Checking for linker %s support... " % flag)
 last_linkflags = context.env['LINKFLAGS']
 context.env.Append(LINKFLAGS=[flag])
 ret = context.TryLink('int main(int, char *[]) { return 0; }', '.cc')
-context.env['LINKFLAGS'] = last_linkflags
+if not autoadd:
+context.env['LINKFLAGS'] = last_linkflags
+if set_for_shared:
+assert(autoadd)
+context.env.Append(SHLINKFLAGS=[flag])
 context.Result(ret)
 return ret

@@ -621,13 +626,9 @@
 CacheDir(main['M5_BUILD_CACHE'])

 if not GetOption('no_compress_debug'):
-if conf.CheckCxxFlag('-gz'):
-main.Append(CXXFLAGS=['-gz'])
-else:
+if not conf.CheckCxxFlag('-gz'):
 warning("Can't enable object file debug section compression")
-if conf.CheckLinkFlag('-gz'):
-main.Append(LINKFLAGS=['-gz'], SHLINKFLAGS=['-gz'])
-else:
+if not conf.CheckLinkFlag('-gz'):
 warning("Can't enable executable debug section compression")

 main['USE_PYTHON'] = not GetOption('without_python')



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--
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Gerrit-Branch: develop
Gerrit-Change-Id: I983222169e9835aeb98570362f7004e2ef0240d0
Gerrit-Change-Number: 40855
Gerrit-PatchSet: 7
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Remove partial linking.

2021-02-10 Thread Gabe Black (Gerrit) via gem5-dev
5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia5aa16a8dd008599645076cea8131799f6086e0f
Gerrit-Change-Number: 40795
Gerrit-PatchSet: 7
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Boris Shingarov 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Delete the empty, default off "nocpu".

2021-02-10 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40871 )


Change subject: cpu: Delete the empty, default off "nocpu".
..

cpu: Delete the empty, default off "nocpu".

This very nearly empty CPU directory does nothing except define a CPU at
the scons level which is off by default. It seems safe to delete it.

Change-Id: I5bd3a52062bbc67fb1ee7d350519cd85a3f8fdb8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40871
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Maintainer: Jason Lowe-Power 
---
D src/cpu/nocpu/SConsopts
1 file changed, 0 insertions(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/nocpu/SConsopts b/src/cpu/nocpu/SConsopts
deleted file mode 100644
index 40bf503..000
--- a/src/cpu/nocpu/SConsopts
+++ /dev/null
@@ -1,4 +0,0 @@
-
-Import('*')
-
-CpuModel('no')



The change was submitted with unreviewed changes in the following files:

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5bd3a52062bbc67fb1ee7d350519cd85a3f8fdb8
Gerrit-Change-Number: 40871
Gerrit-PatchSet: 7
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Add support for debug info compression.

2021-02-10 Thread Gabe Black (Gerrit) via gem5-dev
   ]

 if not self.targets:
diff --git a/tests/jenkins/presubmit-stage2.sh  
b/tests/jenkins/presubmit-stage2.sh

index be90b2b..aed60fd 100755
--- a/tests/jenkins/presubmit-stage2.sh
+++ b/tests/jenkins/presubmit-stage2.sh
@@ -46,4 +46,5 @@
 # Look for tests in the gem5 subdirectory
 # Once complete, run the Google Tests
 cd tests
-./main.py run -j4 -t4 gem5 && scons -C .. build/NULL/unittests.opt
+./main.py run -j4 -t4 gem5 && scons -C .. --no-compress-debug \
+build/NULL/unittests.opt
diff --git a/tests/jenkins/presubmit.sh b/tests/jenkins/presubmit.sh
index 8e76d98..f27c23c 100755
--- a/tests/jenkins/presubmit.sh
+++ b/tests/jenkins/presubmit.sh
@@ -62,4 +62,4 @@
 rm -rf build
 docker run -u $UID:$GID --volume $(pwd):$(pwd) -w $(pwd) --rm \
 "${DOCKER_IMAGE_CLANG_COMPILE}" /usr/bin/env python3 /usr/bin/scons \
-build/X86/gem5.fast -j4
+build/X86/gem5.fast -j4 --no-compress-debug

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I71919062d23742b7658918b0fa9c4d91d0521fbf
Gerrit-Change-Number: 40715
Gerrit-PatchSet: 7
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Track misc regs in vectors in the O3 CPU instruction class.

2021-02-09 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38388 )


Change subject: cpu: Track misc regs in vectors in the O3 CPU instruction  
class.

..

cpu: Track misc regs in vectors in the O3 CPU instruction class.

Most instructions won't actually write to misc regs, so the overhead
should be quite small, particularlly compared to the other overheads in
the O3.

Change-Id: I840d6002cc8151f91611cfcbe2bfa52acc284c0f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38388
Tested-by: kokoro 
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
---
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/dyn_inst_impl.hh
2 files changed, 8 insertions(+), 18 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index b89b3c7..f084368 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -93,17 +93,13 @@
 using BaseDynInst::cpu;

 /** Values to be written to the destination misc. registers. */
-std::array _destMiscRegVal;
+std::vector _destMiscRegVal;

 /** Indexes of the destination misc. registers. They are needed to  
defer
  * the write accesses to the misc. registers until the commit stage,  
when

  * the instruction is out of its speculative state.
  */
-std::array _destMiscRegIdx;
-
-/** Number of destination misc. registers. */
-uint8_t _numDestMiscRegs;
-
+std::vector _destMiscRegIdx;

   public:
 #if TRACING_ON
@@ -139,17 +135,13 @@
  * committed instead of making a new entry. If not, make a new
  * entry and record the write.
  */
-for (int idx = 0; idx < _numDestMiscRegs; idx++) {
-if (_destMiscRegIdx[idx] == misc_reg) {
-   _destMiscRegVal[idx] = val;
-   return;
-}
+for (auto : _destMiscRegIdx) {
+if (idx == misc_reg)
+return;
 }

-assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs);
-_destMiscRegIdx[_numDestMiscRegs] = misc_reg;
-_destMiscRegVal[_numDestMiscRegs] = val;
-_numDestMiscRegs++;
+_destMiscRegIdx.push_back(misc_reg);
+_destMiscRegVal.push_back(val);
 }

 /** Reads a misc. register, including any side-effects the read
@@ -185,7 +177,7 @@
 bool no_squash_from_TC = this->thread->noSquashFromTC;
 this->thread->noSquashFromTC = true;

-for (int i = 0; i < _numDestMiscRegs; i++)
+for (int i = 0; i < _destMiscRegIdx.size(); i++)
 this->cpu->setMiscReg(
 _destMiscRegIdx[i], _destMiscRegVal[i],  
this->threadNumber);


diff --git a/src/cpu/o3/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh
index d960ad0..07131c3 100644
--- a/src/cpu/o3/dyn_inst_impl.hh
+++ b/src/cpu/o3/dyn_inst_impl.hh
@@ -106,8 +106,6 @@
 {
 this->regs.init();

-_numDestMiscRegs = 0;
-
 #if TRACING_ON
 // Value -1 indicates that particular phase
 // hasn't happened (yet).



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[gem5-dev] Change in gem5/gem5[develop]: cpu: Track flat register indices in the Minor CPU with a vector.

2021-02-09 Thread Gabe Black (Gerrit) via gem5-dev
iginate  
here */

 dyn_inst->id.fetchSeqNum = fetch_info.fetchSeqNum;
@@ -404,12 +411,6 @@
  *  has not been set */
 assert(dyn_inst->id.execSeqNum == 0);

-/* Note that the decoder can update the given PC.
- *  Remember not to assign it until *after* calling
- *  decode */
-StaticInstPtr decoded_inst =  
decoder->decode(fetch_info.pc);

-dyn_inst->staticInst = decoded_inst;
-
 dyn_inst->pc = fetch_info.pc;
 DPRINTF(Fetch, "decoder inst %s\n", *dyn_inst);




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Gerrit-Change-Id: I4e49695ba06365d52eb4ce128d5cbb30db665bd7
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Gerrit-PatchSet: 9
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Factor MaxInst(SrcDest)Regs out of the trace CPU.

2021-02-09 Thread Gabe Black (Gerrit) via gem5-dev
nclude 
 #include 
 #include 
 #include 
@@ -555,18 +555,11 @@
 class GraphNode
 {
   public:
-/**
- * The maximum no. of ROB dependencies. There can be at most 2
- * order dependencies which could exist for a store. For a load
- * and comp node there can be at most one order dependency.
- */
-static const uint8_t maxRobDep = 2;
+/** Typedef for the list containing the ROB dependencies */
+typedef std::list RobDepList;

-/** Typedef for the array containing the ROB dependencies */
-typedef std::array RobDepArray;
-
-/** Typedef for the array containing the register dependencies  
*/
-typedef std::array  
RegDepArray;
+/** Typedef for the list containing the register dependencies  
*/

+typedef std::list RegDepList;

 /** Instruction sequence number */
 NodeSeqNum seqNum;
@@ -595,23 +588,17 @@
 /** Instruction PC */
 Addr pc;

-/** Array of order dependencies. */
-RobDepArray robDep;
-
-/** Number of order dependencies */
-uint8_t numRobDep;
+/** List of order dependencies. */
+RobDepList robDep;

 /** Computational delay */
 uint64_t compDelay;

 /**
- * Array of register dependencies (incoming) if any. Maximum  
number
+ * List of register dependencies (incoming) if any. Maximum  
number

  * of source registers used to set maximum size of the array
  */
-RegDepArray regDep;
-
-/** Number of register dependencies */
-uint8_t numRegDep;
+RegDepList regDep;

 /**
  * A vector of nodes dependent (outgoing) on this node. A
@@ -629,12 +616,6 @@
 /** Is the node a compute (non load/store) node */
 bool isComp() const { return (type == Record::COMP); }

-/** Initialize register dependency array to all zeroes */
-void clearRegDep();
-
-/** Initialize register dependency array to all zeroes */
-void clearRobDep();
-
 /** Remove completed instruction from register dependency  
array */

 bool removeRegDep(NodeSeqNum reg_dep);

@@ -891,14 +872,11 @@
  * to the list of dependents of the parent node.
  *
  * @param   new_nodenew node to add to the graph
- * @tparam  dep_array   the dependency array of type rob or  
register,
+ * @tparam  dep_listthe dependency list of type rob or  
register,
  *  that is to be iterated, and may get  
modified

- * @param   num_dep the number of dependencies set in the array
- *  which may get modified during iteration
  */
 template
-void addDepsOnParent(GraphNode *new_node, T& dep_array,
- uint8_t& num_dep);
+void addDepsOnParent(GraphNode *new_node, T& dep_list);

 /**
  * This is the main execute function which consumes nodes from the

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[gem5-dev] Change in gem5/gem5[develop]: sim: Get rid of the IsConforming type trait template.

2021-02-08 Thread Gabe Black (Gerrit) via gem5-dev
tatic Arg
 get(ThreadContext *tc, typename ABI::State )



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Gerrit-Change-Number: 40495
Gerrit-PatchSet: 5
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Gerrit-Reviewer: Bobby R. Bruce 
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Gerrit-Reviewer: Jason Lowe-Power 
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