[gem5-dev] Re: SimObject params() method

2020-10-23 Thread Gabe Black via gem5-dev
er the constructor. If some >> object had a good reason to go against this best practice, that would be >> OK, and we wouldn't need to enforce any specific design or pattern on these >> exceptions. I would prefer to remove the params() function than add more >> template magic

[gem5-dev] Re: SimObject params() method

2020-10-22 Thread Gabe Black via gem5-dev
gt; int myint; >> }; >> >> main.cc >> #include >> #include >> >> #include "MySimObject.hh" >> >> int >> main( int argc, char *argv[]){ >> MySimObject::Params p; >> p.myint = 5; >> MySimObject my_so_insta

[gem5-dev] Re: SimObject params() method

2020-10-22 Thread Gabe Black via gem5-dev
#include > #include > > #include "MySimObject.hh" > > int > main( int argc, char *argv[]){ > MySimObject::Params p; > p.myint = 5; > MySimObject my_so_instance(); > std::cout << my_so_instance.myInt() << std::endl; > retu

[gem5-dev] Re: SimObject params() method

2020-10-22 Thread Gabe Black via gem5-dev
ev >>> *Sent:* 22 October 2020 16:26 >>> *To:* gem5 Developer List >>> *Cc:* Gabe Black ; Jason Lowe-Power < >>> ja...@lowepower.com> >>> *Subject:* [gem5-dev] Re: SimObject params() method >>> >>> >>> >>>

[gem5-dev] Re: SimObject params() method

2020-10-22 Thread Gabe Black via gem5-dev
ad a good reason to go against this best practice, that would be > OK, and we wouldn't need to enforce any specific design or pattern on these > exceptions. I would prefer to remove the params() function than add more > template magic. > > On Thu, Oct 22, 2020 at 1:18 AM Gabe Bl

[gem5-dev] Re: Changes to SE mode

2020-10-22 Thread Gabe Black via gem5-dev
For fans of the classics, you can look up my email with subject "Merging of FS and SE mode" from 2011, but I suspect that's too old for most people to have seen, and not completely the same as what I'm trying to do here. This is the other half of the workload concept which is already applied to FS

[gem5-dev] SimObject params() method

2020-10-22 Thread Gabe Black via gem5-dev
Hi folks. I'm looking at the SimObject header, and I see a few things in there which are marked as part of the API and maybe shouldn't be. Specifically I'm talking about the Params typedef, and the params() method. There is also the _params member variable which I can see being a part of the API

[gem5-dev] Re: A call for maintainers

2020-10-21 Thread Gabe Black via gem5-dev
I think when we first split things into areas for maintainers, we just went with the top level directories in the source tree. That was a good first approximation, but I think it will often make sense to break things down a little differently in practice, particularly with directories like ext

[gem5-dev] Re: Implementing PSHUFB instruction

2020-10-13 Thread Gabe Black via gem5-dev
g on this project. > > Cheers, > Jason > > On Mon, Oct 12, 2020 at 10:34 PM Gabe Black via gem5-dev < > gem5-dev@gem5.org> wrote: > >> Hi Hao. The shuffle microop is implemented in >> arch/x86/isa/microops/mediaop.isa. It looks like you'll need to do three

[gem5-dev] Re: Implementing PSHUFB instruction

2020-10-12 Thread Gabe Black via gem5-dev
Hi Hao. The shuffle microop is implemented in arch/x86/isa/microops/mediaop.isa. It looks like you'll need to do three things to implement PSHUFB. 1. Figure out a realistic way to get all three register operands into the instruction. The current version takes a destination register, and both

[gem5-dev] Re: simple simulator performance check?

2020-10-10 Thread Gabe Black via gem5-dev
t, generally. > > Cheers, > Jason > > On Mon, Oct 5, 2020 at 3:07 AM Gabe Black via gem5-dev > wrote: > >> Hey folks. I'm trying out using dynamically allocated arrays to track >> source and destination register indices in static and dynamic instructions >> rather

[gem5-dev] Register bank abstraction

2020-10-08 Thread Gabe Black via gem5-dev
Hey folks! I've been looking at some device models recently, both to fix them and to develop them, and I've seen a lot of boilerplate code which tries to figure out what size of data to extract from the packet, how to map that to registers, sometimes handling accesses that aren't on register

[gem5-dev] simple simulator performance check?

2020-10-05 Thread Gabe Black via gem5-dev
Hey folks. I'm trying out using dynamically allocated arrays to track source and destination register indices in static and dynamic instructions rather than fixed size arrays and would like to check what the impact on performance is. I used to use the twolf SPEC benchmark for that since it was

[gem5-dev] Re: Trouble building 20.1.0.0

2020-10-03 Thread Gabe Black via gem5-dev
Hi folks. I haven't dug into this too deeply, but it sounds like protobuf may also define NDEBUG, and it may leak into the rest of gem5? If that's what's happening, ideally we'll be able to get protobuf to stop doing that, etc., and we should look into how. A simpler approach to get you unstuck

[gem5-dev] PCI memory BARs broken on ARM

2020-10-01 Thread Gabe Black via gem5-dev
Hi folks. We locally just rebased and picked up a change where the ARM PCI controller's configuration was fixed so that it had the appropriate starting address for memory mappings. Now that that's correct, it means that instead of setting memory BARs to 0x4000 (for example) to get them in the

[gem5-dev] Re: MMU object vs. DTB and ITB

2020-09-21 Thread Gabe Black via gem5-dev
t to post the same patchset (which is: > removing the TLB from the CPU interface and make it interface with an MMU > instead) > > > > Giacomo > > > > *From:* Gabe Black via gem5-dev > *Sent:* 20 September 2020 04:44 > *To:* gem5 Developer List > *Cc:* Gabe Black

[gem5-dev] Re: MMU object vs. DTB and ITB

2020-09-19 Thread Gabe Black via gem5-dev
Oh, this will also absorb multilevel TLBs too, like how ARM has second level translation in some cases. This isn't really implemented in x86, but could also be used for it's multilevel translation in SVM and VT's nested page table schemes. Gabe On Sat, Sep 19, 2020 at 8:25 PM Gabe Black wrote:

[gem5-dev] MMU object vs. DTB and ITB

2020-09-19 Thread Gabe Black via gem5-dev
Hi folks. I've been thinking about how to rework the scanning-through-page-translation thing we currently do when translating a region of addresses through both the ITB and DTB. We currently do that one page at a time by trying one, and then the other. That requires knowing what "the" page size

[gem5-dev] Re: A few quick thoughts

2020-09-18 Thread Gabe Black via gem5-dev
nything >>> that directly stated that you aren't allowed to do that, without explicit >>> support I think it flies in the face of how C++ templates, types, etc. work >>> to the point where if you *did* find a way to do it, it would almost >>> certainly be a bug or

[gem5-dev] Re: A few quick thoughts

2020-09-18 Thread Gabe Black via gem5-dev
way to make it work. Gabe On Thu, Sep 17, 2020 at 2:53 PM Jason Lowe-Power wrote: > > > On Thu, Sep 17, 2020 at 2:48 PM Gabe Black via gem5-dev > wrote: > >> 1. Sounds good, I'll hopefully have some time to put together a CL in no >> too long (weekend?). >>

[gem5-dev] Re: A few quick thoughts

2020-09-17 Thread Gabe Black via gem5-dev
e.com/w/cpp/language/attributes/deprecated > > -- > Dr. Bobby R. Bruce > Room 2235, > Kemper Hall, UC Davis > Davis, > CA, 95616 > > web: https://www.bobbybruce.net > > > On Thu, Sep 17, 2020 at 8:25 AM Jason Lowe-Power via gem5-dev < > gem5-dev@gem5.org> w

[gem5-dev] A few quick thoughts

2020-09-17 Thread Gabe Black via gem5-dev
1. Use __builtin_expect() for panic, fatal, etc. Preexisting library functions like assert probably already have this, but our versions don't and have similar behavior patterns. This should improve performance. 2. Create template versions of the bits, etc functions in bitfields.hh which use

[gem5-dev] Re: Error in Building gem5

2020-09-13 Thread Gabe Black via gem5-dev
That looks like a problem we've had where gem5 half uses its own local libelf, and half uses the system one. It's been fixed on the develop branch and will be fixed in the next release which *should* happen in the next few weeks. I think this change should fix it on the current master branch.

[gem5-dev] Re: Error in Building gem5

2020-09-12 Thread Gabe Black via gem5-dev
I have a very similar setup and have been fixing problems like this recently. It's probably just because gcc version 10.2 has new warnings which are triggering and turning into errors because of -Werror. The version of python should have nothing to do with it. I must just have not tried a build

[gem5-dev] Re: Use of page size and TLBs in the prefetchers

2020-09-08 Thread Gabe Black via gem5-dev
Ok, no problem, that makes sense. Prefetching pages which are only physically contiguous could be counterproductive, and you'd need to know where that boundary is. Would it make sense to add a page size parameter to the prefetcher? It would be a little less automatic, but would avoid the

[gem5-dev] Re: ChunkGenerator granularity, interface

2020-09-08 Thread Gabe Black via gem5-dev
Yep, I agree. While the new thing can be inspired by the ChunkGenerator, unless it shares a significant chunk of implementation (not likely, there isn't a ton of code in ChunkGenerator), they don't have to actually be related to each other. I think particularly since in cases like the TLB example,

[gem5-dev] Re: Use of page size and TLBs in the prefetchers

2020-09-07 Thread Gabe Black via gem5-dev
Actually that's not *quite* the end for isa_traits.hh since the system class uses the PageBytes and PageShift internally to allocate physical memory. It's still very close though. Gabe On Mon, Sep 7, 2020 at 1:06 AM Gabe Black wrote: > Hi folks. I've *almost* eliminated use of the getPageBytes

[gem5-dev] ChunkGenerator granularity, interface

2020-09-07 Thread Gabe Black via gem5-dev
Hi folks. In gem5, there is a simple but useful utility class called the ChunkGenerator which takes a region of memory and a size, and breaks the region into chunks which are broken on that size aligned boundaries. So for instance, if you wanted to translate every page that some big array was

[gem5-dev] Use of page size and TLBs in the prefetchers

2020-09-07 Thread Gabe Black via gem5-dev
Hi folks. I've *almost* eliminated use of the getPageBytes and getPageShift functions in the System class, which in combination with a change from Andreas will eliminate the need for the isa_traits.hh switching header file. The only use left is in the Ruby and cache prefetchers:

[gem5-dev] Re: Scons minimum version breaks GCN-gpu dockerfile build

2020-09-02 Thread Gabe Black via gem5-dev
What's a ROCM? Gabe On Tue, Sep 1, 2020 at 11:43 AM Jason Lowe-Power via gem5-dev < gem5-dev@gem5.org> wrote: > Hi Dan, > > :facepalm: At least this is on develop and not the stable branch! > > I think we need to get input from Kyle on this since he developed that > docker image. TBH, I think

[gem5-dev] ARM build failures

2020-08-30 Thread Gabe Black via gem5-dev
Hi folks. I'm seeing a few build failures for ARM with gcc version 10.2. Since these look like they may be real bugs and I don't want to make a mess fixing them or do a bunch of research, I'll mention them here so we can collectively find the right fix. There are a lot of instances of these two:

[gem5-dev] Arch and operating system detection in SE mode

2020-08-29 Thread Gabe Black via gem5-dev
Hi folks. Right now, when you want to run a particular binary in SE mode, you assign it to the "workload" parameter of a CPU. When gem5 goes to load it, it passes it around to different loaders and sees which one knows how to load it. Then it passes it around a second time to see which process

[gem5-dev] Re: Namespace creation on develop branch

2020-08-29 Thread Gabe Black via gem5-dev
PTAL https://gem5-review.googlesource.com/c/public/gem5/+/33695 https://gem5.atlassian.net/browse/GEM5-753 Gabe On Thu, Aug 27, 2020 at 4:24 AM Daniel Carvalho via gem5-dev < gem5-dev@gem5.org> wrote: > Hello, > > > This message only concerns those who use the *develop* branch. > > > We have

[gem5-dev] switching to python 3 for config scripts?

2020-08-26 Thread Gabe Black via gem5-dev
Hi folks. We've been moving to python 3 for many things, but for gem5's built in python, aka config scripts, we still default to python 2 instead of python 3. When do we plan to change that? I ask because I ran into a problem where the python 2.7 pyconfig.h doesn't compile correctly on my desktop,

[gem5-dev] Re: Problem with libelf

2020-08-26 Thread Gabe Black via gem5-dev
For reasons I won't bother to get into here, I just fought with using python 3 as the interpreter in gem5, and reran into what I think was this issue: https://gem5.atlassian.net/browse/GEM5-731 After some digging I found that it was this same issue, so I'm extra motivated for it to be fixed now.

[gem5-dev] Re: problem running tests?

2020-08-24 Thread Gabe Black via gem5-dev
A couple thoughts I have are to reduce the enormous directory names the test results go in (when that works again), and also to make it easy to get the relevant details from a failure. I think I've said this somewhere else, but I think the debugging loop might look like: 1. Run tests. 2. See a

[gem5-dev] Re: problem running tests?

2020-08-24 Thread Gabe Black via gem5-dev
This at least seems reasonable, although I haven't thought about it long enough to commit to too strongly :-). I *used* to be able to find what I would need (with enough digging) in .testing-results/blah-blah, but now there are only two files in there, results.xml and results.pickle. Did this

[gem5-dev] Re: problem running tests?

2020-08-23 Thread Gabe Black via gem5-dev
Adding Bobby and Giacomo specifically, since I see their fingerprints on the testing stuff. Gabe On Sun, Aug 23, 2020 at 8:03 PM Gabe Black wrote: > At the risk of sounding over dramatic, this is a major problem. Before it > was difficult to see what happened when a test failed when running

[gem5-dev] Re: problem running tests?

2020-08-23 Thread Gabe Black via gem5-dev
At the risk of sounding over dramatic, this is a major problem. Before it was difficult to see what happened when a test failed when running the test automation, but now it's impossible. As far as I can tell, the results end up in a temp directory and are then wiped out and not copied anywhere. I

[gem5-dev] problem running tests?

2020-08-23 Thread Gabe Black via gem5-dev
Hey folks, I'm trying to run tests on a change I'm working on, and the test infrastructure is not actually saving any test results where it claims it will. I also tried selecting what ISAs to use, and after selecting all of them the run script claimed no tests would be run. Is this something

[gem5-dev] CPU/decoder interface restructuring

2020-08-20 Thread Gabe Black via gem5-dev
Hi folks. I would like to narrow and simplify the interface between the CPU and the decoder. I think I have a pretty decent working plan at the moment, and wanted to run this by everybody. *Existing design* Right now, there are three logical components which are bound together into the ISA

[gem5-dev] Re: Remove CP annotation support?

2020-08-19 Thread Gabe Black via gem5-dev
ost of which are >>> contributing to gem5 in their "spare time." Supporting such a sprawling >>> codebase is taking time away from making deeper and more impactful changes. >>> >>> In conclusion, I think you should remove the code! >>> >>&g

[gem5-dev] Re: Remove CP annotation support?

2020-08-19 Thread Gabe Black via gem5-dev
20." >> >> We have an extremely lean development team, most of which are >> contributing to gem5 in their "spare time." Supporting such a sprawling >> codebase is taking time away from making deeper and more impactful changes. >> >> In conclusion,

[gem5-dev] Remove CP annotation support?

2020-08-19 Thread Gabe Black via gem5-dev
Hi folks. I was doing some spelunking trying to eliminate more ISA related dependencies from common code, and I ran across the CPA (critical path annotation) support in, among maybe a few other places, base/cp_annotate.cc. This code can't actually compile since it depends on there being a

[gem5-dev] Decoder cache hit rate

2020-08-18 Thread Gabe Black via gem5-dev
Hi folks. I thought I'd do a quick measurement of the effectiveness of the various caches which cache StaticInsts from the decoder using X86. For SE mode, I did a very simple run of hello world. For such a short program, the hit rate was pretty low and I don't think representative. To get

[gem5-dev] document describing instruction decoding in gem5

2020-08-17 Thread Gabe Black via gem5-dev
Hi folks. I've been thinking about some changes I might want to make to how decoding is done for the various ISAs, how the work is split up between the decoder and the CPU, what decoders are and aren't allowed to do, and how some of the important but less visited aspects of x86 microcode work.

[gem5-dev] Re: Problem with libelf

2020-08-11 Thread Gabe Black via gem5-dev
I see that we had a local version of libelf as far back as when we started using scons in 2004, where we referred to it's SConscript in m5/libelf/SConscript (not src/m5 or util/m5, just m5), although that directory and all its history seems to have been dropped during one of the times we switched

[gem5-dev] Re: Problem with libelf

2020-08-11 Thread Gabe Black via gem5-dev
I'm pretty sure it's been that way "forever", where forever is defined as as far back as I can remember. Looking at the history, I see that Nate replaced a GNU libelf with "autoconf nastiness" (I can imagine), and replaced it with a freeBSD version in 2007, so it's been that way at least as long

[gem5-dev] Re: Build failed in Jenkins: Nightly #27

2020-08-07 Thread Gabe Black via gem5-dev
Sorry for the breakage, thanks for the fix! Gabe On Fri, Aug 7, 2020 at 8:03 AM Jason Lowe-Power via gem5-dev < gem5-dev@gem5.org> wrote: > Feel free to post a fix if you have one! > > Cheers, > Jason > > On Fri, Aug 7, 2020 at 7:58 AM Poremba, Matthew > wrote: > >> [AMD Public Use] >> >> >>

[gem5-dev] Re: Possible race condition (Remote GDB)

2020-08-07 Thread Gabe Black via gem5-dev
I think this code was originally written by Nate who is no longer with us. Looking at it, what I *think* it's doing starts in listen(). That sets up a poll queue event which listens for connection from gdb. When that gets triggered, that (slightly indirectly) calls connect which will check if

[gem5-dev] Minimum scons version?

2020-08-05 Thread Gabe Black via gem5-dev
Hi folks. Our scons scripts currently require (through a programmatic check) that you're using at least version 0.98.1. Since scons is now up to version 4.0, this version is ancient and so we effectively don't have a minimum. Because scons adds features, fixes bugs, etc, over time, it would be

[gem5-dev] Re: mercurial support?

2020-07-06 Thread Gabe Black via gem5-dev
an't see any reason to keep Mercurial-related cruft > in the new repo. > > Cheers, > Andreas > > On 05/07/2020 02:08, Gabe Black via gem5-dev wrote: > > Hi folks. Have we officially dropped support for checking out gem5 through > mercurial? If so, we should probably del

[gem5-dev] mercurial support?

2020-07-04 Thread Gabe Black via gem5-dev
Hi folks. Have we officially dropped support for checking out gem5 through mercurial? If so, we should probably delete the various bits and pieces lying around which were for that. If not then never mind... Gabe ___ gem5-dev mailing list --

[gem5-dev] Re: [Suggestion] Replace gem5-users mailing-list with Discourse

2020-07-02 Thread Gabe Black via gem5-dev
I haven't used Slack before (yeah, I know, behind the times :-), but I 100% agree with that last part. Having the perfect medium won't help if there aren't enough people around to actually use it to answer questions. Gabe On Thu, Jul 2, 2020 at 9:45 AM Andreas Sandberg via gem5-dev <

[gem5-dev] Re: bug squashing renamed pinned registers in o3?

2020-06-24 Thread Gabe Black via gem5-dev
tering this in a simulation which is using a CPU >switch or checkpoint save/restore > > > > Kind Regards > > > > Giacomo > > > > *From:* Gabe Black via gem5-dev > *Sent:* 23 June 2020 06:24 > *To:* gem5 Developer List > *Cc:* Gabe Black > *Subj

[gem5-dev] bug squashing renamed pinned registers in o3?

2020-06-22 Thread Gabe Black via gem5-dev
Hi folks, specifically ARM folks. We've been seeing a problem with O3 where when switching vector register renaming modes (full vectors vs vector elements), the CPU checks its bookkeeping and finds that a vector register is missing, ie with no instructions in flight, the free list has one fewer

[gem5-dev] broken style checker script

2020-06-12 Thread Gabe Black via gem5-dev
Btw, I ran into a bug in the style checker script which was checked in fairly recently. I commented on the CL, but I want to make sure somebody sees it and it doesn't get tuned out. https://gem5-review.googlesource.com/c/public/gem5/+/28588 Gabe ___

[gem5-dev] support for multiple threads over one remote GDB connection

2020-06-10 Thread Gabe Black via gem5-dev
Hey folks. I filed a bug in Jira a couple days ago about adding support for multiple threads within a single remote GDB session over here: https://gem5.atlassian.net/browse/GEM5-626?atlOrigin=eyJpIjoiNjE5ZDZlYzZkZTA2NDE3NGE3MGYyZTE3NWQ1YTk3NTQiLCJwIjoiaiJ9 It's fine (and welcome) for

[gem5-dev] Re: Helping with testing/CI/documentation

2020-06-05 Thread Gabe Black via gem5-dev
I think Bobby would be a good person to talk to. Gabe On Fri, Jun 5, 2020 at 11:53 AM michael upton via gem5-dev < gem5-dev@gem5.org> wrote: > Hi, > > I am interested in helping with CI and testing in general. > > I poked around jira, and can start there, but are there specific things > you

[gem5-dev] Re: checkpoint "schema"s

2020-06-01 Thread Gabe Black via gem5-dev
Oh, and the implication is that devices should fall into a certain schema, and as long as the configuration loading the checkpoint has objects in the same places using the same schemas it should just work. Checking for that could even be an automatic part of loading a checkpoint. Gabe On Mon,

[gem5-dev] checkpoint "schema"s

2020-06-01 Thread Gabe Black via gem5-dev
Hi folks. Another idea I had which I don't have time to look into is to have more rigorously defined contents and names for things in checkpoints. Right now, we just dump in whatever we have lying around in whatever way is convenient, occasionally causing checkpoint incompatibilities and making it

[gem5-dev] Re: ISA description structure

2020-06-01 Thread Gabe Black via gem5-dev
huge > > header definition inclusion. > > > > > > I also intend some day to try and reduce the usage of .isa in general, > > because it is too insane/hard to learn/debug. The decoder part is already > > basically pure C++ for ARM at least already, so a conversi

[gem5-dev] Re: Add AVX512 Support?

2020-05-31 Thread Gabe Black via gem5-dev
cience Department > University of California, Los Angeles > California, USA > 90024 > > Work Email: seanyukig...@gmail.com > Mobile :+1 310-447-4568 <(310)%20447-4568> > > > > > Gabe Black via gem5-dev 于2020年5月31日周日 下午7:44写道: > > > Hi Sean. I'm not

[gem5-dev] Re: ISA description structure

2020-05-31 Thread Gabe Black via gem5-dev
ly pure C++ for ARM at least already, so a conversion would be > trivial. And I wonder how much we could get rid of with modern C++ template > features from the execute itself. > > > > From: Gabe Black via gem5-dev > > Sent: Sunday, May 3

[gem5-dev] Re: ISA description structure

2020-05-31 Thread Gabe Black via gem5-dev
it is too insane/hard to learn/debug. The decoder part is already > basically pure C++ for ARM at least already, so a conversion would be > trivial. And I wonder how much we could get rid of with modern C++ template > features from the execute itself. > -------------- >

[gem5-dev] Re: Add AVX512 Support?

2020-05-31 Thread Gabe Black via gem5-dev
Hi Sean. I'm not aware of anyone working on AVX-512, but it would be nice if the AMD folks could chime in and confirm that. The x86 microcode was originally based off of the microcode for the K6 as described in a patent. The floating point parts of that patent were very vague and hand wavy, so I

[gem5-dev] ISA description structure

2020-05-30 Thread Gabe Black via gem5-dev
Hi folks. This is just a quick email with some thoughts on the structure of ISA descriptions in gem5, both to record my thinking thus far, and to encourage discussion. Right now, the structure of an ISA description flows from the specification of the decode function. That takes an instruction

[gem5-dev] Re: c64 simulation

2020-05-11 Thread Gabe Black via gem5-dev
uld serve as a good small ISA example. > > Is it running ROMs fine? Is the simulation fast enough for interactive > play? Wiki says it run at 1MHz so its just about what Atomic does, so I'm > guessing it could. > > ---------- > *From:* Gabe Black via gem5

[gem5-dev] c64 simulation

2020-05-10 Thread Gabe Black via gem5-dev
Hi folks. For my own amusement, I've been working on a c64 emulator based on gem5 which can be built in using EXTRAS. Would it make sense to put that up on gerrit somewhere in its own repository? I put what I have so far in a directory called "toys" to make it clear it's just for fun. Gabe

[gem5-dev] Re: review flurry

2020-04-28 Thread Gabe Black via gem5-dev
; exciting! > > Remember, we'll have a two week time period for deep testing on the > "staging" branch before we make the final release. The purpose of this time > period is to catch all of the remaining bugs that we can. > > Cheers, > Jason > > On Mon, Apr 27

[gem5-dev] review flurry

2020-04-27 Thread Gabe Black via gem5-dev
Hey everybody, lets slow down here a little so that I have a chance to actually see a review before the change gets checked in. I think we have at least one bug checked in already. If a change hangs around for months that's too long, but at least a day so everyone has a chance to see what's going

[gem5-dev] Re: keep lua bindings for m5 ops?

2020-04-25 Thread Gabe Black via gem5-dev
So, I looked into this a little more and tried switching to 5.3. The problem there is subtle, and is that 5.1 puts its headers in their own directory under /usr/include, at least on my system, and 5.3 puts its headers right in the top directory, in /usr/include directly. When you run pkg-config,

[gem5-dev] Pseudo instruction based gem5 ops on ARM

2020-04-23 Thread Gabe Black via gem5-dev
Hi ARM gem5 folks. I've been trying to develop some tests for the various forms of calling gem5 ops, and am trying to run them on QEMU as an easy way to (approximately) run them on other architectures. I've run into a few problems which I've been discussing with the QEMU folks, and outside of a

Re: [gem5-dev] changeset in gem5: x86: Enable three bits in the FamilyModelStep...

2015-02-20 Thread Gabe Black via gem5-dev
features through the xsave setting. Can you please let me know which of the bits in the CpuidResult vector I should disable to test if xsave is the problem? Thanks! Joel On Wed, Jan 7, 2015 at 12:06 AM, Gabe Black via gem5-dev gem5-dev@gem5.org wrote: changeset 5d119a460f15

[gem5-dev] Removing ExtMachInst concept

2015-02-11 Thread Gabe Black via gem5-dev
I'd like to remove the ExtMachInst concept from gem5, or at least hide it within the ISAs that need it. The only place where it isn't obvious how to do that is in the Minor cpu where it treats the ExtMachInst as a 64 bit integer (!) and masks it against a bit mask (!) to see when certain

Re: [gem5-dev] Removing ExtMachInst concept

2015-02-11 Thread Gabe Black via gem5-dev
need to have any additional state in ExtMachInst relative to the MachInst object. If you end up going that direction, though, what's the advantage of eliminating ExtMachInst vs. just defining ExtMachInst == MachInst for that ISA? Steve On Wed, Feb 11, 2015 at 4:52 PM, Gabe Black via gem5-dev

Re: [gem5-dev] Removing ExtMachInst concept

2015-02-11 Thread Gabe Black via gem5-dev
need to have any additional state in ExtMachInst relative to the MachInst object. If you end up going that direction, though, what's the advantage of eliminating ExtMachInst vs. just defining ExtMachInst == MachInst for that ISA? Steve On Wed, Feb 11, 2015 at 4:52 PM, Gabe Black via gem5

Re: [gem5-dev] Review Request 2642: syscall_emul: fix warning with wrong syscall name and nix extra whitespace

2015-02-06 Thread Gabe Black via gem5-dev
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2642/#review5862 --- Ship it! Ship It! - Gabe Black On Feb. 6, 2015, 10:07 p.m., Brandon

[gem5-dev] Decoding using decoder state

2015-02-04 Thread Gabe Black via gem5-dev
In the x86 decoder, some architectural state (CPU mode, a couple other things) is used to pick an active decode cache from a hash map of caches. That state could then be used when decoding instructions since we'd still always get the same thing for a particular ExtMachInst given a particular

Re: [gem5-dev] Decoding using decoder state

2015-02-04 Thread Gabe Black via gem5-dev
I realize the context for this might not be something everybody is familiar with. If you need me to explain what this is about more I can do that. Gabe On Wed, Feb 4, 2015 at 2:23 PM, Gabe Black gabebl...@google.com wrote: In the x86 decoder, some architectural state (CPU mode, a couple other

[gem5-dev] fxsave and fxrstor assume 64 bit mode

2015-02-01 Thread Gabe Black via gem5-dev
I just noticed that the fxsave and fxrstor implementations Andreas did (going by the copyright header in the file) incorrectly assume that the CPU is in 64 bit mode and save XMM8-15 unconditionally. I'll likely put together a patch to fix that, but I wanted to mention it here so it didn't slip

Re: [gem5-dev] windows fs boot and simulation

2015-01-29 Thread Gabe Black via gem5-dev
to contribute back to the public code base). Steve On Thu, Jan 29, 2015 at 1:38 AM, Gabe Black via gem5-dev gem5-dev@gem5.org wrote: Hi Mike. When we boot Linux on gem5, the simulator acts as the bootloader. It unpacks the kernel, provides various tables in memory that would normally

Re: [gem5-dev] windows fs boot and simulation

2015-01-28 Thread Gabe Black via gem5-dev
Hi Mike. When we boot Linux on gem5, the simulator acts as the bootloader. It unpacks the kernel, provides various tables in memory that would normally be provided by the BIOS/firmware, does some setup of machine state, and then jumps to the kernel. On a real system, the components that get you to

Re: [gem5-dev] Review Request 2557: x86: kvm: Fix the KVM CPU in SE and FS on Intel CPUs.

2015-01-21 Thread Gabe Black via gem5-dev
On Jan. 21, 2015, 9:22 p.m., mike upton wrote: src/arch/x86/process.cc, lines 218-237 http://reviews.gem5.org/r/2557/diff/2/?file=42948#file42948line218 For AMD systems, the sys descriptors need to come first. On intel systems they need to come second. I do not know

Re: [gem5-dev] Review Request 2557: x86: kvm: Fix the KVM CPU in SE and FS on Intel CPUs.

2015-01-21 Thread Gabe Black via gem5-dev
On Jan. 21, 2015, 9:22 p.m., mike upton wrote: src/arch/x86/process.cc, lines 218-237 http://reviews.gem5.org/r/2557/diff/2/?file=42948#file42948line218 For AMD systems, the sys descriptors need to come first. On intel systems they need to come second. I do not know

Re: [gem5-dev] Bug With Thread Suspend Instructions, Interrupts, x86 O3 CPU?

2015-01-20 Thread Gabe Black via gem5-dev
It sounds like a bug/race condition in the O3 CPU, which I think you already knew. You could try moving the suspend call into a fault returned by the MicroHalt microop instead of the instruction itself. That might break the race, although it's not really fixing the issue with O3. Gabe On Tue,

Re: [gem5-dev] Review Request 2557: x86: kvm: Fix the KVM CPU in SE and FS on Intel CPUs.

2015-01-19 Thread Gabe Black via gem5-dev
On Jan. 16, 2015, 11:56 p.m., mike upton wrote: src/arch/x86/process.cc, lines 212-213 http://reviews.gem5.org/r/2557/diff/2/?file=42948#file42948line212 when limitHigh and limitLow get set by dataSegDesc(), it seems that limitHigh and limitLow get reversed. This patch

Re: [gem5-dev] Review Request 2557: x86: kvm: Fix the KVM CPU in SE and FS on Intel CPUs.

2015-01-19 Thread Gabe Black via gem5-dev
On Jan. 16, 2015, 11:28 p.m., mike upton wrote: src/arch/x86/utility.hh, line 219 http://reviews.gem5.org/r/2557/diff/2/?file=42952#file42952line219 Is there a reason the desc.l does not get set for the dataSegDesc()? code sets p,l,d,g,s. Yes. The long mode bit only means

Re: [gem5-dev] Review Request 2557: x86: kvm: Fix the KVM CPU in SE and FS on Intel CPUs.

2015-01-15 Thread Gabe Black via gem5-dev
On Jan. 16, 2015, 12:44 a.m., mike upton wrote: src/arch/x86/regs/misc.hh, line 922 http://reviews.gem5.org/r/2557/diff/2/?file=42949#file42949line922 really 32, 0 in the new code? Yeah, I think that should be 31, 0 - Gabe

Re: [gem5-dev] Review Request 2604: cpu: commit probe notification on every microop or macroop

2015-01-14 Thread Gabe Black via gem5-dev
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2604/#review5755 --- This will break GDB single stepping. - Gabe Black On Jan. 14, 2015,

Re: [gem5-dev] Review Request 2604: cpu: commit probe notification on every microop or macroop

2015-01-14 Thread Gabe Black via gem5-dev
On Jan. 14, 2015, 8:52 p.m., Gabe Black wrote: This will break GDB single stepping. Nikos Nikoleris wrote: If I undestand correctly, it won't be affected. When set, the GDB single step schedules the corresponding event at the comInstEventQueue. The comInstEventQueue services

Re: [gem5-dev] Review Request 2546: scons: Avoid implicit command dependencies

2015-01-13 Thread Gabe Black via gem5-dev
On Jan. 13, 2015, 10:53 p.m., Andreas Hansson wrote: I suspect I am the only one annoyed by this...unless someone else feels the same I will discard the patch. If this is what I think it is, it can be pretty annoying when running regressions. The param stuff swamps the console and its

Re: [gem5-dev] SMT with x86

2015-01-08 Thread Gabe Black via gem5-dev
t0 must always return 0, and writes to it must always be ignored (or overwritten before the next instruction). You're corrupted program counter might be because you're using physical registers which aren't actually there, accessing beyond the end of an array and reading/writing something random.

[gem5-dev] changeset in gem5: stats: x86: Update stats for the CPUID change.

2015-01-07 Thread Gabe Black via gem5-dev
changeset 469cf1ea40f5 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=469cf1ea40f5 description: stats: x86: Update stats for the CPUID change. diffstat: tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini | 6 +

[gem5-dev] changeset in gem5: test: Add a unittest for the BitUnion types.

2015-01-07 Thread Gabe Black via gem5-dev
changeset 04923a93f2b5 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=04923a93f2b5 description: test: Add a unittest for the BitUnion types. diffstat: src/unittest/SConscript |1 + src/unittest/bituniontest.cc | 182

Re: [gem5-dev] Review Request 2553: dev: Prevent intel 8254 timer events firing before startup

2015-01-07 Thread Gabe Black via gem5-dev
Unless you're using the KVM CPU or human input (neither should be true for regressions), gem5 is supposed to be entirely deterministic. If you're worried about last nights regressions, the x86 problem was because I pushed a CPUID related change but hadn't generated a stats CL to go with it. While

Re: [gem5-dev] Review Request 2595: x86: Delay X86 table walk on receiving walker response

2015-01-06 Thread Gabe Black via gem5-dev
On Jan. 5, 2015, 10:48 p.m., Andreas Hansson wrote: Can you explain the sequence of events that result in bad behavior? If possible (which is not necessarily the case), it would be best to fix this without adding arbitrary delays. Andreas Hansson wrote: The crossbar is processing

Re: [gem5-dev] Review Request 2590: cpuid, x86: Revert Enabling more features in CPUid

2015-01-06 Thread Gabe Black via gem5-dev
On Jan. 6, 2015, 7:21 p.m., Steve Reinhardt wrote: Can you be more specific about what doesn't work? Do we really need to back out all of the enabled features? Also, it would be nice to replace the comments with different comments, rather than just getting rid of them. If you

[gem5-dev] changeset in gem5: x86: Enable three bits in the FamilyModelStep...

2015-01-06 Thread Gabe Black via gem5-dev
changeset 5d119a460f15 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=5d119a460f15 description: x86: Enable three bits in the FamilyModelStepping ECX CPUID bitfield. These are for the monitor/mwait instructions, SSSE3, and XSAVE. diffstat:

[gem5-dev] changeset in gem5: cpuid, x86: Revert Enabling more features in...

2015-01-06 Thread Gabe Black via gem5-dev
changeset e9bc4cde5d8e in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=e9bc4cde5d8e description: cpuid, x86: Revert Enabling more features in CPUid That change enables CPUID bits for features that aren't implemented in gem5. If a simulated system

  1   2   3   4   >