[gem5-dev] Change in gem5/gem5[develop]: arch-arm: dtb_addr is already encoding the loadAddrOffset

2021-01-18 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39216 )



Change subject: arch-arm: dtb_addr is already encoding the loadAddrOffset
..

arch-arm: dtb_addr is already encoding the loadAddrOffset

This fixes a bug in AArch32 where the dtb_address is
adding the loadAddrOffset twice to the dtb base address
after

https://gem5-review.googlesource.com/c/public/gem5/+/35076

Change-Id: Ia8bd35a02d998c54fbc3a889739c9abbeb506d96
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/freebsd/fs_workload.cc
M src/arch/arm/linux/fs_workload.cc
2 files changed, 5 insertions(+), 5 deletions(-)



diff --git a/src/arch/arm/freebsd/fs_workload.cc  
b/src/arch/arm/freebsd/fs_workload.cc

index 8eb3c70..cc0151b 100644
--- a/src/arch/arm/freebsd/fs_workload.cc
+++ b/src/arch/arm/freebsd/fs_workload.cc
@@ -95,7 +95,7 @@
 // Kernel supports flattened device tree and dtb file specified.
 // Using Device Tree Blob to describe system configuration.
 inform("Loading DTB file: %s at address %#x\n", params().dtb_filename,
-params().dtb_addr + _loadAddrOffset);
+params().dtb_addr);

 auto *dtb_file = new ::Loader::DtbFile(params().dtb_filename);

@@ -108,7 +108,7 @@
 bootReleaseAddr = ra & ~ULL(0x7F);

 dtb_file->buildImage().
-offset(params().dtb_addr + _loadAddrOffset).
+offset(params().dtb_addr).
 write(system->physProxy);
 delete dtb_file;

@@ -116,7 +116,7 @@
 for (auto *tc: system->threads) {
 tc->setIntReg(0, 0);
 tc->setIntReg(1, params().machine_type);
-tc->setIntReg(2, params().dtb_addr + _loadAddrOffset);
+tc->setIntReg(2, params().dtb_addr);
 }
 }

diff --git a/src/arch/arm/linux/fs_workload.cc  
b/src/arch/arm/linux/fs_workload.cc

index f05fd6f..b296b68 100644
--- a/src/arch/arm/linux/fs_workload.cc
+++ b/src/arch/arm/linux/fs_workload.cc
@@ -151,7 +151,7 @@
 DPRINTF(Loader, "Boot atags was %d bytes in total\n", size << 2);
 DDUMP(Loader, boot_data, size << 2);

-system->physProxy.writeBlob(params().dtb_addr + _loadAddrOffset,
+system->physProxy.writeBlob(params().dtb_addr,
 boot_data, size << 2);

 delete[] boot_data;
@@ -170,7 +170,7 @@
 for (auto *tc: system->threads) {
 tc->setIntReg(0, 0);
 tc->setIntReg(1, params().machine_type);
-tc->setIntReg(2, params().dtb_addr + _loadAddrOffset);
+tc->setIntReg(2, params().dtb_addr);
 }
 }
 }

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Gerrit-Branch: develop
Gerrit-Change-Id: Ia8bd35a02d998c54fbc3a889739c9abbeb506d96
Gerrit-Change-Number: 39216
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[develop]: sim: Add units to src/sim

2021-01-18 Thread Hoa Nguyen (Gerrit) via gem5-dev
  "Number of power state transitions"),
+ADD_STAT_WITH_UNIT(numPwrMatchStateTransitions, UNIT_COUNT,
+   "Number of power state transitions due match  
request"),

+ADD_STAT_WITH_UNIT(ticksClkGated, UNIT_TICK,
+   "Distribution of time spent in the clock gated  
state"),

+ADD_STAT_WITH_UNIT(pwrStateResidencyTicks, UNIT_TICK,
+   "Cumulative time (in ticks) in various power  
states")

 {
 }

diff --git a/src/sim/process.cc b/src/sim/process.cc
index 7819820..4b11390 100644
--- a/src/sim/process.cc
+++ b/src/sim/process.cc
@@ -129,7 +129,7 @@
   _pgid(params.pgid), drivers(params.drivers),
   fds(make_shared(params.input, params.output,  
params.errout)),

   childClearTID(0),
-  ADD_STAT(numSyscalls, "Number of system calls")
+  ADD_STAT_WITH_UNIT(numSyscalls, UNIT_COUNT, "Number of system calls")
 {
 if (_pid >= System::maxPID)
 fatal("_pid is too large: %d", _pid);
diff --git a/src/sim/root.cc b/src/sim/root.cc
index 4927940..e0a544b 100644
--- a/src/sim/root.cc
+++ b/src/sim/root.cc
@@ -54,14 +54,21 @@

 Root::RootStats::RootStats()
 : Stats::Group(nullptr),
-ADD_STAT(simSeconds, "Number of seconds simulated"),
-ADD_STAT(simTicks, "Number of ticks simulated"),
-ADD_STAT(finalTick, "Number of ticks from beginning of simulation "
-"(restored from checkpoints and never reset)"),
-ADD_STAT(simFreq, "Frequency of simulated ticks"),
-ADD_STAT(hostSeconds, "Real time elapsed on the host"),
-ADD_STAT(hostTickRate, "Simulator tick rate (ticks/s)"),
-ADD_STAT(hostMemory, "Number of bytes of host memory used"),
+ADD_STAT_WITH_UNIT(simSeconds, UNIT_SECOND, "Number of seconds  
simulated"),

+ADD_STAT_WITH_UNIT(simTicks, UNIT_TICK, "Number of ticks simulated"),
+ADD_STAT_WITH_UNIT(finalTick, UNIT_TICK,
+   "Number of ticks from beginning of simulation "
+   "(restored from checkpoints and never reset)"),
+ADD_STAT_WITH_UNIT(simFreq,
+   UNIT_RATE(Stats::Units::Count, Stats::Units::Tick),
+   "Frequency of simulated ticks"),
+ADD_STAT_WITH_UNIT(hostSeconds, UNIT_SECOND,
+   "Real time elapsed on the host"),
+ADD_STAT_WITH_UNIT(hostTickRate,
+   UNIT_RATE(Stats::Units::Tick, Stats::Units::Second),
+   "Simulator tick rate (ticks/s)"),
+ADD_STAT_WITH_UNIT(hostMemory, UNIT_BYTE,
+   "Number of bytes of host memory used"),

 statTime(true),
 startTick(0)
diff --git a/src/sim/voltage_domain.cc b/src/sim/voltage_domain.cc
index f6f8396..4208278 100644
--- a/src/sim/voltage_domain.cc
+++ b/src/sim/voltage_domain.cc
@@ -139,7 +139,7 @@

 VoltageDomain::VoltageDomainStats::VoltageDomainStats(VoltageDomain )
 : Stats::Group(),
-ADD_STAT(voltage, "Voltage in Volts")
+ADD_STAT_WITH_UNIT(voltage, UNIT_VOLT, "Voltage in Volts")
 {
 voltage.method(, ::voltage);
 }
diff --git a/src/sim/workload.hh b/src/sim/workload.hh
index f7d3b06..53706eb 100644
--- a/src/sim/workload.hh
+++ b/src/sim/workload.hh
@@ -50,8 +50,10 @@
 Stats::Scalar quiesce;

 InstStats(Stats::Group *parent) : Stats::Group(parent, "inst"),
-ADD_STAT(arm, "number of arm instructions executed"),
-ADD_STAT(quiesce, "number of quiesce instructions  
executed")

+    ADD_STAT_WITH_UNIT(arm, UNIT_COUNT,
+   "number of arm instructions executed"),
+ADD_STAT_WITH_UNIT(quiesce, UNIT_COUNT,
+   "number of quiesce instructions  
executed")

 {}

 } instStats;

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Gerrit-Change-Id: I5fa147aa1319d62be1790bbd74fd097ac566f808
Gerrit-Change-Number: 39296
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Gerrit-Owner: Hoa Nguyen 
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[gem5-dev] Change in gem5/gem5[develop]: arch: Remove copyMiscRegs from utility.hh.

2021-01-18 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39325 )



Change subject: arch: Remove copyMiscRegs from utility.hh.
..

arch: Remove copyMiscRegs from utility.hh.

This function is occasionally used internally in copyRegs, but is not
used by anything else and doesn't need to be publically exposed in the
header file.

Change-Id: Id02a77e7dd19c6c089a408bfe0099466822c523d
---
M src/arch/arm/utility.hh
M src/arch/mips/utility.cc
M src/arch/mips/utility.hh
M src/arch/power/utility.cc
M src/arch/power/utility.hh
M src/arch/sparc/utility.hh
M src/arch/x86/utility.hh
7 files changed, 5 insertions(+), 22 deletions(-)



diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 302967b..853643b 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -86,12 +86,6 @@

 void copyRegs(ThreadContext *src, ThreadContext *dest);

-static inline void
-copyMiscRegs(ThreadContext *src, ThreadContext *dest)
-{
-panic("Copy Misc. Regs Not Implemented Yet\n");
-}
-
 /** Send an event (SEV) to a specific PE if there isn't
  * already a pending event */
 void sendEvent(ThreadContext *tc);
diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index cf8515f..7f98122 100644
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -228,10 +228,4 @@
 dest->pcState(src->pcState());
 }

-void
-copyMiscRegs(ThreadContext *src, ThreadContext *dest)
-{
-panic("Copy Misc. Regs Not Implemented Yet\n");
-}
-
 } // namespace MipsISA
diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index eb7f74a..1804680 100644
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -73,7 +73,6 @@
 }

 void copyRegs(ThreadContext *src, ThreadContext *dest);
-void copyMiscRegs(ThreadContext *src, ThreadContext *dest);

 inline void
 advancePC(PCState , const StaticInstPtr )
diff --git a/src/arch/power/utility.cc b/src/arch/power/utility.cc
index bed0be9..9003b13 100644
--- a/src/arch/power/utility.cc
+++ b/src/arch/power/utility.cc
@@ -35,6 +35,11 @@
 namespace PowerISA {

 void
+copyMiscRegs(ThreadContext *stc, ThreadContext *dest)
+{
+}
+
+void
 copyRegs(ThreadContext *src, ThreadContext *dest)
 {
 // First loop through the integer registers.
diff --git a/src/arch/power/utility.hh b/src/arch/power/utility.hh
index 7c892d4..03df7fb 100644
--- a/src/arch/power/utility.hh
+++ b/src/arch/power/utility.hh
@@ -39,11 +39,6 @@

 void copyRegs(ThreadContext *src, ThreadContext *dest);

-static inline void
-copyMiscRegs(ThreadContext *src, ThreadContext *dest)
-{
-}
-
 inline void
 advancePC(PCState , const StaticInstPtr )
 {
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index 2bf8af0..792d7c4 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -43,8 +43,6 @@

 void copyRegs(ThreadContext *src, ThreadContext *dest);

-void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
-
 inline void
 advancePC(PCState , const StaticInstPtr )
 {
diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index a7c2dfc..9cd4e94 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -46,8 +46,6 @@
 {
 void copyRegs(ThreadContext *src, ThreadContext *dest);

-void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
-
 inline void
 advancePC(PCState , const StaticInstPtr )
 {

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Gerrit-Change-Number: 39325
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[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Move buildRetPC into the StaticInst class.

2021-01-18 Thread Gabe Black (Gerrit) via gem5-dev
etPC.advance();
-retPC.pc(curPC.npc());
-return retPC;
-}
-
 inline void
 copyRegs(ThreadContext *src, ThreadContext *dest)
 {
diff --git a/src/arch/sparc/insts/static_inst.hh  
b/src/arch/sparc/insts/static_inst.hh

index 0237c98..eeb4bd9 100644
--- a/src/arch/sparc/insts/static_inst.hh
+++ b/src/arch/sparc/insts/static_inst.hh
@@ -111,6 +111,15 @@
 {
 return simpleAsBytes(buf, size, machInst);
 }
+
+PCState
+buildRetPC(const PCState , const PCState ) const override
+{
+PCState ret = callPC;
+ret.uEnd();
+ret.pc(curPC.npc());
+return ret;
+}
 };

 }
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index 8ec3e10..2bf8af0 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -41,15 +41,6 @@
 namespace SparcISA
 {

-inline PCState
-buildRetPC(const PCState , const PCState )
-{
-PCState ret = callPC;
-ret.uEnd();
-ret.pc(curPC.npc());
-return ret;
-}
-
 void copyRegs(ThreadContext *src, ThreadContext *dest);

 void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/x86/insts/static_inst.hh  
b/src/arch/x86/insts/static_inst.hh

index de41f47..6b12cf6 100644
--- a/src/arch/x86/insts/static_inst.hh
+++ b/src/arch/x86/insts/static_inst.hh
@@ -179,6 +179,14 @@
 {
 pcState.advance();
 }
+
+PCState
+buildRetPC(const PCState , const PCState ) const  
override

+{
+PCState retPC = callPC;
+retPC.uEnd();
+return retPC;
+}
 };
 }

diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index 79274ca..a7c2dfc 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -44,15 +44,6 @@

 namespace X86ISA
 {
-
-inline PCState
-buildRetPC(const PCState , const PCState )
-{
-PCState retPC = callPC;
-retPC.uEnd();
-return retPC;
-}
-
 void copyRegs(ThreadContext *src, ThreadContext *dest);

 void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/cpu/pred/bpred_unit.cc b/src/cpu/pred/bpred_unit.cc
index e618fb5..5d6c969 100644
--- a/src/cpu/pred/bpred_unit.cc
+++ b/src/cpu/pred/bpred_unit.cc
@@ -166,7 +166,7 @@
 // If it's a function return call, then look up the address
 // in the RAS.
 TheISA::PCState rasTop = RAS[tid].top();
-target = TheISA::buildRetPC(pc, rasTop);
+target = inst->buildRetPC(pc, rasTop);

 // Record the top entry of the RAS, and its index.
 predict_record.usedRAS = true;
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index e5d9753..5e81a79 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -340,6 +340,13 @@

 virtual void advancePC(TheISA::PCState ) const = 0;

+virtual TheISA::PCState
+buildRetPC(const TheISA::PCState ,
+const TheISA::PCState ) const
+{
+panic("buildRetPC not defined!");
+}
+
 /**
  * Return the microop that goes with a particular micropc. This should
  * only be defined/used in macroops which will contain microops

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[gem5-dev] Change in gem5/gem5[develop]: sim: Eliminate the generic PseudoInstABI.

2021-01-18 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39319 )



Change subject: sim: Eliminate the generic PseudoInstABI.
..

sim: Eliminate the generic PseudoInstABI.

Calls to gem5 ops are now handled by locally defined ABIs in each of the
ISAs that support them.

Change-Id: I30aac7b49fa8dc8e18aa7724338d1fd2adacda90
---
M src/sim/pseudo_inst.hh
1 file changed, 3 insertions(+), 24 deletions(-)



diff --git a/src/sim/pseudo_inst.hh b/src/sim/pseudo_inst.hh
index d244adb..b0b65c6 100644
--- a/src/sim/pseudo_inst.hh
+++ b/src/sim/pseudo_inst.hh
@@ -45,35 +45,14 @@

 class ThreadContext;

-#include "arch/utility.hh"
 #include "base/bitfield.hh"
+#include "base/logging.hh"
+#include "base/trace.hh"
 #include "base/types.hh" // For Tick and Addr data types.
+#include "cpu/thread_context.hh"
 #include "debug/PseudoInst.hh"
 #include "sim/guest_abi.hh"

-struct PseudoInstABI
-{
-using State = int;
-};
-
-namespace GuestABI
-{
-
-template <>
-struct Argument
-{
-static uint64_t
-get(ThreadContext *tc, PseudoInstABI::State )
-{
-uint64_t result =
-TheISA::getArgument(tc, state, sizeof(uint64_t), false);
-state++;
-return result;
-}
-};
-
-} // namespace GuestABI
-
 namespace PseudoInst
 {


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[gem5-dev] Change in gem5/gem5[develop]: arm: Export the mostly generic syscall ABI.

2021-01-18 Thread Gabe Black (Gerrit) via gem5-dev
arm/se_workload.hh b/src/arch/arm/se_workload.hh
index cad350e..8538edd 100644
--- a/src/arch/arm/se_workload.hh
+++ b/src/arch/arm/se_workload.hh
@@ -28,10 +28,9 @@
 #ifndef __ARCH_ARM_SE_WORKLOAD_HH__
 #define __ARCH_ARM_SE_WORKLOAD_HH__

+#include "arch/arm/reg_abi.hh"
 #include "params/ArmSEWorkload.hh"
 #include "sim/se_workload.hh"
-#include "sim/syscall_abi.hh"
-#include "sim/syscall_desc.hh"

 namespace ArmISA
 {
@@ -51,42 +50,10 @@

 ::Loader::Arch getArch() const override { return ::Loader::Arm64; }

-struct SyscallABI32 : public GenericSyscallABI32
-{
-static const std::vector ArgumentRegs;
-};
-
-struct SyscallABI64 : public GenericSyscallABI64
-{
-static const std::vector ArgumentRegs;
-};
+using SyscallABI32 = RegABI32;
+using SyscallABI64 = RegABI64;
 };

 } // namespace ArmISA

-namespace GuestABI
-{
-
-template 
-struct Argument::value &&
-ABI::template IsWide::value>>
-{
-static Arg
-get(ThreadContext *tc, typename ABI::State )
-{
-// 64 bit arguments are passed starting in an even register.
-if (state % 2)
-state++;
-panic_if(state + 1 >= ABI::ArgumentRegs.size(),
-"Ran out of syscall argument registers.");
-auto low = ABI::ArgumentRegs[state++];
-auto high = ABI::ArgumentRegs[state++];
-return (Arg)ABI::mergeRegs(tc, low, high);
-}
-};
-
-} // namespace GuestABI
-
 #endif // __ARCH_ARM_SE_WORKLOAD_HH__

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[gem5-dev] Change in gem5/gem5[develop]: riscv: Export the system call ABI for use in gem5 ops.

2021-01-18 Thread Gabe Black (Gerrit) via gem5-dev
16, 17};
 const int AMOTempReg = 32;

diff --git a/src/arch/riscv/se_workload.hh b/src/arch/riscv/se_workload.hh
index e0be5a1..d6df19c 100644
--- a/src/arch/riscv/se_workload.hh
+++ b/src/arch/riscv/se_workload.hh
@@ -28,11 +28,11 @@
 #ifndef __ARCH_RISCV_SE_WORKLOAD_HH__
 #define __ARCH_RISCV_SE_WORKLOAD_HH__

+#include "arch/riscv/reg_abi.hh"
 #include "arch/riscv/registers.hh"
 #include "params/RiscvSEWorkload.hh"
 #include "sim/se_workload.hh"
 #include "sim/syscall_abi.hh"
-#include "sim/syscall_desc.hh"

 namespace RiscvISA
 {
@@ -53,10 +53,7 @@
 ::Loader::Arch getArch() const override { return ::Loader::Riscv64; }

 //FIXME RISCV needs to handle 64 bit arguments in its 32 bit ISA.
-struct SyscallABI : public GenericSyscallABI64
-{
-static const std::vector ArgumentRegs;
-};
+using SyscallABI = RegABI64;
 };

 } // namespace RiscvISA

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[gem5-dev] Change in gem5/gem5[develop]: arch: Eliminate the getArgument function.

2021-01-18 Thread Gabe Black (Gerrit) via gem5-dev
h
+++ b/src/arch/power/utility.hh
@@ -58,8 +58,6 @@
 pc.advance();
 }

-uint64_t getArgument(ThreadContext *tc, int , uint16_t size, bool  
fp);

-
 static inline bool
 inUserMode(ThreadContext *tc)
 {
diff --git a/src/arch/riscv/utility.hh b/src/arch/riscv/utility.hh
index d4cf221..1f82d2b 100644
--- a/src/arch/riscv/utility.hh
+++ b/src/arch/riscv/utility.hh
@@ -107,19 +107,6 @@
 return retPC;
 }

-inline uint64_t
-getArgument(ThreadContext *tc, int , uint16_t size, bool fp)
-{
-panic_if(fp, "getArgument(): Floating point arguments not  
implemented");
-panic_if(size != 8, "getArgument(): Can only handle 64-bit  
arguments.");

-panic_if(number >= ArgumentRegs.size(),
- "getArgument(): Don't know how to handle stack arguments");
-
-// The first 8 integer arguments are passed in registers, the rest
-// are passed on the stack.
-return tc->readIntReg(ArgumentRegs[number]);
-}
-
 inline void
 copyRegs(ThreadContext *src, ThreadContext *dest)
 {
diff --git a/src/arch/sparc/utility.cc b/src/arch/sparc/utility.cc
index 66fabd1..a0c0f8b 100644
--- a/src/arch/sparc/utility.cc
+++ b/src/arch/sparc/utility.cc
@@ -31,31 +31,8 @@
 #include "arch/sparc/faults.hh"
 #include "mem/port_proxy.hh"

-namespace SparcISA {
-
-
-// The caller uses %o0-%05 for the first 6 arguments even if their floating
-// point. Double precision floating point values take two registers/args.
-// Quads, structs, and unions are passed as pointers. All arguments beyond
-// the sixth are passed on the stack past the 16 word window save area,
-// space for the struct/union return pointer, and space reserved for the
-// first 6 arguments which the caller may use but doesn't have to.
-uint64_t
-getArgument(ThreadContext *tc, int , uint16_t size, bool fp)
+namespace SparcISA
 {
-panic_if(!FullSystem, "getArgument() only implemented for full  
system");

-
-const int NumArgumentRegs = 6;
-if (number < NumArgumentRegs) {
-return tc->readIntReg(8 + number);
-} else {
-Addr sp = tc->readIntReg(StackPointerReg);
-PortProxy  = tc->getVirtProxy();
-uint64_t arg = vp.read(sp + 92 +
-(number-NumArgumentRegs) * sizeof(uint64_t));
-return arg;
-}
-}

 void
 copyMiscRegs(ThreadContext *src, ThreadContext *dest)
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index 4738eb4..8a638e1 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -50,8 +50,6 @@
 return ret;
 }

-uint64_t getArgument(ThreadContext *tc, int , uint16_t size, bool  
fp);

-
 static inline bool
 inUserMode(ThreadContext *tc)
 {
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index 7d891af..c664620 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -46,29 +46,8 @@
 #include "fputils/fp80.h"
 #include "sim/full_system.hh"

-namespace X86ISA {
-
-uint64_t
-getArgument(ThreadContext *tc, int , uint16_t size, bool fp)
+namespace X86ISA
 {
-if (fp) {
-panic("getArgument(): Floating point arguments not implemented\n");
-} else if (size != 8) {
-panic("getArgument(): Can only handle 64-bit arguments.\n");
-}
-
-// The first 6 integer arguments are passed in registers, the rest
-// are passed on the stack.
-const int int_reg_map[] = {
-INTREG_RDI, INTREG_RSI, INTREG_RDX,
-INTREG_RCX, INTREG_R8, INTREG_R9
-};
-if (number < sizeof(int_reg_map) / sizeof(*int_reg_map)) {
-return tc->readIntReg(int_reg_map[number]);
-} else {
-panic("getArgument(): Don't know how to handle stack  
arguments.\n");

-}
-}

 void
 copyMiscRegs(ThreadContext *src, ThreadContext *dest)
diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index 39a142c..4ae8102 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -53,9 +53,6 @@
 return retPC;
 }

-uint64_t
-getArgument(ThreadContext *tc, int , uint16_t size, bool fp);
-
 static inline bool
     inUserMode(ThreadContext *tc)
 {

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Gerrit-Branch: develop
Gerrit-Change-Id: Ic6020c5fa6d976d9dbf1e9f517809acf9b0b7cd8
Gerrit-Change-Number: 39321
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
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[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Move getExecutingAsid to the ISA class.

2021-01-18 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39322 )



Change subject: arch,cpu: Move getExecutingAsid to the ISA class.
..

arch,cpu: Move getExecutingAsid to the ISA class.

This function was switched based on the ISA, and returned 0 on
everything except SPARC and ARM. It was used only when tracing
instruction execution with --debug-flags=Exec.

Change-Id: I70c274cb76fb229d0e2bc606ba41f458ed18ab81
---
M src/arch/arm/isa.hh
M src/arch/arm/utility.hh
M src/arch/generic/isa.hh
M src/arch/mips/utility.hh
M src/arch/power/utility.hh
M src/arch/riscv/utility.hh
M src/arch/sparc/isa.hh
M src/arch/sparc/utility.hh
M src/arch/x86/utility.hh
M src/cpu/exetrace.cc
10 files changed, 14 insertions(+), 38 deletions(-)



diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index dce5e37..97b41cc 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -886,6 +886,12 @@
 const Params () const;

 ISA(const Params );
+
+uint64_t
+getExecutingAsid() const override
+{
+return readMiscRegNoEffect(MISCREG_CONTEXTIDR);
+}
 };
 }

diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index fcaefbb..e255b1c 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -409,12 +409,6 @@
 Addr truncPage(Addr addr);
 Addr roundPage(Addr addr);

-inline uint64_t
-getExecutingAsid(ThreadContext *tc)
-{
-return tc->readMiscReg(MISCREG_CONTEXTIDR);
-}
-
 // Decodes the register index to access based on the fields used in a MSR
 // or MRS instruction
 bool
diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh
index df07763..9ea2d9f 100644
--- a/src/arch/generic/isa.hh
+++ b/src/arch/generic/isa.hh
@@ -57,6 +57,8 @@
 {}

 virtual void setThreadContext(ThreadContext *_tc) { tc = _tc; }
+
+virtual uint64_t getExecutingAsid() const { return 0; }
 };

 #endif // __ARCH_GENERIC_ISA_HH__
diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index a0d222e..0cb9349 100644
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -106,12 +106,6 @@
 pc.advance();
 }

-inline uint64_t
-getExecutingAsid(ThreadContext *tc)
-{
-return 0;
-}
-
 };


diff --git a/src/arch/power/utility.hh b/src/arch/power/utility.hh
index 80b98c6..9092a23 100644
--- a/src/arch/power/utility.hh
+++ b/src/arch/power/utility.hh
@@ -64,12 +64,6 @@
 return 0;
 }

-inline uint64_t
-getExecutingAsid(ThreadContext *tc)
-{
-return 0;
-}
-
 } // namespace PowerISA


diff --git a/src/arch/riscv/utility.hh b/src/arch/riscv/utility.hh
index 1f82d2b..c2f4ac8 100644
--- a/src/arch/riscv/utility.hh
+++ b/src/arch/riscv/utility.hh
@@ -163,12 +163,6 @@
 return true;
 }

-inline uint64_t
-getExecutingAsid(ThreadContext *tc)
-{
-return 0;
-}
-
 } // namespace RiscvISA

 #endif // __ARCH_RISCV_UTILITY_HH__
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 2881384..21143dd 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -215,6 +215,11 @@
 int flattenCCIndex(int reg) const { return reg; }
 int flattenMiscIndex(int reg) const { return reg; }

+uint64_t
+getExecutingAsid() const override
+{
+return readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT);
+}

 typedef SparcISAParams Params;
 const Params () const;
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index 8a638e1..18b5164 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -68,12 +68,6 @@
 inst->advancePC(pc);
 }

-inline uint64_t
-getExecutingAsid(ThreadContext *tc)
-{
-return tc->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT);
-}
-
 } // namespace SparcISA

 #endif
diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index 4ae8102..1ff7b16 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -74,13 +74,6 @@
 inst->advancePC(pc);
 }

-inline uint64_t
-getExecutingAsid(ThreadContext *tc)
-{
-return 0;
-}
-
-
 /**
  * Reconstruct the rflags register from the internal gem5 register
  * state.
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 4980c91..17c877e 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -70,7 +70,7 @@
 }

 if (Debug::ExecAsid)
-outs << "A" << dec << TheISA::getExecutingAsid(thread) << " ";
+outs << "A" << dec << thread->getIsaPtr()->getExecutingAsid()  
<< " ";


 if (Debug::ExecThread)
 outs << "T" << thread->threadId() << " : ";

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[gem5-dev] Change in gem5/gem5[develop]: arm: Use the "reg" ABI for gem5 ops.

2021-01-18 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39316 )



Change subject: arm: Use the "reg" ABI for gem5 ops.
..

arm: Use the "reg" ABI for gem5 ops.

The generic PseudoInstABI just calls back into the ISA specific
getArgument function, and that adds a lot of handling for cases that
aren't used and, besides those, basically just boils down to the "reg"
ABI anyway.

Change-Id: I57e738631dbccbf89cba3a6ca62b1f954b39e959
---
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa/insts/m5ops.isa
M src/arch/arm/tlb.cc
3 files changed, 15 insertions(+), 3 deletions(-)



diff --git a/src/arch/arm/isa/includes.isa b/src/arch/arm/isa/includes.isa
index 13b47c8..6af382a 100644
--- a/src/arch/arm/isa/includes.isa
+++ b/src/arch/arm/isa/includes.isa
@@ -105,6 +105,7 @@
 #include "arch/arm/htm.hh"
 #include "arch/arm/isa_traits.hh"
 #include "arch/arm/pauth_helpers.hh"
+#include "arch/arm/reg_abi.hh"
 #include "arch/arm/semihosting.hh"
 #include "arch/arm/utility.hh"
 #include "arch/generic/memhelpers.hh"
diff --git a/src/arch/arm/isa/insts/m5ops.isa  
b/src/arch/arm/isa/insts/m5ops.isa

index 48d533d..f3a8eeb 100644
--- a/src/arch/arm/isa/insts/m5ops.isa
+++ b/src/arch/arm/isa/insts/m5ops.isa
@@ -38,8 +38,13 @@
 let {{
 gem5OpCode = '''
 uint64_t ret;
-bool recognized = PseudoInst::pseudoInst(
-xc->tcBase(), bits(machInst, 23, 16), ret);
+bool recognized;
+int func = bits(machInst, 23, 16);
+auto *tc = xc->tcBase();
+if (inAArch64(tc))
+recognized = PseudoInst::pseudoInst(tc, func, ret);
+else
+recognized = PseudoInst::pseudoInst(tc, func, ret);
 if (!recognized)
 fault = std::make_shared(machInst, true);
 '''
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 5d2ed90..91c7088 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -47,6 +47,7 @@
 #include "arch/arm/faults.hh"
 #include "arch/arm/isa.hh"
 #include "arch/arm/pagetable.hh"
+#include "arch/arm/reg_abi.hh"
 #include "arch/arm/self_debug.hh"
 #include "arch/arm/stage2_lookup.hh"
 #include "arch/arm/stage2_mmu.hh"
@@ -146,9 +147,14 @@
 [func, mode](ThreadContext *tc, PacketPtr pkt) -> Cycles
 {
 uint64_t ret;
-PseudoInst::pseudoInst(tc, func, ret);
+if (inAArch64(tc))
+PseudoInst::pseudoInst(tc, func, ret);
+else
+PseudoInst::pseudoInst(tc, func, ret);
+
 if (mode == Read)
 pkt->setLE(ret);
+
 return Cycles(1);
 }
 );

--
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Gerrit-Change-Id: I57e738631dbccbf89cba3a6ca62b1f954b39e959
Gerrit-Change-Number: 39316
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Move the inUserMode function to the ISA object.

2021-01-18 Thread Gabe Black (Gerrit) via gem5-dev
| !inUserMode(thread)) &&
+if (Debug::ExecSymbol && (!FullSystem || !in_user_mode) &&
 (it = Loader::debugSymbolTable.findNearest(cur_pc)) !=
 Loader::debugSymbolTable.end()) {
 Addr delta = cur_pc - it->address;

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[gem5-dev] Change in gem5/gem5[develop]: arm,kern: Stop using the getArgument function for kernel events.

2021-01-18 Thread Gabe Black (Gerrit) via gem5-dev
e __KERN_FREEBSD_EVENTS_HH__

 #include "kern/system_events.hh"
+#include "sim/guest_abi.hh"

 namespace FreeBSD
 {

-void onUDelay(ThreadContext *tc, uint64_t div, uint64_t mul);
+void onUDelay(ThreadContext *tc, uint64_t div, uint64_t mul, uint64_t  
time);


 /** A class to skip udelay() and related calls in the kernel.
- * This class has two additional parameters that take the argument to  
udelay and

- * manipulated it to come up with ns and eventually ticks to quiesce for.
+ * This class has two additional parameters that take the argument to  
udelay
+ * and manipulated it to come up with ns and eventually ticks to quiesce  
for.

  * See descriptions of argDivToNs and argMultToNs below.
  */
-template 
+template 
 class SkipUDelay : public Base
 {
   private:
@@ -69,7 +70,13 @@
 void
 process(ThreadContext *tc) override
 {
-onUDelay(tc, argDivToNs, argMultToNs);
+// Use Addr since it's handled specially and will act as a natively
+// sized data type.
+std::function call_udelay =
+[this](ThreadContext *tc, Addr time) {
+onUDelay(tc, argDivToNs, argMultToNs, time);
+};
+invokeSimcall(tc, call_udelay);
 Base::process(tc);
 }
 };
diff --git a/src/kern/linux/events.cc b/src/kern/linux/events.cc
index db487e8..8ae76b3 100644
--- a/src/kern/linux/events.cc
+++ b/src/kern/linux/events.cc
@@ -78,13 +78,8 @@
 }

 void
-onUDelay(ThreadContext *tc, uint64_t div, uint64_t mul)
+onUDelay(ThreadContext *tc, uint64_t div, uint64_t mul, uint64_t time)
 {
-int arg_num = 0;
-
-// Get the time in native size
-uint64_t time = TheISA::getArgument(tc, arg_num, (uint16_t)-1, false);
-
 // convert parameter to ns
 if (div)
 time /= div;
diff --git a/src/kern/linux/events.hh b/src/kern/linux/events.hh
index 2ca97a4..8785345 100644
--- a/src/kern/linux/events.hh
+++ b/src/kern/linux/events.hh
@@ -56,7 +56,7 @@
 namespace Linux
 {

-template 
+template 
 class DebugPrintk : public Base
 {
   public:
@@ -71,7 +71,7 @@
 PrintkVarArgs args) -> int {
 return printk(str, tc, format_ptr, args);
 };
-invokeSimcall(tc, func);
+invokeSimcall(tc, func);
 DPRINTFN("%s", str);
 }
 Base::process(tc);
@@ -120,7 +120,7 @@
 void process(ThreadContext *tc) override;
 };

-void onUDelay(ThreadContext *tc, uint64_t div, uint64_t mul);
+void onUDelay(ThreadContext *tc, uint64_t div, uint64_t mul, uint64_t  
time);


 /**
  * A class to skip udelay() and related calls in the kernel.
@@ -128,7 +128,7 @@
  * and manipulated it to come up with ns and eventually ticks to quiesce  
for.

  * See descriptions of argDivToNs and argMultToNs below.
  */
-template 
+template 
 class SkipUDelay : public Base
 {
   private:
@@ -156,7 +156,13 @@
 void
 process(ThreadContext *tc) override
 {
-onUDelay(tc, argDivToNs, argMultToNs);
+// Use Addr since it's handled specially and will act as a natively
+// sized data type.
+std::function call_udelay =
+[this](ThreadContext *tc, Addr time) {
+    onUDelay(tc, argDivToNs, argMultToNs, time);
+};
+invokeSimcall(tc, call_udelay);
 Base::process(tc);
 }
 };

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[gem5-dev] Change in gem5/gem5[develop]: riscv: Get rid of some unused constants.

2021-01-18 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39317 )



Change subject: riscv: Get rid of some unused constants.
..

riscv: Get rid of some unused constants.

Change-Id: I464e86dc6bfcd333a0bee32e56d9dcaa6fdf682d
---
M src/arch/riscv/registers.hh
1 file changed, 0 insertions(+), 2 deletions(-)



diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index ed8b916..84a1924 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -101,8 +101,6 @@
 const std::vector ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17};
 const int AMOTempReg = 32;

-const int SyscallPseudoReturnReg = 10;
-const std::vector SyscallArgumentRegs = {10, 11, 12, 13, 14, 15, 16};
 const int SyscallNumReg = 17;

 const std::vector IntRegNames = {

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[gem5-dev] Change in gem5/gem5[develop]: tests: Fix syntax error in cpu_tests/test.py

2021-01-18 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39295 )



Change subject: tests: Fix syntax error in cpu_tests/test.py
..

tests: Fix syntax error in cpu_tests/test.py

The testsuite was not loaded with the following error:

Exception thrown while loading
/scratch/jactra01/GEM/external/reviews/gem5/tests/gem5/cpu_tests/test.py

Signed-off-by: Giacomo Travaglini 
Change-Id: I1e88b8957bb24471e1bb6113ffc7c78886b6ed70
---
M tests/gem5/cpu_tests/test.py
1 file changed, 3 insertions(+), 3 deletions(-)



diff --git a/tests/gem5/cpu_tests/test.py b/tests/gem5/cpu_tests/test.py
index 393ff26..ee56400 100644
--- a/tests/gem5/cpu_tests/test.py
+++ b/tests/gem5/cpu_tests/test.py
@@ -60,9 +60,9 @@
 base_url = config.resource_url + '/gem5/cpu_tests/benchmarks/bin/'

 isa_url = {
-constants.gcn3_x86_tag : base_url + "x86"
-constants.arm_tag : base_url + "arm"
-constants.riscv_tag : base_url + "riscv"
+constants.gcn3_x86_tag : base_url + "x86",
+constants.arm_tag : base_url + "arm",
+constants.riscv_tag : base_url + "riscv",
 }

 for isa in valid_isas:

--
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Gerrit-Change-Id: I1e88b8957bb24471e1bb6113ffc7c78886b6ed70
Gerrit-Change-Number: 39295
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Gerrit-Owner: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[develop]: mem: Add Units to mem stats

2021-01-18 Thread Hoa Nguyen (Gerrit) via gem5-dev
d006da..ac07b94 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -423,9 +423,10 @@
 AbstractController::
 ControllerStats::ControllerStats(Stats::Group *parent)
 : Stats::Group(parent),
-  ADD_STAT(m_fully_busy_cycles,
-   "cycles for which number of transistions == max  
transitions"),

-  ADD_STAT(m_delayHistogram, "delay_histogram")
+  ADD_STAT_WITH_UNIT(m_fully_busy_cycles, UNIT_CYCLE,
+ "cycles for which number of transistions == max "
+ "transitions"),
+  ADD_STAT_WITH_UNIT(m_delayHistogram, UNIT_CYCLE, "delay_histogram")
 {
 m_fully_busy_cycles
 .flags(Stats::nozero);
diff --git a/src/mem/ruby/structures/RubyPrefetcher.cc  
b/src/mem/ruby/structures/RubyPrefetcher.cc

index 7848b14..5ec6289 100644
--- a/src/mem/ruby/structures/RubyPrefetcher.cc
+++ b/src/mem/ruby/structures/RubyPrefetcher.cc
@@ -66,17 +66,23 @@
 RubyPrefetcher::
 RubyPrefetcherStats::RubyPrefetcherStats(Stats::Group *parent)
 : Stats::Group(parent, "RubyPrefetcher"),
-  ADD_STAT(numMissObserved, "Number of misses observed"),
-  ADD_STAT(numAllocatedStreams, "Number of streams allocated for "
-"prefetching"),
-  ADD_STAT(numPrefetchRequested, "Number of prefetch requests made"),
-  ADD_STAT(numHits, "Number of prefetched blocks accessed "
-"(for the first time)"),
-  ADD_STAT(numPartialHits, "Number of misses observed for a block  
being "

-   "prefetched"),
-  ADD_STAT(numPagesCrossed, "Number of prefetches across pages"),
-  ADD_STAT(numMissedPrefetchedBlocks, "Number of misses for blocks  
that "

-  "were prefetched, yet missed")
+  ADD_STAT_WITH_UNIT(numMissObserved, UNIT_COUNT,
+ "Number of misses observed"),
+  ADD_STAT_WITH_UNIT(numAllocatedStreams, UNIT_COUNT,
+ "Number of streams allocated for prefetching"),
+  ADD_STAT_WITH_UNIT(numPrefetchRequested, UNIT_COUNT,
+ "Number of prefetch requests made"),
+  ADD_STAT_WITH_UNIT(numHits, UNIT_COUNT,
+ "Number of prefetched blocks accessed "
+ "(for the first time)"),
+  ADD_STAT_WITH_UNIT(numPartialHits, UNIT_COUNT,
+ "Number of misses observed for a block being "
+ "prefetched"),
+  ADD_STAT_WITH_UNIT(numPagesCrossed, UNIT_COUNT,
+ "Number of prefetches across pages"),
+  ADD_STAT_WITH_UNIT(numMissedPrefetchedBlocks, UNIT_COUNT,
+ "Number of misses for blocks that were  
prefetched, "

+     "yet missed")
 {
 }

diff --git a/src/mem/ruby/system/HTMSequencer.cc  
b/src/mem/ruby/system/HTMSequencer.cc

index 15071fa..52c2f4d 100644
--- a/src/mem/ruby/system/HTMSequencer.cc
+++ b/src/mem/ruby/system/HTMSequencer.cc
@@ -64,11 +64,13 @@

 HTMSequencer::HTMSequencer(const RubyHTMSequencerParams )
 : Sequencer(p),
-  ADD_STAT(m_htm_transaction_cycles, "number of cycles spent in an  
outer "

- "transaction"),
-  ADD_STAT(m_htm_transaction_instructions, "number of instructions  
spent "

-   "in an outer transaction"),
-  ADD_STAT(m_htm_transaction_abort_cause, "cause of htm transaction  
abort")

+  ADD_STAT_WITH_UNIT(m_htm_transaction_cycles, UNIT_CYCLE,
+"number of cycles spent in an outer transaction"),
+  ADD_STAT_WITH_UNIT(m_htm_transaction_instructions, UNIT_COUNT,
+ "number of instructions spent in an outer "
+ "transaction"),
+  ADD_STAT_WITH_UNIT(m_htm_transaction_abort_cause, UNIT_COUNT,
+ "cause of htm transaction abort")
 {
 m_htmstart_tick = 0;
 m_htmstart_instruction = 0;

--
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fix incorrect interrupt checking logic

2021-01-17 Thread Cui Jin (Gerrit) via gem5-dev
Cui Jin has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39035 )


Change subject: arch-riscv: fix incorrect interrupt checking logic
..

arch-riscv: fix incorrect interrupt checking logic

Whether global interrupt enabling or not is not simply decided by
xIE bit in mstatus, it also depends on current privilige level.
All level lower/higher than current should be disabled/enabled
regardless of the xIE bit. xIE bit is only control the enabling
of interrupt in current privilige level.

The fix is verified in FS.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-883

Change-Id: I37f83ab77af2efbf1da9b81845828d322e49bf5f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39035
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Ayaz Akram 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/riscv/interrupts.hh
1 file changed, 25 insertions(+), 6 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Ayaz Akram: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/riscv/interrupts.hh b/src/arch/riscv/interrupts.hh
index fba925e..e1460ab 100644
--- a/src/arch/riscv/interrupts.hh
+++ b/src/arch/riscv/interrupts.hh
@@ -72,12 +72,31 @@
 {
 INTERRUPT mask = 0;
 STATUS status = tc->readMiscReg(MISCREG_STATUS);
-if (status.mie)
-mask.mei = mask.mti = mask.msi = 1;
-if (status.sie)
-mask.sei = mask.sti = mask.ssi = 1;
-if (status.uie)
-mask.uei = mask.uti = mask.usi = 1;
+PrivilegeMode prv = (PrivilegeMode)tc->readMiscReg(MISCREG_PRV);
+switch (prv) {
+case PRV_U:
+mask.mei = mask.mti = mask.msi = 1;
+mask.sei = mask.sti = mask.ssi = 1;
+if (status.uie)
+mask.uei = mask.uti = mask.usi = 1;
+break;
+case PRV_S:
+mask.mei = mask.mti = mask.msi = 1;
+if (status.sie)
+mask.sei = mask.sti = mask.ssi = 1;
+mask.uei = mask.uti = mask.usi = 0;
+break;
+case PRV_M:
+if (status.mie)
+ mask.mei = mask.mti = mask.msi = 1;
+mask.sei = mask.sti = mask.ssi = 0;
+mask.uei = mask.uti = mask.usi = 0;
+break;
+default:
+panic("Unknown privilege mode %d.", prv);
+break;
+}
+
 return std::bitset(mask);
 }


--
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Gerrit-Change-Number: 39035
Gerrit-PatchSet: 2
Gerrit-Owner: Cui Jin 
Gerrit-Reviewer: Ayaz Akram 
Gerrit-Reviewer: Cui Jin 
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Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: arch: Wrap InstObjParams with a class and not a function.

2021-01-17 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39275 )



Change subject: arch: Wrap InstObjParams with a class and not a function.
..

arch: Wrap InstObjParams with a class and not a function.

When parsing an ISA description, the InstObjParams class needs to have a
reference to the current parser. It does that by exposing a wrapper to
the description rather than the actual InstObjParams class. That wrapper
injects an additional argument into the InstObjParams constructor.

Originally, the wrapper which injectect the additional argument was a
function which masqueraded as a class. That made it impossible to
subclass InstObjParams.

Instead, this change replaces that function wrapper with a class
wrapper, and injects the extra argument in the __init__ method. This
preserves the fact that the InstObjParams name refers to a class, and
allows any sort of interaction that's normally allowed with a class like
subclassing.

Change-Id: I550ea2e60eadac3c7c0b9afa7d71f4607b49a5d2
---
M src/arch/isa_parser/isa_parser.py
1 file changed, 6 insertions(+), 5 deletions(-)



diff --git a/src/arch/isa_parser/isa_parser.py  
b/src/arch/isa_parser/isa_parser.py

index 9ca813e..a0b9f74 100755
--- a/src/arch/isa_parser/isa_parser.py
+++ b/src/arch/isa_parser/isa_parser.py
@@ -1436,11 +1436,12 @@
 # END OF GRAMMAR RULES

 def updateExportContext(self):
-
-# create a continuation that allows us to grab the current parser
-def wrapInstObjParams(*args):
-return InstObjParams(self, *args)
-self.exportContext['InstObjParams'] = wrapInstObjParams
+# Create a wrapper class that allows us to grab the current parser.
+class InstObjParamsWrapper(InstObjParams):
+def __init__(iop, *args, **kwargs):
+super(InstObjParamsWrapper, iop).__init__(
+self, *args, **kwargs)
+self.exportContext['InstObjParams'] = InstObjParamsWrapper
 self.exportContext.update(self.templateMap)

 def defFormat(self, id, params, code, lineno):

--
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Gerrit-Owner: Gabe Black 
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[gem5-dev] Change in gem5/gem5[develop]: misc: Fix some includes

2021-01-15 Thread Daniel Carvalho (Gerrit) via gem5-dev
c/mem/physical.cc
@@ -54,6 +54,7 @@
 #include "debug/AddrRanges.hh"
 #include "debug/Checkpoint.hh"
 #include "mem/abstract_mem.hh"
+#include "sim/serialize.hh"

 /**
  * On Linux, MAP_NORESERVE allow us to simulate a very large memory
diff --git a/src/mem/ruby/network/simple/PerfectSwitch.cc  
b/src/mem/ruby/network/simple/PerfectSwitch.cc

index 156b96d..432b6d6 100644
--- a/src/mem/ruby/network/simple/PerfectSwitch.cc
+++ b/src/mem/ruby/network/simple/PerfectSwitch.cc
@@ -31,6 +31,7 @@
 #include 

 #include "base/cast.hh"
+#include "base/cprintf.hh"
 #include "base/random.hh"
 #include "debug/RubyNetwork.hh"
 #include "mem/ruby/network/MessageBuffer.hh"
diff --git a/src/sim/clock_domain.cc b/src/sim/clock_domain.cc
index 61d5654..f27a8f3 100644
--- a/src/sim/clock_domain.cc
+++ b/src/sim/clock_domain.cc
@@ -41,12 +41,14 @@
 #include 
 #include 

+#include "base/logging.hh"
 #include "base/trace.hh"
 #include "debug/ClockDomain.hh"
 #include "params/ClockDomain.hh"
 #include "params/DerivedClockDomain.hh"
 #include "params/SrcClockDomain.hh"
 #include "sim/clocked_object.hh"
+#include "sim/serialize.hh"
 #include "sim/voltage_domain.hh"

 ClockDomain::ClockDomainStats::ClockDomainStats(ClockDomain )
diff --git a/src/sim/dvfs_handler.cc b/src/sim/dvfs_handler.cc
index 38ca35c..53b4271 100644
--- a/src/sim/dvfs_handler.cc
+++ b/src/sim/dvfs_handler.cc
@@ -40,12 +40,10 @@
 #include 
 #include 

-#include "base/logging.hh"
 #include "base/trace.hh"
 #include "debug/DVFS.hh"
 #include "params/DVFSHandler.hh"
-#include "sim/clock_domain.hh"
-#include "sim/eventq.hh"
+#include "sim/serialize.hh"
 #include "sim/stat_control.hh"
 #include "sim/voltage_domain.hh"

diff --git a/src/sim/dvfs_handler.hh b/src/sim/dvfs_handler.hh
index da04fc5..fccaf63 100644
--- a/src/sim/dvfs_handler.hh
+++ b/src/sim/dvfs_handler.hh
@@ -46,8 +46,12 @@
 #ifndef __SIM_DVFS_HANDLER_HH__
 #define __SIM_DVFS_HANDLER_HH__

+#include 
+#include 
 #include 

+#include "base/logging.hh"
+#include "base/types.hh"
 #include "debug/DVFS.hh"
 #include "params/DVFSHandler.hh"
 #include "sim/clock_domain.hh"
diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh
index 5fb0877..a9ab29b 100644
--- a/src/sim/eventq.hh
+++ b/src/sim/eventq.hh
@@ -40,6 +40,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 

diff --git a/src/sim/power/thermal_domain.cc  
b/src/sim/power/thermal_domain.cc

index dabf2fe..e9f4d3c 100644
--- a/src/sim/power/thermal_domain.cc
+++ b/src/sim/power/thermal_domain.cc
@@ -46,6 +46,7 @@
 #include "sim/linear_solver.hh"
 #include "sim/power/thermal_model.hh"
 #include "sim/probe/probe.hh"
+#include "sim/serialize.hh"
 #include "sim/sub_system.hh"

 ThermalDomain::ThermalDomain(const Params )
diff --git a/src/sim/power/thermal_model.cc b/src/sim/power/thermal_model.cc
index 65649e5..408642c 100644
--- a/src/sim/power/thermal_model.cc
+++ b/src/sim/power/thermal_model.cc
@@ -44,6 +44,7 @@
 #include "sim/clocked_object.hh"
 #include "sim/linear_solver.hh"
 #include "sim/power/thermal_domain.hh"
+#include "sim/serialize.hh"
 #include "sim/sim_object.hh"

 /**
diff --git a/src/sim/power_state.cc b/src/sim/power_state.cc
index a11ed43..ffa1972 100644
--- a/src/sim/power_state.cc
+++ b/src/sim/power_state.cc
@@ -37,10 +37,13 @@

 #include "sim/power_state.hh"

+#include 
+
 #include "base/logging.hh"
 #include "base/trace.hh"
 #include "debug/PowerDomain.hh"
 #include "sim/power_domain.hh"
+#include "sim/serialize.hh"

 PowerState::PowerState(const PowerStateParams ) :
 SimObject(p), _currState(p.default_state),
diff --git a/src/sim/power_state.hh b/src/sim/power_state.hh
index fe869ff..fb9a581 100644
--- a/src/sim/power_state.hh
+++ b/src/sim/power_state.hh
@@ -44,6 +44,7 @@
 #define __SIM_POWER_STATE_HH__

 #include 
+#include 

 #include "base/callback.hh"
 #include "base/statistics.hh"
diff --git a/src/sim/redirect_path.cc b/src/sim/redirect_path.cc
index f270057..57286f7 100644
--- a/src/sim/redirect_path.cc
+++ b/src/sim/redirect_path.cc
@@ -30,6 +30,8 @@

 #include 

+#include "base/str.hh"
+
 static std::string
 normalizePath(std::string path)
 {
diff --git a/src/sim/root.hh b/src/sim/root.hh
index 817e2f3..2db4223 100644
--- a/src/sim/root.hh
+++ b/src/sim/root.hh
@@ -53,6 +53,7 @@

 #include "base/statistics.hh"
 #include "base/time.hh"
+#include "base/types.hh"
 #include "params/Root.hh"
 #include "sim/eventq.hh"
 #include "sim/sim_object.hh"
diff --git a/src/sim/serialize_handlers.hh b/src/sim/serialize_handlers.hh
index 8efd895..5e5c3ff 100644
--- a/src/sim/serialize_handlers.hh
+++ b/src/sim/serialize_handlers.hh
@@ -47,8 +47,8 @@


 #include 
-#include 
 #include 
+#include 

 #include "base/str.hh"

diff --git a/src/sim/sim_exit.hh b/src/sim/sim_exit.hh
index a79d3e2..d1791f5 100644
--- a/src/sim/sim_exit.hh
+++ b/src/sim/sim_exit.hh
@@ -29,6 +29,7 @@
 #ifndef __SIM_EXIT_HH__
 #define __SIM_EXIT_HH__

+#include 
 #include 

 #include "base/types.hh"
diff --git a/src/sim/ticked_object.cc b/src/sim/ticked_object.cc
index 3564b4d..79cbd41 100644
--- a/src/sim/ticked_object.cc
+++ b/src/sim/ticked_object.cc
@@ -39,6 +39,7 @@

 #include "params/TickedObject.hh"
 #include "sim/clocked_object.hh"
+#include "sim/serialize.hh"

 Ticked::Ticked(ClockedObject _,
 Stats::Scalar *imported_num_cycles,
diff --git a/src/sim/voltage_domain.cc b/src/sim/voltage_domain.cc
index f6f8396..d770af8 100644
--- a/src/sim/voltage_domain.cc
+++ b/src/sim/voltage_domain.cc
@@ -39,11 +39,11 @@

 #include 

-#include "base/statistics.hh"
+#include "base/logging.hh"
 #include "base/trace.hh"
 #include "debug/VoltageDomain.hh"
 #include "params/VoltageDomain.hh"
-#include "sim/sim_object.hh"
+#include "sim/serialize.hh"

 VoltageDomain::VoltageDomain(const Params )
 : SimObject(p), voltageOpPoints(p.voltage), _perfLevel(0), stats(*this)

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Gerrit-Change-Number: 38738
Gerrit-PatchSet: 5
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
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Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: util: Fix gem5_within_systemc and tlm coupling

2021-01-15 Thread Lukas Steiner (Gerrit) via gem5-dev
Lukas Steiner has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39215 )


Change subject: util: Fix gem5_within_systemc and tlm coupling
..

util: Fix gem5_within_systemc and tlm coupling

Adapt the code to changes introduced with commits 3fb9139 and 392c1ce.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-874

Change-Id: I0023157f1a2e5935f624c0a12e61f6b3e0d98b97
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39215
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M util/systemc/gem5_within_systemc/sc_module.cc
M util/tlm/src/sc_master_port.cc
2 files changed, 2 insertions(+), 1 deletion(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/systemc/gem5_within_systemc/sc_module.cc  
b/util/systemc/gem5_within_systemc/sc_module.cc

index 9e6d5aa..a0f36c7 100644
--- a/util/systemc/gem5_within_systemc/sc_module.cc
+++ b/util/systemc/gem5_within_systemc/sc_module.cc
@@ -71,6 +71,7 @@
 setTickFrequency()
 {
 ::setClockFrequency(1);
+::fixClockFrequency();
 }

 Module::Module(sc_core::sc_module_name name) : sc_core::sc_channel(name),
diff --git a/util/tlm/src/sc_master_port.cc b/util/tlm/src/sc_master_port.cc
index 2d569e8..0008e9b 100644
--- a/util/tlm/src/sc_master_port.cc
+++ b/util/tlm/src/sc_master_port.cc
@@ -47,7 +47,7 @@
 Request::Flags flags;
 auto req = std::make_shared(
 trans.get_address(), trans.get_data_length(), flags,
-owner.masterId);
+owner.id);

 MemCmd cmd;


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Gerrit-Change-Number: 39215
Gerrit-PatchSet: 2
Gerrit-Owner: Lukas Steiner 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Lukas Steiner 
Gerrit-Reviewer: Matthias Jung 
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Fix race related to atomics in VIPER

2021-01-15 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39175 )


Change subject: mem-ruby: Fix race related to atomics in VIPER
..

mem-ruby: Fix race related to atomics in VIPER

There is a race condition in VIPER where an atomic issued to the same
address can occur resulting in multiple trigger messages signalling the
compleition of the atomic operation. The first message was deallocating
the TBE causing the second message to dereference a nullptr when looking
up the TBE.

A counter is added to track the number of in flight AtomicDone trigger
messages. The AtomicDone is not called until the last in flight message
arrives at the trigger queue. The remaining messages call AtomicNotDone
which simply pops the message from the queue and keeps the TBE
allocated.

Change-Id: Ie1de0436861a7c393ad6d2fb2faceb83c18d4cc3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39175
Reviewed-by: Matt Sinclair 
Reviewed-by: Jason Lowe-Power 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/mem/ruby/protocol/GPU_VIPER-TCC.sm
1 file changed, 12 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm  
b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm

index 5edd7db..e21ba99 100644
--- a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
@@ -108,6 +108,7 @@
 MachineID From, desc="Waiting for writeback from...";
 NetDest Destination, desc="Data destination";
 int numAtomics, desc="number remaining atomics";
+int atomicDoneCnt,  desc="number AtomicDones triggered";
   }

   structure(TBETable, external="yes") {
@@ -256,9 +257,17 @@
   peek(triggerQueue_in, TriggerMsg) {
 TBE tbe := TBEs.lookup(in_msg.addr);
 Entry cache_entry := getCacheEntry(in_msg.addr);
-if (tbe.numAtomics == 0) {
+
+// There is a possible race where multiple AtomicDone triggers can  
be

+// sent if another Atomic to the same address is issued after the
+// AtomicDone is triggered but before the message arrives here. For
+// that case we count the number of AtomicDones in flight for this
+// address and only call AtomicDone to deallocate the TBE when it  
is

+// the last in flight message.
+if (tbe.numAtomics == 0 && tbe.atomicDoneCnt == 1) {
 trigger(Event:AtomicDone, in_msg.addr, cache_entry, tbe);
 } else {
+tbe.atomicDoneCnt := tbe.atomicDoneCnt - 1;
 trigger(Event:AtomicNotDone, in_msg.addr, cache_entry, tbe);
 }
   }
@@ -453,6 +462,7 @@
   set_tbe(TBEs.lookup(address));
   tbe.Destination.clear();
   tbe.numAtomics := 0;
+  tbe.atomicDoneCnt := 0;
 }
 if (coreRequestNetwork_in.isReady(clockEdge())) {
   peek(coreRequestNetwork_in, CPURequestMsg) {
@@ -573,6 +583,7 @@
 tbe.numAtomics := tbe.numAtomics - 1;
 if (tbe.numAtomics==0) {
   enqueue(triggerQueue_out, TriggerMsg, 1) {
+tbe.atomicDoneCnt := tbe.atomicDoneCnt + 1;
 out_msg.addr := address;
 out_msg.Type := TriggerType:AtomicDone;
   }

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Gerrit-Change-Number: 39175
Gerrit-PatchSet: 3
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Kyle Roarty 
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[gem5-dev] Change in gem5/gem5[develop]: util-docker: Add gdb to gcn-gpu Dockerfile

2021-01-15 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39096 )


Change subject: util-docker: Add gdb to gcn-gpu Dockerfile
..

util-docker: Add gdb to gcn-gpu Dockerfile

gdb is generally useful.

Change-Id: Ic73822a5f61914cafba0699949dccabc81c03d2a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39096
Reviewed-by: Matt Sinclair 
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Bobby R. Bruce 
Reviewed-by: Kyle Roarty 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M util/dockerfiles/gcn-gpu/Dockerfile
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  Kyle Roarty: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/dockerfiles/gcn-gpu/Dockerfile  
b/util/dockerfiles/gcn-gpu/Dockerfile

index dad41b92..e5683ab 100644
--- a/util/dockerfiles/gcn-gpu/Dockerfile
+++ b/util/dockerfiles/gcn-gpu/Dockerfile
@@ -40,7 +40,8 @@
 libboost-filesystem-dev \
 libboost-system-dev \
 libboost-dev \
-libpng12-dev
+libpng12-dev \
+gdb

 # Use python 3.9 by default
 RUN update-alternatives --install /usr/bin/python3 python3  
/usr/bin/python3.9 1


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Gerrit-Change-Number: 39096
Gerrit-PatchSet: 2
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Kyle Roarty 
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[gem5-dev] Change in gem5/gem5[develop]: base: Add unit test for debug.hh

2021-01-15 Thread Daniel Carvalho (Gerrit) via gem5-dev
changeFlag("FlagChangeFlagTestB", false));
+ASSERT_FALSE(flag_b.status());
+EXPECT_TRUE(Debug::changeFlag("FlagChangeFlagTestB", true));
+ASSERT_TRUE(flag_b.status());
+
+// Change a non-existent flag
+ASSERT_FALSE(Debug::changeFlag("FlagChangeFlagTestC", true));
+}
+
+/** Test changing flag status with aux functions. */
+TEST(DebugFlagTest, SetClearDebugFlag)
+{
+Debug::Flag::globalEnable();
+Debug::SimpleFlag flag_a("FlagSetClearDebugFlagTestA", "");
+Debug::SimpleFlag flag_b("FlagSetClearDebugFlagTestB", "");
+
+// Enable and disable a flag
+ASSERT_FALSE(flag_a.status());
+setDebugFlag("FlagSetClearDebugFlagTestA");
+ASSERT_TRUE(flag_a.status());
+clearDebugFlag("FlagSetClearDebugFlagTestA");
+ASSERT_FALSE(flag_a.status());
+
+// Disable and enable a flag
+ASSERT_FALSE(flag_b.status());
+clearDebugFlag("FlagSetClearDebugFlagTestB");
+ASSERT_FALSE(flag_b.status());
+setDebugFlag("FlagSetClearDebugFlagTestB");
+ASSERT_TRUE(flag_b.status());
+
+// Change a non-existent flag
+setDebugFlag("FlagSetClearDebugFlagTestC");
+clearDebugFlag("FlagSetClearDebugFlagTestC");
+}
+
+/** Test dumping no enabled debug flags. */
+TEST(DebugFlagTest, NoDumpDebugFlags)
+{
+Debug::Flag::globalEnable();
+Debug::SimpleFlag flag("FlagDumpDebugFlagTest", "");
+
+// Verify that the names of the enabled flags are printed
+testing::internal::CaptureStdout();
+dumpDebugFlags();
+std::string output = testing::internal::GetCapturedStdout();
+EXPECT_EQ(output, "");
+ASSERT_FALSE(flag.status());
+}
+
+/** Test dumping enabled debug flags with a larger set of flags. */
+TEST(DebugFlagTest, DumpDebugFlags)
+{
+Debug::Flag::globalEnable();
+Debug::SimpleFlag flag_a("FlagDumpDebugFlagTestA", "");
+Debug::SimpleFlag flag_b("FlagDumpDebugFlagTestB", "");
+Debug::SimpleFlag flag_c("FlagDumpDebugFlagTestC", "");
+Debug::SimpleFlag flag_d("FlagDumpDebugFlagTestD", "");
+Debug::SimpleFlag flag_e("FlagDumpDebugFlagTestE", "");
+Debug::CompoundFlag  
compound_flag_a("CompoundFlagDumpDebugFlagTestA", "",

+{_d});
+Debug::CompoundFlag  
compound_flag_b("CompoundFlagDumpDebugFlagTestB", "",

+{_e});
+
+// Enable a few flags
+ASSERT_FALSE(flag_a.status());
+ASSERT_FALSE(flag_b.status());
+ASSERT_FALSE(flag_c.status());
+ASSERT_FALSE(flag_d.status());
+ASSERT_FALSE(flag_e.status());
+flag_a.enable();
+flag_c.enable();
+compound_flag_b.enable();
+
+    // Verify that the names of the enabled flags are printed
+testing::internal::CaptureStdout();
+dumpDebugFlags();
+std::string output = testing::internal::GetCapturedStdout();
+EXPECT_EQ(output, "FlagDumpDebugFlagTestA\nFlagDumpDebugFlagTestC\n" \
+"FlagDumpDebugFlagTestE\n");
+}

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Gerrit-Change-Number: 38710
Gerrit-PatchSet: 5
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
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[gem5-dev] Change in gem5/gem5[develop]: base: Rename Flag status to enabled

2021-01-15 Thread Daniel Carvalho (Gerrit) via gem5-dev
tus. */
+/** Test changing flag enabled. */
 TEST(DebugFlagTest, ChangeFlag)
 {
 Debug::Flag::globalEnable();
@@ -203,24 +205,24 @@

 // Enable the found flags and verify that the original flags are
 // enabled too
-ASSERT_FALSE(flag_a.status());
+ASSERT_FALSE(flag_a.enabled());
 EXPECT_TRUE(Debug::changeFlag("FlagChangeFlagTestA", true));
-ASSERT_TRUE(flag_a.status());
+ASSERT_TRUE(flag_a.enabled());
 EXPECT_TRUE(Debug::changeFlag("FlagChangeFlagTestA", false));
-ASSERT_FALSE(flag_a.status());
+ASSERT_FALSE(flag_a.enabled());

 // Disable and enable a flag
-ASSERT_FALSE(flag_b.status());
+ASSERT_FALSE(flag_b.enabled());
 EXPECT_TRUE(Debug::changeFlag("FlagChangeFlagTestB", false));
-ASSERT_FALSE(flag_b.status());
+ASSERT_FALSE(flag_b.enabled());
 EXPECT_TRUE(Debug::changeFlag("FlagChangeFlagTestB", true));
-ASSERT_TRUE(flag_b.status());
+ASSERT_TRUE(flag_b.enabled());

 // Change a non-existent flag
 ASSERT_FALSE(Debug::changeFlag("FlagChangeFlagTestC", true));
 }

-/** Test changing flag status with aux functions. */
+/** Test changing flag enabled with aux functions. */
 TEST(DebugFlagTest, SetClearDebugFlag)
 {
 Debug::Flag::globalEnable();
@@ -228,18 +230,18 @@
 Debug::SimpleFlag flag_b("FlagSetClearDebugFlagTestB", "");

 // Enable and disable a flag
-ASSERT_FALSE(flag_a.status());
+ASSERT_FALSE(flag_a.enabled());
 setDebugFlag("FlagSetClearDebugFlagTestA");
-ASSERT_TRUE(flag_a.status());
+ASSERT_TRUE(flag_a.enabled());
 clearDebugFlag("FlagSetClearDebugFlagTestA");
-ASSERT_FALSE(flag_a.status());
+ASSERT_FALSE(flag_a.enabled());

 // Disable and enable a flag
-ASSERT_FALSE(flag_b.status());
+ASSERT_FALSE(flag_b.enabled());
 clearDebugFlag("FlagSetClearDebugFlagTestB");
-ASSERT_FALSE(flag_b.status());
+ASSERT_FALSE(flag_b.enabled());
 setDebugFlag("FlagSetClearDebugFlagTestB");
-ASSERT_TRUE(flag_b.status());
+ASSERT_TRUE(flag_b.enabled());

 // Change a non-existent flag
 setDebugFlag("FlagSetClearDebugFlagTestC");
@@ -257,7 +259,7 @@
 dumpDebugFlags();
 std::string output = testing::internal::GetCapturedStdout();
 EXPECT_EQ(output, "");
-ASSERT_FALSE(flag.status());
+ASSERT_FALSE(flag.enabled());
 }

 /** Test dumping enabled debug flags with a larger set of flags. */
@@ -275,11 +277,11 @@
 {_e});

 // Enable a few flags
-ASSERT_FALSE(flag_a.status());
-ASSERT_FALSE(flag_b.status());
-ASSERT_FALSE(flag_c.status());
-ASSERT_FALSE(flag_d.status());
-ASSERT_FALSE(flag_e.status());
+ASSERT_FALSE(flag_a.enabled());
+ASSERT_FALSE(flag_b.enabled());
+ASSERT_FALSE(flag_c.enabled());
+ASSERT_FALSE(flag_d.enabled());
+ASSERT_FALSE(flag_e.enabled());
 flag_a.enable();
 flag_c.enable();
 compound_flag_b.enable();
diff --git a/src/python/pybind11/debug.cc b/src/python/pybind11/debug.cc
index 84673f1..1284d56 100644
--- a/src/python/pybind11/debug.cc
+++ b/src/python/pybind11/debug.cc
@@ -94,9 +94,9 @@
 .def_property_readonly("desc", ::Flag::desc)
 .def("enable", ::Flag::enable)
 .def("disable", ::Flag::disable)
-.def_property("status",
+.def_property("enabled",
   [](const Debug::Flag *flag) {
-  return flag->status();
+  return flag->enabled();
   },
   [](Debug::Flag *flag, bool state) {
   if (state) {
@@ -106,7 +106,7 @@
       }
       })
 .def("__bool__", [](const Debug::Flag *flag) {
-return flag->status();
+    return flag->enabled();
 })
 ;


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Gerrit-Change-Id: I8cdd76766d80d65007a9f204abcf71b18211ab42
Gerrit-Change-Number: 38711
Gerrit-PatchSet: 5
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
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Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base: Add XOR and modulo operator to ChannelAddr

2021-01-15 Thread Ciro Santilli (Gerrit) via gem5-dev

Attention is currently required from: Andreas Sandberg.
Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/39235

to review the following change.


Change subject: base: Add XOR and modulo operator to ChannelAddr
..

base: Add XOR and modulo operator to ChannelAddr

Channel address class did not offer bitwise
XOR and modulo operation. These two functions
where now added to the ChannelAddr class.

Change-Id: I02a5e49e9700cc5283415c921a25989a130e5d07
Reviewed-by: Andreas Sandberg 
Reviewed-by: Ciro Santilli 
---
M src/base/channel_addr.hh
1 file changed, 9 insertions(+), 1 deletion(-)



diff --git a/src/base/channel_addr.hh b/src/base/channel_addr.hh
index 2cfe380..55d227b 100644
--- a/src/base/channel_addr.hh
+++ b/src/base/channel_addr.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019 ARM Limited
+ * Copyright (c) 2019, 2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -93,6 +93,14 @@
 return ChannelAddr(a << b);
 }

+constexpr ChannelAddr operator^(const int b) const {
+return ChannelAddr(a ^ b);
+}
+
+constexpr ChannelAddr operator%(const int b) const {
+return ChannelAddr(a % b);
+}
+
 constexpr ChannelAddr operator*(const Type ) const {
 return ChannelAddr(a * b);
 }

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Gerrit-Change-Number: 39235
Gerrit-PatchSet: 1
Gerrit-Owner: Ciro Santilli 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Attention: Andreas Sandberg 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: util: Fix gem5_within_systemc and tlm coupling

2021-01-15 Thread Lukas Steiner (Gerrit) via gem5-dev
Lukas Steiner has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39215 )



Change subject: util: Fix gem5_within_systemc and tlm coupling
..

util: Fix gem5_within_systemc and tlm coupling

Adapt the code to changes introduced with commits 3fb9139 and 392c1ce.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-874

Change-Id: I0023157f1a2e5935f624c0a12e61f6b3e0d98b97
---
M util/systemc/gem5_within_systemc/sc_module.cc
M util/tlm/src/sc_master_port.cc
2 files changed, 2 insertions(+), 1 deletion(-)



diff --git a/util/systemc/gem5_within_systemc/sc_module.cc  
b/util/systemc/gem5_within_systemc/sc_module.cc

index 9e6d5aa..a0f36c7 100644
--- a/util/systemc/gem5_within_systemc/sc_module.cc
+++ b/util/systemc/gem5_within_systemc/sc_module.cc
@@ -71,6 +71,7 @@
 setTickFrequency()
 {
 ::setClockFrequency(1);
+::fixClockFrequency();
 }

 Module::Module(sc_core::sc_module_name name) : sc_core::sc_channel(name),
diff --git a/util/tlm/src/sc_master_port.cc b/util/tlm/src/sc_master_port.cc
index 2d569e8..0008e9b 100644
--- a/util/tlm/src/sc_master_port.cc
+++ b/util/tlm/src/sc_master_port.cc
@@ -47,7 +47,7 @@
 Request::Flags flags;
 auto req = std::make_shared(
 trans.get_address(), trans.get_data_length(), flags,
-owner.masterId);
+owner.id);

 MemCmd cmd;


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Gerrit-Change-Id: I0023157f1a2e5935f624c0a12e61f6b3e0d98b97
Gerrit-Change-Number: 39215
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Gerrit-Owner: Lukas Steiner 
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[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Fix LGKM decrementing for flat atomic insts

2021-01-14 Thread Kyle Roarty (Gerrit) via gem5-dev
Kyle Roarty has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39155 )


Change subject: gpu-compute: Fix LGKM decrementing for flat atomic insts
..

gpu-compute: Fix LGKM decrementing for flat atomic insts

A prior commit (f6ec145fc0) fixed early LGKM decrementing for flat loads
and stores, but failed to address flat atomics.

Per the GCN3 ISA, LGKM count is decremented on flat atomics with return
when the data has been returned. This patch checks if the flat
instruction is an atomic with return, and decrements LGKM count if so.

Change-Id: I5c0c2c205a8b21327d4c42ba71c59842c15bd63b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39155
Reviewed-by: Matthew Poremba 
Reviewed-by: Matt Sinclair 
Maintainer: Matthew Poremba 
Tested-by: kokoro 
---
M src/gpu-compute/global_memory_pipeline.cc
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Matthew Poremba: Looks good to me, approved; Looks good to me, approved
  Matt Sinclair: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/gpu-compute/global_memory_pipeline.cc  
b/src/gpu-compute/global_memory_pipeline.cc

index a2b24e4..f6d60cf 100644
--- a/src/gpu-compute/global_memory_pipeline.cc
+++ b/src/gpu-compute/global_memory_pipeline.cc
@@ -130,7 +130,7 @@
 DPRINTF(GPUMem, "CU%d: WF[%d][%d]: Completing global mem  
instr %s\n",

 m->cu_id, m->simdId, m->wfSlotId, m->disassemble());
 m->completeAcc(m);
-if (m->isFlat() && m->isLoad()) {
+if (m->isFlat() && (m->isLoad() || m->isAtomicRet())) {
 w->decLGKMInstsIssued();
 }
 w->decVMemInstsIssued();

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Gerrit-Change-Id: I5c0c2c205a8b21327d4c42ba71c59842c15bd63b
Gerrit-Change-Number: 39155
Gerrit-PatchSet: 2
Gerrit-Owner: Kyle Roarty 
Gerrit-Reviewer: Kyle Roarty 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim: Rename the root stats group to RootStats

2021-01-14 Thread Hoa Nguyen (Gerrit) via gem5-dev
Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38915 )


Change subject: sim: Rename the root stats group to RootStats
..

sim: Rename the root stats group to RootStats

Currently, the name of the stats group of thr Root object is
Stats, which is likely to be confused with the Stats namespace.

This commit renames the struct to RootStats. This allows the
Stats namespace to be expressed as `Stats::`, which is
consistent with how the namespace is accessed in other part of
gem5.

Change-Id: Ieb425c3df1f5c0d5f11b1a467a36b2e0e07b2771
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38915
Reviewed-by: Daniel Carvalho 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/sim/root.cc
M src/sim/root.hh
2 files changed, 18 insertions(+), 18 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/root.cc b/src/sim/root.cc
index d9098a6..7ca84bf 100644
--- a/src/sim/root.cc
+++ b/src/sim/root.cc
@@ -49,10 +49,10 @@
 #include "sim/root.hh"

 Root *Root::_root = NULL;
-Root::Stats Root::Stats::instance;
-Root::Stats  = Root::Stats::instance;
+Root::RootStats Root::RootStats::instance;
+Root::RootStats  = Root::RootStats::instance;

-Root::Stats::Stats()
+Root::RootStats::RootStats()
 : Stats::Group(nullptr),
 simSeconds(this, "sim_seconds", "Number of seconds simulated"),
 simTicks(this, "sim_ticks", "Number of ticks simulated"),
@@ -92,7 +92,7 @@
 }

 void
-Root::Stats::resetStats()
+Root::RootStats::resetStats()
 {
 statTime.setTimer();
 startTick = curTick();
@@ -180,7 +180,7 @@
 // stat formulas. The most convenient way to implement that is by
 // having a single global stat group for global stats. Merge that
 // group into the root object here.
-mergeStatGroup(::Stats::instance);
+mergeStatGroup(::RootStats::instance);
 }

 void
diff --git a/src/sim/root.hh b/src/sim/root.hh
index fa152ff..817e2f3 100644
--- a/src/sim/root.hh
+++ b/src/sim/root.hh
@@ -90,26 +90,26 @@
 }

   public: // Global statistics
-struct Stats : public ::Stats::Group
+struct RootStats : public Stats::Group
 {
 void resetStats() override;

-::Stats::Formula simSeconds;
-::Stats::Value simTicks;
-::Stats::Value finalTick;
-::Stats::Value simFreq;
-::Stats::Value hostSeconds;
+Stats::Formula simSeconds;
+Stats::Value simTicks;
+Stats::Value finalTick;
+Stats::Value simFreq;
+Stats::Value hostSeconds;

-::Stats::Formula hostTickRate;
-::Stats::Value hostMemory;
+Stats::Formula hostTickRate;
+Stats::Value hostMemory;

-static Stats instance;
+static RootStats instance;

   private:
-Stats();
+RootStats();

-Stats(const Stats &) = delete;
-Stats =(const Stats &) = delete;
+RootStats(const RootStats &) = delete;
+RootStats =(const RootStats &) = delete;

 Time statTime;
 Tick startTick;
@@ -151,6 +151,6 @@
  * Global simulator statistics that are not associated with a
  * specific SimObject.
  */
-extern Root::Stats 
+extern Root::RootStats 

 #endif // __SIM_ROOT_HH__

--
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Gerrit-Change-Number: 38915
Gerrit-PatchSet: 4
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Hoa Nguyen 
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Fix race related to atomics in VIPER

2021-01-14 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39175 )



Change subject: mem-ruby: Fix race related to atomics in VIPER
..

mem-ruby: Fix race related to atomics in VIPER

There is a race condition in VIPER where an atomic issued to the same
address can occur resulting in multiple trigger messages signalling the
compleition of the atomic operation. The first message was deallocating
the TBE causing the second message to dereference a nullptr when looking
up the TBE.

A counter is added to track the number of in flight AtomicDone trigger
messages. The AtomicDone is not called until the last in flight message
arrives at the trigger queue. The remaining messages call AtomicNotDone
which simply pops the message from the queue and keeps the TBE
allocated.

Change-Id: Ie1de0436861a7c393ad6d2fb2faceb83c18d4cc3
---
M src/mem/ruby/protocol/GPU_VIPER-TCC.sm
1 file changed, 12 insertions(+), 1 deletion(-)



diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm  
b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm

index 5edd7db..12097ae 100644
--- a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
@@ -108,6 +108,7 @@
 MachineID From, desc="Waiting for writeback from...";
 NetDest Destination, desc="Data destination";
 int numAtomics, desc="number remaining atomics";
+int atomicDoneCnt,  desc="number AtomicDones triggered";
   }

   structure(TBETable, external="yes") {
@@ -256,9 +257,17 @@
   peek(triggerQueue_in, TriggerMsg) {
 TBE tbe := TBEs.lookup(in_msg.addr);
 Entry cache_entry := getCacheEntry(in_msg.addr);
-if (tbe.numAtomics == 0) {
+
+// The is a possible race where multiple AtomicDone triggers can be
+// sent if another Atomic to the same address is issues after the
+// AtomicDone is triggered but before the message arrives here. For
+// that case we count the number of AtomicDones in flight for this
+// address and only call AtomicDone to deallocate the TBE when it  
is

+// the last in flight message.
+if (tbe.numAtomics == 0 && tbe.atomicDoneCnt == 1) {
 trigger(Event:AtomicDone, in_msg.addr, cache_entry, tbe);
 } else {
+tbe.atomicDoneCnt := tbe.atomicDoneCnt - 1;
 trigger(Event:AtomicNotDone, in_msg.addr, cache_entry, tbe);
 }
   }
@@ -453,6 +462,7 @@
   set_tbe(TBEs.lookup(address));
   tbe.Destination.clear();
   tbe.numAtomics := 0;
+  tbe.atomicDoneCnt := 0;
 }
 if (coreRequestNetwork_in.isReady(clockEdge())) {
   peek(coreRequestNetwork_in, CPURequestMsg) {
@@ -573,6 +583,7 @@
 tbe.numAtomics := tbe.numAtomics - 1;
 if (tbe.numAtomics==0) {
   enqueue(triggerQueue_out, TriggerMsg, 1) {
+tbe.atomicDoneCnt := tbe.atomicDoneCnt + 1;
 out_msg.addr := address;
 out_msg.Type := TriggerType:AtomicDone;
   }

--
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[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Fix LGKM decrementing for flat atomic insts

2021-01-14 Thread Kyle Roarty (Gerrit) via gem5-dev
Kyle Roarty has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39155 )



Change subject: gpu-compute: Fix LGKM decrementing for flat atomic insts
..

gpu-compute: Fix LGKM decrementing for flat atomic insts

A prior commit (f6ec145fc0) fixed early LGKM decrementing for flat loads
and stores, but failed to address flat atomics.

Per the GCN3 ISA, LGKM count is decremented on flat atomics with return
when the data has been returned. This patch checks if the flat
instruction is an atomic with return, and decrements LGKM count if so.

Change-Id: I5c0c2c205a8b21327d4c42ba71c59842c15bd63b
---
M src/gpu-compute/global_memory_pipeline.cc
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/gpu-compute/global_memory_pipeline.cc  
b/src/gpu-compute/global_memory_pipeline.cc

index a2b24e4..f6d60cf 100644
--- a/src/gpu-compute/global_memory_pipeline.cc
+++ b/src/gpu-compute/global_memory_pipeline.cc
@@ -130,7 +130,7 @@
 DPRINTF(GPUMem, "CU%d: WF[%d][%d]: Completing global mem  
instr %s\n",

 m->cu_id, m->simdId, m->wfSlotId, m->disassemble());
 m->completeAcc(m);
-if (m->isFlat() && m->isLoad()) {
+if (m->isFlat() && (m->isLoad() || m->isAtomicRet())) {
 w->decLGKMInstsIssued();
 }
 w->decVMemInstsIssued();

--
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Gerrit-Change-Id: I5c0c2c205a8b21327d4c42ba71c59842c15bd63b
Gerrit-Change-Number: 39155
Gerrit-PatchSet: 1
Gerrit-Owner: Kyle Roarty 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: base: Remove the curTick prototype from base/statistics.hh.

2021-01-14 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38997 )


Change subject: base: Remove the curTick prototype from base/statistics.hh.
..

base: Remove the curTick prototype from base/statistics.hh.

This prototype might convince the compiler that it should refer to
curTick indirectly through the linker, but curTick is inline (and making
it not has very high overhead), so there's a decent chance no non-inline
version will be emitted.

Change-Id: Iab5aacb145d4a974bc1bc0abdf7275c40fbb9c38
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38997
Reviewed-by: Daniel Carvalho 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/base/statistics.hh
1 file changed, 2 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Daniel Carvalho: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/statistics.hh b/src/base/statistics.hh
index 1ad64e9..7115b88 100644
--- a/src/base/statistics.hh
+++ b/src/base/statistics.hh
@@ -81,9 +81,8 @@
 #include "base/intmath.hh"
 #include "base/str.hh"
 #include "base/types.hh"
-
-/** The current simulated tick. */
-extern Tick curTick();
+// For curTick().
+#include "sim/core.hh"

 /* A namespace for all of the Statistics */
 namespace Stats {

--
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Gerrit-Change-Number: 38997
Gerrit-PatchSet: 5
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in gem5/gem5[develop]: sim: Break the eventq.hh dependency in core.hh.

2021-01-14 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38996 )


Change subject: sim: Break the eventq.hh dependency in core.hh.
..

sim: Break the eventq.hh dependency in core.hh.

The original implementation of curTick used a thread local variable,
_curEventQueue, and its getCurTick() method, to retrieve the curTick for
the currently active event queue. That meant that core.hh needed to
include eventq.hh so that the EventQueue type was available, which also
indirectly brought in a lot of other dependencies.

Unfortunately this couldn't easily be fixed by making curTick()
non-inline since this added a significant amount of overhead when
tested.

Instead, this change makes the code in core.hh/core.cc keep a pointer
directly to a Tick. The code which sets _curEventQueue now also sets
that pointer when _curEventQueue changes.

The way curTick() now reaches into the guts of the current EventQueue
directly is not great from a modularity perspective, but if curTick is
considered an extension of the EventQueue, then it's just odd that this
part is broken out into a different file.

Change-Id: I8341b40fe75e90672eb1d70e1a368975fcbfe926
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38996
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Daniel Carvalho 
Reviewed-by: Jason Lowe-Power 
---
M src/sim/core.cc
M src/sim/core.hh
M src/sim/eventq.hh
3 files changed, 27 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Daniel Carvalho: Looks good to me, but someone else must approve
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/core.cc b/src/sim/core.cc
index 8b36245..ace699a 100644
--- a/src/sim/core.cc
+++ b/src/sim/core.cc
@@ -41,6 +41,13 @@

 using namespace std;

+namespace Gem5Internal
+{
+
+__thread Tick *_curTickPtr;
+
+} // namespace Gem5Internal
+
 namespace SimClock {
 /// The simulated frequency of curTick(). (In ticks per second)
 Tick Frequency;
diff --git a/src/sim/core.hh b/src/sim/core.hh
index 2e443e7..c592049 100644
--- a/src/sim/core.hh
+++ b/src/sim/core.hh
@@ -39,10 +39,17 @@
 #include 

 #include "base/types.hh"
-#include "sim/eventq.hh"
+
+namespace Gem5Internal
+{
+
+// This pointer is maintained by curEventQueue in src/sim/eventq.hh.
+extern __thread Tick *_curTickPtr;
+
+} // namespace Gem5Internal

 /// The universal simulation clock.
-inline Tick curTick() { return _curEventQueue->getCurTick(); }
+inline Tick curTick() { return *Gem5Internal::_curTickPtr; }

 /// These are variables that are set based on the simulator frequency
 ///@{
diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh
index 45a5ab8..5fb0877 100644
--- a/src/sim/eventq.hh
+++ b/src/sim/eventq.hh
@@ -48,6 +48,7 @@
 #include "base/types.hh"
 #include "base/uncontended_mutex.hh"
 #include "debug/Event.hh"
+#include "sim/core.hh"
 #include "sim/serialize.hh"

 class EventQueue;   // forward declaration
@@ -81,7 +82,7 @@
 EventQueue *getEventQueue(uint32_t index);

 inline EventQueue *curEventQueue() { return _curEventQueue; }
-inline void curEventQueue(EventQueue *q) { _curEventQueue = q; }
+inline void curEventQueue(EventQueue *q);

 /**
  * Common base class for Event and GlobalEvent, so they can share flag
@@ -617,6 +618,8 @@
 class EventQueue
 {
   private:
+friend void curEventQueue(EventQueue *);
+
 std::string objName;
 Event *head;
 Tick _curTick;
@@ -968,6 +971,13 @@
 }
 };

+inline void
+curEventQueue(EventQueue *q)
+{
+_curEventQueue = q;
+Gem5Internal::_curTickPtr = (q == nullptr) ? nullptr : >_curTick;
+}
+
 void dumpMainQueue();

 class EventManager

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I8341b40fe75e90672eb1d70e1a368975fcbfe926
Gerrit-Change-Number: 38996
Gerrit-PatchSet: 5
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Support for dynamic register alloc

2021-01-14 Thread Matt Sinclair (Gerrit) via gem5-dev
oolManager(const PoolManagerParams )
+: PoolManager(p), _regionSize(0), _nxtFreeIdx(0)
+{
+_totRegSpaceAvailable = p.pool_size;
+}
+
+uint32_t allocateRegion(const uint32_t size, uint32_t  
*reservedPoolSize) override;

+bool canAllocate(uint32_t numRegions, uint32_t size) override;
+void freeRegion(uint32_t firstIdx, uint32_t lastIdx) override;
+uint32_t minAllocatedElements(uint32_t size);
+std::string printRegion() override;
+uint32_t regionSize(std::pair ) override;
+void resetRegion(const int & regsPerSimd) override;
+
+  private:
+// actual size of a region (normalized to the minimum size that can
+// be reserved)
+uint32_t _regionSize;
+// next index to allocate a region
+int _nxtFreeIdx;
+// total registers available - across chunks
+uint32_t _totRegSpaceAvailable;
+// regIndex and freeSpace record
+std::list> freeSpaceRecord;
+int reservedSpaceRecord;
+// total registers to be allocated -- treat as a const
+int totalRegSpace;
+};
+
+#endif // __DYN_POOL_MANAGER_HH__
diff --git a/src/gpu-compute/pool_manager.hh  
b/src/gpu-compute/pool_manager.hh

index 0f102c2..2de8fd2 100644
--- a/src/gpu-compute/pool_manager.hh
+++ b/src/gpu-compute/pool_manager.hh
@@ -57,6 +57,14 @@

 virtual void freeRegion(uint32_t firstIdx, uint32_t lastIdx) = 0;
 uint32_t poolSize() { return _poolSize; }
+// I don't think with the current API it is possible to do what
+// we intend to - reset the entire register pool.
+// Because we need to reset the register pool when all WGs on
+// the Compute Unit are finished - before launching WGs from
+// another kernel.
+// TsungTai Yeh added a virtual method do the very same - at a diff
+// place though.
+virtual void resetRegion(const int & regsPerSimd) {}; // do nothing

   private:
 // minimum size that can be reserved per allocation
diff --git a/src/gpu-compute/shader.cc b/src/gpu-compute/shader.cc
index 012b987..9ae3fd7 100644
--- a/src/gpu-compute/shader.cc
+++ b/src/gpu-compute/shader.cc
@@ -207,6 +207,9 @@
 _dispatcher.updateInvCounter(kernId, +1);
 // all necessary INV flags are all set now, call cu to execute
 cuList[i_cu]->doInvalidate(req, task->dispatchId());
+
+// I don't like this. This is intrusive coding.
+cuList[i_cu]->resetRegisterPool();
 }
 }

diff --git a/src/gpu-compute/static_register_manager_policy.cc  
b/src/gpu-compute/static_register_manager_policy.cc

index 85f530b..f1bc1e6 100644
--- a/src/gpu-compute/static_register_manager_policy.cc
+++ b/src/gpu-compute/static_register_manager_policy.cc
@@ -152,13 +152,13 @@
  w->simdId,
  w->computeUnit->scalarRegsReserved[w->simdId]);

-int endIndex = (w->startVgprIndex + w->reservedVectorRegs - 1) %
-w->computeUnit->vrf[w->simdId]->numRegs();
+// Current dynamic register allocation does not handle wraparound
+int endIndex = w->startVgprIndex + w->reservedVectorRegs;

 w->computeUnit->registerManager->vrfPoolMgrs[w->simdId]->
 freeRegion(w->startVgprIndex, endIndex);

-// mark/pre-mark all registers as not busy
+// mark/pre-mark all registers are not busy
 for (int i = 0; i < w->reservedVectorRegs; i++) {
 uint32_t physVgprIdx = mapVgpr(w, i);
 w->computeUnit->vrf[w->simdId]->markReg(physVgprIdx, false);
@@ -167,12 +167,11 @@
 w->reservedVectorRegs = 0;
 w->startVgprIndex = 0;

-endIndex = (w->startSgprIndex + w->reservedScalarRegs - 1) %
-w->computeUnit->srf[w->simdId]->numRegs();
+endIndex = w->startSgprIndex + w->reservedScalarRegs;
 w->computeUnit->registerManager->srfPoolMgrs[w->simdId]->
 freeRegion(w->startSgprIndex, endIndex);

-// mark/pre-mark all registers as not busy
+// mark/pre-mark all registers are not busy
 for (int i = 0; i < w->reservedScalarRegs; i++) {
 uint32_t physSgprIdx = mapSgpr(w, i);
 w->computeUnit->srf[w->simdId]->markReg(physSgprIdx, false);

--
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Gerrit-Change-Id: I2255c68d4b421615d7b231edc05d3ebb27cbd66c
Gerrit-Change-Number: 32034
Gerrit-PatchSet: 6
Gerrit-Owner: GAURAV JAIN 
Gerrit-Reviewer: Alexandru Duțu 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Bradford Beckmann 
Gerrit-CC: Kyle Roarty 
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[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: Add missing tid in Rename's debug message

2021-01-14 Thread Daniel Carvalho (Gerrit) via gem5-dev
Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39075 )


Change subject: cpu-o3: Add missing tid in Rename's debug message
..

cpu-o3: Add missing tid in Rename's debug message

These arguments were missing.

Change-Id: I8a76e46b2bcfc57f299145954fe72196f5969f29
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39075
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/cpu/o3/rename_impl.hh
1 file changed, 4 insertions(+), 2 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index 007ec87..68150f9 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -612,7 +612,8 @@

 if (inst->isLoad()) {
 if (calcFreeLQEntries(tid) <= 0) {
-DPRINTF(Rename, "[tid:%i] Cannot rename due to no free  
LQ\n");
+DPRINTF(Rename, "[tid:%i] Cannot rename due to no free  
LQ\n",

+tid);
 source = LQ;
 incrFullStat(source);
 break;
@@ -621,7 +622,8 @@

 if (inst->isStore() || inst->isAtomic()) {
 if (calcFreeSQEntries(tid) <= 0) {
-DPRINTF(Rename, "[tid:%i] Cannot rename due to no free  
SQ\n");
+DPRINTF(Rename, "[tid:%i] Cannot rename due to no free  
SQ\n",

+tid);
 source = SQ;
 incrFullStat(source);
 break;

--
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Gerrit-Change-Number: 39075
Gerrit-PatchSet: 2
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[develop]: util-docker: Add gdb to gcn-gpu Dockerfile

2021-01-14 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39096 )



Change subject: util-docker: Add gdb to gcn-gpu Dockerfile
..

util-docker: Add gdb to gcn-gpu Dockerfile

gdb is generally useful.

Change-Id: Ic73822a5f61914cafba0699949dccabc81c03d2a
---
M util/dockerfiles/gcn-gpu/Dockerfile
1 file changed, 2 insertions(+), 1 deletion(-)



diff --git a/util/dockerfiles/gcn-gpu/Dockerfile  
b/util/dockerfiles/gcn-gpu/Dockerfile

index dad41b92..e5683ab 100644
--- a/util/dockerfiles/gcn-gpu/Dockerfile
+++ b/util/dockerfiles/gcn-gpu/Dockerfile
@@ -40,7 +40,8 @@
 libboost-filesystem-dev \
 libboost-system-dev \
 libboost-dev \
-libpng12-dev
+libpng12-dev \
+gdb

 # Use python 3.9 by default
 RUN update-alternatives --install /usr/bin/python3 python3  
/usr/bin/python3.9 1


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Gerrit-Change-Number: 39096
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[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3: Implementation of s_sleep

2021-01-14 Thread Gerrit
on in the instruction buffer.
@@ -143,7 +152,8 @@
 // through this logic and always return not ready.
 if (!(ii->isBarrier() || ii->isNop() || ii->isReturn() ||  
ii->isBranch() ||

  ii->isALU() || ii->isLoad() || ii->isStore() || ii->isAtomic() ||
- ii->isEndOfKernel() || ii->isMemSync() || ii->isFlat())) {
+ ii->isEndOfKernel() || ii->isMemSync() || ii->isFlat() ||
+ ii->isSleep())) {
 panic("next instruction: %s is of unknown type\n",  
ii->disassemble());

 }

diff --git a/src/gpu-compute/scoreboard_check_stage.hh  
b/src/gpu-compute/scoreboard_check_stage.hh

index c45ea75..714c761 100644
--- a/src/gpu-compute/scoreboard_check_stage.hh
+++ b/src/gpu-compute/scoreboard_check_stage.hh
@@ -64,6 +64,7 @@
 NRDY_WF_STOP,
 NRDY_IB_EMPTY,
 NRDY_WAIT_CNT,
+NRDY_SLEEP,
 NRDY_BARRIER_WAIT,
 NRDY_VGPR_NRDY,
 NRDY_SGPR_NRDY,
diff --git a/src/gpu-compute/wavefront.cc b/src/gpu-compute/wavefront.cc
index b7ff95a..00c4fd9 100644
--- a/src/gpu-compute/wavefront.cc
+++ b/src/gpu-compute/wavefront.cc
@@ -49,7 +49,7 @@
 maxIbSize(p.max_ib_size), _gpuISA(*this),
 vmWaitCnt(-1), expWaitCnt(-1), lgkmWaitCnt(-1),
 vmemInstsIssued(0), expInstsIssued(0), lgkmInstsIssued(0),
-barId(WFBarrier::InvalidID)
+sleepCnt(0), barId(WFBarrier::InvalidID)
 {
 lastTrace = 0;
 execUnitId = -1;
@@ -653,6 +653,20 @@
 }

 bool
+Wavefront::isOldestInstSleep()
+{
+if (instructionBuffer.empty())
+return false;
+
+GPUDynInstPtr ii = instructionBuffer.front();
+
+if (ii->isSleep()) {
+return true;
+}
+return false;
+}
+
+bool
 Wavefront::isOldestInstWaitcnt()
 {
 if (instructionBuffer.empty())
@@ -1282,6 +1296,32 @@
 return true;
 }

+bool
+Wavefront::sleepDone()
+{
+assert(status == S_STALLED_SLEEP);
+
+// if the sleep count has not been set, then the sleep instruction has  
not
+// been executed yet, so we will return true without setting the  
wavefront

+// status
+if (sleepCnt == 0)
+return false;
+
+sleepCnt--;
+if (sleepCnt != 0)
+return false;
+
+status = S_RUNNING;
+return true;
+}
+
+void
+Wavefront::setSleepTime(int sleep_time)
+{
+assert(sleepCnt == 0);
+sleepCnt = sleep_time;
+}
+
 void
 Wavefront::setWaitCnts(int vm_wait_cnt, int exp_wait_cnt, int  
lgkm_wait_cnt)

 {
diff --git a/src/gpu-compute/wavefront.hh b/src/gpu-compute/wavefront.hh
index 80fc324..414240c 100644
--- a/src/gpu-compute/wavefront.hh
+++ b/src/gpu-compute/wavefront.hh
@@ -66,6 +66,9 @@
 S_RUNNING,
 // wavefront is stalled
 S_STALLED,
+
+S_STALLED_SLEEP,
+
 /**
  * wavefront has unsatisfied wait counts
  *
@@ -132,6 +135,7 @@
 bool isGmInstruction(GPUDynInstPtr ii);
 bool isLmInstruction(GPUDynInstPtr ii);
 bool isOldestInstWaitcnt();
+bool isOldestInstSleep();
 bool isOldestInstGMem();
 bool isOldestInstLMem();
 bool isOldestInstPrivMem();
@@ -314,6 +318,9 @@
 /** Freeing VRF space */
 void freeRegisterFile();

+bool sleepDone();
+void setSleepTime(int sleep_time);
+
 TheGpuISA::GPUISA&
 gpuISA()
 {
@@ -353,6 +360,7 @@
 int vmemInstsIssued;
 int expInstsIssued;
 int lgkmInstsIssued;
+int sleepCnt;
 status_e status;
 Addr _pc;
 VectorMask _execMask;

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: CSR registers support in RISC-V remote GDB.

2021-01-13 Thread Peter Yuen (Gerrit) via gem5-dev
:
 char *data() const { return (char *) }
@@ -79,6 +142,19 @@
   public:
 RemoteGDB(System *_system, ThreadContext *tc, int _port);
 BaseGdbRegCache *gdbRegs() override;
+    /**
+ * Informs GDB remote serial protocol that XML features are supported
+ * GDB then queries for xml blobs using qXfer:features:read:xxx.xml
+ */
+std::vector
+availableFeatures() const
+{
+    return {"qXfer:features:read+"};
+};
+/**
+ * Reply to qXfer:features:read:xxx.xml qeuries
+ */
+bool getXferFeaturesRead(const std::string , std::string  
);

 };

 } // namespace RiscvISA

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Gerrit-PatchSet: 3
Gerrit-Owner: Peter Yuen 
Gerrit-Reviewer: Boris Shingarov 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Peter Yuen 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: scons: Add an "All" compound debug flag

2021-01-13 Thread Daniel Carvalho (Gerrit) via gem5-dev
Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39077 )



Change subject: scons: Add an "All" compound debug flag
..

scons: Add an "All" compound debug flag

Add an "All" compound debug flag, which encapsulates all
debug flags.

Since this is the broadest compound flag, allowing users
to include it would imply in extremely generic includes.
Moreover, it is highly unlikely that any correct C++ code
would ever use all debug flags. Therefore, a header file
for this flag is not generated to force users to directly
include only the debug flags they need.

Change-Id: If40f2f708be1495fa2b2380266164d5d44d7cffa
Signed-off-by: Daniel R. Carvalho 
---
M src/SConscript
1 file changed, 12 insertions(+), 0 deletions(-)



diff --git a/src/SConscript b/src/SConscript
index 2533810..910df32 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -1176,14 +1176,26 @@

 code.write(str(target[0]))

+# Generate the files for the debug and debug-format flags
+simple_flags = []
 for name,flag in sorted(debug_flags.items()):
 n, compound, desc, fmt = flag
 assert n == name

+if not compound and not fmt:
+simple_flags.append(n)
+
 hh_file = 'debug/%s.hh' % name
 env.Command(hh_file, Value(flag),
 MakeAction(makeDebugFlagHH, Transform("TRACING", 0)))

+# Create a compound debug flag that encapsulates all flags: "All". This  
flag
+# should not be used within C++ code - it is a compound meta flag;  
therefore,

+# its header file is purposefully not generated
+CompoundFlag("All", simple_flags,
+"Controls all debug flags. It should not be used within C++ code.")
+del simple_flags
+
 env.Command('debug/flags.cc', Value(debug_flags),
 MakeAction(makeDebugFlagCC, Transform("TRACING", 0)))
 Source('debug/flags.cc')

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[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: Add missing tid in Rename's debug message

2021-01-13 Thread Daniel Carvalho (Gerrit) via gem5-dev
Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39075 )



Change subject: cpu-o3: Add missing tid in Rename's debug message
..

cpu-o3: Add missing tid in Rename's debug message

These arguments were missing.

Change-Id: I8a76e46b2bcfc57f299145954fe72196f5969f29
Signed-off-by: Daniel R. Carvalho 
---
M src/cpu/o3/rename_impl.hh
1 file changed, 4 insertions(+), 2 deletions(-)



diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index 007ec87..68150f9 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -612,7 +612,8 @@

 if (inst->isLoad()) {
 if (calcFreeLQEntries(tid) <= 0) {
-DPRINTF(Rename, "[tid:%i] Cannot rename due to no free  
LQ\n");
+DPRINTF(Rename, "[tid:%i] Cannot rename due to no free  
LQ\n",

+tid);
 source = LQ;
 incrFullStat(source);
 break;
@@ -621,7 +622,8 @@

 if (inst->isStore() || inst->isAtomic()) {
 if (calcFreeSQEntries(tid) <= 0) {
-DPRINTF(Rename, "[tid:%i] Cannot rename due to no free  
SQ\n");
+DPRINTF(Rename, "[tid:%i] Cannot rename due to no free  
SQ\n",

+tid);
 source = SQ;
 incrFullStat(source);
 break;

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[gem5-dev] Change in gem5/gem5[develop]: scons: Separate debug flags from debug-format flags

2021-01-13 Thread Daniel Carvalho (Gerrit) via gem5-dev
Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39076 )



Change subject: scons: Separate debug flags from debug-format flags
..

scons: Separate debug flags from debug-format flags

Debug flags are flags that aid with debugging by printing
relevant information when enabled. Debug-formatting flags
define how the debug flags will print the information.

Although a viability, this patch does not support declaring
compound format flags.

Finally, as of this patch, the C++ debug flag code is still
unaware of this difference.

Change-Id: Ieae68745276218cf4e9c1d37d7bf3bd1f19709ae
Signed-off-by: Daniel R. Carvalho 
---
M src/SConscript
M src/base/SConscript
2 files changed, 15 insertions(+), 10 deletions(-)



diff --git a/src/SConscript b/src/SConscript
index b55f485..2533810 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -623,20 +623,24 @@
 # Debug Flags
 #
 debug_flags = {}
-def DebugFlag(name, desc=None):
+def DebugFlag(name, desc=None, fmt=False):
 if name in debug_flags:
 raise AttributeError("Flag {} already specified".format(name))
-debug_flags[name] = (name, (), desc)
+debug_flags[name] = (name, (), desc, fmt)

 def CompoundFlag(name, flags, desc=None):
 if name in debug_flags:
 raise AttributeError("Flag {} already specified".format(name))

 compound = tuple(flags)
-debug_flags[name] = (name, compound, desc)
+debug_flags[name] = (name, compound, desc, False)
+
+def DebugFormatFlag(name, desc=None):
+DebugFlag(name, desc, True)

 Export('DebugFlag')
 Export('CompoundFlag')
+Export('DebugFormatFlag')

 
 #
@@ -1114,7 +1118,7 @@
 ''')

 for name, flag in sorted(source[0].read().items()):
-n, compound, desc = flag
+n, compound, desc, fmt = flag
 assert n == name

 if not compound:
@@ -1137,7 +1141,7 @@
 assert(len(target) == 1 and len(source) == 1)

 val = eval(source[0].get_contents())
-name, compound, desc = val
+name, compound, desc, fmt = val

 code = code_formatter()

@@ -1173,7 +1177,7 @@
 code.write(str(target[0]))

 for name,flag in sorted(debug_flags.items()):
-n, compound, desc = flag
+n, compound, desc, fmt = flag
 assert n == name

 hh_file = 'debug/%s.hh' % name
diff --git a/src/base/SConscript b/src/base/SConscript
index 3ac9838..5b5e578 100644
--- a/src/base/SConscript
+++ b/src/base/SConscript
@@ -99,10 +99,6 @@
 DebugFlag('Annotate', "State machine annotation debugging")
 DebugFlag('AnnotateQ', "State machine annotation queue debugging")
 DebugFlag('AnnotateVerbose', "Dump all state machine annotation details")
-DebugFlag('FmtFlag', "Show the --debug-flag that enabled each debug  
message")

-DebugFlag('FmtStackTrace',
-"Print a stack trace after every debug message")
-DebugFlag('FmtTicksOff', "Don't show tick count on debug messages")
 DebugFlag('GDBAcc', "Remote debugger accesses")
 DebugFlag('GDBExtra', "Dump extra information on reads and writes")
 DebugFlag('GDBMisc', "Breakpoints, traps, watchpoints, etc.")
@@ -121,3 +117,8 @@
 CompoundFlag('AnnotateAll', ['Annotate', 'AnnotateQ', 'AnnotateVerbose'],
 desc="All Annotation flags")

+DebugFormatFlag('FmtFlag',
+"Show the --debug-flag that enabled each debug message")
+DebugFormatFlag('FmtStackTrace',
+"Print a stack trace after every debug message")
+DebugFormatFlag('FmtTicksOff', "Don't show tick count on debug messages")

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[gem5-dev] Change in gem5/gem5[develop]: dev: Let the pixel pump bypass the DMA FIFO in non-caching mode.

2021-01-13 Thread Gabe Black (Gerrit) via gem5-dev
dex 86a0ae0..b2987bb 100644
--- a/src/dev/pixelpump.hh
+++ b/src/dev/pixelpump.hh
@@ -38,6 +38,8 @@
 #ifndef __DEV_PIXELPUMP_HH__
 #define __DEV_PIXELPUMP_HH__

+#include 
+
 #include "base/framebuffer.hh"
 #include "sim/clocked_object.hh"

@@ -171,7 +173,7 @@
 /** Update frame size using display timing */
 void updateTimings(const DisplayTimings );

-/** Render an entire frame in KVM execution mode */
+/** Render an entire frame in non-caching mode */
 void renderFrame();

 /** Starting pushing pixels in timing mode */
@@ -219,6 +221,28 @@
  */
 virtual bool nextPixel(Pixel ) = 0;

+/**
+ * Get the next line of pixels directly from memory. This is for use  
from

+ * the renderFrame which is called in non-caching mode.
+ *
+ * The default implementation falls back to calling nextPixel over and
+ * over, but a more efficient implementation could retrieve the entire  
line

+ * of pixels all at once using fewer access to memory which bypass any
+ * intermediate structures like an incoming FIFO.
+ *
+ * @param ps  A vector iterator to store retrieved pixels into.
+ * @param line_length The number of pixels being requested.
+ * @return The number of pixels actually retrieved.
+ */
+virtual size_t
+nextLine(std::vector::iterator ps, size_t line_length)
+{
+size_t count = 0;
+while (count < line_length && nextPixel(*ps++))
+count++;
+return count;
+}
+
 /** First pixel clock of the first VSync line. */
 virtual void onVSyncBegin() {};


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[gem5-dev] Change in gem5/gem5[develop]: tests, base: Added GTests for base/amo.hh

2021-01-13 Thread Neil Natekar (Gerrit) via gem5-dev
+TypedAtomicOpFunctor *amo_op_char = new AtomicOpDec();
+amo_op_int->execute(_int);
+amo_op_char->execute(_char);
+
+EXPECT_EQ(test_int, 9);
+EXPECT_EQ(test_char, 'b');
+}
+
+TEST(AmoTest, AtomicOpInc)
+{
+int test_int = 10;
+char test_char = 'c';
+
+TypedAtomicOpFunctor *amo_op_int = new AtomicOpInc();
+TypedAtomicOpFunctor *amo_op_char = new AtomicOpInc();
+amo_op_int->execute(_int);
+amo_op_char->execute(_char);
+
+EXPECT_EQ(test_int, 11);
+EXPECT_EQ(test_char, 'd');
+}
+
+TEST(AmoTest, AtomicOpSub)
+{
+int test_int = 10;
+char test_char = 'c';
+
+TypedAtomicOpFunctor *amo_op_int = new AtomicOpSub(2);
+TypedAtomicOpFunctor *amo_op_char = new AtomicOpSub('a');
+amo_op_int->execute(_int);
+amo_op_char->execute(_char);
+
+EXPECT_EQ(test_int, 8);
+EXPECT_EQ(test_char, 2);
+}
+
+TEST(AmoTest, AtomicOpAdd)
+{
+int test_int = 10;
+char test_char = 'c';
+
+TypedAtomicOpFunctor *amo_op_int = new AtomicOpAdd(2);
+TypedAtomicOpFunctor *amo_op_char = new AtomicOpAdd(2);
+amo_op_int->execute(_int);
+amo_op_char->execute(_char);
+
+EXPECT_EQ(test_int, 12);
+EXPECT_EQ(test_char, 'e');
+}
+
+TEST(AmoTest, AtomicOpExch)
+{
+int test_int = 10;
+char test_char = 'c';
+
+TypedAtomicOpFunctor *amo_op_int = new AtomicOpExch(2);
+TypedAtomicOpFunctor *amo_op_char = new AtomicOpExch('a');
+amo_op_int->execute(_int);
+amo_op_char->execute(_char);
+
+EXPECT_EQ(test_int, 2);
+EXPECT_EQ(test_char, 'a');
+}
+
+TEST(AmoTest, AtomicOpXor)
+{
+int test_int = 10;
+char test_char = 'c';
+
+TypedAtomicOpFunctor *amo_op_int = new AtomicOpXor(2);
+TypedAtomicOpFunctor *amo_op_char = new AtomicOpXor('a');
+amo_op_int->execute(_int);
+amo_op_char->execute(_char);
+
+EXPECT_EQ(test_int, 8); // 1010 ^ 0010 = 1000
+EXPECT_EQ(test_char, 2); // 99 ^ 97 = 2
+}
+
+TEST(AmoTest, AtomicOpOr)
+{
+int test_int = 8;
+bool test_bool = true;
+
+TypedAtomicOpFunctor *amo_op_int = new AtomicOpOr(2);
+TypedAtomicOpFunctor *amo_op_bool = new AtomicOpOr(false);
+amo_op_int->execute(_int);
+amo_op_bool->execute(_bool);
+
+EXPECT_EQ(test_int, 10);
+EXPECT_EQ(test_bool, true);
+}
+
+TEST(AmoTest, AtomicOpAnd)
+{
+int test_int = 10;
+char test_char = 'c';
+
+TypedAtomicOpFunctor *amo_op_int = new AtomicOpAnd(6);
+TypedAtomicOpFunctor *amo_op_char = new AtomicOpAnd('a');
+amo_op_int->execute(_int);
+amo_op_char->execute(_char);
+
+EXPECT_EQ(test_int, 2);
+EXPECT_EQ(test_char, 'a');
+}
+
+TEST(AmoTest, AtomicGeneric2Op)
+{
+int test_int = 9;
+
+TypedAtomicOpFunctor *amo_op_int =
+new AtomicGeneric2Op(9, multiply2Op);
+amo_op_int->execute(_int);
+
+EXPECT_EQ(test_int, 81);
+}
+
+TEST(AmoTest, AtomicGeneric3Op)
+{
+int test_int = 2;
+
+TypedAtomicOpFunctor *amo_op_int =
+new AtomicGeneric3Op(4, 3, multiply3Op);
+amo_op_int->execute(_int);
+
+EXPECT_EQ(test_int, 24);
+}
+
+TEST(AmoTest, AtomicGenericPair3Op)
+{
+int test_int = 5;
+
+std::array a = {6, 3};
+std::array c = {10, 8};
+TypedAtomicOpFunctor *amo_op_int =
+ new AtomicGenericPair3Op(a, c, addSubColumns);
+amo_op_int->execute(_int);
+
+EXPECT_EQ(test_int, 10);
+}

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Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Neil Natekar 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: inform bootloader of kernel position with a register

2021-01-13 Thread Ciro Santilli (Gerrit) via gem5-dev
e at that address must be 0, which is the default memory
+ * value set by gem5 for otherwise uninitialized memory, leading to
+ * WFE.
+ */
+ldr x4, [x22]
 cbzx4, 1b
 br x4  // branch to the given address

@@ -180,9 +199,13 @@
 /*
  * Primary CPU
  */
-ldrx0, =PHYS_OFFSET + 0x800 // device tree blob
-ldr x6, =PHYS_OFFSET + 0x8   // kernel start address
-br x6
+// The kernel boot protocol specifies that the DTB address is  
placed

+// in x0.
+// https://github.com/torvalds/linux/blob/v5.7/Documentation/arm64/
+// booting.rst#4-call-the-kernel-image
+mov x0, x21
+// Jump into the kernel entry point.
+br x20

 .ltorg

diff --git a/system/arm/bootloader/arm64/makefile  
b/system/arm/bootloader/arm64/makefile

index 2112b6e..dbf7128 100644
--- a/system/arm/bootloader/arm64/makefile
+++ b/system/arm/bootloader/arm64/makefile
@@ -34,11 +34,7 @@
 DESTDIR = $(error Please set DESTDIR to wanted installation directory)

 CFLAGS = -march=armv8-a
-CPPFLAGS = -DPHYS_OFFSET=0x8000 \
-  -DUART_BASE=0x1c09 -DSYSREGS_BASE=0x1c010000 \
-      -Dkernel=0x8008 \
-      -Dmbox=0x8000fff8 -Ddtb=0x8100
-
+CPPFLAGS = -DUART_BASE=0x1c09 -DSYSREGS_BASE=0x1c01
 LDFLAGS = -N -Ttext 0x0010 -static

 .PHONY: all clean install mkdir

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Gerrit-Change-Number: 35076
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Gerrit-Owner: Ciro Santilli 
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Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[develop]: base: Add documentation to flags.hh

2021-01-13 Thread Daniel Carvalho (Gerrit) via gem5-dev
+ * Replace the contents of the bits matching the mask with the
+ * corresponding bits in the provided flags.
+ *
+ * This is equivalent to:
+ * flags.clear(mask); flags.set(flags & mask);
+ *
+ * @param flags Flags to extract new bits from.
+ * @param mask Mask used to determine which bits are replaced.
+ */
 void
 update(Type flags, Type mask)
 {

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[gem5-dev] Change in gem5/gem5[develop]: base: Remove Flags assignment

2021-01-13 Thread Daniel Carvalho (Gerrit) via gem5-dev
Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38713 )


Change subject: base: Remove Flags assignment
..

base: Remove Flags assignment

Currently unused and broken. Since these are templated classes,
and _flags is private, the assignment is a compilation error.
Furthermore, assignment of flags of different types is likely
undefined behavior.

Change-Id: I8430045c42c003efc74e343cc5b4a4350bc2ad92
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38713
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Reviewed-by: Bobby R. Bruce 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/base/flags.hh
1 file changed, 0 insertions(+), 11 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, but someone else must approve
  kokoro: Regressions pass



diff --git a/src/base/flags.hh b/src/base/flags.hh
index 505a1e5..8cefd2d 100644
--- a/src/base/flags.hh
+++ b/src/base/flags.hh
@@ -58,17 +58,6 @@
 /**
  * @ingroup api_flags
  */
-template 
-const Flags &
-operator=(const Flags )
-{
-_flags = flags._flags;
-return *this;
-}
-
-/**
- * @ingroup api_flags
- */
 const Flags &
 operator=(T flags)
 {

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Gerrit-Change-Number: 38713
Gerrit-PatchSet: 4
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Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
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[gem5-dev] Change in gem5/gem5[develop]: base: Fix uninitialized variable in Flag

2021-01-13 Thread Daniel Carvalho (Gerrit) via gem5-dev
Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38707 )


Change subject: base: Fix uninitialized variable in Flag
..

base: Fix uninitialized variable in Flag

This was uninitialized, and was breaking expected values
under certain situations.

Change-Id: If51ab6ae038c7c397bc83de1c73af348c1db4ef8
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38707
Reviewed-by: Bobby R. Bruce 
Reviewed-by: Andreas Sandberg 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/base/debug.cc
M src/base/debug.hh
2 files changed, 5 insertions(+), 5 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/debug.cc b/src/base/debug.cc
index 45d9f9d..9cfd45e 100644
--- a/src/base/debug.cc
+++ b/src/base/debug.cc
@@ -100,6 +100,8 @@
 panic("Flag %s already defined!", name);

 ++allFlagsVersion;
+
+sync();
 }

 Flag::~Flag()
diff --git a/src/base/debug.hh b/src/base/debug.hh
index 7cc7137..6006b14 100644
--- a/src/base/debug.hh
+++ b/src/base/debug.hh
@@ -82,15 +82,13 @@
 class SimpleFlag : public Flag
 {
   protected:
-bool _tracing; // tracing is enabled and flag is on
-bool _status;  // flag status
+bool _tracing = false; // tracing is enabled and flag is on
+bool _status = false;  // flag status

 void sync() override { _tracing = _globalEnable && _status; }

   public:
-SimpleFlag(const char *name, const char *desc)
-: Flag(name, desc), _status(false)
-{ }
+SimpleFlag(const char *name, const char *desc) : Flag(name, desc) {}

 bool status() const override { return _tracing; }


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Gerrit-Change-Number: 38707
Gerrit-PatchSet: 4
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
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[gem5-dev] Change in gem5/gem5[develop]: base: Remove flag from allFlags on destruction

2021-01-13 Thread Daniel Carvalho (Gerrit) via gem5-dev
Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38709 )


Change subject: base: Remove flag from allFlags on destruction
..

base: Remove flag from allFlags on destruction

When a flag is destroyed it must be removed from the list
containing all flags.

Use this opportunity to remove "using namespace std" since
it is barely used.

Change-Id: I201371a770c56e11b92532e146d577c6ecb29d34
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38709
Reviewed-by: Andreas Sandberg 
Reviewed-by: Gabe Black 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/base/debug.cc
1 file changed, 3 insertions(+), 5 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/debug.cc b/src/base/debug.cc
index 9cfd45e..8eaf2c6 100644
--- a/src/base/debug.cc
+++ b/src/base/debug.cc
@@ -49,8 +49,6 @@
 #include "base/cprintf.hh"
 #include "base/logging.hh"

-using namespace std;
-
 namespace Debug {

 //
@@ -93,8 +91,8 @@
 Flag::Flag(const char *name, const char *desc)
 : _name(name), _desc(desc)
 {
-pair result =
-allFlags().insert(make_pair(name, this));
+std::pair result =
+allFlags().insert(std::make_pair(name, this));

 if (!result.second)
 panic("Flag %s already defined!", name);
@@ -106,7 +104,7 @@

 Flag::~Flag()
 {
-// should find and remove flag.
+allFlags().erase(name());
 }

 void

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Gerrit-Change-Number: 38709
Gerrit-PatchSet: 4
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
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[gem5-dev] Change in gem5/gem5[develop]: base: Assert Flags' type is unsigned

2021-01-13 Thread Daniel Carvalho (Gerrit) via gem5-dev
Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38712 )


Change subject: base: Assert Flags' type is unsigned
..

base: Assert Flags' type is unsigned

Operations rely on the use of unsigned integers.

Change-Id: I825a88f81b54577585976d6558b1409870897721
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38712
Reviewed-by: Jason Lowe-Power 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/base/flags.hh
1 file changed, 4 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/flags.hh b/src/base/flags.hh
index c9525fa..505a1e5 100644
--- a/src/base/flags.hh
+++ b/src/base/flags.hh
@@ -29,10 +29,14 @@
 #ifndef __BASE_FLAGS_HH__
 #define __BASE_FLAGS_HH__

+#include 
+
 template 
 class Flags
 {
   private:
+static_assert(std::is_unsigned::value, "Flag type must be  
unsigned");

+
 T _flags;

   public:

--
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Gerrit-Change-Number: 38712
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Gerrit-Owner: Daniel Carvalho 
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[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Fix update of useful prefetches

2021-01-13 Thread Daniel Carvalho (Gerrit) via gem5-dev
Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38177 )


Change subject: mem-cache: Fix update of useful prefetches
..

mem-cache: Fix update of useful prefetches

The probe notification must be parsed on every hit, even if
the prefetcher is set not to generate prefetches on accesses.
This fixes the calculation of useful prefetches.

Change-Id: Iff298f7bea11013f411f4ba39dba705fd81a0cd4
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38177
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/mem/cache/prefetch/base.cc
1 file changed, 3 insertions(+), 4 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc
index 28aaa62..e347992 100644
--- a/src/mem/cache/prefetch/base.cc
+++ b/src/mem/cache/prefetch/base.cc
@@ -125,6 +125,7 @@
 bool read = pkt->isRead();
 bool inv = pkt->isInvalidate();

+if (!miss && !prefetchOnAccess) return false;
 if (pkt->req->isUncacheable()) return false;
 if (fetch && !onInst) return false;
 if (!fetch && !onData) return false;
@@ -236,10 +237,8 @@
 true));
 listeners.push_back(new PrefetchListener(*this, pm, "Fill", true,
  false));
-if (prefetchOnAccess) {
-listeners.push_back(new PrefetchListener(*this, pm, "Hit",  
false,

- false));
-}
+listeners.push_back(new PrefetchListener(*this, pm, "Hit", false,
+ false));
 }
 }


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iff298f7bea11013f411f4ba39dba705fd81a0cd4
Gerrit-Change-Number: 38177
Gerrit-PatchSet: 3
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base: Reinstate Debug::All flag

2021-01-13 Thread Nathanael Premillieu (Gerrit) via gem5-dev
bda kv: isinstance(kv[1], CompoundFlag),
  sorted_flags):
 print("%s: %s" % (name, flag.desc))
diff --git a/src/python/pybind11/debug.cc b/src/python/pybind11/debug.cc
index 84673f1..681c27a 100644
--- a/src/python/pybind11/debug.cc
+++ b/src/python/pybind11/debug.cc
@@ -114,6 +114,7 @@
 py::class_(m_debug, "CompoundFlag", c_flag)
 .def("kids", ::CompoundFlag::kids)
 ;
+py::class_(m_debug, "AllFlag", c_flag);


 py::module m_trace = m_native.def_submodule("trace");

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Gerrit-Change-Id: I9e66265896b6ef5882bb8935300679c9ad30a9c9
Gerrit-Change-Number: 39055
Gerrit-PatchSet: 1
Gerrit-Owner: Nathanael Premillieu 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: misc: Fix missing includes.

2021-01-13 Thread Gabe Black (Gerrit) via gem5-dev
 #include "base/addr_range_map.hh"
 #include "mem/packet.hh"
+#include "sim/serialize.hh"

 /**
  * Forward declaration to avoid header dependencies.
diff --git a/src/mem/request.hh b/src/mem/request.hh
index 79cb724..38b64fd 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -48,12 +48,16 @@
 #ifndef __MEM_REQUEST_HH__
 #define __MEM_REQUEST_HH__

+#include 
 #include 
-#include 
+#include 
+#include 
+#include 
+#include 
+#include 

 #include "base/amo.hh"
 #include "base/flags.hh"
-#include "base/logging.hh"
 #include "base/types.hh"
 #include "cpu/inst_seq.hh"
 #include "mem/htm.hh"
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh  
b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh

index b568425..f7f8a01 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
@@ -47,6 +47,7 @@
 #define __MEM_RUBY_SLICC_INTERFACE_RUBYSLICC_UTIL_HH__

 #include 
+#include 

 #include "debug/RubySlicc.hh"
 #include "mem/packet.hh"

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Gerrit-Change-Number: 38995
Gerrit-PatchSet: 5
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fix unintentionally CSR bit overwritten in different mode

2021-01-13 Thread Cui Jin (Gerrit) via gem5-dev
Cui Jin has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39036 )



Change subject: arch-riscv: fix unintentionally CSR bit overwritten in  
different mode

..

arch-riscv: fix unintentionally CSR bit overwritten in different mode

Some CSR register is physically shared between different privilige
level. Current implementation of CSR setting only considers to verify
the bits visable in current privilige level, and directly writes the
masked bits back to register. This leads to other bits invisable
to current mode is overwritten and wrong behavior across the modes.
Thus, CSR updating should always keep the bits value for other modes.
e.g. disabling interrupt in S mode with setting
SSTATUS SIE bit will lead to clear MIE bit as well (the interrupt
is disabled unintentionally).

All CSR register sharing same physical register in different mode
may have similar issue. I only fixed some important ones.

The fix is verified in FS.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-860

Change-Id: I34d4766a4b483b5add2c3bbefd28b21b9abf37f6
---
M src/arch/riscv/isa/formats/standard.isa
1 file changed, 19 insertions(+), 9 deletions(-)



diff --git a/src/arch/riscv/isa/formats/standard.isa  
b/src/arch/riscv/isa/formats/standard.isa

index b95af76..76c1996 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -356,6 +356,7 @@
 break;
 }
 auto mask = CSRMasks.find(csr);
+auto olddata_all = olddata;
 if (mask != CSRMasks.end())
 olddata &= mask->second;
 DPRINTF(RiscvMisc, "Reading CSR %s: %#x\n", CSRData.at(csr).name,
@@ -373,23 +374,32 @@
  CSRData.at(csr).name);
 fault = make_shared(error,  
machInst);

 } else {
-DPRINTF(RiscvMisc, "Writing %#x to CSR %s.\n",  
data,

+auto newdata_all = data;
+if (mask != CSRMasks.end()) {
+// we must keep those original bits not in mask
+// olddata and data only contain thebits  
visable

+// in current privilige level
+newdata_all = (olddata_all & (~mask->second))
+  | data;
+}
+DPRINTF(RiscvMisc, "Writing %#x to CSR %s.\n",
+newdata_all,
 CSRData.at(csr).name);
-INTERRUPT oldinterrupt = olddata;
-INTERRUPT newinterrupt = data;
 switch (csr) {
   case CSR_FCSR:
 xc->setMiscReg(MISCREG_FFLAGS, bits(data, 4,  
0));

 xc->setMiscReg(MISCREG_FRM, bits(data, 7, 5));
 break;
   case CSR_MIP: case CSR_MIE:
-if (oldinterrupt.mei != newinterrupt.mei ||
-oldinterrupt.mti != newinterrupt.mti ||
-oldinterrupt.msi != newinterrupt.msi) {
- 
xc->setMiscReg(CSRData.at(csr).physIndex,data);

+  case CSR_SIP: case CSR_SIE:
+  case CSR_UIP: case CSR_UIE:
+  case CSR_MSTATUS: case CSR_SSTATUS: case  
CSR_USTATUS:

+if (newdata_all != olddata_all) {
+xc->setMiscReg(CSRData.at(csr).physIndex,
+   newdata_all);
 } else {
-std::string error = "Interrupt m bits are "
-"read-only\n";
+std::string error = "Only bits in mask  
are "

+"allowed to be set\n";
 fault =  
make_shared(error,
   
machInst);

 }

--
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Gerrit-Change-Number: 39036
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Gerrit-Owner: Cui Jin 
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fix incorrect interrupt checking logic

2021-01-12 Thread Cui Jin (Gerrit) via gem5-dev
Cui Jin has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39035 )



Change subject: arch-riscv: fix incorrect interrupt checking logic
..

arch-riscv: fix incorrect interrupt checking logic

Whether global interrupt enabling or not is not simply decided by
xIE bit in mstatus, it also depends on current privilige level.
All level lower/higher than current should be disabled/enabled
regardless of the xIE bit. xIE bit is only control the enabling
of interrupt in current privilige level.

The fix is verified in FS.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-883

Change-Id: I37f83ab77af2efbf1da9b81845828d322e49bf5f
---
M src/arch/riscv/interrupts.hh
1 file changed, 25 insertions(+), 6 deletions(-)



diff --git a/src/arch/riscv/interrupts.hh b/src/arch/riscv/interrupts.hh
index fba925e..e1460ab 100644
--- a/src/arch/riscv/interrupts.hh
+++ b/src/arch/riscv/interrupts.hh
@@ -72,12 +72,31 @@
 {
 INTERRUPT mask = 0;
 STATUS status = tc->readMiscReg(MISCREG_STATUS);
-if (status.mie)
-mask.mei = mask.mti = mask.msi = 1;
-if (status.sie)
-mask.sei = mask.sti = mask.ssi = 1;
-if (status.uie)
-mask.uei = mask.uti = mask.usi = 1;
+PrivilegeMode prv = (PrivilegeMode)tc->readMiscReg(MISCREG_PRV);
+switch (prv) {
+case PRV_U:
+mask.mei = mask.mti = mask.msi = 1;
+mask.sei = mask.sti = mask.ssi = 1;
+if (status.uie)
+mask.uei = mask.uti = mask.usi = 1;
+break;
+case PRV_S:
+mask.mei = mask.mti = mask.msi = 1;
+if (status.sie)
+mask.sei = mask.sti = mask.ssi = 1;
+mask.uei = mask.uti = mask.usi = 0;
+break;
+case PRV_M:
+if (status.mie)
+ mask.mei = mask.mti = mask.msi = 1;
+mask.sei = mask.sti = mask.ssi = 0;
+mask.uei = mask.uti = mask.usi = 0;
+break;
+default:
+panic("Unknown privilege mode %d.", prv);
+break;
+}
+
 return std::bitset(mask);
 }


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Gerrit-Change-Id: I37f83ab77af2efbf1da9b81845828d322e49bf5f
Gerrit-Change-Number: 39035
Gerrit-PatchSet: 1
Gerrit-Owner: Cui Jin 
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[gem5-dev] Change in gem5/gem5[develop]: base: Remove begin() and end() from CircleBuf.

2021-01-12 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38998 )


Change subject: base: Remove begin() and end() from CircleBuf.
..

base: Remove begin() and end() from CircleBuf.

These functions return iterators which are inconsistent with the usage
model for this type. It should be accessed using the peek, push, and pop
methods and not iterators. If you need a class with iterators which is
oriented around accessing individual elements at a time, the
CircularQueue type is likely a better choice.

Change-Id: I9f37eab12e490b63d870d378a91f601dad353f25
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38998
Reviewed-by: Daniel Carvalho 
Reviewed-by: Andreas Sandberg 
Maintainer: Gabe Black 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/base/circlebuf.hh
1 file changed, 0 insertions(+), 11 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/circlebuf.hh b/src/base/circlebuf.hh
index 0f1cea6..bcfa91a 100644
--- a/src/base/circlebuf.hh
+++ b/src/base/circlebuf.hh
@@ -62,8 +62,6 @@

   public:
 using value_type = T;
-using iterator = typename std::vector::iterator;
-using const_iterator = typename std::vector::const_iterator;

 explicit CircleBuf(size_t size) : buffer(size), maxSize(size) {}

@@ -71,15 +69,6 @@
 size_t size() const { return used; }
 size_t capacity() const { return maxSize; }

-iterator begin() { return buffer.begin() + start % maxSize; }
-const_iterator begin() const { return buffer.begin() + start %  
maxSize; }

-iterator end() { return buffer.begin() + (start + used) % maxSize; }
-const_iterator
-end() const
-{
-return buffer.begin() + (start + used) % maxSize;
-}
-
 /**
  * Throw away any data in the buffer.
  */

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Gerrit-Branch: develop
Gerrit-Change-Id: I9f37eab12e490b63d870d378a91f601dad353f25
Gerrit-Change-Number: 38998
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
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[gem5-dev] Change in gem5/gem5[develop]: dev: Use regular atomic accesses for DMA in bypass mode.

2021-01-12 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38720 )


Change subject: dev: Use regular atomic accesses for DMA in bypass mode.
..

dev: Use regular atomic accesses for DMA in bypass mode.

These are now accelerated with backdoor accesses and should be at least
as fast as functional accesses. This removes a dependency on port
proxies, and also stops the HDLCD from using functional accesses.

Change-Id: I5e959288eb533d09cffa7b79938aa2f61e4aff7d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38720
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/dev/dma_device.cc
M src/dev/dma_device.hh
2 files changed, 10 insertions(+), 10 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/dma_device.cc b/src/dev/dma_device.cc
index bbdae7d..9aebb7b 100644
--- a/src/dev/dma_device.cc
+++ b/src/dev/dma_device.cc
@@ -370,8 +370,8 @@
  unsigned max_pending,
  Request::Flags flags)
 : maxReqSize(max_req_size), fifoSize(size),
-  reqFlags(flags), port(_port), proxy(port, port.sys->cacheLineSize()),
-  cacheLineSize(port.sys->cacheLineSize()), buffer(size)
+  reqFlags(flags), port(_port),  
cacheLineSize(port.sys->cacheLineSize()),

+  buffer(size)
 {
 freeRequests.resize(max_pending);
 for (auto  : freeRequests)
@@ -465,7 +465,7 @@
 const bool old_eob(atEndOfBlock());

 if (port.sys->bypassCaches())
-resumeFillFunctional();
+resumeFillBypass();
 else
 resumeFillTiming();

@@ -474,7 +474,7 @@
 }

 void
-DmaReadFifo::resumeFillFunctional()
+DmaReadFifo::resumeFillBypass()
 {
 const size_t fifo_space = buffer.capacity() - buffer.size();
 if (fifo_space >= cacheLineSize || buffer.capacity() < cacheLineSize) {
@@ -483,11 +483,13 @@
 std::vector tmp_buffer(xfer_size);

 assert(pendingRequests.empty());
-DPRINTF(DMA, "KVM Bypassing startAddr=%#x xfer_size=%#x " \
+DPRINTF(DMA, "Direct bypass startAddr=%#x xfer_size=%#x " \
 "fifo_space=%#x block_remaining=%#x\n",
 nextAddr, xfer_size, fifo_space, block_remaining);

-proxy.readBlob(nextAddr, tmp_buffer.data(), xfer_size);
+port.dmaAction(MemCmd::ReadReq, nextAddr, xfer_size, nullptr,
+tmp_buffer.data(), 0, reqFlags);
+
 buffer.write(tmp_buffer.begin(), xfer_size);
 nextAddr += xfer_size;
 }
diff --git a/src/dev/dma_device.hh b/src/dev/dma_device.hh
index 3904a08..330be1a 100644
--- a/src/dev/dma_device.hh
+++ b/src/dev/dma_device.hh
@@ -49,7 +49,6 @@
 #include "base/circlebuf.hh"
 #include "dev/io_device.hh"
 #include "mem/backdoor.hh"
-#include "mem/port_proxy.hh"
 #include "params/DmaDevice.hh"
 #include "sim/drain.hh"
 #include "sim/system.hh"
@@ -508,7 +507,6 @@
 const Request::Flags reqFlags;

 DmaPort 
-PortProxy proxy;

 const int cacheLineSize;

@@ -554,8 +552,8 @@
 /** Try to issue new DMA requests during normal execution*/
 void resumeFillTiming();

-/** Try to bypass DMA requests in KVM execution mode */
-void resumeFillFunctional();
+/** Try to bypass DMA requests in non-caching mode */
+void resumeFillBypass();

   private: // Internal state
 Fifo buffer;

--
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Gerrit-Project: public/gem5
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Gerrit-Change-Id: I5e959288eb533d09cffa7b79938aa2f61e4aff7d
Gerrit-Change-Number: 38720
Gerrit-PatchSet: 13
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
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[gem5-dev] Change in gem5/gem5[develop]: dev: Teach the DmaPort to use atomic memory backdoors.

2021-01-12 Thread Gabe Black (Gerrit) via gem5-dev
*/
-void handleResp(PacketPtr pkt, Tick delay=0);
-
 struct DmaReqState : public Packet::SenderState
 {
 /** Event to call on the device when this transaction (all packets)
@@ -132,6 +122,27 @@
 PacketPtr createPacket();
 };

+/** Send the next packet from a DMA request in atomic mode. */
+bool sendAtomicReq(DmaReqState *state);
+/**
+ * Send the next packet from a DMA request in atomic mode, and request
+ * and/or use memory backdoors if possible.
+ */
+bool sendAtomicBdReq(DmaReqState *state);
+
+/**
+ * Handle a response packet by updating the corresponding DMA
+ * request state to reflect the bytes received, and also update
+ * the pending request counter. If the DMA request that this
+ * packet is part of is complete, then signal the completion event
+ * if present, potentially with a delay added to it.
+ *
+ * @param pkt Response packet to handler
+ * @param delay Additional delay for scheduling the completion event
+ */
+void handleRespPacket(PacketPtr pkt, Tick delay=0);
+void handleResp(DmaReqState *state, Addr addr, Addr size, Tick  
delay=0);

+
   public:
 /** The device that owns this port. */
     ClockedObject *const device;

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Gerrit-Change-Number: 38719
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Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Daniel Carvalho 
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[gem5-dev] Change in gem5/gem5[develop]: dev: Generate DMA packets as needed.

2021-01-12 Thread Gabe Black (Gerrit) via gem5-dev
rator.hh"
 #include "base/circlebuf.hh"
 #include "dev/io_device.hh"
 #include "mem/port_proxy.hh"
@@ -101,9 +102,34 @@
 /** Amount to delay completion of dma by */
 const Tick delay;

-DmaReqState(Event *ce, Addr tb, Tick _delay)
-: completionEvent(ce), totBytes(tb), delay(_delay)
+/** Object to track what chunks of bytes to send at a time. */
+ChunkGenerator gen;
+
+/** Pointer to a buffer for the data. */
+uint8_t *const data = nullptr;
+
+/** The flags to use for requests. */
+const Request::Flags flags;
+
+/** The requestor ID to use for requests. */
+const RequestorID id;
+
+/** Stream IDs. */
+const uint32_t sid;
+const uint32_t ssid;
+
+/** Command for the request. */
+const Packet::Command cmd;
+
+DmaReqState(Packet::Command _cmd, Addr addr, Addr chunk_sz, Addr  
tb,

+uint8_t *_data, Request::Flags _flags, RequestorID _id,
+uint32_t _sid, uint32_t _ssid, Event *ce, Tick _delay)
+: completionEvent(ce), totBytes(tb), delay(_delay),
+  gen(addr, tb, chunk_sz), data(_data), flags(_flags), id(_id),
+  sid(_sid), ssid(_ssid), cmd(_cmd)
 {}
+
+PacketPtr createPacket();
 };

   public:
@@ -119,7 +145,7 @@

   protected:
 /** Use a deque as we never do any insertion or removal in the middle  
*/

-std::deque transmitList;
+std::deque transmitList;

 /** Event used to schedule a future sending from the transmit list. */
 EventFunctionWrapper sendEvent;
@@ -127,9 +153,8 @@
 /** Number of outstanding packets the dma port has. */
 uint32_t pendingCount = 0;

-/** If the port is currently waiting for a retry before it can
- * send whatever it is that it's sending. */
-bool inRetry = false;
+/** The packet (if any) waiting for a retry to send. */
+PacketPtr inRetry = nullptr;

 /** Default streamId */
 const uint32_t defaultSid;
@@ -144,8 +169,6 @@
 bool recvTimingResp(PacketPtr pkt) override;
 void recvReqRetry() override;

-void queueDma(PacketPtr pkt);
-
   public:

 DmaPort(ClockedObject *dev, System *s, uint32_t sid=0, uint32_t  
ssid=0);


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Gerrit-Change-Id: I04d399fb7bce1ff9a44979c311be356baf2db555
Gerrit-Change-Number: 38717
Gerrit-PatchSet: 13
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Alexandru Duțu 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
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[gem5-dev] Change in gem5/gem5[develop]: base: Re-implement CircleBuf without using CircularQueue.

2021-01-12 Thread Gabe Black (Gerrit) via gem5-dev
len);
+used -= len;
+start += len;
 }

 /**
- * Add elements to the end of the ring buffers and advance.
+ * Add elements to the end of the ring buffers and advance. Writes  
which

+ * would exceed the capacity of the queue fill the avaialble space, and
+ * then continue overwriting the head of the queue. The head advances  
as

+ * if that data had been read out.
  *
  * @param in Input iterator/pointer
  * @param len Number of elements to read
@@ -121,15 +165,42 @@
 void
 write(InputIterator in, size_t len)
 {
-// Writes that are larger than the backing store are allowed,
-// but only the last part of the buffer will be written.
-if (len > capacity()) {
-in += len - capacity();
-len = capacity();
+if (!len)
+return;
+
+// Writes that are larger than the buffer size are allowed, but  
only

+// the last part of the date will be written since the rest will be
+// overwritten and not remain in the buffer.
+if (len > maxSize) {
+in += len - maxSize;
+flush();
+len = maxSize;
 }

-std::copy(in, in + len, end());
-advance_tail(len);
+// How much existing data will be overwritten?
+const size_t overflow = std::max(0, used + len - maxSize);
+// The iterator of the next byte to add.
+auto next_it = buffer.begin() + (start + used) % maxSize;
+// How much there is to copy to the end of the buffer.
+const size_t to_end = buffer.end() - next_it;
+
+// If this addition wraps, take care of the first part here.
+if (to_end < len) {
+// Copy it.
+std::copy_n(in, to_end, next_it);
+// Update state to reflect what's left.
+next_it = buffer.begin();
+std::advance(in, to_end);
+len -= to_end;
+used += to_end;
+}
+// Copy the remaining (or only) chunk of data.
+std::copy_n(in, len, next_it);
+used += len;
+
+// Don't count data that was overwritten.
+used -= overflow;
+start += overflow;
 }
 };


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Gerrit-Change-Number: 38896
Gerrit-PatchSet: 5
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
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[gem5-dev] Change in gem5/gem5[develop]: misc: Fix coding style for class-opening braces

2021-01-12 Thread Daniel Carvalho (Gerrit) via gem5-dev
me when request is ready to be  
serviced
diff --git a/src/mem/cache/write_queue_entry.hh  
b/src/mem/cache/write_queue_entry.hh

index 2aebacf..d50de35 100644
--- a/src/mem/cache/write_queue_entry.hh
+++ b/src/mem/cache/write_queue_entry.hh
@@ -73,7 +73,8 @@
 friend class WriteQueue;

   public:
-class TargetList : public std::list {
+class TargetList : public std::list
+{

   public:

diff --git a/src/mem/packet_queue.hh b/src/mem/packet_queue.hh
index baf6152..1509862 100644
--- a/src/mem/packet_queue.hh
+++ b/src/mem/packet_queue.hh
@@ -63,7 +63,8 @@
 {
   private:
 /** A deferred packet, buffered to transmit later. */
-class DeferredPacket {
+class DeferredPacket
+{
   public:
 Tick tick;  ///< The tick when the packet is ready to transmit
 PacketPtr pkt;  ///< Pointer to the packet to transmit
diff --git a/src/mem/ruby/system/CacheRecorder.hh  
b/src/mem/ruby/system/CacheRecorder.hh

index 53ab8e5..b295be6 100644
--- a/src/mem/ruby/system/CacheRecorder.hh
+++ b/src/mem/ruby/system/CacheRecorder.hh
@@ -51,7 +51,8 @@
  * length object, so that while writing the data to a file one does not
  * need to copy the meta data and the actual data separately.
  */
-class TraceRecord {
+class TraceRecord
+{
   public:
 int m_cntrl_id;
 Tick m_time;
diff --git a/src/mem/snoop_filter.hh b/src/mem/snoop_filter.hh
index abd66a8..42f95ca 100644
--- a/src/mem/snoop_filter.hh
+++ b/src/mem/snoop_filter.hh
@@ -83,7 +83,8 @@
  * (4) ordering: there is no single point of order in the system.  Instead,
  * requesting MSHRs track order between local requests and remote  
snoops

  */
-class SnoopFilter : public SimObject {
+class SnoopFilter : public SimObject
+{
   public:

 // Change for systems with more than 256 ports tracked by this object
diff --git a/src/sim/futex_map.hh b/src/sim/futex_map.hh
index 081b850..a8a8141 100644
--- a/src/sim/futex_map.hh
+++ b/src/sim/futex_map.hh
@@ -38,7 +38,8 @@
  * FutexKey class defines an unique identifier for a particular futex in  
the

  * system. The tgid and an address are the unique values needed as the key.
  */
-class FutexKey {
+class FutexKey
+{
   public:
 uint64_t addr;
 uint64_t tgid;
@@ -65,7 +66,8 @@
  * WaiterState defines internal state of a waiter thread. The state
  * includes a pointer to the thread's context and its associated bitmask.
  */
-class WaiterState {
+class WaiterState
+{
   public:
 ThreadContext* tc;
 int bitmask;
diff --git a/src/sim/linear_solver.hh b/src/sim/linear_solver.hh
index ca59a81..0ecf7f7 100644
--- a/src/sim/linear_solver.hh
+++ b/src/sim/linear_solver.hh
@@ -49,7 +49,8 @@
  * N+1 coefficients.
  */

-class LinearEquation {
+class LinearEquation
+{
   public:
 LinearEquation(unsigned unknowns) {
 eq = std::vector  (unknowns + 1, 0);
@@ -104,7 +105,8 @@
 std::vector  eq;
 };

-class LinearSystem {
+class LinearSystem
+{
   public:
 LinearSystem(unsigned unknowns) {
 for (unsigned i = 0; i < unknowns; i++)
diff --git a/src/sim/mathexpr.hh b/src/sim/mathexpr.hh
index 3dfe2b8..73247c2 100644
--- a/src/sim/mathexpr.hh
+++ b/src/sim/mathexpr.hh
@@ -44,7 +44,8 @@
 #include 
 #include 

-class MathExpr {
+class MathExpr
+{
   public:

 MathExpr(std::string expr);
@@ -102,7 +103,8 @@
 /** Operator list */
 std::array ops;

-class Node {
+class Node
+{
   public:
 Node() : op(nInvalid), l(0), r(0), value(0) {}
 std::string toStr() const {
diff --git a/src/sim/se_signal.hh b/src/sim/se_signal.hh
index e3241f5..f5f1675 100644
--- a/src/sim/se_signal.hh
+++ b/src/sim/se_signal.hh
@@ -33,7 +33,8 @@

 class Process;

-class BasicSignal {
+class BasicSignal
+{
   public:
 Process *sender;
 Process *receiver;
diff --git a/src/sim/serialize.hh b/src/sim/serialize.hh
index 3acefa4..7525c1f 100644
--- a/src/sim/serialize.hh
+++ b/src/sim/serialize.hh
@@ -164,7 +164,8 @@
 class Serializable
 {
   public:
-class ScopedCheckpointSection {
+class ScopedCheckpointSection
+{
   public:
 /**
  * This is the constructor for Scoped checkpoint section helper
diff --git a/src/sim/syscall_emul_buf.hh b/src/sim/syscall_emul_buf.hh
index dbe9f96..2a79ccd 100644
--- a/src/sim/syscall_emul_buf.hh
+++ b/src/sim/syscall_emul_buf.hh
@@ -51,7 +51,8 @@
  * and copyOut() methods copy the user-space buffer to and from the
  * simulator-space buffer, respectively.
  */
-class BaseBufferArg {
+class BaseBufferArg
+{

   public:

diff --git a/src/unittest/stattest.cc b/src/unittest/stattest.cc
index 4030735..301fea2 100644
--- a/src/unittest/stattest.cc
+++ b/src/unittest/stattest.cc
@@ -63,7 +63,8 @@
 return 9.8;
 }

-class TestClass {
+class TestClass
+{
   public:
 double operator()() { return 9.7; }
 };

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[gem5-dev] Change in gem5/gem5[develop]: util: Add verifier for opening braces of classes

2021-01-12 Thread Daniel Carvalho (Gerrit) via gem5-dev
Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39016 )



Change subject: util: Add verifier for opening braces of classes
..

util: Add verifier for opening braces of classes

Make sure that opening braces of classes are not declared
in the same line of the class name.

This does not work for multi-line classes.

Change-Id: I232df1a9ebd974b9f4f66e1d96d03b12513bd49f
Signed-off-by: Daniel R. Carvalho 
---
M util/style/verifiers.py
1 file changed, 27 insertions(+), 0 deletions(-)



diff --git a/util/style/verifiers.py b/util/style/verifiers.py
index 7d27fda..ddfc0fb 100644
--- a/util/style/verifiers.py
+++ b/util/style/verifiers.py
@@ -460,6 +460,33 @@
   "comparisons with false/False.\n")
 return line

+class ClassBraces(LineVerifier):
+""" Check if the opening braces of classes are not on the same line of
+the class name.
+
+@todo Make this work for multi-line class declarations. e.g.,
+
+class MultiLineClass
+  : public BaseClass {
+"""
+
+languages = set(('C', 'C++'))
+test_name = 'class opening brace position'
+opt_name = 'classbrace'
+
+regex = re.compile(r'\A(\s*)(class\s+[A-Z].*\S)\s*\{')
+
+def check_line(self, line, **kwargs):
+return self.regex.search(line) == None
+
+def fix_line(self, line, **kwargs):
+match = self.regex.search(line)
+if match:
+# Group 1 is indentation, group 2 is class declaration
+line = match.group(1) + match.group(2) + "\n" + \
+match.group(1) + "{"
+return line
+
 def is_verifier(cls):
 """Determine if a class is a Verifier that can be instantiated"""


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Gerrit-Change-Id: I232df1a9ebd974b9f4f66e1d96d03b12513bd49f
Gerrit-Change-Number: 39016
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[gem5-dev] Change in gem5/gem5[develop]: base: Remove begin() and end() from CircleBuf.

2021-01-12 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38998 )



Change subject: base: Remove begin() and end() from CircleBuf.
..

base: Remove begin() and end() from CircleBuf.

These functions return iterators which are inconsistent with the usage
model for this type. It should be accessed using the peek, push, and pop
methods and not iterators. If you need a class with iterators which is
oriented around accessing individual elements at a time, the
CircularQueue type is likely a better choice.

Change-Id: I9f37eab12e490b63d870d378a91f601dad353f25
---
M src/base/circlebuf.hh
1 file changed, 0 insertions(+), 11 deletions(-)



diff --git a/src/base/circlebuf.hh b/src/base/circlebuf.hh
index 0f1cea6..bcfa91a 100644
--- a/src/base/circlebuf.hh
+++ b/src/base/circlebuf.hh
@@ -62,8 +62,6 @@

   public:
 using value_type = T;
-using iterator = typename std::vector::iterator;
-using const_iterator = typename std::vector::const_iterator;

 explicit CircleBuf(size_t size) : buffer(size), maxSize(size) {}

@@ -71,15 +69,6 @@
 size_t size() const { return used; }
 size_t capacity() const { return maxSize; }

-iterator begin() { return buffer.begin() + start % maxSize; }
-const_iterator begin() const { return buffer.begin() + start %  
maxSize; }

-iterator end() { return buffer.begin() + (start + used) % maxSize; }
-const_iterator
-end() const
-{
-return buffer.begin() + (start + used) % maxSize;
-}
-
 /**
  * Throw away any data in the buffer.
  */

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[gem5-dev] Change in gem5/gem5[develop]: sim: Break the eventq.hh dependency in core.hh.

2021-01-12 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38996 )



Change subject: sim: Break the eventq.hh dependency in core.hh.
..

sim: Break the eventq.hh dependency in core.hh.

The original implementation of curTick used a thread local variable,
_curEventQueue, and its getCurTick() method, to retrieve the curTick for
the currently active event queue. That meant that core.hh needed to
include eventq.hh so that the EventQueue type was available, which also
indirectly brought in a lot of other dependencies.

Unfortunately this couldn't easily be fixed by making curTick()
non-inline since this added a significant amount of overhead when
tested.

Instead, this change makes the code in core.hh/core.cc keep a pointer
directly to a Tick. The code which sets _curEventQueue now also sets
that pointer when _curEventQueue changes.

The way curTick() now reaches into the guts of the current EventQueue
directly is not great from a modularity perspective, but if curTick is
considered an extension of the EventQueue, then it's just odd that this
part is broken out into a different file.

Change-Id: I8341b40fe75e90672eb1d70e1a368975fcbfe926
---
M src/sim/core.cc
M src/sim/core.hh
M src/sim/eventq.hh
3 files changed, 27 insertions(+), 3 deletions(-)



diff --git a/src/sim/core.cc b/src/sim/core.cc
index 8b36245..ace699a 100644
--- a/src/sim/core.cc
+++ b/src/sim/core.cc
@@ -41,6 +41,13 @@

 using namespace std;

+namespace Gem5Internal
+{
+
+__thread Tick *_curTickPtr;
+
+} // namespace Gem5Internal
+
 namespace SimClock {
 /// The simulated frequency of curTick(). (In ticks per second)
 Tick Frequency;
diff --git a/src/sim/core.hh b/src/sim/core.hh
index 2e443e7..c592049 100644
--- a/src/sim/core.hh
+++ b/src/sim/core.hh
@@ -39,10 +39,17 @@
 #include 

 #include "base/types.hh"
-#include "sim/eventq.hh"
+
+namespace Gem5Internal
+{
+
+// This pointer is maintained by curEventQueue in src/sim/eventq.hh.
+extern __thread Tick *_curTickPtr;
+
+} // namespace Gem5Internal

 /// The universal simulation clock.
-inline Tick curTick() { return _curEventQueue->getCurTick(); }
+inline Tick curTick() { return *Gem5Internal::_curTickPtr; }

 /// These are variables that are set based on the simulator frequency
 ///@{
diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh
index 45a5ab8..3ef3f56 100644
--- a/src/sim/eventq.hh
+++ b/src/sim/eventq.hh
@@ -48,6 +48,7 @@
 #include "base/types.hh"
 #include "base/uncontended_mutex.hh"
 #include "debug/Event.hh"
+#include "sim/core.hh"
 #include "sim/serialize.hh"

 class EventQueue;   // forward declaration
@@ -81,7 +82,7 @@
 EventQueue *getEventQueue(uint32_t index);

 inline EventQueue *curEventQueue() { return _curEventQueue; }
-inline void curEventQueue(EventQueue *q) { _curEventQueue = q; }
+inline void curEventQueue(EventQueue *q);

 /**
  * Common base class for Event and GlobalEvent, so they can share flag
@@ -617,6 +618,8 @@
 class EventQueue
 {
   private:
+friend void curEventQueue(EventQueue *);
+
 std::string objName;
 Event *head;
 Tick _curTick;
@@ -968,6 +971,13 @@
 }
 };

+inline void
+curEventQueue(EventQueue *q)
+{
+_curEventQueue = q;
+Gem5Internal::_curTickPtr = q ? >_curTick : nullptr;
+}
+
 void dumpMainQueue();

 class EventManager

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[gem5-dev] Change in gem5/gem5[develop]: base: Remove the curTick prototype from base/statistics.hh.

2021-01-12 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38997 )



Change subject: base: Remove the curTick prototype from base/statistics.hh.
..

base: Remove the curTick prototype from base/statistics.hh.

This prototype might convince the compiler that it should refer to
curTick indirectly through the linker, but curTick is inline (and making
it not has very high overhead), so there's a decent chance no non-inline
version will be emitted.

Change-Id: Iab5aacb145d4a974bc1bc0abdf7275c40fbb9c38
---
M src/base/statistics.hh
1 file changed, 2 insertions(+), 3 deletions(-)



diff --git a/src/base/statistics.hh b/src/base/statistics.hh
index 1ad64e9..7115b88 100644
--- a/src/base/statistics.hh
+++ b/src/base/statistics.hh
@@ -81,9 +81,8 @@
 #include "base/intmath.hh"
 #include "base/str.hh"
 #include "base/types.hh"
-
-/** The current simulated tick. */
-extern Tick curTick();
+// For curTick().
+#include "sim/core.hh"

 /* A namespace for all of the Statistics */
 namespace Stats {

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[gem5-dev] Change in gem5/gem5[develop]: misc: Fix missing includes.

2021-01-11 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38995 )



Change subject: misc: Fix missing includes.
..

misc: Fix missing includes.

Change-Id: I545ff03041e8fe66dc489c6aa95c009e54df0970
---
M src/arch/x86/pagetable.hh
M src/base/pollevent.hh
M src/base/remote_gdb.hh
M src/base/trace.hh
M src/cpu/testers/traffic_gen/base_gen.hh
M src/mem/physical.hh
M src/mem/request.hh
7 files changed, 9 insertions(+), 0 deletions(-)



diff --git a/src/arch/x86/pagetable.hh b/src/arch/x86/pagetable.hh
index 803d0de..d45f84c 100644
--- a/src/arch/x86/pagetable.hh
+++ b/src/arch/x86/pagetable.hh
@@ -49,6 +49,7 @@
 #include "base/trie.hh"
 #include "debug/MMU.hh"
 #include "mem/port_proxy.hh"
+#include "sim/serialize.hh"

 class Checkpoint;
 class ThreadContext;
diff --git a/src/base/pollevent.hh b/src/base/pollevent.hh
index 28e16a6..36c083b 100644
--- a/src/base/pollevent.hh
+++ b/src/base/pollevent.hh
@@ -34,6 +34,7 @@
 #include 

 #include "sim/core.hh"
+#include "sim/serialize.hh"

 class Checkpoint;
 class PollQueue;
diff --git a/src/base/remote_gdb.hh b/src/base/remote_gdb.hh
index 3ab0feb..20fb32b 100644
--- a/src/base/remote_gdb.hh
+++ b/src/base/remote_gdb.hh
@@ -53,6 +53,7 @@
 #include "base/pollevent.hh"
 #include "base/socket.hh"
 #include "cpu/pc_event.hh"
+#include "sim/eventq.hh"

 class System;
 class ThreadContext;
diff --git a/src/base/trace.hh b/src/base/trace.hh
index aafb9c8..d826d90 100644
--- a/src/base/trace.hh
+++ b/src/base/trace.hh
@@ -34,6 +34,7 @@

 #include 

+#include "base/compiler.hh"
 #include "base/cprintf.hh"
 #include "base/debug.hh"
 #include "base/match.hh"
diff --git a/src/cpu/testers/traffic_gen/base_gen.hh  
b/src/cpu/testers/traffic_gen/base_gen.hh

index ab9d385..cc9d2a2 100644
--- a/src/cpu/testers/traffic_gen/base_gen.hh
+++ b/src/cpu/testers/traffic_gen/base_gen.hh
@@ -46,6 +46,7 @@
 #include "base/bitfield.hh"
 #include "base/intmath.hh"
 #include "mem/packet.hh"
+#include "sim/sim_object.hh"

 class BaseTrafficGen;

diff --git a/src/mem/physical.hh b/src/mem/physical.hh
index 9d4ff9a..cd914d0 100644
--- a/src/mem/physical.hh
+++ b/src/mem/physical.hh
@@ -40,6 +40,7 @@

 #include "base/addr_range_map.hh"
 #include "mem/packet.hh"
+#include "sim/serialize.hh"

 /**
  * Forward declaration to avoid header dependencies.
diff --git a/src/mem/request.hh b/src/mem/request.hh
index 79cb724..2882374 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -48,8 +48,11 @@
 #ifndef __MEM_REQUEST_HH__
 #define __MEM_REQUEST_HH__

+#include 
 #include 
 #include 
+#include 
+#include 

 #include "base/amo.hh"
 #include "base/flags.hh"

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[gem5-dev] Change in gem5/gem5[develop]: configs: Fix numa_nodes in MeshDirCorners_XY.py config

2021-01-11 Thread Jiayi Huang (Gerrit) via gem5-dev
Jiayi Huang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38975 )



Change subject: configs: Fix numa_nodes in MeshDirCorners_XY.py config
..

configs: Fix numa_nodes in MeshDirCorners_XY.py config

The 'numa_nodes' in makeTopology() cannot be accessed in
registerTopology().

Change-Id: I2ac5c9c841a3d1e55e54995f93108c9532407bb1
---
M configs/topologies/MeshDirCorners_XY.py
1 file changed, 10 insertions(+), 10 deletions(-)



diff --git a/configs/topologies/MeshDirCorners_XY.py  
b/configs/topologies/MeshDirCorners_XY.py

index e0aea52..dc6e4d7 100644
--- a/configs/topologies/MeshDirCorners_XY.py
+++ b/configs/topologies/MeshDirCorners_XY.py
@@ -100,24 +100,24 @@

 # NUMA Node for each quadrant
 # With odd columns or rows, the nodes will be unequal
-numa_nodes = [ [], [], [], []]
+self.numa_nodes = [ [], [], [], []]
 for i in range(num_routers):
 if i % num_columns < num_columns / 2  and \
i < num_routers / 2:
-numa_nodes[0].append(i)
+self.numa_nodes[0].append(i)
 elif i % num_columns >= num_columns / 2  and \
i < num_routers / 2:
-numa_nodes[1].append(i)
+self.numa_nodes[1].append(i)
 elif i % num_columns < num_columns / 2  and \
i >= num_routers / 2:
-numa_nodes[2].append(i)
+self.numa_nodes[2].append(i)
 else:
-numa_nodes[3].append(i)
+self.numa_nodes[3].append(i)

-num_numa_nodes = 0
-for n in numa_nodes:
+self.num_numa_nodes = 0
+for n in self.numa_nodes:
 if n:
-num_numa_nodes += 1
+self.num_numa_nodes += 1

 # Connect the dir nodes to the corners.
 ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[0],
@@ -215,9 +215,9 @@
 # Register nodes with filesystem
 def registerTopology(self, options):
 i = 0
-for n in numa_nodes:
+for n in self.numa_nodes:
 if n:
 FileSystemConfig.register_node(n,
-MemorySize(options.mem_size) // num_numa_nodes, i)
+MemorySize(options.mem_size) // self.num_numa_nodes, i)
 i += 1


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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: CSR registers support in RISC-V remote GDB.

2021-01-11 Thread Peter Yuen (Gerrit) via gem5-dev
RData.at(CSR_MCOUNTEREN).physIndex, r.mcounteren);
+context->setMiscRegNoEffect(
+CSRData.at(CSR_MSCRATCH).physIndex, r.mscratch);
+context->setMiscRegNoEffect(
+CSRData.at(CSR_MEPC).physIndex, r.mepc);
+context->setMiscRegNoEffect(
+CSRData.at(CSR_MCAUSE).physIndex, r.mcause);
+context->setMiscRegNoEffect(
+CSRData.at(CSR_MTVAL).physIndex, r.mtval);
+oldVal = context->readMiscRegNoEffect(
+CSRData.at(CSR_MIP).physIndex);
+mask = CSRMasks.at(CSR_MIP);
+newVal = (oldVal & ~mask) | (r.mip & mask);
+context->setMiscRegNoEffect(
+CSRData.at(CSR_MIP).physIndex, newVal);
+
+// H mode CSR (to be implemented)
 }

-BaseGdbRegCache*
+bool
+RemoteGDB::getXferFeaturesRead(const std::string , std::string  
)

+{
+/**
+ * Blobs e.g. gdb_xml_riscv_target are generated by adding
+ * GdbXml(, ) to src/arch/riscv/Sconscript.
+ *
+ * Import using #include blobs/.hh
+ */
+#define GDB_XML(x, s)\
+{\
+x, std::string(reinterpret_cast(Blobs::s), \
+   Blobs::s##_len)   \
+}
+static const std::map annexMap{
+GDB_XML("target.xml", gdb_xml_riscv_target),
+GDB_XML("riscv-64bit-cpu.xml", gdb_xml_riscv_cpu),
+GDB_XML("riscv-64bit-fpu.xml", gdb_xml_riscv_fpu),
+GDB_XML("riscv-64bit-csr.xml", gdb_xml_riscv_csr)};
+#undef GDB_XML
+auto it = annexMap.find(annex);
+if (it == annexMap.end())
+return false;
+output = it->second;
+return true;
+}
+
+BaseGdbRegCache *
 RemoteGDB::gdbRegs()
 {
 return 
diff --git a/src/arch/riscv/remote_gdb.hh b/src/arch/riscv/remote_gdb.hh
index a9d3b0c..f6aa3cb 100644
--- a/src/arch/riscv/remote_gdb.hh
+++ b/src/arch/riscv/remote_gdb.hh
@@ -57,9 +57,71 @@
 {
   using BaseGdbRegCache::BaseGdbRegCache;
   private:
+/**
+ * RISC-V Register Cache
+ * Order and sizes of registers found in ext/gdb-xml/riscv.xml
+ * To add support for more CSRs:
+ * 1. Uncomment relevant lines in ext/gdb-xml/riscv-64bit-csr.xml
+ * 2. Add register to struct below
+ * 3. Modify RiscvGdbRegCache::getRegs and setRegs
+ */
 struct {
 uint64_t gpr[NumIntArchRegs];
 uint64_t pc;
+uint64_t fpu[NumFloatRegs];
+uint32_t fflags;
+uint32_t frm;
+uint32_t fcsr;
+// Placeholder for byte alignment
+uint32_t placeholder;
+uint64_t cycle;
+uint64_t time;
+uint64_t ustatus;
+uint64_t uie;
+uint64_t utvec;
+uint64_t uscratch;
+uint64_t uepc;
+uint64_t ucause;
+uint64_t utval;
+uint64_t uip;
+uint64_t sstatus;
+uint64_t sedeleg;
+uint64_t sideleg;
+uint64_t sie;
+uint64_t stvec;
+uint64_t scounteren;
+uint64_t sscratch;
+uint64_t sepc;
+uint64_t scause;
+uint64_t stval;
+uint64_t sip;
+uint64_t satp;
+uint64_t mvendorid;
+uint64_t marchid;
+uint64_t mimpid;
+uint64_t mhartid;
+uint64_t mstatus;
+uint64_t misa;
+uint64_t medeleg;
+uint64_t mideleg;
+uint64_t mie;
+uint64_t mtvec;
+uint64_t mcounteren;
+uint64_t mscratch;
+uint64_t mepc;
+uint64_t mcause;
+uint64_t mtval;
+uint64_t mip;
+uint64_t hstatus;
+uint64_t hedeleg;
+uint64_t hideleg;
+uint64_t hie;
+uint64_t htvec;
+uint64_t hscratch;
+uint64_t hepc;
+uint64_t hcause;
+uint64_t hbadaddr;
+uint64_t hip;
 } r;
   public:
 char *data() const { return (char *) }
@@ -79,6 +141,19 @@
   public:
 RemoteGDB(System *_system, ThreadContext *tc, int _port);
 BaseGdbRegCache *gdbRegs() override;
+    /**
+ * Informs GDB remote serial protocol that XML features are supported
+ * GDB then queries for xml blobs using qXfer:features:read:xxx.xml
+ */
+std::vector
+availableFeatures() const
+{
+return {"qXfer:features:read+"};
+};
+/**
+ * Reply to qXfer:features:read:xxx.xml qeuries
+ */
+bool getXferFeaturesRead(const std::string , std::string  
);

 };

 } // namespace RiscvISA

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[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: Fix lsq unit address limit overflow

2021-01-11 Thread Gerrit
周耀阳 has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38935 )



Change subject: cpu-o3: Fix lsq unit address limit overflow
..

cpu-o3: Fix lsq unit address limit overflow

Change-Id: I036e0fc7fe421d8536a6d627f0f76ff5c609bbc7
---
M src/cpu/o3/lsq_unit.hh
1 file changed, 8 insertions(+), 5 deletions(-)



diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index dbe15e6..8b10370 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -753,14 +753,17 @@
 // Check if the store data is within the lower and upper  
bounds of

 // addresses that the request needs.
 auto req_s = req->mainRequest()->getVaddr();
-auto req_e = req_s + req->mainRequest()->getSize();
+auto req_e = req_s - 1 + req->mainRequest()->getSize();
 auto st_s = store_it->instruction()->effAddr;
-auto st_e = st_s + store_size;
+auto st_e = st_s - 1 + store_size;

 bool store_has_lower_limit = req_s >= st_s;
-bool store_has_upper_limit = req_e <= st_e;
-bool lower_load_has_store_part = req_s < st_e;
-bool upper_load_has_store_part = req_e > st_s;
+// bool store_has_upper_limit = req_e <= st_e;
+bool store_has_upper_limit =
+req_s - store_size <= st_s - req->mainRequest()->getSize();
+
+bool lower_load_has_store_part = req_s <= st_e;
+bool upper_load_has_store_part = req_e >= st_s;

 auto coverage = AddrRangeCoverage::NoAddrRangeCoverage;


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[gem5-dev] Change in gem5/gem5[develop]: cpu,mem,sim: Use ADD_STAT macro where possible

2021-01-11 Thread Hoa Nguyen (Gerrit) via gem5-dev
sponder  
(bytes)"),

-  pktSize(this, "pkt_size", "Cumulative packet size per connected "
- "requestor and responder (bytes)")
+  ADD_STAT(transDist, "Transaction distribution"),
+  ADD_STAT(pktCount,
+   "Packet count per connected requestor and responder  
(bytes)"),
+  ADD_STAT(pktSize, "Cumulative packet size per connected requestor  
and "

+    "responder (bytes)")
 {
 }

diff --git a/src/sim/root.cc b/src/sim/root.cc
index 7ca84bf..4927940 100644
--- a/src/sim/root.cc
+++ b/src/sim/root.cc
@@ -54,15 +54,14 @@

 Root::RootStats::RootStats()
 : Stats::Group(nullptr),
-simSeconds(this, "sim_seconds", "Number of seconds simulated"),
-simTicks(this, "sim_ticks", "Number of ticks simulated"),
-finalTick(this, "final_tick",
-  "Number of ticks from beginning of simulation "
-  "(restored from checkpoints and never reset)"),
-simFreq(this, "sim_freq", "Frequency of simulated ticks"),
-hostSeconds(this, "host_seconds", "Real time elapsed on the host"),
-hostTickRate(this, "host_tick_rate", "Simulator tick rate (ticks/s)"),
-hostMemory(this, "host_mem_usage", "Number of bytes of host memory  
used"),

+ADD_STAT(simSeconds, "Number of seconds simulated"),
+ADD_STAT(simTicks, "Number of ticks simulated"),
+ADD_STAT(finalTick, "Number of ticks from beginning of simulation "
+"(restored from checkpoints and never reset)"),
+ADD_STAT(simFreq, "Frequency of simulated ticks"),
+ADD_STAT(hostSeconds, "Real time elapsed on the host"),
+ADD_STAT(hostTickRate, "Simulator tick rate (ticks/s)"),
+ADD_STAT(hostMemory, "Number of bytes of host memory used"),

 statTime(true),
 startTick(0)
diff --git a/src/sim/workload.hh b/src/sim/workload.hh
index c789b65..647225b 100644
--- a/src/sim/workload.hh
+++ b/src/sim/workload.hh
@@ -48,9 +48,8 @@
 Stats::Scalar quiesce;

 WorkloadStats(Workload *workload) : Stats::Group(workload),
-arm(this, "inst.arm", "number of arm instructions executed"),
-quiesce(this, "inst.quiesce",
-"number of quiesce instructions executed")
+ADD_STAT(arm, "number of arm instructions executed"),
+ADD_STAT(quiesce, "number of quiesce instructions executed")
 {}
 } stats;


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[gem5-dev] Change in gem5/gem5[develop]: sim: Rename the root stats group to RootStats

2021-01-11 Thread Hoa Nguyen (Gerrit) via gem5-dev
Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38915 )



Change subject: sim: Rename the root stats group to RootStats
..

sim: Rename the root stats group to RootStats

Currently, the name of the stats group of thr Root object is
Stats, which is likely to be confused with the Stats namespace.

This commit renames the struct to RootStats. This allows the
Stats namespace to be expressed as `Stats::`, which is
consistent with how the namespace is accessed in other part of
gem5.

Change-Id: Ieb425c3df1f5c0d5f11b1a467a36b2e0e07b2771
Signed-off-by: Hoa Nguyen 
---
M src/sim/root.cc
M src/sim/root.hh
2 files changed, 18 insertions(+), 18 deletions(-)



diff --git a/src/sim/root.cc b/src/sim/root.cc
index d9098a6..7ca84bf 100644
--- a/src/sim/root.cc
+++ b/src/sim/root.cc
@@ -49,10 +49,10 @@
 #include "sim/root.hh"

 Root *Root::_root = NULL;
-Root::Stats Root::Stats::instance;
-Root::Stats  = Root::Stats::instance;
+Root::RootStats Root::RootStats::instance;
+Root::RootStats  = Root::RootStats::instance;

-Root::Stats::Stats()
+Root::RootStats::RootStats()
 : Stats::Group(nullptr),
 simSeconds(this, "sim_seconds", "Number of seconds simulated"),
 simTicks(this, "sim_ticks", "Number of ticks simulated"),
@@ -92,7 +92,7 @@
 }

 void
-Root::Stats::resetStats()
+Root::RootStats::resetStats()
 {
 statTime.setTimer();
 startTick = curTick();
@@ -180,7 +180,7 @@
 // stat formulas. The most convenient way to implement that is by
 // having a single global stat group for global stats. Merge that
 // group into the root object here.
-mergeStatGroup(::Stats::instance);
+mergeStatGroup(::RootStats::instance);
 }

 void
diff --git a/src/sim/root.hh b/src/sim/root.hh
index fa152ff..b360f3b 100644
--- a/src/sim/root.hh
+++ b/src/sim/root.hh
@@ -90,26 +90,26 @@
 }

   public: // Global statistics
-struct Stats : public ::Stats::Group
+struct RootStats : public ::Stats::Group
 {
 void resetStats() override;

-::Stats::Formula simSeconds;
-::Stats::Value simTicks;
-::Stats::Value finalTick;
-::Stats::Value simFreq;
-::Stats::Value hostSeconds;
+Stats::Formula simSeconds;
+Stats::Value simTicks;
+Stats::Value finalTick;
+Stats::Value simFreq;
+Stats::Value hostSeconds;

-::Stats::Formula hostTickRate;
-::Stats::Value hostMemory;
+Stats::Formula hostTickRate;
+Stats::Value hostMemory;

-static Stats instance;
+static RootStats instance;

   private:
-Stats();
+RootStats();

-Stats(const Stats &) = delete;
-Stats =(const Stats &) = delete;
+RootStats(const RootStats &) = delete;
+RootStats =(const RootStats &) = delete;

 Time statTime;
 Tick startTick;
@@ -151,6 +151,6 @@
  * Global simulator statistics that are not associated with a
  * specific SimObject.
  */
-extern Root::Stats 
+extern Root::RootStats 

 #endif // __SIM_ROOT_HH__

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[gem5-dev] Change in gem5/gem5[develop]: base: Re-implement CircleBuf without using CircularQueue.

2021-01-10 Thread Gabe Black (Gerrit) via gem5-dev
maxSize;
+len = maxSize;
 }

-std::copy(in, in + len, end());
-advance_tail(len);
+// How much existing data will be overwritten?
+const size_t overflow = std::max(0, used + len - maxSize);
+// The iterator of the next byte to add.
+auto next_it = buffer.begin() + (start + used) % maxSize;
+// How much there is to copy to the end of the buffer.
+const size_t to_end = buffer.end() - next_it;
+
+// If this addition wraps, take care of the first part here.
+if (to_end < len) {
+// Copy it.
+std::copy_n(in, to_end, next_it);
+// Update state to reflect what's left.
+next_it = buffer.begin();
+std::advance(in, to_end);
+len -= to_end;
+used += to_end;
+}
+// Copy the remaining (or only) chunk of data.
+std::copy_n(in, len, next_it);
+used += len;
+
+// Don't count data that was overwritten.
+used -= overflow;
+start += overflow;
 }
 };


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[gem5-dev] Change in gem5/gem5[develop]: tests: Stop using memcmp in the circlebuf test.

2021-01-10 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38895 )



Change subject: tests: Stop using memcmp in the circlebuf test.
..

tests: Stop using memcmp in the circlebuf test.

Comparing arrays with memcmp is fairly easy to do and will correctly
identify when a value is incorrect, but gtest doesn't know what
comparison actually happened and can't print any diagnostic information
to help the person running the test determine what went wrong.

Unfortunately, gtest is also slightly too smart and also not smart
enough to make it easy to compare the contents of sub-arrays with each
other. The thing you're checking the value of *must* be an array with a
well defined size (not a pointer), and the size *must* exactly match the
number of elements it expects to find.

One fairly clean way to get around this problem would be to use the new
std::span type introduced in c++20 which lets you refer to a sub-section
of another container in place, adjusting indexing, sizing, etc as
needed. Unfortunately since we only require up to c++-14 currently we
can't use that type.

Instead, we can create vectors which hold copies of the required data.
This is suboptimal since it means we're copying around data which
doesn't really need to be copied, but it means that the templates in
gtest will get a type they can handle, and the sizes will match like it
expects them to. Since the number of checks/copies is still small, the
overhead should be trivial in practice.

A helper function, subArr, has been added to help keep things fairly
clutter free.

Change-Id: I9f88c583a6a742346b177dba7cae791824b65942
---
M src/base/circlebuf.test.cc
1 file changed, 20 insertions(+), 8 deletions(-)



diff --git a/src/base/circlebuf.test.cc b/src/base/circlebuf.test.cc
index a2babc5..f7d0ea9 100644
--- a/src/base/circlebuf.test.cc
+++ b/src/base/circlebuf.test.cc
@@ -35,15 +35,27 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */

+#include 
 #include 

 #include "base/circlebuf.hh"

+using testing::ElementsAreArray;
+
 const char data[] = {
 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7,
 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
 };

+// A better way to implement this would be with std::span, but that is only
+// available starting in c++20.
+template 
+std::vector
+subArr(T *arr, int size, int offset=0)
+{
+return std::vector(arr + offset, arr + offset + size);
+}
+
 // Basic non-overflow functionality
 TEST(CircleBufTest, BasicReadWriteNoOverflow)
 {
@@ -54,14 +66,14 @@
 buf.write(data, 8);
 EXPECT_EQ(buf.size(), 8);
 buf.peek(foo, 8);
-EXPECT_EQ(memcmp(foo, data, 8), 0);
+EXPECT_THAT(subArr(foo, 8), ElementsAreArray(data, 8));

 // Read 2
 buf.read(foo, 2);
-EXPECT_EQ(memcmp(foo, data, 2), 0);
+EXPECT_THAT(subArr(foo, 2), ElementsAreArray(data, 2));
 EXPECT_EQ(buf.size(), 6);
 buf.read(foo, 6);
-EXPECT_EQ(memcmp(foo, data + 2, 6), 0);
+EXPECT_THAT(subArr(foo, 6), ElementsAreArray(data + 2, 6));
 EXPECT_EQ(buf.size(), 0);
 }

@@ -74,7 +86,7 @@
 buf.write(data, 16);
 EXPECT_EQ(buf.size(), 8);
 buf.peek(foo, 8);
-EXPECT_EQ(memcmp(data + 8, foo, 8), 0);
+EXPECT_THAT(subArr(foo, 8), ElementsAreArray(data + 8, 8));
 }


@@ -89,8 +101,8 @@
 buf.write(data + 8, 6);
 EXPECT_EQ(buf.size(), 8);
 buf.peek(foo, 8);
-EXPECT_EQ(memcmp(data + 4, foo, 2), 0);
-EXPECT_EQ(memcmp(data + 8, foo + 2, 6), 0);
+EXPECT_THAT(subArr(foo, 2), ElementsAreArray(data + 4, 2));
+EXPECT_THAT(subArr(foo, 6, 2), ElementsAreArray(data + 8, 6));
 }

 // Pointer wrap around
@@ -110,9 +122,9 @@
 // Normalized: _start == 2, _stop = 4
 buf.read(foo + 4, 6);
 EXPECT_EQ(buf.size(), 2);
-EXPECT_EQ(memcmp(data, foo, 10), 0);
+EXPECT_THAT(subArr(foo, 10), ElementsAreArray(data, 10));
 // Normalized: _start == 4, _stop = 4
 buf.read(foo + 10, 2);
 EXPECT_EQ(buf.size(), 0);
-EXPECT_EQ(memcmp(data, foo, 12), 0);
+EXPECT_THAT(subArr(foo, 12), ElementsAreArray(data, 12));
 }

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[gem5-dev] Change in gem5/gem5[develop]: base: Add a setNext method to the ChunkGenerator.

2021-01-09 Thread Gabe Black (Gerrit) via gem5-dev
4, chunk_generator.size());
+EXPECT_TRUE(chunk_generator.last());
+EXPECT_FALSE(chunk_generator.next());
+EXPECT_TRUE(chunk_generator.done());
+}
+
+/*
  * A test to consume chunks until the last chunk.
  */
 TEST(ChunkGeneratorTest, AdvanceToLastChunk)

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Gerrit-PatchSet: 9
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Alexandru Duțu 
Gerrit-Reviewer: Bobby R. Bruce 
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Gerrit-Reviewer: Gabe Black 
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[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Fix FLAT insts decrementing lgkm count early

2021-01-07 Thread Matt Sinclair (Gerrit) via gem5-dev
Matt Sinclair has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38696 )


Change subject: gpu-compute: Fix FLAT insts decrementing lgkm count early
..

gpu-compute: Fix FLAT insts decrementing lgkm count early

FLAT instructions used to decrement lgkm count on execute, while the
GCN3 ISA specifies that lgkm count should be decremented on data being
returned or data being written.

This patch changes it so that lgkm is decremented after initiateAcc (for
stores) and after completeAcc (for loads) to better reflect the ISA
definition.

This fixes a bug where waitcnts would be satisfied even though the
memory access wasn't completed, which lead to instructions using the
wrong data.

Change-Id: I596cb031af9cda8d47a1b5e146e4a4ffd793d36c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38696
Reviewed-by: Matt Sinclair 
Reviewed-by: Matthew Poremba 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/gpu-compute/global_memory_pipeline.cc
M src/gpu-compute/gpu_dyn_inst.cc
2 files changed, 7 insertions(+), 1 deletion(-)

Approvals:
  Matthew Poremba: Looks good to me, approved
  Matt Sinclair: Looks good to me, but someone else must approve; Looks  
good to me, approved

  kokoro: Regressions pass



diff --git a/src/gpu-compute/global_memory_pipeline.cc  
b/src/gpu-compute/global_memory_pipeline.cc

index bcd93f8..a2b24e4 100644
--- a/src/gpu-compute/global_memory_pipeline.cc
+++ b/src/gpu-compute/global_memory_pipeline.cc
@@ -130,6 +130,9 @@
 DPRINTF(GPUMem, "CU%d: WF[%d][%d]: Completing global mem  
instr %s\n",

 m->cu_id, m->simdId, m->wfSlotId, m->disassemble());
 m->completeAcc(m);
+if (m->isFlat() && m->isLoad()) {
+w->decLGKMInstsIssued();
+}
 w->decVMemInstsIssued();

 if (m->isLoad() || m->isAtomicRet()) {
@@ -193,6 +196,10 @@
 mp->disassemble(), mp->seqNum());
 mp->initiateAcc(mp);

+if (mp->isFlat() && mp->isStore()) {
+mp->wavefront()->decLGKMInstsIssued();
+}
+
 if (mp->isStore() && mp->isGlobalSeg()) {
 mp->wavefront()->decExpInstsIssued();
 }
diff --git a/src/gpu-compute/gpu_dyn_inst.cc  
b/src/gpu-compute/gpu_dyn_inst.cc

index 03ed689..38e4ecf 100644
--- a/src/gpu-compute/gpu_dyn_inst.cc
+++ b/src/gpu-compute/gpu_dyn_inst.cc
@@ -819,7 +819,6 @@
 if (executedAs() == Enums::SC_GLOBAL) {
 // no transormation for global segment
 wavefront()->execUnitId =  wavefront()->flatGmUnitId;
-wavefront()->decLGKMInstsIssued();
 if (isLoad()) {
 wavefront()->rdLmReqsInPipe--;
 } else if (isStore()) {

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Gerrit-PatchSet: 4
Gerrit-Owner: Kyle Roarty 
Gerrit-Reviewer: Alexandru Duțu 
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[gem5-dev] Change in gem5/gem5[develop]: configs: Remove default bootscript option for fs_bigLITTLE.py

2021-01-07 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38815 )


Change subject: configs: Remove default bootscript option for  
fs_bigLITTLE.py

..

configs: Remove default bootscript option for fs_bigLITTLE.py

Since the beginning fs_bigLITTLE has been pointing to a default

default_rcs = 'bootscript.rcS'

as a System.readfile parameter. That script is not present in
the gem5 repo and all the other fs scripts (starter_fs.py, fs.py
through Options.py) are using an emptry string as default
readfile param value.

We are hence aligning to the other scripts by removing this
default value

Change-Id: I20dc7714deae890d61706459c8d13bd8f5aac7a0
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38815
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M configs/example/arm/fs_bigLITTLE.py
1 file changed, 2 insertions(+), 3 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/example/arm/fs_bigLITTLE.py  
b/configs/example/arm/fs_bigLITTLE.py

index 76de0eb..090e071 100644
--- a/configs/example/arm/fs_bigLITTLE.py
+++ b/configs/example/arm/fs_bigLITTLE.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2016-2017, 2019-2020 ARM Limited
+# Copyright (c) 2016-2017, 2019-2021 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -60,7 +60,6 @@


 default_disk = 'aarch64-ubuntu-trusty-headless.img'
-default_rcs = 'bootscript.rcS'

 default_mem_size= "2GB"

@@ -175,7 +174,7 @@
 help="Hardware platform class")
 parser.add_argument("--disk", action="append", type=str, default=[],
 help="Disks to instantiate")
-parser.add_argument("--bootscript", type=str, default=default_rcs,
+parser.add_argument("--bootscript", type=str, default="",
 help="Linux bootscript")
 parser.add_argument("--cpu-type", type=str,  
choices=list(cpu_types.keys()),

 default="timing",

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I20dc7714deae890d61706459c8d13bd8f5aac7a0
Gerrit-Change-Number: 38815
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: SMMUv3, enable interrupt interface

2021-01-07 Thread Adrian Herrera (Gerrit) via gem5-dev
Adrian Herrera has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38555 )


Change subject: dev-arm: SMMUv3, enable interrupt interface
..

dev-arm: SMMUv3, enable interrupt interface

Users can set "irq_interface_enable" to allow software to program
SMMU_IRQ_CTRL and SMMU_IRQ_CTRLACK. This is required to boot Linux v5.4+
in a reasonable time. Notice the model does not implement architectural
interrupt sources, so no assertions will happen.

Change-Id: Ie138befdf5a204fe8fce961081c575c2166e22b9
Signed-off-by: Adrian Herrera 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38555
Tested-by: kokoro 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M src/dev/arm/SMMUv3.py
M src/dev/arm/smmu_v3.cc
M src/dev/arm/smmu_v3.hh
3 files changed, 17 insertions(+), 2 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/SMMUv3.py b/src/dev/arm/SMMUv3.py
index f53b8ec..f444d64 100644
--- a/src/dev/arm/SMMUv3.py
+++ b/src/dev/arm/SMMUv3.py
@@ -91,6 +91,11 @@
 reg_map = Param.AddrRange('Address range for control registers')
 system = Param.System(Parent.any, "System this device is part of")

+irq_interface_enable = Param.Bool(False,
+"This flag enables software to program SMMU_IRQ_CTRL and "
+"SMMU_IRQ_CTRLACK as if the model implemented architectural "
+"interrupt sources")
+
 device_interfaces = VectorParam.SMMUv3DeviceInterface([],
 "Responder interfaces")

diff --git a/src/dev/arm/smmu_v3.cc b/src/dev/arm/smmu_v3.cc
index 543a11a..3076f5e 100644
--- a/src/dev/arm/smmu_v3.cc
+++ b/src/dev/arm/smmu_v3.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013, 2018-2019 ARM Limited
+ * Copyright (c) 2013, 2018-2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -58,6 +58,7 @@
 requestPort(name() + ".request", *this),
 tableWalkPort(name() + ".walker", *this),
 controlPort(name() + ".control", *this, params.reg_map),
+irqInterfaceEnable(params.irq_interface_enable),
 tlb(params.tlb_entries, params.tlb_assoc, params.tlb_policy, this),
 configCache(params.cfg_entries, params.cfg_assoc, params.cfg_policy,  
this),
 ipaCache(params.ipa_entries, params.ipa_assoc, params.ipa_policy,  
this),

@@ -627,6 +628,13 @@
 assert(pkt->getSize() == sizeof(uint32_t));
 regs.cr0 = regs.cr0ack = pkt->getLE();
 break;
+case offsetof(SMMURegs, irq_ctrl):
+assert(pkt->getSize() == sizeof(uint32_t));
+if (irqInterfaceEnable) {
+warn("SMMUv3::%s No support for interrupt sources",  
__func__);

+regs.irq_ctrl = regs.irq_ctrlack = pkt->getLE();
+}
+break;

 case offsetof(SMMURegs, cr1):
 case offsetof(SMMURegs, cr2):
diff --git a/src/dev/arm/smmu_v3.hh b/src/dev/arm/smmu_v3.hh
index 2d9c1c5..e20ab4d 100644
--- a/src/dev/arm/smmu_v3.hh
+++ b/src/dev/arm/smmu_v3.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013, 2018-2019 ARM Limited
+ * Copyright (c) 2013, 2018-2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -94,6 +94,8 @@
 SMMUTableWalkPort tableWalkPort;
 SMMUControlPort   controlPort;

+const bool irqInterfaceEnable;
+
 ARMArchTLB  tlb;
 ConfigCache configCache;
 IPACacheipaCache;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie138befdf5a204fe8fce961081c575c2166e22b9
Gerrit-Change-Number: 38555
Gerrit-PatchSet: 3
Gerrit-Owner: Adrian Herrera 
Gerrit-Reviewer: Adrian Herrera 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base: Move Named class to its own file

2021-01-06 Thread Daniel Carvalho (Gerrit) via gem5-dev
Tick  
complete)

+MemChecker::ByteTracker::completeWrite(MemChecker::Serial serial,
+Tick complete)
 {
 getIncompleteWriteCluster()->completeWrite(serial, complete);
 pruneTransactions();
@@ -282,7 +285,7 @@

 // Pruning of readObservations
 readObservations.erase(readObservations.begin(),
-       lastCompletedTransaction(,  
before));

+lastCompletedTransaction(, before));

 // Pruning of writeClusters
 if (!writeClusters.empty()) {
diff --git a/src/mem/mem_checker.hh b/src/mem/mem_checker.hh
index 41aa691..7060f88 100644
--- a/src/mem/mem_checker.hh
+++ b/src/mem/mem_checker.hh
@@ -38,13 +38,15 @@
 #ifndef __MEM_MEM_CHECKER_HH__
 #define __MEM_MEM_CHECKER_HH__

+#include 
+#include 
 #include 
 #include 
 #include 
 #include 
 #include 

-#include "base/logging.hh"
+#include "base/named.hh"
 #include "base/trace.hh"
 #include "base/types.hh"
 #include "debug/MemChecker.hh"

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I314e850b4fafd7804d919fd3fe6dec44822e1f48
Gerrit-Change-Number: 38743
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: base: Add M5_VAR_USED in Debug::Flag

2021-01-06 Thread Daniel Carvalho (Gerrit) via gem5-dev
Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38742 )



Change subject: base: Add M5_VAR_USED in Debug::Flag
..

base: Add M5_VAR_USED in Debug::Flag

Add M5_VAR_USED to a variable that is not used in .fast builds.

Change-Id: Ib50043dfd9e9734c0d6435c37ba8d6d65f5723a7
Signed-off-by: Daniel R. Carvalho 
---
M src/base/debug.cc
1 file changed, 4 insertions(+), 3 deletions(-)



diff --git a/src/base/debug.cc b/src/base/debug.cc
index dbf92cf..06597f6 100644
--- a/src/base/debug.cc
+++ b/src/base/debug.cc
@@ -45,7 +45,9 @@

 #include 
 #include 
+#include 

+#include "base/compiler.hh"
 #include "base/cprintf.hh"
 #include "base/logging.hh"

@@ -91,11 +93,10 @@
 Flag::Flag(const char *name, const char *desc)
 : _name(name), _desc(desc)
 {
-std::pair result =
+M5_VAR_USED std::pair result =
 allFlags().insert(std::make_pair(name, this));

-if (!result.second)
-panic("Flag %s already defined!", name);
+panic_if(!result.second, "Flag %s already defined!", name);

 ++allFlagsVersion;


--
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Gerrit-Change-Id: Ib50043dfd9e9734c0d6435c37ba8d6d65f5723a7
Gerrit-Change-Number: 38742
Gerrit-PatchSet: 1
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[gem5-dev] Change in gem5/gem5[develop]: configs: Remove default bootscript option for fs_bigLITTLE.py

2021-01-06 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38815 )



Change subject: configs: Remove default bootscript option for  
fs_bigLITTLE.py

..

configs: Remove default bootscript option for fs_bigLITTLE.py

Since the beginning fs_bigLITTLE has been pointing to a default

default_rcs = 'bootscript.rcS'

as a System.readfile parameter. That script is not present in
the gem5 repo and all the other fs scripts (starter_fs.py, fs.py
through Options.py) are using an emptry string as default
readfile param value.

We are hence aligning to the other scripts by removing this
default value

Change-Id: I20dc7714deae890d61706459c8d13bd8f5aac7a0
Signed-off-by: Giacomo Travaglini 
---
M configs/example/arm/fs_bigLITTLE.py
1 file changed, 2 insertions(+), 3 deletions(-)



diff --git a/configs/example/arm/fs_bigLITTLE.py  
b/configs/example/arm/fs_bigLITTLE.py

index 76de0eb..090e071 100644
--- a/configs/example/arm/fs_bigLITTLE.py
+++ b/configs/example/arm/fs_bigLITTLE.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2016-2017, 2019-2020 ARM Limited
+# Copyright (c) 2016-2017, 2019-2021 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -60,7 +60,6 @@


 default_disk = 'aarch64-ubuntu-trusty-headless.img'
-default_rcs = 'bootscript.rcS'

 default_mem_size= "2GB"

@@ -175,7 +174,7 @@
 help="Hardware platform class")
 parser.add_argument("--disk", action="append", type=str, default=[],
 help="Disks to instantiate")
-parser.add_argument("--bootscript", type=str, default=default_rcs,
+parser.add_argument("--bootscript", type=str, default="",
 help="Linux bootscript")
 parser.add_argument("--cpu-type", type=str,  
choices=list(cpu_types.keys()),

 default="timing",

--
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Gerrit-Change-Id: I20dc7714deae890d61706459c8d13bd8f5aac7a0
Gerrit-Change-Number: 38815
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Gerrit-Owner: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[develop]: dev: Remove the return type from DmaPort::dmaAction.

2021-01-05 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38716 )


Change subject: dev: Remove the return type from DmaPort::dmaAction.
..

dev: Remove the return type from DmaPort::dmaAction.

This function had a comment claiming that returning an arbitrary request
from the call was necessary for page table walker statistics, but
looking at the actual code, the return type was never used. Also
returning whatever the last request happens to be seems arbitrary, and a
bad boundary for modularization. The page table walker should not depend
on the internal implementation of the DMA port.

Change-Id: I00281fbaf6aeb85b15baf54f3d4a23ca1ac72b8b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38716
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/dev/dma_device.cc
M src/dev/dma_device.hh
2 files changed, 6 insertions(+), 12 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/dma_device.cc b/src/dev/dma_device.cc
index 429773d..da35833 100644
--- a/src/dev/dma_device.cc
+++ b/src/dev/dma_device.cc
@@ -141,7 +141,7 @@
 trySendTimingReq();
 }

-RequestPtr
+void
 DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay,
Request::Flags flag)
@@ -151,10 +151,6 @@
 // i.e. cache line size
 DmaReqState *reqState = new DmaReqState(event, size, delay);

-// (functionality added for Table Walker statistics)
-// We're only interested in this when there will only be one request.
-// For simplicity, we return the last request, which would also be
-// the only request in that case.
 RequestPtr req = nullptr;

 DPRINTF(DMA, "Starting DMA for addr: %#x size: %d sched: %d\n", addr,  
size,

@@ -186,16 +182,14 @@
 // just created, for atomic this involves actually completing all
 // the requests
 sendDma();
-
-return req;
 }

-RequestPtr
+void
 DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
uint8_t *data, Tick delay, Request::Flags flag)
 {
-return dmaAction(cmd, addr, size, event, data,
- defaultSid, defaultSSid, delay, flag);
+dmaAction(cmd, addr, size, event, data,
+  defaultSid, defaultSSid, delay, flag);
 }

 void
diff --git a/src/dev/dma_device.hh b/src/dev/dma_device.hh
index f617223..00af98d 100644
--- a/src/dev/dma_device.hh
+++ b/src/dev/dma_device.hh
@@ -150,11 +150,11 @@

 DmaPort(ClockedObject *dev, System *s, uint32_t sid=0, uint32_t  
ssid=0);


-RequestPtr
+void
 dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
   uint8_t *data, Tick delay, Request::Flags flag=0);

-RequestPtr
+void
 dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
   uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay,
   Request::Flags flag=0);

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Gerrit-Change-Id: I00281fbaf6aeb85b15baf54f3d4a23ca1ac72b8b
Gerrit-Change-Number: 38716
Gerrit-PatchSet: 7
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Alexandru Duțu 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev: Fix style in the pixel pump base class.

2021-01-05 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38715 )


Change subject: dev: Fix style in the pixel pump base class.
..

dev: Fix style in the pixel pump base class.

Change-Id: I8aa25911b367d36d6862780b39781f13724e79dc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38715
Reviewed-by: Daniel Carvalho 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/dev/pixelpump.hh
1 file changed, 31 insertions(+), 10 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Daniel Carvalho: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/pixelpump.hh b/src/dev/pixelpump.hh
index 853b9d0..86a0ae0 100644
--- a/src/dev/pixelpump.hh
+++ b/src/dev/pixelpump.hh
@@ -65,37 +65,51 @@
 void unserialize(CheckpointIn ) override;

 /** How many pixel clocks are required for one line? */
-Cycles cyclesPerLine() const {
+Cycles
+cyclesPerLine() const
+{
 return Cycles(hSync + hBackPorch +  width + hBackPorch);
 }

 /** How many pixel clocks are required for one frame? */
-Cycles cyclesPerFrame() const {
+Cycles
+cyclesPerFrame() const
+{
 return Cycles(cyclesPerLine() * linesPerFrame());
 }

 /** Calculate the first line of the vsync signal */
-unsigned lineVSyncStart() const {
+unsigned
+lineVSyncStart() const
+{
 return 0;
 }

 /** Calculate the first line of the vertical back porch */
-unsigned lineVBackPorchStart() const {
+unsigned
+lineVBackPorchStart() const
+{
 return lineVSyncStart() + vSync;
 }

 /** Calculate the first line of the visible region */
-unsigned lineFirstVisible() const {
+unsigned
+lineFirstVisible() const
+{
 return lineVBackPorchStart() + vBackPorch;
 }

 /** Calculate the first line of the back porch */
-unsigned lineFrontPorchStart() const {
+unsigned
+lineFrontPorchStart() const
+{
 return lineFirstVisible() + height;
 }

 /** Calculate the total number of lines in a frame */
-unsigned linesPerFrame() const {
+unsigned
+linesPerFrame() const
+{
 return lineFrontPorchStart() + vFrontPorch;
 }

@@ -176,7 +190,9 @@
 bool underrun() const { return _underrun; }

 /** Is the current line within the visible range? */
-bool visibleLine() const {
+bool
+visibleLine() const
+{
 return line >= _timings.lineFirstVisible() &&
 line < _timings.lineFrontPorchStart();
 }
@@ -185,7 +201,9 @@
 unsigned posX() const { return _posX; }

 /** Current pixel position within the visible area */
-unsigned posY() const {
+unsigned
+posY() const
+{
 return visibleLine() ? line - _timings.lineFirstVisible() : 0;
 }

@@ -269,7 +287,10 @@
 void unserialize(CheckpointIn ) override;

 const std::string name() const override { return _name; }
-void process() override {
+
+void
+process() override
+{
 (parent.*func)();
 }


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Gerrit-Change-Id: I8aa25911b367d36d6862780b39781f13724e79dc
Gerrit-Change-Number: 38715
Gerrit-PatchSet: 7
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Alexandru Duțu 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev: Style fixes in the ARM HDLCD device.

2021-01-05 Thread Gabe Black (Gerrit) via gem5-dev
hen the converter is enabled. */
-    PixelConverter conv;
+PixelConverter conv = PixelConverter::rgba_le;

 PixelPump pixelPump;


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Gerrit-Change-Number: 38484
Gerrit-PatchSet: 8
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fix the wrong cause register setting

2021-01-05 Thread Cui Jin (Gerrit) via gem5-dev
Cui Jin has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38755 )


Change subject: arch-riscv: fix the wrong cause register setting
..

arch-riscv: fix the wrong cause register setting

The most significant bit should be set based on interrupt or
exception. I assume in current RV64 implementation the bit should
be 63rd, rather than 31st. This causes interrupt handler to get
invalid cause code.

Minor bug is for the mpie is suppossed to be set to the value of
old mie.

The fix is verified in FS.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-858

Change-Id: I1cc166c254b35f5c1acb3f5774c43149c61cc37a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38755
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/riscv/faults.cc
1 file changed, 7 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index ac4c582..5ac2a3c 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -113,7 +113,7 @@
 tval = MISCREG_MTVAL;

 status.mpp = pp;
-status.mpie = status.sie;
+status.mpie = status.mie;
 status.mie = 0;
 break;
   default:
@@ -122,8 +122,12 @@
 }

 // Set fault cause, privilege, and return PC
-tc->setMiscReg(cause,
-   (isInterrupt() << (sizeof(uint64_t) * 4 - 1)) |  
_code);

+// Interrupt is indicated on the MSB of cause (bit 63 in RV64)
+uint64_t _cause = _code;
+if (isInterrupt()) {
+   _cause |= (1L << 63);
+}
+tc->setMiscReg(cause, _cause);
 tc->setMiscReg(epc, tc->instAddr());
 tc->setMiscReg(tval, trap_value());
 tc->setMiscReg(MISCREG_PRV, prv);

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Gerrit-Change-Id: I1cc166c254b35f5c1acb3f5774c43149c61cc37a
Gerrit-Change-Number: 38755
Gerrit-PatchSet: 3
Gerrit-Owner: Cui Jin 
Gerrit-Reviewer: Cui Jin 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm, system-arm: Remove HDLcd from VExpress_GEM5_VX platforms

2021-01-05 Thread Giacomo Travaglini (Gerrit) via gem5-dev
em5_v2_hdlcd.dtsi \
platforms/vexpress_gem5_v2_base.dtsi

 GEN_DTS=mkdir -p .gen; \
@@ -62,22 +75,45 @@

 all: $(TARGETS)

-.gen/armv7_gem5_v1_%cpu.dts: armv7.dts $(VEXPRESS_GEM5_V1_DTSIS)
-   $(call GEN_DTS,vexpress_gem5_v1.dtsi,$*)
+.gen/armv7_gem5_v1_%cpu.dts: armv7.dts \
+   $(VEXPRESS_GEM5_V1_DTSIS)
+   $(call GEN_DTS,vexpress_gem5_v1_base.dtsi,$*)

-.gen/armv8_gem5_v1_%cpu.dts: armv8.dts $(VEXPRESS_GEM5_V1_DTSIS)
-   $(call GEN_DTS,vexpress_gem5_v1.dtsi,$*)
+.gen/armv7_gem5_v1_hdlcd_%cpu.dts: armv7.dts \
+   $(VEXPRESS_GEM5_V1_HDLCD_DTSIS)
+   $(call GEN_DTS,vexpress_gem5_v1_hdlcd.dtsi,$*)

-.gen/armv8_gem5_v2_%cpu.dts: armv8.dts $(VEXPRESS_GEM5_V2_DTSIS)
-   $(call GEN_DTS,vexpress_gem5_v2.dtsi,$*)
+.gen/armv8_gem5_v1_%cpu.dts: armv8.dts \
+   $(VEXPRESS_GEM5_V1_DTSIS)
+   $(call GEN_DTS,vexpress_gem5_v1_base.dtsi,$*)
+
+.gen/armv8_gem5_v1_hdlcd_%cpu.dts: armv8.dts \
+   $(VEXPRESS_GEM5_V1_HDLCD_DTSIS)
+   $(call GEN_DTS,vexpress_gem5_v1_hdlcd.dtsi,$*)
+
+.gen/armv8_gem5_v2_%cpu.dts: armv8.dts \
+   $(VEXPRESS_GEM5_V2_DTSIS)
+   $(call GEN_DTS,vexpress_gem5_v2_base.dtsi,$*)
+
+.gen/armv8_gem5_v2_hdlcd_%cpu.dts: armv8.dts \
+   $(VEXPRESS_GEM5_V2_HDLCD_DTSIS)
+   $(call GEN_DTS,vexpress_gem5_v2_hdlcd.dtsi,$*)

 .gen/armv8_gem5_v1_big_little%.dts: armv8_big_little.dts \
$(VEXPRESS_GEM5_V1_DTSIS)
-   $(call GEN_DTS,vexpress_gem5_v1.dtsi,$*)
+   $(call GEN_DTS,vexpress_gem5_v1_base.dtsi,$*)
+
+.gen/armv8_gem5_v1_hdlcd_big_little%.dts: armv8_big_little.dts \
+   $(VEXPRESS_GEM5_V1_HDLCD_DTSIS)
+   $(call GEN_DTS,vexpress_gem5_v1_hdlcd.dtsi,$*)

 .gen/armv8_gem5_v2_big_little%.dts: armv8_big_little.dts \
$(VEXPRESS_GEM5_V2_DTSIS)
-   $(call GEN_DTS,vexpress_gem5_v2.dtsi,$*)
+   $(call GEN_DTS,vexpress_gem5_v2_base.dtsi,$*)
+
+.gen/armv8_gem5_v2_hdlcd_big_little%.dts: armv8_big_little.dts \
+   $(VEXPRESS_GEM5_V2_HDLCD_DTSIS)
+   $(call GEN_DTS,vexpress_gem5_v2_hdlcd.dtsi,$*)

 %.dtb: .gen/%.dts
$(DTC) -I dts -O dtb -o $@ $<
diff --git a/system/arm/dt/platforms/vexpress_gem5_v1.dtsi  
b/system/arm/dt/platforms/vexpress_gem5_v1_hdlcd.dtsi

similarity index 100%
rename from system/arm/dt/platforms/vexpress_gem5_v1.dtsi
rename to system/arm/dt/platforms/vexpress_gem5_v1_hdlcd.dtsi
diff --git a/system/arm/dt/platforms/vexpress_gem5_v2.dtsi  
b/system/arm/dt/platforms/vexpress_gem5_v2_hdlcd.dtsi

similarity index 100%
rename from system/arm/dt/platforms/vexpress_gem5_v2.dtsi
rename to system/arm/dt/platforms/vexpress_gem5_v2_hdlcd.dtsi

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[gem5-dev] Change in gem5/gem5[develop]: system-arm: Enabled HDLcd by default in DTS

2021-01-05 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38797 )



Change subject: system-arm: Enabled HDLcd by default in DTS
..

system-arm: Enabled HDLcd by default in DTS

This is fine as people using *_hdlcd.dtsi are willing to simulate
an HDLcd

Change-Id: Ifd5d6ecc81de920dbc29a05b07f30c13dcee3aa4
Signed-off-by: Giacomo Travaglini 
---
M system/arm/dt/platforms/display.dtsi
M system/arm/dt/platforms/vexpress_gem5_v1_hdlcd.dtsi
M system/arm/dt/platforms/vexpress_gem5_v2_hdlcd.dtsi
3 files changed, 4 insertions(+), 15 deletions(-)



diff --git a/system/arm/dt/platforms/display.dtsi  
b/system/arm/dt/platforms/display.dtsi

index 16a029a..64c41e6 100644
--- a/system/arm/dt/platforms/display.dtsi
+++ b/system/arm/dt/platforms/display.dtsi
@@ -55,8 +55,6 @@
 };

  {
-   status = "ok";
-
port {
dp0_output: endpoint@0 {
remote-endpoint = <_virt_input>;
diff --git a/system/arm/dt/platforms/vexpress_gem5_v1_hdlcd.dtsi  
b/system/arm/dt/platforms/vexpress_gem5_v1_hdlcd.dtsi

index efca66d..a11dcb6 100644
--- a/system/arm/dt/platforms/vexpress_gem5_v1_hdlcd.dtsi
+++ b/system/arm/dt/platforms/vexpress_gem5_v1_hdlcd.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019 ARM Limited
+ * Copyright (c) 2015-2019, 2021 ARM Limited
  * All rights reserved
  *
  * Redistribution and use in source and binary forms, with or without
@@ -29,18 +29,13 @@
 /include/ "vexpress_gem5_v1_base.dtsi"

 / {
-   /* The display processor needs custom configuration to setup its
- * output ports. Disable it by default in the platform until the
- * DT bindings have stabilize.
-*/
dp0: hdlcd@2b00 {
compatible = "arm,hdlcd";
reg = <0x0 0x2b00 0x0 0x1000>;
interrupts = <0 63 4>;
clocks = <_pxl>;
clock-names = "pxlclk";
-
-   status = "disabled";
+   status = "ok";
};
 };

diff --git a/system/arm/dt/platforms/vexpress_gem5_v2_hdlcd.dtsi  
b/system/arm/dt/platforms/vexpress_gem5_v2_hdlcd.dtsi

index 6775727..3e8003a 100644
--- a/system/arm/dt/platforms/vexpress_gem5_v2_hdlcd.dtsi
+++ b/system/arm/dt/platforms/vexpress_gem5_v2_hdlcd.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019 ARM Limited
+ * Copyright (c) 2015-2019, 2021 ARM Limited
  * All rights reserved
  *
  * Redistribution and use in source and binary forms, with or without
@@ -29,17 +29,13 @@
 /include/ "vexpress_gem5_v2_base.dtsi"

 / {
-   /* The display processor needs custom configuration to setup its
-* output ports. Disable it by default in the platform until the
-* DT bindings have stabilize.
-*/
dp0: hdlcd@2b00 {
compatible = "arm,hdlcd";
reg = <0x0 0x2b00 0x0 0x1000>;
interrupts = <0 63 4>;
clocks = <_pxl>;
clock-names = "pxlclk";
-   status = "disabled";
+   status = "ok";
};
 };


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Gerrit-Change-Id: Ifd5d6ecc81de920dbc29a05b07f30c13dcee3aa4
Gerrit-Change-Number: 38797
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Gerrit-Owner: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[develop]: system-arm: Move display node into a shared DTS file

2021-01-05 Thread Giacomo Travaglini (Gerrit) via gem5-dev
front-porch = <148>;
-   hback-porch = <88>;
-   hsync-len = <44>;
-   vfront-porch = <36>;
-   vback-porch = <4>;
-   vsync-len = <5>;
-   };
-   };
-   };
 };
-
- {
-   status = "ok";
-
-   port {
-   dp0_output: endpoint@0 {
-   remote-endpoint = <_virt_input>;
-   };
-   };
-};
-
-
diff --git a/system/arm/dt/platforms/display.dtsi  
b/system/arm/dt/platforms/display.dtsi

new file mode 100644
index 000..16a029a
--- /dev/null
+++ b/system/arm/dt/platforms/display.dtsi
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2015-2016, 2019, 2021 ARM Limited
+ * All rights reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/ {
+   virt-encoder {
+   compatible = "drm,virtual-encoder";
+   port {
+   dp0_virt_input: endpoint@0 {
+   remote-endpoint = <_output>;
+   };
+   };
+
+   display-timings {
+   native-mode = <>;
+
+   timing0: timing_1080p60 {
+   /* 1920x1080-60 */
+   clock-frequency = <14850>;
+   hactive = <1920>;
+   vactive = <1080>;
+   hfront-porch = <148>;
+   hback-porch = <88>;
+   hsync-len = <44>;
+   vfront-porch = <36>;
+   vback-porch = <4>;
+   vsync-len = <5>;
+   };
+   };
+   };
+};
+
+ {
+   status = "ok";
+
+   port {
+   dp0_output: endpoint@0 {
+   remote-endpoint = <_virt_input>;
+   };
+   };
+};
diff --git a/system/arm/dt/platforms/vexpress_gem5_v1.dtsi  
b/system/arm/dt/platforms/vexpress_gem5_v1.dtsi

index 91e82c0..efca66d 100644
--- a/system/arm/dt/platforms/vexpress_gem5_v1.dtsi
+++ b/system/arm/dt/platforms/vexpress_gem5_v1.dtsi
@@ -43,3 +43,5 @@
status = "disabled";
};
 };
+
+/include/ "display.dtsi"
diff --git a/system/arm/dt/platforms/vexpress_gem5_v2.dtsi  
b/system/arm/dt/platforms/vexpress_gem5_v2.dtsi

index 6c4dddc..6775727 100644
--- a/system/arm/dt/platforms/vexpress_gem5_v2.dtsi
+++ b/system/arm/dt/platforms/vexpress_gem5_v2.dtsi
@@ -42,3 +42,5 @@
    status = "disabled";
};
 };
+
+/include/ "display.dtsi"

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[gem5-dev] Change in gem5/gem5[develop]: arch: Add a mechanism to pad the src or dest reg index arrays.

2021-01-04 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38380 )


Change subject: arch: Add a mechanism to pad the src or dest reg index  
arrays.

..

arch: Add a mechanism to pad the src or dest reg index arrays.

ARM reaches in and pads out the source register index list behind the
parser's back to force dest regs to also be sources in case an
instruction fails predication and needs to forward the original register
values. It shouldn't be hacking up these values in that way, but since
it is, this will let it continue to do so while still fitting in the new
system where each instruction allocates its src/dest reg index arrays to
size.

Change-Id: Ia296be9f63123f18f6cdc0d3bb1314d33e759b3a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38380
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/isa_parser/isa_parser.py
1 file changed, 11 insertions(+), 1 deletion(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/isa_parser/isa_parser.py  
b/src/arch/isa_parser/isa_parser.py

index ff54889..9ca813e 100755
--- a/src/arch/isa_parser/isa_parser.py
+++ b/src/arch/isa_parser/isa_parser.py
@@ -107,7 +107,8 @@

 myDict['reg_idx_arr_decl'] = \
 'RegId srcRegIdxArr[%d]; RegId destRegIdxArr[%d]' % \
-(d.operands.numSrcRegs, d.operands.numDestRegs)
+(d.operands.numSrcRegs + d.srcRegIdxPadding,
+ d.operands.numDestRegs + d.destRegIdxPadding)

 # The reinterpret casts are largely because an array with a  
known
 # size cannot be passed as an argument which is an array with  
an

@@ -391,6 +392,9 @@

 self.operands = OperandList(parser, compositeCode)

+self.srcRegIdxPadding = 0
+self.destRegIdxPadding = 0
+
 # The header of the constructor declares the variables to be used
 # in the body of the constructor.
 header = ''
@@ -464,6 +468,12 @@
 else:
 self.fp_enable_check = ''

+def padSrcRegIdx(self, padding):
+self.srcRegIdxPadding = padding
+
+def padDestRegIdx(self, padding):
+self.destRegIdxPadding = padding
+

 ###
 #

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Gerrit-Change-Id: Ia296be9f63123f18f6cdc0d3bb1314d33e759b3a
Gerrit-Change-Number: 38380
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev: Cache the cacheLineSize in the DMA read FIFO.

2021-01-04 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38482 )


Change subject: dev: Cache the cacheLineSize in the DMA read FIFO.
..

dev: Cache the cacheLineSize in the DMA read FIFO.

This is a minor simplification which decouples the FIFO from the system
object at run time, although it does need to read the cache line size
out at construction time.

Change-Id: I57d96a676b9604663b6c9ed7c662640f507c5305
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38482
Reviewed-by: Andreas Sandberg 
Reviewed-by: Giacomo Travaglini 
Reviewed-by: Daniel Carvalho 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/dev/dma_device.cc
M src/dev/dma_device.hh
2 files changed, 8 insertions(+), 5 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  Daniel Carvalho: Looks good to me, but someone else must approve
  kokoro: Regressions pass



diff --git a/src/dev/dma_device.cc b/src/dev/dma_device.cc
index 0597306..429773d 100644
--- a/src/dev/dma_device.cc
+++ b/src/dev/dma_device.cc
@@ -53,7 +53,7 @@
 : RequestPort(dev->name() + ".dma", dev),
   device(dev), sys(s), requestorId(s->getRequestorId(dev)),
   sendEvent([this]{ sendDma(); }, dev->name()),
-  defaultSid(sid), defaultSSid(ssid)
+  defaultSid(sid), defaultSSid(ssid), cacheLineSize(s->cacheLineSize())
 { }

 void
@@ -159,7 +159,7 @@

 DPRINTF(DMA, "Starting DMA for addr: %#x size: %d sched: %d\n", addr,  
size,

 event ? event->scheduled() : -1);
-for (ChunkGenerator gen(addr, size, sys->cacheLineSize());
+for (ChunkGenerator gen(addr, size, cacheLineSize);
  !gen.done(); gen.next()) {

 req = std::make_shared(
@@ -286,7 +286,7 @@
  Request::Flags flags)
 : maxReqSize(max_req_size), fifoSize(size),
   reqFlags(flags), port(_port), proxy(port, port.sys->cacheLineSize()),
-  buffer(size)
+  cacheLineSize(port.sys->cacheLineSize()), buffer(size)
 {
 freeRequests.resize(max_pending);
 for (auto  : freeRequests)
@@ -392,8 +392,7 @@
 DmaReadFifo::resumeFillFunctional()
 {
 const size_t fifo_space = buffer.capacity() - buffer.size();
-const size_t kvm_watermark = port.sys->cacheLineSize();
-if (fifo_space >= kvm_watermark || buffer.capacity() < kvm_watermark) {
+if (fifo_space >= cacheLineSize || buffer.capacity() < cacheLineSize) {
 const size_t block_remaining = endAddr - nextAddr;
 const size_t xfer_size = std::min(fifo_space, block_remaining);
 std::vector tmp_buffer(xfer_size);
diff --git a/src/dev/dma_device.hh b/src/dev/dma_device.hh
index 4dec839..f617223 100644
--- a/src/dev/dma_device.hh
+++ b/src/dev/dma_device.hh
@@ -137,6 +137,8 @@
 /** Default substreamId */
 const uint32_t defaultSSid;

+const int cacheLineSize;
+
   protected:

 bool recvTimingResp(PacketPtr pkt) override;
@@ -474,6 +476,8 @@
 DmaPort 
 PortProxy proxy;

+const int cacheLineSize;
+
   private:
 class DmaDoneEvent : public Event
 {

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Gerrit-Change-Number: 38482
Gerrit-PatchSet: 7
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Alexandru Duțu 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim: Fix ParseParam and add Parse/ShowParam tests

2020-12-31 Thread Daniel Carvalho (Gerrit) via gem5-dev
e));
+EXPECT_FALSE(parser.parse("-1000", value));
+
+// 32-bit values
+EXPECT_FALSE(parser.parse("2147483648", value));
+EXPECT_FALSE(parser.parse("-1073741824", value));
+
+// Doubles
+EXPECT_FALSE(parser.parse("123456.789", value));
+EXPECT_FALSE(parser.parse("-123456.789", value));
+EXPECT_TRUE(parser.parse("9.87654e+06", value));
+EXPECT_EQ(char(9), value);
+
+// Characters
+EXPECT_TRUE(parser.parse("69", value));
+EXPECT_EQ('E', value);
+EXPECT_TRUE(parser.parse("97", value));
+EXPECT_EQ('a', value);
+
+// Strings
+EXPECT_FALSE(parser.parse("Test", value));
+}
+
+TEST(SerializeTest, ParseParamString)
+{
+ParseParam parser;
+std::string value("");
+
+// Zero
+EXPECT_TRUE(parser.parse("0", value));
+EXPECT_EQ("0", value);
+
+// Booleans
+EXPECT_TRUE(parser.parse("true", value));
+EXPECT_EQ("true", value);
+EXPECT_TRUE(parser.parse("false", value));
+EXPECT_EQ("false", value);
+
+// 8-bit values
+EXPECT_TRUE(parser.parse("255", value));
+EXPECT_EQ("255", value);
+EXPECT_TRUE(parser.parse("-128", value));
+EXPECT_EQ("-128", value);
+
+// 16-bit values
+EXPECT_TRUE(parser.parse("1000", value));
+EXPECT_EQ("1000", value);
+EXPECT_TRUE(parser.parse("-1000", value));
+EXPECT_EQ("-1000", value);
+
+// 32-bit values
+EXPECT_TRUE(parser.parse("2147483648", value));
+EXPECT_EQ("2147483648", value);
+EXPECT_TRUE(parser.parse("-1073741824", value));
+EXPECT_EQ("-1073741824", value);
+
+// Doubles
+EXPECT_TRUE(parser.parse("123456.789", value));
+EXPECT_EQ("123456.789", value);
+EXPECT_TRUE(parser.parse("-123456.789", value));
+EXPECT_EQ("-123456.789", value);
+EXPECT_TRUE(parser.parse("9.87654e+06", value));
+EXPECT_EQ("9.87654e+06", value);
+
+// Characters
+EXPECT_TRUE(parser.parse("E", value));
+EXPECT_EQ("E", value);
+EXPECT_TRUE(parser.parse("a", value));
+EXPECT_EQ("a", value);
+
+// Strings
+EXPECT_TRUE(parser.parse("Test", value));
+EXPECT_EQ("Test", value);
+}
+
+TEST(SerializeTest, ShowParamInt8)
+{
+ShowParam parser;
+std::stringstream ss;
+
+parser.show(ss, 0);
+EXPECT_EQ("0", ss.str());
+ss.str("");
+parser.show(ss, 127);
+EXPECT_EQ("127", ss.str());
+ss.str("");
+parser.show(ss, -128);
+EXPECT_EQ("-128", ss.str());
+ss.str("");
+}
+
+TEST(SerializeTest, ShowParamUint32)
+{
+ShowParam parser;
+std::stringstream ss;
+
+parser.show(ss, 0);
+EXPECT_EQ("0", ss.str());
+ss.str("");
+parser.show(ss, 255);
+EXPECT_EQ("255", ss.str());
+ss.str("");
+parser.show(ss, 1000);
+EXPECT_EQ("1000", ss.str());
+ss.str("");
+parser.show(ss, 2147483648);
+EXPECT_EQ("2147483648", ss.str());
+ss.str("");
+parser.show(ss, 123456.789);
+EXPECT_EQ("123456", ss.str());
+ss.str("");
+parser.show(ss, 9.87654e+06);
+EXPECT_EQ("9876540", ss.str());
+ss.str("");
+}
+
+/**
+ * Test converting doubles to strings. Floating numbers are expected to
+ * have 6-digit precision.
+ */
+TEST(SerializeTest, ShowParamDouble)
+{
+ShowParam parser;
+std::stringstream ss;
+
+parser.show(ss, 0);
+EXPECT_EQ("0", ss.str());
+ss.str("");
+parser.show(ss, 255);
+EXPECT_EQ("255", ss.str());
+ss.str("");
+parser.show(ss, -1000);
+EXPECT_EQ("-1000", ss.str());
+ss.str("");
+parser.show(ss, 123456.789);
+EXPECT_EQ("123457", ss.str());
+ss.str("");
+parser.show(ss, -123456.789);
+    EXPECT_EQ("-123457", ss.str());
+ss.str("");
+parser.show(ss, 1234567.89);
+    EXPECT_EQ("1.23457e+06", ss.str());
+ss.str("");
+parser.show(ss, -1234567.89);
+EXPECT_EQ("-1.23457e+06", ss.str());
+ss.str("");
+parser.show(ss, 9.87654e+06);
+EXPECT_EQ("9.87654e+06", ss.str());
+ss.str("");
+}
+
+TEST(SerializeTest, ShowParamBool)
+{
+ShowParam parser;
+std::stringstream ss;
+
+parser.show(ss, true);
+EXPECT_EQ("true", ss.str());
+ss.str("");
+parser.show(ss, false);
+EXPECT_EQ("false", ss.str());
+ss.str("");
+}
+
+TEST(SerializeTest, ShowParamChar)
+{
+ShowParam parser;
+std::stringstream ss;
+
+parser.show(ss, 'E');
+EXPECT_EQ("69", ss.str()); // int('E')=69
+ss.str("");
+parser.show(ss, 'a');
+EXPECT_EQ("97", ss.str()); // int('a')=97
+ss.str("");
+}
+
+TEST(SerializeTest, ShowParamString)
+{
+ShowParam parser;
+std::stringstream ss;
+
+parser.show(ss, "test");
+EXPECT_EQ("test", ss.str());
+ss.str("");
+parser.show(ss, "tEsT");
+EXPECT_EQ("tEsT", ss.str());
+ss.str("");
+}

--
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Gerrit-Change-Id: I1128c7adb12a3c7d091e26db13733ba45e1e61fe
Gerrit-Change-Number: 38776
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Gerrit-Owner: Daniel Carvalho 
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[gem5-dev] Change in gem5/gem5[develop]: base: Add double tests to base/str

2020-12-31 Thread Daniel Carvalho (Gerrit) via gem5-dev
Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38775 )



Change subject: base: Add double tests to base/str
..

base: Add double tests to base/str

Add a few extra tests for conversions from double string.
One verifies that strings containing a double are always
rounded down when converted to integer types; the second
verifies that converting numbers in scientific notation
to integers will yield incorrect results; and the third
converts a string containing a number in scientific
notation to double.

Change-Id: I6a9599d8473909d274326b6f8c268e3603044ab4
Signed-off-by: Daniel R. Carvalho 
---
M src/base/str.test.cc
1 file changed, 27 insertions(+), 0 deletions(-)



diff --git a/src/base/str.test.cc b/src/base/str.test.cc
index a064a87..9d8aa60 100644
--- a/src/base/str.test.cc
+++ b/src/base/str.test.cc
@@ -285,6 +285,24 @@
 EXPECT_FALSE(to_number(input, output));
 }

+TEST(StrTest, ToNumberIntRoundDown)
+{
+uint32_t output;
+std::string input = "2.99";
+EXPECT_TRUE(to_number(input, output));
+EXPECT_EQ(2, output);
+}
+
+TEST(StrTest, ToNumberIntScientific)
+{
+// Scientific number conversion should be done with floating numbers.
+// If converting to ints, conversion will be done incorrectly, as  
expected

+uint32_t output;
+std::string input = "8.234e+08";
+EXPECT_TRUE(to_number(input, output));
+EXPECT_EQ(8, output);
+}
+
 TEST(StrTest, ToNumber64BitInt)
 {
 int64_t output;
@@ -355,6 +373,15 @@
 EXPECT_EQ(expected_output, output);
 }

+TEST(StrTest, ToNumberScientific)
+{
+double output;
+std::string input = "8.234e+08";
+double expected_output = 82340;
+EXPECT_TRUE(to_number(input, output));
+EXPECT_EQ(expected_output, output);
+}
+
 /*
  * The "to_bool" function takes a string, "true" or "false"
  * (case-insenstive), and sets the second argument to the bool equivilent.

--
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Gerrit-Change-Id: I6a9599d8473909d274326b6f8c268e3603044ab4
Gerrit-Change-Number: 38775
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho 
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[gem5-dev] Change in gem5/gem5[develop]: dev: Make DMA devices use their own ports for functional accesses.

2020-12-31 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38481 )


Change subject: dev: Make DMA devices use their own ports for functional  
accesses.

..

dev: Make DMA devices use their own ports for functional accesses.

DMA devices already have ports they use for non-functional accesses. We
can just attach a port proxy to that instead of getting one from the
system object.

Change-Id: I5e9adee43c7fe07b4c90978dbb7ec71468caadbb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38481
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Alexandru Duțu 
---
M src/dev/dma_device.cc
M src/dev/dma_device.hh
2 files changed, 5 insertions(+), 3 deletions(-)

Approvals:
  Alexandru Duțu: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/dma_device.cc b/src/dev/dma_device.cc
index efa9ef7..0597306 100644
--- a/src/dev/dma_device.cc
+++ b/src/dev/dma_device.cc
@@ -45,7 +45,6 @@
 #include "base/chunk_generator.hh"
 #include "debug/DMA.hh"
 #include "debug/Drain.hh"
-#include "mem/port_proxy.hh"
 #include "sim/clocked_object.hh"
 #include "sim/system.hh"

@@ -286,7 +285,8 @@
  unsigned max_pending,
  Request::Flags flags)
 : maxReqSize(max_req_size), fifoSize(size),
-  reqFlags(flags), port(_port), buffer(size)
+  reqFlags(flags), port(_port), proxy(port, port.sys->cacheLineSize()),
+  buffer(size)
 {
 freeRequests.resize(max_pending);
 for (auto  : freeRequests)
@@ -403,7 +403,7 @@
 "fifo_space=%#x block_remaining=%#x\n",
 nextAddr, xfer_size, fifo_space, block_remaining);

-port.sys->physProxy.readBlob(nextAddr, tmp_buffer.data(),  
xfer_size);

+proxy.readBlob(nextAddr, tmp_buffer.data(), xfer_size);
 buffer.write(tmp_buffer.begin(), xfer_size);
 nextAddr += xfer_size;
 }
diff --git a/src/dev/dma_device.hh b/src/dev/dma_device.hh
index 9752c21..4dec839 100644
--- a/src/dev/dma_device.hh
+++ b/src/dev/dma_device.hh
@@ -46,6 +46,7 @@

 #include "base/circlebuf.hh"
 #include "dev/io_device.hh"
+#include "mem/port_proxy.hh"
 #include "params/DmaDevice.hh"
 #include "sim/drain.hh"
 #include "sim/system.hh"
@@ -471,6 +472,7 @@
 const Request::Flags reqFlags;

 DmaPort 
+PortProxy proxy;

   private:
 class DmaDoneEvent : public Event

--
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Gerrit-Change-Id: I5e9adee43c7fe07b4c90978dbb7ec71468caadbb
Gerrit-Change-Number: 38481
Gerrit-PatchSet: 7
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Alexandru Duțu 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev: Style fixes in src/dev/dma_device.(cc|hh).

2020-12-31 Thread Gabe Black (Gerrit) via gem5-dev
td::deque freeRequests;

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Gerrit-Change-Number: 38480
Gerrit-PatchSet: 6
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Alexandru Duțu 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: base: Style fixes in the CircleBuf and Fifo classes.

2020-12-31 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38479 )


Change subject: base: Style fixes in the CircleBuf and Fifo classes.
..

base: Style fixes in the CircleBuf and Fifo classes.

Change-Id: Ia08548027973e2b18e09bc3f05a6498855bdd7f7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38479
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Daniel Carvalho 
---
M src/base/circlebuf.hh
1 file changed, 22 insertions(+), 17 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/circlebuf.hh b/src/base/circlebuf.hh
index 548e73f..8d7297a 100644
--- a/src/base/circlebuf.hh
+++ b/src/base/circlebuf.hh
@@ -74,7 +74,9 @@
  * @param len Number of elements to copy
  */
 template 
-void peek(OutputIterator out, size_t len) const {
+void
+peek(OutputIterator out, size_t len) const
+{
 peek(out, 0, len);
 }

@@ -86,9 +88,11 @@
  * @param len Number of elements to copy
  */
 template 
-void peek(OutputIterator out, off_t offset, size_t len) const {
+void
+peek(OutputIterator out, off_t offset, size_t len) const
+{
 panic_if(offset + len > size(),
- "Trying to read past end of circular buffer.\n");
+ "Trying to read past end of circular buffer.");

 std::copy(begin() + offset, begin() + offset + len, out);
 }
@@ -100,7 +104,9 @@
  * @param len Number of elements to read
  */
 template 
-void read(OutputIterator out, size_t len) {
+void
+read(OutputIterator out, size_t len)
+{
 peek(out, len);
 pop_front(len);
 }
@@ -112,7 +118,9 @@
  * @param len Number of elements to read
  */
 template 
-void write(InputIterator in, size_t len) {
+void
+write(InputIterator in, size_t len)
+{
 // Writes that are larger than the backing store are allowed,
 // but only the last part of the buffer will be written.
 if (len > capacity()) {
@@ -143,8 +151,7 @@
 typedef T value_type;

   public:
-Fifo(size_t size)
-: buf(size) {}
+Fifo(size_t size) : buf(size) {}

 bool empty() const { return buf.empty(); }
 size_t size() const { return buf.size(); }
@@ -158,9 +165,10 @@
 void read(OutputIterator out, size_t len) { buf.read(out, len); }

 template 
-void write(InputIterator in, size_t len) {
-panic_if(size() + len > capacity(),
- "Trying to overfill FIFO buffer.\n");
+void
+write(InputIterator in, size_t len)
+{
+panic_if(size() + len > capacity(), "Trying to overfill FIFO  
buffer.");

 buf.write(in, len);
 }

@@ -181,8 +189,7 @@

 template 
 void
-arrayParamIn(CheckpointIn , const std::string ,
- CircleBuf )
+arrayParamIn(CheckpointIn , const std::string , CircleBuf  
)

 {
 std::vector temp;
 arrayParamIn(cp, name, temp);
@@ -193,8 +200,7 @@

 template 
 void
-arrayParamOut(CheckpointOut , const std::string ,
-  const Fifo )
+arrayParamOut(CheckpointOut , const std::string , const Fifo  
)

 {
 std::vector temp(param.size());
 param.peek(temp.begin(), temp.size());
@@ -203,14 +209,13 @@

 template 
 void
-arrayParamIn(CheckpointIn , const std::string ,
- Fifo )
+arrayParamIn(CheckpointIn , const std::string , Fifo )
 {
 std::vector temp;
 arrayParamIn(cp, name, temp);

 fatal_if(param.capacity() < temp.size(),
- "Trying to unserialize data into too small FIFO\n");
+ "Trying to unserialize data into too small FIFO");

 param.flush();
 param.write(temp.cbegin(), temp.size());

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia08548027973e2b18e09bc3f05a6498855bdd7f7
Gerrit-Change-Number: 38479
Gerrit-PatchSet: 6
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base,cpu: Simplify the CircularQueue class significantly.

2020-12-31 Thread Gabe Black (Gerrit) via gem5-dev
st(this), tail() + 1);
 }

-/**
- * Return an iterator to an index in the vector.
- * This poses the problem of round determination. By convention, the  
round

- * is picked so that isValidIndex(idx, round) is true. If that is not
- * possible, then the round value is _round, unless _tail is at the  
end of

- * the storage, in which case the PTE wraps up and becomes _round + 1
- */
-iterator
-getIterator(size_t idx)
-{
-assert(isValidIdx(idx) || moduloAdd(_tail, 1) == idx);
-if (_empty)
-return end();
-
-uint32_t round = _round;
-if (idx > _tail) {
-if (idx >= _head && _head > _tail) {
-round -= 1;
-}
-} else if (idx < _head && _tail + 1 == _capacity) {
-round += 1;
-}
-return iterator(this, idx, round);
-}
+/** Return an iterator to an index in the queue. */
+iterator getIterator(size_t idx) { return iterator(this, idx); }
 };

 #endif /* __BASE_CIRCULARQUEUE_HH__ */
diff --git a/src/base/circular_queue.test.cc  
b/src/base/circular_queue.test.cc

index 51d3c01..ffbdce2 100644
--- a/src/base/circular_queue.test.cc
+++ b/src/base/circular_queue.test.cc
@@ -57,7 +57,7 @@
 {
 const auto cq_size = 8;
 CircularQueue cq(cq_size);
-ASSERT_EQ(cq.head(), cq.tail() + 1);
+ASSERT_EQ(cq.head(), (cq.tail() + 1) % cq_size);
 }

 /** Adding elements to the circular queue.
@@ -135,7 +135,7 @@
 }

 ASSERT_TRUE(cq.full());
-ASSERT_EQ(cq.head(), cq.tail() + 1);
+ASSERT_EQ(cq.head(), (cq.tail() + 1) % cq_size);
 }

 /** Testing CircularQueue::begin(), CircularQueue::end()
@@ -196,10 +196,8 @@
 cq.push_back(first_value);
 cq.push_back(second_value);

-auto negative_offset = -(cq_size + 1);
 auto it_1 = cq.begin();
 auto it_2 = cq.begin() + 1;
-auto it_3 = cq.begin() - negative_offset;

 // Operators test
 ASSERT_TRUE(it_1 != it_2);
@@ -213,7 +211,6 @@
 ASSERT_EQ(it_1, it_2 - 1);
 ASSERT_EQ(it_2 - it_1, 1);
 ASSERT_EQ(it_1 - it_2, -1);
-ASSERT_EQ(it_3._round, 1);

 auto temp_it = it_1;
 ASSERT_EQ(++temp_it, it_2);
@@ -240,7 +237,7 @@
 auto starting_it = cq.begin();
 auto ending_it = starting_it + cq_size;

-ASSERT_EQ(starting_it._idx, ending_it._idx);
+ASSERT_EQ(ending_it - starting_it, cq_size);
 ASSERT_TRUE(starting_it != ending_it);
 }

@@ -264,6 +261,5 @@
 auto starting_it = cq.begin();
 auto ending_it = cq.end();

-ASSERT_EQ(starting_it._round + 1, ending_it._round);
 ASSERT_EQ(ending_it - starting_it, cq_size);
 }
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 9fe5b53..0b8a272 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -223,11 +223,11 @@
 uint8_t *memData;

 /** Load queue index. */
-int16_t lqIdx;
+ssize_t lqIdx;
 LQIterator lqIt;

 /** Store queue index. */
-int16_t sqIdx;
+ssize_t sqIdx;
 SQIterator sqIt;


diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 93ac009..2c6a16c 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -343,6 +343,7 @@
 assert(!loadQueue.back().valid());
 loadQueue.back().set(load_inst);
 load_inst->lqIdx = loadQueue.tail();
+assert(load_inst->lqIdx > 0);
 load_inst->lqIt = loadQueue.getIterator(load_inst->lqIdx);

 ++loads;
@@ -400,7 +401,8 @@
 storeQueue.advance_tail();

 store_inst->sqIdx = storeQueue.tail();
-    store_inst->lqIdx = loadQueue.moduloAdd(loadQueue.tail(), 1);
+store_inst->lqIdx = loadQueue.tail() + 1;
+assert(store_inst->lqIdx > 0);
 store_inst->lqIt = loadQueue.end();

 storeQueue.back().set(store_inst);

--
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Gerrit-Change-Number: 38478
Gerrit-PatchSet: 7
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base: Fix style issues in the circular queue.

2020-12-31 Thread Gabe Black (Gerrit) via gem5-dev
larQueue(uint32_t size=0) : _capacity(size)
 {
 Base::resize(size);
 }
@@ -533,7 +535,8 @@
  *
  * @ingroup api_base_utils
  */
-void flush()
+void
+flush()
 {
 _head = 1;
 _round = 0;
@@ -544,7 +547,8 @@
 /**
  * Test if the index is in the range of valid elements.
  */
-bool isValidIdx(size_t idx) const
+bool
+isValidIdx(size_t idx) const
 {
 /* An index is invalid if:
  *   - The queue is empty.
@@ -568,7 +572,8 @@
  * Test if the index is in the range of valid elements.
  * The round counter is used to disambiguate aliasing.
  */
-bool isValidIdx(size_t idx, uint32_t round) const
+bool
+isValidIdx(size_t idx, uint32_t round) const
 {
 /* An index is valid if:
  *   - The queue is not empty.
@@ -630,7 +635,8 @@
 /**
  * @ingroup api_base_utils
  */
-uint32_t size() const
+uint32_t
+size() const
 {
 if (_empty)
 return 0;
@@ -640,12 +646,14 @@
 return _capacity - _head + _tail + 1;
 }

-uint32_t moduloAdd(uint32_t s1, uint32_t s2) const
+uint32_t
+moduloAdd(uint32_t s1, uint32_t s2) const
 {
 return moduloAdd(s1, s2, _capacity);
 }

-uint32_t moduloSub(uint32_t s1, uint32_t s2) const
+uint32_t
+moduloSub(uint32_t s1, uint32_t s2) const
 {
 return moduloSub(s1, s2, _capacity);
 }
@@ -660,9 +668,11 @@
  *
  * @ingroup api_base_utils
  */
-void pop_front(size_t num_elem = 1)
+void
+pop_front(size_t num_elem=1)
 {
-if (num_elem == 0) return;
+if (num_elem == 0)
+return;
 auto hIt = begin();
 hIt += num_elem;
 assert(hIt <= end());
@@ -675,9 +685,10 @@
  *
  * @ingroup api_base_utils
  */
-void pop_back()
+void
+pop_back()
 {
-assert (!_empty);
+assert(!_empty);
 _empty = _head == _tail;
 if (_tail == 0)
 --_round;
@@ -689,7 +700,8 @@
  *
  * @ingroup api_base_utils
  */
-void push_back(typename Base::value_type val)
+void
+push_back(typename Base::value_type val)
 {
 advance_tail();
 (*this)[_tail] = val;
@@ -701,7 +713,8 @@
  *
  * @ingroup api_base_utils
  */
-void advance_tail()
+void
+advance_tail()
 {
 increase(_tail);
 if (_tail == 0)
@@ -720,7 +733,8 @@
  *
  * @ingroup api_base_utils
  */
-void advance_tail(uint32_t len)
+void
+advance_tail(uint32_t len)
 {
 for (auto idx = 0; idx < len; idx++)
 advance_tail();
@@ -741,7 +755,8 @@
  *
  * @ingroup api_base_utils
  */
-bool full() const
+bool
+full() const
 {
 return !_empty &&
 (_tail + 1 == _head || (_tail + 1 == _capacity && _head == 0));
@@ -752,7 +767,8 @@
  *
  * @ingroup api_base_utils
  */
-iterator begin()
+iterator
+begin()
 {
 if (_empty)
 return end();
@@ -766,7 +782,8 @@
 /**
  * @ingroup api_base_utils
  */
-iterator begin() const
+iterator
+begin() const
 {
 if (_empty)
 return end();
@@ -781,7 +798,8 @@
 /**
  * @ingroup api_base_utils
  */
-iterator end()
+iterator
+end()
 {
 auto poi = moduloAdd(_tail, 1);
 auto round = _round;
@@ -793,7 +811,8 @@
 /**
  * @ingroup api_base_utils
  */
-iterator end() const
+iterator
+end() const
 {
 auto poi = moduloAdd(_tail, 1);
 auto round = _round;
@@ -809,7 +828,8 @@
  * possible, then the round value is _round, unless _tail is at the  
end of

  * the storage, in which case the PTE wraps up and becomes _round + 1
  */
-iterator getIterator(size_t idx)
+iterator
+    getIterator(size_t idx)
     {
 assert(isValidIdx(idx) || moduloAdd(_tail, 1) == idx);
 if (_empty)

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I61da587d760019a338522f098745f375a5ce429e
Gerrit-Change-Number: 38477
Gerrit-PatchSet: 6
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fix the wrong cause register setting

2020-12-31 Thread Cui Jin (Gerrit) via gem5-dev
Cui Jin has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38755 )



Change subject: arch-riscv: fix the wrong cause register setting
..

arch-riscv: fix the wrong cause register setting

The most significant bit should be set based on interrupt or
exception. I assume in current RV64 implementation the bit should
be 63rd, rather than 31st. This causes interrupt handler to get
invalid cause code.

Minor bug is for the mpie is suppossed to be set to the value of
old mie.

The fix is verified in FS.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-858

Change-Id: I1cc166c254b35f5c1acb3f5774c43149c61cc37a
---
M src/arch/riscv/faults.cc
1 file changed, 3 insertions(+), 2 deletions(-)



diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index ac4c582..9f0b9a1 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -113,7 +113,7 @@
 tval = MISCREG_MTVAL;

 status.mpp = pp;
-status.mpie = status.sie;
+status.mpie = status.mie;
 status.mie = 0;
 break;
   default:
@@ -123,7 +123,8 @@

 // Set fault cause, privilege, and return PC
 tc->setMiscReg(cause,
-   (isInterrupt() << (sizeof(uint64_t) * 4 - 1)) |  
_code);
+   ((uint64_t)isInterrupt() << (sizeof(uint64_t) * 8 -  
1))

+   | _code);
 tc->setMiscReg(epc, tc->instAddr());
 tc->setMiscReg(tval, trap_value());
 tc->setMiscReg(MISCREG_PRV, prv);

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I1cc166c254b35f5c1acb3f5774c43149c61cc37a
Gerrit-Change-Number: 38755
Gerrit-PatchSet: 1
Gerrit-Owner: Cui Jin 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fix MIE csr register setting bugs

2020-12-30 Thread Cui Jin (Gerrit) via gem5-dev
Cui Jin has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38578 )


Change subject: arch-riscv: fix MIE csr register setting bugs
..

arch-riscv: fix MIE csr register setting bugs

Any changes on xIE bits changes should trigger the updating
of CSR register. The old condition is wrongly reversed.

The fix is verified in FS.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-855

Change-Id: Ia2c6d3fbfd24d7f9d23f7cfa6f25f893544f4157
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38578
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Ayaz Akram 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/riscv/isa/formats/standard.isa
1 file changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Ayaz Akram: Looks good to me, but someone else must approve
  kokoro: Regressions pass



diff --git a/src/arch/riscv/isa/formats/standard.isa  
b/src/arch/riscv/isa/formats/standard.isa

index 72f7dc1..b95af76 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -383,9 +383,9 @@
 xc->setMiscReg(MISCREG_FRM, bits(data, 7, 5));
 break;
   case CSR_MIP: case CSR_MIE:
-if (oldinterrupt.mei == newinterrupt.mei &&
-oldinterrupt.mti == newinterrupt.mti &&
-oldinterrupt.msi == newinterrupt.msi) {
+if (oldinterrupt.mei != newinterrupt.mei ||
+oldinterrupt.mti != newinterrupt.mti ||
+oldinterrupt.msi != newinterrupt.msi) {
  
xc->setMiscReg(CSRData.at(csr).physIndex,data);

 } else {
 std::string error = "Interrupt m bits are "

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia2c6d3fbfd24d7f9d23f7cfa6f25f893544f4157
Gerrit-Change-Number: 38578
Gerrit-PatchSet: 2
Gerrit-Owner: Cui Jin 
Gerrit-Reviewer: Ayaz Akram 
Gerrit-Reviewer: Cui Jin 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Bobby R. Bruce 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: ext: googletest: upgrade to googletest 1.10

2020-12-29 Thread Yu-hsin Wang (Gerrit) via gem5-dev
.cc
M ext/googletest/googletest/test/gtest_xml_test_utils.py
M ext/googletest/googletest/test/production.cc
M ext/googletest/googletest/test/production.h
D ext/googletest/googletest/xcode/Config/DebugProject.xcconfig
D ext/googletest/googletest/xcode/Config/FrameworkTarget.xcconfig
D ext/googletest/googletest/xcode/Config/General.xcconfig
D ext/googletest/googletest/xcode/Config/ReleaseProject.xcconfig
D ext/googletest/googletest/xcode/Config/StaticLibraryTarget.xcconfig
D ext/googletest/googletest/xcode/Config/TestTarget.xcconfig
D ext/googletest/googletest/xcode/Resources/Info.plist
D ext/googletest/googletest/xcode/Samples/FrameworkSample/Info.plist
D  
ext/googletest/googletest/xcode/Samples/FrameworkSample/WidgetFramework.xcodeproj/project.pbxproj

D ext/googletest/googletest/xcode/Samples/FrameworkSample/widget.cc
D ext/googletest/googletest/xcode/Samples/FrameworkSample/widget.h
D ext/googletest/googletest/xcode/Samples/FrameworkSample/widget_test.cc
D ext/googletest/googletest/xcode/Scripts/runtests.sh
D ext/googletest/googletest/xcode/Scripts/versiongenerate.py
D ext/googletest/googletest/xcode/gtest.xcodeproj/project.pbxproj
A ext/googletest/library.json
A ext/googletest/platformio.ini
364 files changed, 33,489 insertions(+), 70,093 deletions(-)

Approvals:
  Gabe Black: Looks good to me, but someone else must approve
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6500e13e9c094efd99ebc72b3ae564861e67c159
Gerrit-Change-Number: 38577
Gerrit-PatchSet: 2
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Ahbong Chang 
Gerrit-CC: Earl Ou 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim: Remove SimObject and Event dependency from serialize.hh

2020-12-29 Thread Daniel Carvalho (Gerrit) via gem5-dev
9b0715..99e27cb 100644
--- a/src/sim/sim_object.cc
+++ b/src/sim/sim_object.cc
@@ -51,6 +51,7 @@
 //
 SimObject::SimObjectList SimObject::simObjectList;
 SimObjectResolver *SimObject::_objNameResolver = NULL;
+Globals SimObject::globals;

 //
 // SimObject constructor: used to maintain static simObjectList
@@ -132,8 +133,13 @@
 // static function: serialize all SimObjects.
 //
 void
-SimObject::serializeAll(CheckpointOut )
+SimObject::serializeAll(const std::string _dir)
 {
+std::ofstream cp;
+Serializable::generateCheckpointOut(cpt_dir, cp);
+
+globals.serializeSection(cp, "Globals");
+
 SimObjectList::reverse_iterator ri = simObjectList.rbegin();
 SimObjectList::reverse_iterator rend = simObjectList.rend();

@@ -145,6 +151,14 @@
}
 }

+void
+SimObject::unserializeGlobals(CheckpointIn )
+{
+globals.unserializeSection(cp, "Globals");
+
+for (uint32_t i = 0; i < numMainEventQueues; ++i)
+mainEventQueue[i]->setCurTick(globals.unserializedCurTick);
+}

 #ifdef DEBUG
 //
@@ -198,3 +212,20 @@
 assert(_objNameResolver);
 return _objNameResolver;
 }
+
+void
+objParamIn(CheckpointIn , const std::string , SimObject * )
+{
+const std::string (Serializable::currentSection());
+std::string path;
+if (!cp.find(section, name, path)) {
+fatal("Can't unserialize '%s:%s'\n", section, name);
+}
+param = SimObject::getSimObjectResolver()->resolveSimObject(path);
+}
+
+void
+debug_serialize(const std::string _dir)
+{
+SimObject::serializeAll(cpt_dir);
+}
diff --git a/src/sim/sim_object.hh b/src/sim/sim_object.hh
index 719f5a5..64b6207 100644
--- a/src/sim/sim_object.hh
+++ b/src/sim/sim_object.hh
@@ -53,6 +53,7 @@
 #include "params/SimObject.hh"
 #include "sim/drain.hh"
 #include "sim/eventq.hh"
+#include "sim/globals.hh"
 #include "sim/port.hh"
 #include "sim/serialize.hh"

@@ -131,6 +132,9 @@
 /** Helper to resolve an object given its name. */
 static SimObjectResolver *_objNameResolver;

+/** The one and only instance of the Globals class. */
+static Globals globals;
+
 /** Manager coordinates hooking up probe points with listeners. */
 ProbeManager *probeManager;

@@ -300,13 +304,14 @@
 /**
  * Serialize all SimObjects in the system.
  */
-static void serializeAll(CheckpointOut );
+static void serializeAll(const std::string _dir);

-#ifdef DEBUG
-  public:
-bool doDebugBreak;
-static void debugObjectBreak(const std::string );
-#endif
+/**
+ * Unserialize globals.
+ *
+ * @ingroup api_serialize
+ */
+void unserializeGlobals(CheckpointIn );

 /**
  * Find the SimObject with the given name and return a pointer to
@@ -332,6 +337,12 @@
  * @return Pointer to the single sim object name resolver.
  */
 static SimObjectResolver *getSimObjectResolver();
+
+#ifdef DEBUG
+  public:
+bool doDebugBreak;
+static void debugObjectBreak(const std::string );
+#endif
 };

 /**
@@ -357,4 +368,47 @@
 void debugObjectBreak(const char *objs);
 #endif

+/**
+ * To avoid circular dependencies the unserialization of SimObjects must be
+ * implemented here.
+ *
+ * @ingroup api_serialize
+ */
+void objParamIn(CheckpointIn , const std::string , SimObject *  
);

+
+void debug_serialize(const std::string _dir);
+
+/**
+ * \def SERIALIZE_OBJ(obj)
+ *
+ * @ingroup api_serialize
+ */
+#define SERIALIZE_OBJ(obj) obj.serializeSection(cp, #obj)
+
+/**
+ * \def UNSERIALIZE_OBJ(obj)
+ *
+ * @ingroup api_serialize
+ */
+#define UNSERIALIZE_OBJ(obj) obj.unserializeSection(cp, #obj)
+
+/**
+ * \def SERIALIZE_OBJPTR(objptr)
+ *
+ * @ingroup api_serialize
+ */
+#define SERIALIZE_OBJPTR(objptr)paramOut(cp, #objptr,  
(objptr)->name())

+
+/**
+ * \def UNSERIALIZE_OBJPTR(objptr)
+ *
+ * @ingroup api_serialize
+ */
+#define UNSERIALIZE_OBJPTR(objptr)  \
+do {\
+SimObject *sptr;\
+objParamIn(cp, #objptr, sptr);  \
+objptr = dynamic_cast(sptr);  \
+} while (0)
+
 #endif // __SIM_OBJECT_HH__

--
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Gerrit-Change-Id: I9438b799d7e9d4c992a62c7f9d1f15f3f3250a5a
Gerrit-Change-Number: 38740
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: sim: Make IniFile non-pointer in CheckpointIn

2020-12-29 Thread Daniel Carvalho (Gerrit) via gem5-dev
Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38741 )



Change subject: sim: Make IniFile non-pointer in CheckpointIn
..

sim: Make IniFile non-pointer in CheckpointIn

There is no need to use a pointer for this variable.

Change-Id: I784c94c8b775880def8339df63540357c2078c7b
Signed-off-by: Daniel R. Carvalho 
---
M src/sim/serialize.cc
M src/sim/serialize.hh
2 files changed, 8 insertions(+), 15 deletions(-)



diff --git a/src/sim/serialize.cc b/src/sim/serialize.cc
index 177aee6..94d0e0f 100644
--- a/src/sim/serialize.cc
+++ b/src/sim/serialize.cc
@@ -49,7 +49,6 @@
 #include 
 #include 

-#include "base/inifile.hh"
 #include "base/trace.hh"
 #include "debug/Checkpoint.hh"

@@ -156,18 +155,14 @@
 }

 CheckpointIn::CheckpointIn(const string _dir)
-: db(new IniFile), _cptDir(setDir(cpt_dir))
+: db(), _cptDir(setDir(cpt_dir))
 {
 string filename = getCptDir() + "/" + CheckpointIn::baseFilename;
-if (!db->load(filename)) {
+if (!db.load(filename)) {
 fatal("Can't load checkpoint file '%s'\n", filename);
 }
 }

-CheckpointIn::~CheckpointIn()
-{
-delete db;
-}
 /**
  * @param section Here we mention the section we are looking for
  * (example: currentsection).
@@ -180,7 +175,7 @@
 bool
 CheckpointIn::entryExists(const string , const string )
 {
-return db->entryExists(section, entry);
+return db.entryExists(section, entry);
 }
 /**
  * @param section Here we mention the section we are looking for
@@ -195,11 +190,11 @@
 bool
 CheckpointIn::find(const string , const string , string  
)

 {
-return db->find(section, entry, value);
+return db.find(section, entry, value);
 }

 bool
 CheckpointIn::sectionExists(const string )
 {
-return db->sectionExists(section);
+return db.sectionExists(section);
 }
diff --git a/src/sim/serialize.hh b/src/sim/serialize.hh
index d4a94f2..3acefa4 100644
--- a/src/sim/serialize.hh
+++ b/src/sim/serialize.hh
@@ -56,24 +56,22 @@
 #include 
 #include 

+#include "base/inifile.hh"
 #include "base/logging.hh"
 #include "sim/serialize_handlers.hh"

-class IniFile;
-
 typedef std::ostream CheckpointOut;

 class CheckpointIn
 {
   private:
-
-IniFile *db;
+IniFile db;

 const std::string _cptDir;

   public:
 CheckpointIn(const std::string _dir);
-~CheckpointIn();
+~CheckpointIn() = default;

 /**
  * @return Returns the current directory being used for creating

--
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[gem5-dev] Change in gem5/gem5[develop]: sim: Move SimObjectResolver dependency to SimObject

2020-12-29 Thread Daniel Carvalho (Gerrit) via gem5-dev
s things that
@@ -127,6 +128,9 @@
 /** List of all instantiated simulation objects. */
 static SimObjectList simObjectList;

+/** Helper to resolve an object given its name. */
+static SimObjectResolver *_objNameResolver;
+
 /** Manager coordinates hooking up probe points with listeners. */
 ProbeManager *probeManager;

@@ -312,6 +316,22 @@
  * @ingroup api_simobject
  */
 static SimObject *find(const char *name);
+
+/**
+ * There is a single object name resolver, and it is only set when
+ * simulation is restoring from checkpoints.
+ *
+ * @param Pointer to the single sim object name resolver.
+ */
+static void setSimObjectResolver(SimObjectResolver *resolver);
+
+/**
+ * There is a single object name resolver, and it is only set when
+ * simulation is restoring from checkpoints.
+ *
+ * @return Pointer to the single sim object name resolver.
+ */
+static SimObjectResolver *getSimObjectResolver();
 };

 /**

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9973bea0e3c6cabb0051a55dbf9aebef8a50fba8
Gerrit-Change-Number: 38739
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: misc: Fix some includes

2020-12-29 Thread Daniel Carvalho (Gerrit) via gem5-dev
quot;base/str.hh"
+
 static std::string
 normalizePath(std::string path)
 {
diff --git a/src/sim/root.hh b/src/sim/root.hh
index fa152ff..a8337ed 100644
--- a/src/sim/root.hh
+++ b/src/sim/root.hh
@@ -53,6 +53,7 @@

 #include "base/statistics.hh"
 #include "base/time.hh"
+#include "base/types.hh"
 #include "params/Root.hh"
 #include "sim/eventq.hh"
 #include "sim/sim_object.hh"
diff --git a/src/sim/serialize_handlers.hh b/src/sim/serialize_handlers.hh
index 8efd895..5e5c3ff 100644
--- a/src/sim/serialize_handlers.hh
+++ b/src/sim/serialize_handlers.hh
@@ -47,8 +47,8 @@


 #include 
-#include 
 #include 
+#include 

 #include "base/str.hh"

diff --git a/src/sim/sim_exit.hh b/src/sim/sim_exit.hh
index a79d3e2..d1791f5 100644
--- a/src/sim/sim_exit.hh
+++ b/src/sim/sim_exit.hh
@@ -29,6 +29,7 @@
 #ifndef __SIM_EXIT_HH__
 #define __SIM_EXIT_HH__

+#include 
 #include 

 #include "base/types.hh"
diff --git a/src/sim/ticked_object.cc b/src/sim/ticked_object.cc
index 3564b4d..79cbd41 100644
--- a/src/sim/ticked_object.cc
+++ b/src/sim/ticked_object.cc
@@ -39,6 +39,7 @@

 #include "params/TickedObject.hh"
 #include "sim/clocked_object.hh"
+#include "sim/serialize.hh"

 Ticked::Ticked(ClockedObject _,
 Stats::Scalar *imported_num_cycles,
diff --git a/src/sim/voltage_domain.cc b/src/sim/voltage_domain.cc
index f6f8396..d770af8 100644
--- a/src/sim/voltage_domain.cc
+++ b/src/sim/voltage_domain.cc
@@ -39,11 +39,11 @@

 #include 

-#include "base/statistics.hh"
+#include "base/logging.hh"
 #include "base/trace.hh"
 #include "debug/VoltageDomain.hh"
 #include "params/VoltageDomain.hh"
-#include "sim/sim_object.hh"
+#include "sim/serialize.hh"

 VoltageDomain::VoltageDomain(const Params )
 : SimObject(p), voltageOpPoints(p.voltage), _perfLevel(0), stats(*this)

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibf314b43a966943a8096958f68382e1e245f29e3
Gerrit-Change-Number: 38738
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho 
Gerrit-MessageType: newchange
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