[gem5-dev] Change in gem5/gem5[develop]: cpu: Rename GpuThread in gpu_ruby_test tester

2021-02-16 Thread Matthew Poremba (Gerrit) via gem5-dev
t/tester_thread.hh
index 1c9fedc..bee4fda 100644
--- a/src/cpu/testers/gpu_ruby_test/gpu_thread.hh
+++ b/src/cpu/testers/gpu_ruby_test/tester_thread.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2020 Advanced Micro Devices, Inc.
+ * Copyright (c) 2017-2021 Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * For use for simulation and test purposes only
@@ -32,11 +32,11 @@
  */

 /*
- * GPU thread issues requests to and receives responses from Ruby memory
+ * Tester thread issues requests to and receives responses from Ruby memory
  */

-#ifndef CPU_TESTERS_PROTOCOL_TESTER_GPU_THREAD_HH_
-#define CPU_TESTERS_PROTOCOL_TESTER_GPU_THREAD_HH_
+#ifndef CPU_TESTERS_PROTOCOL_TESTER_TESTER_THREAD_HH_
+#define CPU_TESTERS_PROTOCOL_TESTER_TESTER_THREAD_HH_

 #include "cpu/testers/gpu_ruby_test/address_manager.hh"
 #include "cpu/testers/gpu_ruby_test/episode.hh"
@@ -45,12 +45,12 @@
 #include "mem/token_port.hh"
 #include "sim/clocked_object.hh"

-class GpuThread : public ClockedObject
+class TesterThread : public ClockedObject
 {
   public:
-typedef GpuThreadParams Params;
-GpuThread(const Params );
-virtual ~GpuThread();
+typedef TesterThreadParams Params;
+TesterThread(const Params );
+virtual ~TesterThread();

 typedef AddressManager::Location Location;
 typedef AddressManager::Value Value;
@@ -60,7 +60,7 @@
 void checkDeadlock();
 void scheduleDeadlockCheckEvent();

-void attachGpuThreadToPorts(ProtocolTester *_tester,
+void attachTesterThreadToPorts(ProtocolTester *_tester,
  ProtocolTester::SeqPort *_port,
  ProtocolTester::GMTokenPort *_tokenPort =  
nullptr,

  ProtocolTester::SeqPort *_sqcPort = nullptr,
@@ -71,7 +71,7 @@
 // must be implemented by a child class
 virtual void hitCallback(PacketPtr pkt) = 0;

-int getGpuThreadId() const { return threadId; }
+int getTesterThreadId() const { return threadId; }
 int getNumLanes() const { return numLanes; }
 // check if the input location would satisfy DRF constraint
 bool checkDRF(Location atomic_loc, Location loc, bool isStore) const;
@@ -79,14 +79,14 @@
 void printAllOutstandingReqs(std::stringstream& ss) const;

   protected:
-class GpuThreadEvent : public Event
+class TesterThreadEvent : public Event
 {
   private:
-GpuThread* thread;
+TesterThread* thread;
 std::string desc;

   public:
-GpuThreadEvent(GpuThread* _thread, std::string _description)
+TesterThreadEvent(TesterThread* _thread, std::string _description)
 : Event(CPU_Tick_Pri), thread(_thread), desc(_description)
 {}
 void setDesc(std::string _description) { desc = _description; }
@@ -94,15 +94,15 @@
 const std::string name() const override { return desc; }
     };

-GpuThreadEvent threadEvent;
+TesterThreadEvent threadEvent;

 class DeadlockCheckEvent : public Event
 {
   private:
-    GpuThread* thread;
+TesterThread* thread;

   public:
-DeadlockCheckEvent(GpuThread* _thread)
+DeadlockCheckEvent(TesterThread* _thread)
 : Event(CPU_Tick_Pri), thread(_thread)
 {}
 void process() override { thread->checkDeadlock(); }
@@ -204,4 +204,4 @@
   std::stringstream& ss) const;
 };

-#endif /* CPU_TESTERS_PROTOCOL_TESTER_GPU_THREAD_HH_ */
+#endif /* CPU_TESTERS_PROTOCOL_TESTER_TESTER_THREAD_HH_ */

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If241edb53ea405c95b0315c609176c6470b29931
Gerrit-Change-Number: 39935
Gerrit-PatchSet: 2
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu,configs: Add DMA thread to Ruby GPU tester

2021-02-16 Thread Matthew Poremba (Gerrit) via gem5-dev
nges() const override
+{
+AddrRangeList ranges;
+ranges.push_back(RangeSize(0, 0xc000));
+return ranges;
+}
+
+// These latencies are not important. Return any integer.
+Tick read(PacketPtr) override { return 10; }
+Tick write(PacketPtr) override { return 10; }
+};
+
+#endif /* __CPU_TESTERS_GPU_RUBY_TEST_TESTER_DMA_HH__ */
diff --git a/src/cpu/testers/gpu_ruby_test/tester_thread.cc  
b/src/cpu/testers/gpu_ruby_test/tester_thread.cc

index 9d12489..0164b5e 100644
--- a/src/cpu/testers/gpu_ruby_test/tester_thread.cc
+++ b/src/cpu/testers/gpu_ruby_test/tester_thread.cc
@@ -159,6 +159,10 @@
 } else {
 curAction = curEpisode->peekCurAction();

+// Only GPU wavefront threads have a token port. For all other  
types

+// of threads evaluate to true.
+bool haveTokens = tokenPort ? tokenPort->haveTokens(numLanes) :  
true;

+
 switch(curAction->getType()) {
 case Episode::Action::Type::ATOMIC:
 // an atomic action must wait for all previous requests
@@ -166,7 +170,7 @@
 if (pendingLdStCount == 0 &&
 pendingFenceCount == 0 &&
 pendingAtomicCount == 0 &&
-tokenPort->haveTokens(numLanes)) {
+haveTokens) {
 return true;
 }

@@ -201,8 +205,7 @@
 assert(pendingAtomicCount == 0);

 // can't issue if there is a pending fence
-if (pendingFenceCount > 0 ||
-!tokenPort->haveTokens(numLanes)) {
+if (pendingFenceCount > 0 || !haveTokens) {
 return false;
 }

@@ -245,7 +248,9 @@
 {
 switch(curAction->getType()) {
     case Episode::Action::Type::ATOMIC:
-tokenPort->acquireTokens(numLanes);
+if (tokenPort) {
+tokenPort->acquireTokens(numLanes);
+}
 issueAtomicOps();
 break;
 case Episode::Action::Type::ACQUIRE:
@@ -255,11 +260,15 @@
 issueReleaseOp();
 break;
 case Episode::Action::Type::LOAD:
-tokenPort->acquireTokens(numLanes);
+if (tokenPort) {
+tokenPort->acquireTokens(numLanes);
+}
 issueLoadOps();
 break;
 case Episode::Action::Type::STORE:
-tokenPort->acquireTokens(numLanes);
+if (tokenPort) {
+tokenPort->acquireTokens(numLanes);
+}
 issueStoreOps();
 break;
 default:

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Gerrit-Change-Id: I63d83e00fd0dcbb1e34c6704d1c2d49ed4e77722
Gerrit-Change-Number: 39936
Gerrit-PatchSet: 3
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Make DMASequencer aware of Atomics

2021-02-16 Thread Matthew Poremba (Gerrit) via gem5-dev
hh
@@ -70,6 +70,7 @@
 /* SLICC callback */
 void dataCallback(const DataBlock , const Addr );
 void ackCallback(const Addr );
+void atomicCallback(const DataBlock , const Addr );

 void recordRequestType(DMASequencerRequestType requestType);


--
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Gerrit-Change-Number: 33716
Gerrit-PatchSet: 3
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu,configs: Add DMA thread to Ruby GPU tester

2021-01-27 Thread Matthew Poremba (Gerrit) via gem5-dev
ntation

+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from  
this

+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS  
IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,  
THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR  
PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS  
BE

+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF  
THE

+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This is a fake DMA device to pass to Ruby.py so it will create the DMA
+ * sequencers and controllers without being protocol specific. It otherwise
+ * does nothing.
+ */
+
+#ifndef __CPU_TESTERS_GPU_RUBY_TEST_TESTER_DMA_HH__
+#define __CPU_TESTERS_GPU_RUBY_TEST_TESTER_DMA_HH__
+
+#include "dev/dma_device.hh"
+#include "params/TesterDma.hh"
+
+class TesterDma : public DmaDevice
+{
+  public:
+typedef TesterDmaParams Params;
+TesterDma(const Params );
+virtual ~TesterDma();
+
+// The tester does not use a huge memory range. The range itself is
+// choosen arbitrarily
+AddrRangeList
+getAddrRanges() const override
+{
+AddrRangeList ranges;
+ranges.push_back(RangeSize(0, 0xc000));
+return ranges;
+}
+
+// These latencies are not important. Return any integer.
+Tick read(PacketPtr) override { return 10; }
+Tick write(PacketPtr) override { return 10; }
+};
+
+#endif /* __CPU_TESTERS_GPU_RUBY_TEST_TESTER_DMA_HH__ */
diff --git a/src/cpu/testers/gpu_ruby_test/tester_thread.cc  
b/src/cpu/testers/gpu_ruby_test/tester_thread.cc

index 9d12489..0164b5e 100644
--- a/src/cpu/testers/gpu_ruby_test/tester_thread.cc
+++ b/src/cpu/testers/gpu_ruby_test/tester_thread.cc
@@ -159,6 +159,10 @@
 } else {
 curAction = curEpisode->peekCurAction();

+// Only GPU wavefront threads have a token port. For all other  
types

+// of threads evaluate to true.
+bool haveTokens = tokenPort ? tokenPort->haveTokens(numLanes) :  
true;

+
 switch(curAction->getType()) {
 case Episode::Action::Type::ATOMIC:
 // an atomic action must wait for all previous requests
@@ -166,7 +170,7 @@
 if (pendingLdStCount == 0 &&
 pendingFenceCount == 0 &&
 pendingAtomicCount == 0 &&
-tokenPort->haveTokens(numLanes)) {
+haveTokens) {
 return true;
 }

@@ -201,8 +205,7 @@
 assert(pendingAtomicCount == 0);

 // can't issue if there is a pending fence
-if (pendingFenceCount > 0 ||
-!tokenPort->haveTokens(numLanes)) {
+if (pendingFenceCount > 0 || !haveTokens) {
 return false;
 }

@@ -245,7 +248,9 @@
 {
 switch(curAction->getType()) {
 case Episode::Action::Type::ATOMIC:
-tokenPort->acquireTokens(numLanes);
+if (tokenPort) {
+tokenPort->acquireTokens(numLanes);
+}
 issueAtomicOps();
 break;
 case Episode::Action::Type::ACQUIRE:
@@ -255,11 +260,15 @@
 issueReleaseOp();
 break;
 case Episode::Action::Type::LOAD:
-tokenPort->acquireTokens(numLanes);
+if (tokenPort) {
+tokenPort->acquireTokens(numLanes);
+}
 issueLoadOps();
 break;
 case Episode::Action::Type::STORE:
-tokenPort->acquireTokens(numLanes);
+if (tokenPort) {
+tokenPort->acquireTokens(numLanes);
+}
 issueStoreOps();
 break;
 default:

--
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Rename GpuThread in gpu_ruby_test tester

2021-01-27 Thread Matthew Poremba (Gerrit) via gem5-dev
 For use for simulation and test purposes only
@@ -32,11 +32,11 @@
  */

 /*
- * GPU thread issues requests to and receives responses from Ruby memory
+ * Tester thread issues requests to and receives responses from Ruby memory
  */

-#ifndef CPU_TESTERS_PROTOCOL_TESTER_GPU_THREAD_HH_
-#define CPU_TESTERS_PROTOCOL_TESTER_GPU_THREAD_HH_
+#ifndef CPU_TESTERS_PROTOCOL_TESTER_TESTER_THREAD_HH_
+#define CPU_TESTERS_PROTOCOL_TESTER_TESTER_THREAD_HH_

 #include "cpu/testers/gpu_ruby_test/address_manager.hh"
 #include "cpu/testers/gpu_ruby_test/episode.hh"
@@ -45,12 +45,12 @@
 #include "mem/token_port.hh"
 #include "sim/clocked_object.hh"

-class GpuThread : public ClockedObject
+class TesterThread : public ClockedObject
 {
   public:
-typedef GpuThreadParams Params;
-GpuThread(const Params );
-virtual ~GpuThread();
+typedef TesterThreadParams Params;
+TesterThread(const Params );
+virtual ~TesterThread();

 typedef AddressManager::Location Location;
 typedef AddressManager::Value Value;
@@ -60,7 +60,7 @@
 void checkDeadlock();
 void scheduleDeadlockCheckEvent();

-void attachGpuThreadToPorts(ProtocolTester *_tester,
+void attachTesterThreadToPorts(ProtocolTester *_tester,
  ProtocolTester::SeqPort *_port,
  ProtocolTester::GMTokenPort *_tokenPort =  
nullptr,

  ProtocolTester::SeqPort *_sqcPort = nullptr,
@@ -71,7 +71,7 @@
 // must be implemented by a child class
 virtual void hitCallback(PacketPtr pkt) = 0;

-int getGpuThreadId() const { return threadId; }
+int getTesterThreadId() const { return threadId; }
 int getNumLanes() const { return numLanes; }
 // check if the input location would satisfy DRF constraint
 bool checkDRF(Location atomic_loc, Location loc, bool isStore) const;
@@ -79,14 +79,14 @@
 void printAllOutstandingReqs(std::stringstream& ss) const;

   protected:
-class GpuThreadEvent : public Event
+class TesterThreadEvent : public Event
 {
   private:
-GpuThread* thread;
+TesterThread* thread;
 std::string desc;

   public:
-GpuThreadEvent(GpuThread* _thread, std::string _description)
+TesterThreadEvent(TesterThread* _thread, std::string _description)
 : Event(CPU_Tick_Pri), thread(_thread), desc(_description)
 {}
 void setDesc(std::string _description) { desc = _description; }
@@ -94,15 +94,15 @@
 const std::string name() const override { return desc; }
     };

-GpuThreadEvent threadEvent;
+TesterThreadEvent threadEvent;

 class DeadlockCheckEvent : public Event
 {
   private:
-GpuThread* thread;
+TesterThread* thread;

   public:
-DeadlockCheckEvent(GpuThread* _thread)
+DeadlockCheckEvent(TesterThread* _thread)
 : Event(CPU_Tick_Pri), thread(_thread)
 {}
 void process() override { thread->checkDeadlock(); }
@@ -204,4 +204,4 @@
   std::stringstream& ss) const;
 };

-#endif /* CPU_TESTERS_PROTOCOL_TESTER_GPU_THREAD_HH_ */
+#endif /* CPU_TESTERS_PROTOCOL_TESTER_TESTER_THREAD_HH_ */

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[gem5-dev] Change in gem5/gem5[develop]: cpu: Implement DMA atomic issue in Ruby GPU tester

2021-01-27 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39937 )



Change subject: cpu: Implement DMA atomic issue in Ruby GPU tester
..

cpu: Implement DMA atomic issue in Ruby GPU tester

This adds the ability to generatic atomic DMA requests using the Ruby
GPU tester.

Change-Id: I2142816b4601229877bb6968cd8ceef54029fa00
---
M src/cpu/testers/gpu_ruby_test/dma_thread.cc
1 file changed, 36 insertions(+), 1 deletion(-)



diff --git a/src/cpu/testers/gpu_ruby_test/dma_thread.cc  
b/src/cpu/testers/gpu_ruby_test/dma_thread.cc

index 254158d..0da3590 100644
--- a/src/cpu/testers/gpu_ruby_test/dma_thread.cc
+++ b/src/cpu/testers/gpu_ruby_test/dma_thread.cc
@@ -174,7 +174,42 @@
 assert(pendingLdStCount == 0);
 assert(pendingAtomicCount == 0);

-// no-op: No DMA protocol exists with Atomics
+Request::Flags flags = Request::ATOMIC_RETURN_OP;
+int lane = 0;
+
+Location location = curAction->getLocation(lane);
+assert(location >= 0);
+
+Addr address = addrManager->getAddress(location);
+
+DPRINTF(ProtocolTest, "%s Episode %d: Issuing Atomic_Inc - Addr %s\n",
+this->getName(), curEpisode->getEpisodeId(),
+printAddress(address));
+
+// must be aligned with store size
+assert(address % sizeof(Value) == 0);
+AtomicOpFunctor *amo_op = new AtomicOpInc();
+auto req = std::make_shared(address, sizeof(Value),
+ flags, tester->requestorId(),
+ 0, threadId,
+ AtomicOpFunctorPtr(amo_op));
+req->setPaddr(address);
+req->setReqInstSeqNum(tester->getActionSeqNum());
+
+PacketPtr pkt = new Packet(req, MemCmd::SwapReq);
+uint8_t* data = new uint8_t[sizeof(Value)];
+pkt->dataDynamic(data);
+pkt->senderState = new ProtocolTester::SenderState(this);
+
+if (!port->sendTimingReq(pkt)) {
+panic("Not expecting failed sendTimingReq\n");
+}
+
+// add an outstanding atomic
+addOutstandingReqs(outstandingAtomics, address, lane, location);
+
+// increment the number of outstanding atomic ops
+pendingAtomicCount++;
 }

 void

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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Fix race related to atomics in VIPER

2021-01-15 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39175 )


Change subject: mem-ruby: Fix race related to atomics in VIPER
..

mem-ruby: Fix race related to atomics in VIPER

There is a race condition in VIPER where an atomic issued to the same
address can occur resulting in multiple trigger messages signalling the
compleition of the atomic operation. The first message was deallocating
the TBE causing the second message to dereference a nullptr when looking
up the TBE.

A counter is added to track the number of in flight AtomicDone trigger
messages. The AtomicDone is not called until the last in flight message
arrives at the trigger queue. The remaining messages call AtomicNotDone
which simply pops the message from the queue and keeps the TBE
allocated.

Change-Id: Ie1de0436861a7c393ad6d2fb2faceb83c18d4cc3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39175
Reviewed-by: Matt Sinclair 
Reviewed-by: Jason Lowe-Power 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/mem/ruby/protocol/GPU_VIPER-TCC.sm
1 file changed, 12 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm  
b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm

index 5edd7db..e21ba99 100644
--- a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
@@ -108,6 +108,7 @@
 MachineID From, desc="Waiting for writeback from...";
 NetDest Destination, desc="Data destination";
 int numAtomics, desc="number remaining atomics";
+int atomicDoneCnt,  desc="number AtomicDones triggered";
   }

   structure(TBETable, external="yes") {
@@ -256,9 +257,17 @@
   peek(triggerQueue_in, TriggerMsg) {
 TBE tbe := TBEs.lookup(in_msg.addr);
 Entry cache_entry := getCacheEntry(in_msg.addr);
-if (tbe.numAtomics == 0) {
+
+// There is a possible race where multiple AtomicDone triggers can  
be

+// sent if another Atomic to the same address is issued after the
+// AtomicDone is triggered but before the message arrives here. For
+// that case we count the number of AtomicDones in flight for this
+// address and only call AtomicDone to deallocate the TBE when it  
is

+// the last in flight message.
+if (tbe.numAtomics == 0 && tbe.atomicDoneCnt == 1) {
 trigger(Event:AtomicDone, in_msg.addr, cache_entry, tbe);
 } else {
+tbe.atomicDoneCnt := tbe.atomicDoneCnt - 1;
 trigger(Event:AtomicNotDone, in_msg.addr, cache_entry, tbe);
 }
   }
@@ -453,6 +462,7 @@
   set_tbe(TBEs.lookup(address));
   tbe.Destination.clear();
   tbe.numAtomics := 0;
+  tbe.atomicDoneCnt := 0;
 }
 if (coreRequestNetwork_in.isReady(clockEdge())) {
   peek(coreRequestNetwork_in, CPURequestMsg) {
@@ -573,6 +583,7 @@
 tbe.numAtomics := tbe.numAtomics - 1;
 if (tbe.numAtomics==0) {
   enqueue(triggerQueue_out, TriggerMsg, 1) {
+tbe.atomicDoneCnt := tbe.atomicDoneCnt + 1;
 out_msg.addr := address;
 out_msg.Type := TriggerType:AtomicDone;
   }

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Gerrit-Change-Id: Ie1de0436861a7c393ad6d2fb2faceb83c18d4cc3
Gerrit-Change-Number: 39175
Gerrit-PatchSet: 3
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Kyle Roarty 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: util-docker: Add gdb to gcn-gpu Dockerfile

2021-01-15 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39096 )


Change subject: util-docker: Add gdb to gcn-gpu Dockerfile
..

util-docker: Add gdb to gcn-gpu Dockerfile

gdb is generally useful.

Change-Id: Ic73822a5f61914cafba0699949dccabc81c03d2a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39096
Reviewed-by: Matt Sinclair 
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Bobby R. Bruce 
Reviewed-by: Kyle Roarty 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M util/dockerfiles/gcn-gpu/Dockerfile
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  Kyle Roarty: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/dockerfiles/gcn-gpu/Dockerfile  
b/util/dockerfiles/gcn-gpu/Dockerfile

index dad41b92..e5683ab 100644
--- a/util/dockerfiles/gcn-gpu/Dockerfile
+++ b/util/dockerfiles/gcn-gpu/Dockerfile
@@ -40,7 +40,8 @@
 libboost-filesystem-dev \
 libboost-system-dev \
 libboost-dev \
-libpng12-dev
+libpng12-dev \
+gdb

 # Use python 3.9 by default
 RUN update-alternatives --install /usr/bin/python3 python3  
/usr/bin/python3.9 1


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Gerrit-Change-Number: 39096
Gerrit-PatchSet: 2
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Kyle Roarty 
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Fix race related to atomics in VIPER

2021-01-14 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39175 )



Change subject: mem-ruby: Fix race related to atomics in VIPER
..

mem-ruby: Fix race related to atomics in VIPER

There is a race condition in VIPER where an atomic issued to the same
address can occur resulting in multiple trigger messages signalling the
compleition of the atomic operation. The first message was deallocating
the TBE causing the second message to dereference a nullptr when looking
up the TBE.

A counter is added to track the number of in flight AtomicDone trigger
messages. The AtomicDone is not called until the last in flight message
arrives at the trigger queue. The remaining messages call AtomicNotDone
which simply pops the message from the queue and keeps the TBE
allocated.

Change-Id: Ie1de0436861a7c393ad6d2fb2faceb83c18d4cc3
---
M src/mem/ruby/protocol/GPU_VIPER-TCC.sm
1 file changed, 12 insertions(+), 1 deletion(-)



diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm  
b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm

index 5edd7db..12097ae 100644
--- a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
@@ -108,6 +108,7 @@
 MachineID From, desc="Waiting for writeback from...";
 NetDest Destination, desc="Data destination";
 int numAtomics, desc="number remaining atomics";
+int atomicDoneCnt,  desc="number AtomicDones triggered";
   }

   structure(TBETable, external="yes") {
@@ -256,9 +257,17 @@
   peek(triggerQueue_in, TriggerMsg) {
 TBE tbe := TBEs.lookup(in_msg.addr);
 Entry cache_entry := getCacheEntry(in_msg.addr);
-if (tbe.numAtomics == 0) {
+
+// The is a possible race where multiple AtomicDone triggers can be
+// sent if another Atomic to the same address is issues after the
+// AtomicDone is triggered but before the message arrives here. For
+// that case we count the number of AtomicDones in flight for this
+// address and only call AtomicDone to deallocate the TBE when it  
is

+// the last in flight message.
+if (tbe.numAtomics == 0 && tbe.atomicDoneCnt == 1) {
 trigger(Event:AtomicDone, in_msg.addr, cache_entry, tbe);
 } else {
+tbe.atomicDoneCnt := tbe.atomicDoneCnt - 1;
 trigger(Event:AtomicNotDone, in_msg.addr, cache_entry, tbe);
 }
   }
@@ -453,6 +462,7 @@
   set_tbe(TBEs.lookup(address));
   tbe.Destination.clear();
   tbe.numAtomics := 0;
+  tbe.atomicDoneCnt := 0;
 }
 if (coreRequestNetwork_in.isReady(clockEdge())) {
   peek(coreRequestNetwork_in, CPURequestMsg) {
@@ -573,6 +583,7 @@
 tbe.numAtomics := tbe.numAtomics - 1;
 if (tbe.numAtomics==0) {
   enqueue(triggerQueue_out, TriggerMsg, 1) {
+tbe.atomicDoneCnt := tbe.atomicDoneCnt + 1;
 out_msg.addr := address;
 out_msg.Type := TriggerType:AtomicDone;
   }

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[gem5-dev] Change in gem5/gem5[develop]: util-docker: Add gdb to gcn-gpu Dockerfile

2021-01-14 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39096 )



Change subject: util-docker: Add gdb to gcn-gpu Dockerfile
..

util-docker: Add gdb to gcn-gpu Dockerfile

gdb is generally useful.

Change-Id: Ic73822a5f61914cafba0699949dccabc81c03d2a
---
M util/dockerfiles/gcn-gpu/Dockerfile
1 file changed, 2 insertions(+), 1 deletion(-)



diff --git a/util/dockerfiles/gcn-gpu/Dockerfile  
b/util/dockerfiles/gcn-gpu/Dockerfile

index dad41b92..e5683ab 100644
--- a/util/dockerfiles/gcn-gpu/Dockerfile
+++ b/util/dockerfiles/gcn-gpu/Dockerfile
@@ -40,7 +40,8 @@
 libboost-filesystem-dev \
 libboost-system-dev \
 libboost-dev \
-libpng12-dev
+libpng12-dev \
+gdb

 # Use python 3.9 by default
 RUN update-alternatives --install /usr/bin/python3 python3  
/usr/bin/python3.9 1


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[gem5-dev] Change in gem5/gem5[develop]: util: Update python version for GCN3

2020-11-09 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/37219 )


Change subject: util: Update python version for GCN3
..

util: Update python version for GCN3

The Python version installed in the Dockerfile for GCN3 by apt-get is
too old to build gem5. This bumps the version to the most recent Python
to avoid needing to update this file too much.

Python 3.9 is install via PPA since it is not available in the official
Ubuntu 16.04 repository. Likewise, pip is installed from "source" as it
is not available for Python 3.9 in from neither the PPA nor Ubuntu.

Change-Id: Ia919f31cf9c9063e1df091cea15590526715739b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37219
Reviewed-by: Matt Sinclair 
Reviewed-by: Daniel Gerzhoy 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M util/dockerfiles/gcn-gpu/Dockerfile
1 file changed, 20 insertions(+), 7 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Daniel Gerzhoy: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/dockerfiles/gcn-gpu/Dockerfile  
b/util/dockerfiles/gcn-gpu/Dockerfile

index 19f3ad7..e13367f 100644
--- a/util/dockerfiles/gcn-gpu/Dockerfile
+++ b/util/dockerfiles/gcn-gpu/Dockerfile
@@ -1,5 +1,12 @@
 FROM ubuntu:16.04

+# Needed for add-apt-repository
+RUN apt-get update && apt-get install -y --no-install-recommends \
+software-properties-common
+
+# Ubuntu 16.04 does not have a python package new enough for gem5, use a  
PPA

+RUN add-apt-repository ppa:deadsnakes/ppa && apt-get update
+
 # Should be minimal needed packages
 RUN apt-get update && apt-get install -y --no-install-recommends \
 findutils \
@@ -20,11 +27,9 @@
 libprotoc-dev \
 libgoogle-perftools-dev \
 python-yaml \
-python3-dev \
-python3 \
-python3-yaml \
-python3-six \
-python3-pip \
+python3.9 \
+python3.9-dev \
+python3.9-distutils \
 wget \
 libpci3 \
 libelf1 \
@@ -37,8 +42,14 @@
 libboost-dev \
 libpng12-dev

-RUN python3 -m pip install -U pip && \
-python3 -m pip install -U setuptools scons==3.1.2
+# Use python 3.9 by default
+RUN update-alternatives --install /usr/bin/python3 python3  
/usr/bin/python3.9 1

+
+# Setuptools is needed for cmake for ROCm build. Install using pip.
+# Instructions to install PIP from https://pypi.org/project/pip/
+RUN wget https://bootstrap.pypa.io/get-pip.py -qO get-pip.py
+RUN python3 get-pip.py
+RUN pip install -U setuptools scons==3.1.2 six

 ARG gem5_dist=http://dist.gem5.org/dist/develop

@@ -152,5 +163,7 @@
 WORKDIR /ROCm-Profiler
 RUN dpkg -i package/rocm-profiler_4.0.6036_amd64.deb

+# Always use python3 and create a link to config command for gem5 to find
 RUN ln -sf /usr/bin/python3 /usr/bin/python
+RUN ln -sf /usr/bin/python3.9-config /usr/bin/python3-config
 WORKDIR /

--
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Gerrit-Change-Id: Ia919f31cf9c9063e1df091cea15590526715739b
Gerrit-Change-Number: 37219
Gerrit-PatchSet: 2
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Daniel Gerzhoy 
Gerrit-Reviewer: Kyle Roarty 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Bobby R. Bruce 
Gerrit-CC: Jason Lowe-Power 
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[gem5-dev] Change in gem5/gem5[develop]: util: Use MAINTAINERS.yaml for valid tags in git hook

2020-11-07 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/37220 )



Change subject: util: Use MAINTAINERS.yaml for valid tags in git hook
..

util: Use MAINTAINERS.yaml for valid tags in git hook

There is a mismatch between the tags in MAINTAINERS.yaml and the
valid_tags in the git hook. This means if a user consults the
MAINTAINERS.yaml file to find the appropriate tag, there is a chance of
the commit being rejected due to this mismatch. Now that the maintainers
file is in yaml format, use that to parse the valid tag options. Some
additional special tags are added (WIP, RFC) and tags that were
previously valid but not in the MAINTAINERS.yaml file.

Change-Id: I3de8f0b6f8507aa1afd2118bc4373ac0610cce40
---
M util/git-commit-msg.py
1 file changed, 8 insertions(+), 12 deletions(-)



diff --git a/util/git-commit-msg.py b/util/git-commit-msg.py
index 9cba896..de23691 100755
--- a/util/git-commit-msg.py
+++ b/util/git-commit-msg.py
@@ -32,6 +32,7 @@
 import os
 import re
 import sys
+import yaml

 from style.repo import GitRepo

@@ -57,8 +58,8 @@

 print("""
 The first line of a commit must contain one or more gem5 tags separated by
-commas (see MAINTAINERS for the possible tags), followed by a colon and a
-commit title. There must be no leading nor trailing whitespaces.
+commas (see MAINTAINERS.yaml for the possible tags), followed by a colon  
and

+a commit title. There must be no leading nor trailing whitespaces.

 This header line must then be followed by an empty line. A detailed  
message,
 although highly recommended, is not mandatory and can follow that empty  
line.

@@ -85,17 +86,12 @@
 """

 # List of valid tags
-# @todo this is error prone, and should be extracted automatically from
-#   a file
+with open(r'MAINTAINERS.yaml') as maint_file:
+valid_tags = [key for key in yaml.load(maint_file)]

-valid_tags = ["arch", "arch-arm", "arch-gcn3",
-"arch-mips", "arch-power", "arch-riscv", "arch-sparc", "arch-x86",
-"base", "configs", "cpu", "cpu-kvm", "cpu-minor", "cpu-o3",
-"cpu-simple", "dev", "dev-arm", "dev-hsa", "dev-virtio", "ext",
-"fastmodel", "gpu-compute", "learning-gem5", "mem", "mem-cache",
-"mem-garnet", "mem-ruby", "misc", "python", "scons", "sim", "sim-se",
-"sim-power", "stats", "system", "system-arm", "systemc", "tests",
-"util", "RFC", "WIP"]
+# Remove non-tag 'pmc' and add special tags not in MAINTAINERS.yaml
+valid_tags.remove('pmc')
+valid_tags.extend(['RFC', 'WIP', 'stats', 'sim-power'])

 tags = ''.join(commit_header.split(':')[0].split()).split(',')
 if (any(tag not in valid_tags for tag in tags)):

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[gem5-dev] Change in gem5/gem5[develop]: util: Update python version for GCN3

2020-11-07 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/37219 )



Change subject: util: Update python version for GCN3
..

util: Update python version for GCN3

The Python version installed in the Dockerfile for GCN3 by apt-get is
too old to build gem5. This bumps the version to the most recent Python
to avoid needing to update this file too much.

Python 3.9 is install via PPA since it is not available in the official
Ubuntu 16.04 repository. Likewise, pip is installed from "source" as it
is not available for Python 3.9 in from neither the PPA nor Ubuntu.

Change-Id: Ia919f31cf9c9063e1df091cea15590526715739b
---
M util/dockerfiles/gcn-gpu/Dockerfile
1 file changed, 20 insertions(+), 7 deletions(-)



diff --git a/util/dockerfiles/gcn-gpu/Dockerfile  
b/util/dockerfiles/gcn-gpu/Dockerfile

index 19f3ad7..e13367f 100644
--- a/util/dockerfiles/gcn-gpu/Dockerfile
+++ b/util/dockerfiles/gcn-gpu/Dockerfile
@@ -1,5 +1,12 @@
 FROM ubuntu:16.04

+# Needed for add-apt-repository
+RUN apt-get update && apt-get install -y --no-install-recommends \
+software-properties-common
+
+# Ubuntu 16.04 does not have a python package new enough for gem5, use a  
PPA

+RUN add-apt-repository ppa:deadsnakes/ppa && apt-get update
+
 # Should be minimal needed packages
 RUN apt-get update && apt-get install -y --no-install-recommends \
 findutils \
@@ -20,11 +27,9 @@
 libprotoc-dev \
 libgoogle-perftools-dev \
 python-yaml \
-python3-dev \
-python3 \
-python3-yaml \
-python3-six \
-python3-pip \
+python3.9 \
+python3.9-dev \
+python3.9-distutils \
 wget \
 libpci3 \
 libelf1 \
@@ -37,8 +42,14 @@
 libboost-dev \
 libpng12-dev

-RUN python3 -m pip install -U pip && \
-python3 -m pip install -U setuptools scons==3.1.2
+# Use python 3.9 by default
+RUN update-alternatives --install /usr/bin/python3 python3  
/usr/bin/python3.9 1

+
+# Setuptools is needed for cmake for ROCm build. Install using pip.
+# Instructions to install PIP from https://pypi.org/project/pip/
+RUN wget https://bootstrap.pypa.io/get-pip.py -qO get-pip.py
+RUN python3 get-pip.py
+RUN pip install -U setuptools scons==3.1.2 six

 ARG gem5_dist=http://dist.gem5.org/dist/develop

@@ -152,5 +163,7 @@
 WORKDIR /ROCm-Profiler
 RUN dpkg -i package/rocm-profiler_4.0.6036_amd64.deb

+# Always use python3 and create a link to config command for gem5 to find
 RUN ln -sf /usr/bin/python3 /usr/bin/python
+RUN ln -sf /usr/bin/python3.9-config /usr/bin/python3-config
 WORKDIR /

--
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[gem5-dev] Change in gem5/gem5[develop]: configs,tests: Add tokens to GPU VIPER tester

2020-11-04 Thread Matthew Poremba (Gerrit) via gem5-dev
State
 {
 GpuThread* th;
@@ -131,10 +146,12 @@
 int numVectorPorts;
 int numSqcPorts;
 int numScalarPorts;
+int numTokenPorts;
 int numCusPerSqc;
 int numCusPerScalar;
 int numWfsPerCu;
 int numWisPerWf;
+int numCuTokens;
 // parameters controlling the address range that the tester can access
 int numAtomicLocs;
 int numNormalLocsPerAtomic;
@@ -150,6 +167,8 @@
 std::vector cuVectorPorts; // ports to GPU vector cache
 std::vector cuSqcPorts;// ports to GPU inst cache
 std::vector cuScalarPorts; // ports to GPU scalar cache
+std::vector cuTokenManagers;
+std::vector cuTokenPorts;
 // all CPU and GPU threads
     std::vector cpuThreads;
 std::vector wfs;

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[gem5-dev] Change in gem5/gem5[develop]: gpu-compute,mem-ruby: Replace ACQUIRE and RELEASE request flags

2020-11-04 Thread Matthew Poremba (Gerrit) via gem5-dev
y supports following memory request types
-//MemSyncReq & Acquire: TCP cache invalidation
+//MemSyncReq & INV_L1 : TCP cache invalidation
 //ReadReq : cache read
 //WriteReq: cache write
 //AtomicOp: cache atomic
 //
 // VIPER does not expect MemSyncReq & Release since in GCN3, compute  
unit

 // does not specify an equivalent type of memory request.
-// TODO: future patches should rename Acquire and Release
-assert((pkt->cmd == MemCmd::MemSyncReq && pkt->req->isAcquire()) ||
+assert((pkt->cmd == MemCmd::MemSyncReq && pkt->req->isInvL1()) ||
 pkt->cmd == MemCmd::ReadReq ||
 pkt->cmd == MemCmd::WriteReq ||
 pkt->isAtomicOp());

-if (pkt->req->isAcquire() && m_cache_inv_pkt) {
+if (pkt->req->isInvL1() && m_cache_inv_pkt) {
 // In VIPER protocol, the coalescer is not able to handle two or
 // more cache invalidation requests at a time. Cache invalidation
 // requests must be serialized to ensure that all stale data in
@@ -94,8 +93,8 @@

 GPUCoalescer::makeRequest(pkt);

-if (pkt->req->isAcquire()) {
-// In VIPER protocol, a compute unit sends a MemSyncReq with  
Acquire

+if (pkt->req->isInvL1()) {
+// In VIPER protocol, a compute unit sends a MemSyncReq with INV_L1
 // flag to invalidate TCP. Upon receiving a request of this type,
 // VIPERCoalescer starts a cache walk to invalidate all valid  
entries
 // in TCP. The request is completed once all entries are  
invalidated.

@@ -276,7 +275,7 @@
 }

 /**
-  * Invalidate TCP (Acquire)
+  * Invalidate TCP
   */
 void
 VIPERCoalescer::invTCP()

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Gerrit-CC: Pouya Fotouhi 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs,mem-ruby: Remove old GPU ptls

2020-11-04 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34197 )


Change subject: configs,mem-ruby: Remove old GPU ptls
..

configs,mem-ruby: Remove old GPU ptls

These protocols are no longer supported, either
because they are not representative of GPU
protocols, or because the have not been updated
to work with GCN3.

Change-Id: I989eeb6826c69225766aaab209302fe638b22719
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34197
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M configs/example/apu_se.py
D configs/ruby/GPU_RfO.py
D configs/ruby/GPU_VIPER_Baseline.py
D configs/ruby/GPU_VIPER_Region.py
D src/mem/ruby/protocol/GPU_RfO-SQC.sm
D src/mem/ruby/protocol/GPU_RfO-TCC.sm
D src/mem/ruby/protocol/GPU_RfO-TCCdir.sm
D src/mem/ruby/protocol/GPU_RfO-TCP.sm
D src/mem/ruby/protocol/GPU_RfO.slicc
D src/mem/ruby/protocol/GPU_VIPER_Baseline.slicc
D src/mem/ruby/protocol/GPU_VIPER_Region-TCC.sm
D src/mem/ruby/protocol/GPU_VIPER_Region.slicc
12 files changed, 9 insertions(+), 8,527 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I989eeb6826c69225766aaab209302fe638b22719
Gerrit-Change-Number: 34197
Gerrit-PatchSet: 12
Gerrit-Owner: Bradford Beckmann 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Make CPUID vendor string a param

2020-11-02 Thread Matthew Poremba (Gerrit) via gem5-dev
ringToRegister(vendor_string + 8));
+}
 break;
   case FamilyModelStepping:
 result = CpuidResult(0x00020f51, 0x0805,
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index e4e526e..2465a19 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -130,8 +130,10 @@
 regVal[MISCREG_APIC_BASE] = lApicBase;
 }

-ISA::ISA(const Params ) : BaseISA(p)
+ISA::ISA(const X86ISAParams ) : BaseISA(p), vendorString(p.vendor_string)
 {
+fatal_if(vendorString.size() != 12,
+ "CPUID vendor string must be 12 characters\n");
 clear();
 }

@@ -434,4 +436,10 @@
 tc->getDecoderPtr()->setM5Reg(regVal[MISCREG_M5_REG]);
 }

+std::string
+ISA::getVendorString() const
+{
+return vendorString;
+}
+
 }
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 3df7cce..2cbce6e 100644
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -108,6 +108,11 @@
 void unserialize(CheckpointIn ) override;

 void setThreadContext(ThreadContext *_tc) override;
+
+std::string getVendorString() const;
+
+  private:
+std::string vendorString;
 };
 }


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Gerrit-Project: public/gem5
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Gerrit-Change-Id: I8de26d5a145867fa23518718a799dd96b5b9bffa
Gerrit-Change-Number: 36156
Gerrit-PatchSet: 4
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Ayaz Akram 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
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[gem5-dev] Change in gem5/gem5[develop]: configs: Make GPU_VIPER config python3 friendly

2020-10-16 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35855 )


Change subject: configs: Make GPU_VIPER config python3 friendly
..

configs: Make GPU_VIPER config python3 friendly

There is no xrange in python3. This will be required when eventually
20.2 is released.

Change-Id: I3a0da6353b70e6e17ce1f77d6177d48059e32487
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35855
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M configs/ruby/GPU_VIPER.py
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/ruby/GPU_VIPER.py b/configs/ruby/GPU_VIPER.py
index 3ea2998..fe52d62 100644
--- a/configs/ruby/GPU_VIPER.py
+++ b/configs/ruby/GPU_VIPER.py
@@ -656,7 +656,7 @@
 # SQC also in GPU cluster
 gpuCluster.add(sqc_cntrl)

-for i in xrange(options.num_scalar_cache):
+for i in range(options.num_scalar_cache):
 scalar_cntrl = SQCCntrl(TCC_select_num_bits = TCC_bits)
 scalar_cntrl.create(options, ruby_system, system)

@@ -678,7 +678,7 @@

 gpuCluster.add(scalar_cntrl)

-for i in xrange(options.num_cp):
+for i in range(options.num_cp):

 tcp_ID = options.num_compute_units + i
 sqc_ID = options.num_sqc + i

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Gerrit-Change-Number: 35855
Gerrit-PatchSet: 4
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
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Gerrit-CC: Kyle Roarty 
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Make CPUID vendor string a param

2020-10-15 Thread Matthew Poremba (Gerrit) via gem5-dev
Funcs - 1,
+  stringToRegister(vendor_string),
+  stringToRegister(vendor_string + 4),
+  stringToRegister(vendor_string + 8));
+}
 break;
   case FamilyModelStepping:
 result = CpuidResult(0x00020f51, 0x0805,

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[gem5-dev] Change in gem5/gem5[develop]: configs: Make GPU_VIPER config python3 friendly

2020-10-09 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35855 )



Change subject: configs: Make GPU_VIPER config python3 friendly
..

configs: Make GPU_VIPER config python3 friendly

There is no xrange in python3. This will be required when eventually
20.2 is released.

Change-Id: I3a0da6353b70e6e17ce1f77d6177d48059e32487
---
M configs/ruby/GPU_VIPER.py
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/configs/ruby/GPU_VIPER.py b/configs/ruby/GPU_VIPER.py
index 6a6dec5..6a5e416 100644
--- a/configs/ruby/GPU_VIPER.py
+++ b/configs/ruby/GPU_VIPER.py
@@ -661,7 +661,7 @@
 # SQC also in GPU cluster
 gpuCluster.add(sqc_cntrl)

-for i in xrange(options.num_scalar_cache):
+for i in range(options.num_scalar_cache):
 scalar_cntrl = SQCCntrl(TCC_select_num_bits = TCC_bits)
 scalar_cntrl.create(options, ruby_system, system)

@@ -683,7 +683,7 @@

 gpuCluster.add(scalar_cntrl)

-for i in xrange(options.num_cp):
+for i in range(options.num_cp):

 tcp_ID = options.num_compute_units + i
 sqc_ID = options.num_sqc + i

--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Fixing token port responses in GPUCoalescer

2020-09-30 Thread Matthew Poremba (Gerrit) via gem5-dev
enderState);
+
+ComputeUnit::DataPort::SenderState* cu_state =
+safe_cast
+(ss->predecessor);
+
+return cu_state->_gpuDynInst;
+}

 bool
 GPUCoalescer::coalescePacket(PacketPtr pkt)
@@ -674,10 +724,7 @@
 // CU will use that instruction to decrement wait counters
 // in the issuing wavefront.
 // For Ruby tester, gpuDynInst == nullptr
-ComputeUnit::DataPort::SenderState* cu_state =
-safe_cast
-(ss->predecessor);
-gpuDynInst = cu_state->_gpuDynInst;
+gpuDynInst = getDynInst(pkt);
 }

 PendingWriteInst& inst = pendingWriteInsts[seqNum];
@@ -698,21 +745,45 @@
 // Iterate over the maximum number of instructions we can coalesce
 // per cycle (coalescingWindow).
 for (int instIdx = 0; instIdx < coalescingWindow; ++instIdx) {
-PerInstPackets *pktList =
+PerInstPackets *pkt_list =
 uncoalescedTable.getInstPackets(instIdx);

 // getInstPackets will return nullptr if no instruction
 // exists at the current offset.
-if (!pktList) {
+if (!pkt_list) {
 break;
+} else if (pkt_list->empty()) {
+// Found something, but it has not been cleaned up by update
+// resources yet. See if there is anything else to coalesce.
+// Assume we can't check anymore if the coalescing window is 1.
+continue;
 } else {
+// All packets in the list have the same seqNum, use first.
+InstSeqNum seq_num =  
pkt_list->front()->req->getReqInstSeqNum();

+
+// The difference in list size before and after tells us the
+// number of packets which were coalesced.
+size_t pkt_list_size = pkt_list->size();
+
 // Since we have a pointer to the list of packets in the inst,
 // erase them from the list if coalescing is successful and
 // leave them in the list otherwise. This aggressively attempts
 // to coalesce as many packets as possible from the current  
inst.

-pktList->remove_if(
+pkt_list->remove_if(
 [&](PacketPtr pkt) { return coalescePacket(pkt); }
 );
+
+assert(pkt_list_size >= pkt_list->size());
+size_t pkt_list_diff = pkt_list_size - pkt_list->size();
+
+int num_remaining =  
uncoalescedTable.getPacketsRemaining(seq_num);

+num_remaining -= pkt_list_diff;
+assert(num_remaining >= 0);
+
+uncoalescedTable.setPacketsRemaining(seq_num, num_remaining);
+DPRINTF(GPUCoalescer,
+"Coalesced %d pkts for seqNum %d, %d remaining\n",
+pkt_list_diff, seq_num, num_remaining);
 }
 }

diff --git a/src/mem/ruby/system/GPUCoalescer.hh  
b/src/mem/ruby/system/GPUCoalescer.hh

index 3b1b7af..2684d51 100644
--- a/src/mem/ruby/system/GPUCoalescer.hh
+++ b/src/mem/ruby/system/GPUCoalescer.hh
@@ -70,12 +70,18 @@
 bool packetAvailable();
 void printRequestTable(std::stringstream& ss);

+// Modify packets remaining map. Init sets value iff the seqNum has not
+// yet been seen before. get/set act as a regular getter/setter.
+void initPacketsRemaining(InstSeqNum seqNum, int count);
+int getPacketsRemaining(InstSeqNum seqNum);
+void setPacketsRemaining(InstSeqNum seqNum, int count);
+
 // Returns a pointer to the list of packets corresponding to an
 // instruction in the instruction map or nullptr if there are no
 // instructions at the offset.
 PerInstPackets* getInstPackets(int offset);
 void updateResources();
-bool areRequestsDone(const uint64_t instSeqNum);
+bool areRequestsDone(const InstSeqNum instSeqNum);

 // Check if a packet hasn't been removed from instMap in too long.
 // Panics if a deadlock is detected and returns nothing otherwise.
@@ -88,7 +94,9 @@
 // which need responses. This data structure assumes the sequence  
number

 // is monotonically increasing (which is true for CU class) in order to
 // issue packets in age order.
-std::map instMap;
+std::map instMap;
+
+std::map instPktsRemaining;
 };

 class CoalescedRequest
@@ -389,6 +397,8 @@

 virtual RubyRequestType getRequestType(PacketPtr pkt);

+GPUDynInstPtr getDynInst(PacketPtr pkt) const;
+
 // Attempt to remove a packet from the uncoalescedTable and coalesce
 // with a previous request from the same instruction. If there is no
 // previous instruction and the max number of outstanding requests has

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[gem5-dev] Change in gem5/gem5[develop]: configs: Fix typo in apu_se.py

2020-09-30 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35175 )


Change subject: configs: Fix typo in apu_se.py
..

configs: Fix typo in apu_se.py

Change parser.add_options to parser.add_option

Change-Id: I8b0235a1bf9e01e915dec71d85b9da02c477eb34
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35175
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Matt Sinclair 
Maintainer: Jason Lowe-Power 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M configs/example/apu_se.py
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/example/apu_se.py b/configs/example/apu_se.py
index 077ce4c..2e24079 100644
--- a/configs/example/apu_se.py
+++ b/configs/example/apu_se.py
@@ -174,7 +174,7 @@
   help="number of physical banks per LDS module")
 parser.add_option("--ldsBankConflictPenalty", type="int", default=1,
   help="number of cycles per LDS bank conflict")
-parser.add_options("--lds-size", type="int", default=65536,
+parser.add_option("--lds-size", type="int", default=65536,
help="Size of the LDS in bytes")
 parser.add_option('--fast-forward-pseudo-op', action='store_true',
   help = 'fast forward using kvm until the m5_switchcpu'

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Gerrit-Change-Number: 35175
Gerrit-PatchSet: 2
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Kyle Roarty 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Fixing token port responses in GPUCoalescer

2020-09-25 Thread Matthew Poremba (Gerrit) via gem5-dev
te);
+
+ComputeUnit::DataPort::SenderState* cu_state =
+safe_cast
+(ss->predecessor);
+
+return cu_state->_gpuDynInst;
+}

 bool
 GPUCoalescer::coalescePacket(PacketPtr pkt)
@@ -674,10 +727,7 @@
 // CU will use that instruction to decrement wait counters
 // in the issuing wavefront.
 // For Ruby tester, gpuDynInst == nullptr
-ComputeUnit::DataPort::SenderState* cu_state =
-safe_cast
-(ss->predecessor);
-gpuDynInst = cu_state->_gpuDynInst;
+gpuDynInst = getDynInst(pkt);
 }

 PendingWriteInst& inst = pendingWriteInsts[seqNum];
@@ -698,21 +748,45 @@
 // Iterate over the maximum number of instructions we can coalesce
 // per cycle (coalescingWindow).
 for (int instIdx = 0; instIdx < coalescingWindow; ++instIdx) {
-PerInstPackets *pktList =
+PerInstPackets *pkt_list =
 uncoalescedTable.getInstPackets(instIdx);

 // getInstPackets will return nullptr if no instruction
 // exists at the current offset.
-if (!pktList) {
+if (!pkt_list) {
 break;
+} else if (pkt_list->empty()) {
+// Found something, but it has not been cleaned up by update
+// resources yet. See if there is anything else to coalesce.
+// Assume we can't check anymore if the coalescing window is 1.
+continue;
 } else {
+// All packets in the list have the same seqNum, use first.
+InstSeqNum seq_num =  
pkt_list->front()->req->getReqInstSeqNum();

+
+// The difference in list size before and after tells us the
+// number of packets which were coalesced.
+size_t pkt_list_size = pkt_list->size();
+
 // Since we have a pointer to the list of packets in the inst,
 // erase them from the list if coalescing is successful and
 // leave them in the list otherwise. This aggressively attempts
 // to coalesce as many packets as possible from the current  
inst.

-pktList->remove_if(
+pkt_list->remove_if(
 [&](PacketPtr pkt) { return coalescePacket(pkt); }
 );
+
+assert(pkt_list_size >= pkt_list->size());
+size_t pkt_list_diff = pkt_list_size - pkt_list->size();
+
+int num_remaining =  
uncoalescedTable.getPacketsRemaining(seq_num);

+num_remaining -= pkt_list_diff;
+assert(num_remaining >= 0);
+
+uncoalescedTable.setPacketsRemaining(seq_num, num_remaining);
+DPRINTF(GPUCoalescer,
+"Coalesced %d pkts for seqNum %d, %d remaining\n",
+pkt_list_diff, seq_num, num_remaining);
 }
 }

diff --git a/src/mem/ruby/system/GPUCoalescer.hh  
b/src/mem/ruby/system/GPUCoalescer.hh

index 3b1b7af..2684d51 100644
--- a/src/mem/ruby/system/GPUCoalescer.hh
+++ b/src/mem/ruby/system/GPUCoalescer.hh
@@ -70,12 +70,18 @@
 bool packetAvailable();
 void printRequestTable(std::stringstream& ss);

+// Modify packets remaining map. Init sets value iff the seqNum has not
+// yet been seen before. get/set act as a regular getter/setter.
+void initPacketsRemaining(InstSeqNum seqNum, int count);
+int getPacketsRemaining(InstSeqNum seqNum);
+void setPacketsRemaining(InstSeqNum seqNum, int count);
+
 // Returns a pointer to the list of packets corresponding to an
 // instruction in the instruction map or nullptr if there are no
 // instructions at the offset.
 PerInstPackets* getInstPackets(int offset);
 void updateResources();
-bool areRequestsDone(const uint64_t instSeqNum);
+bool areRequestsDone(const InstSeqNum instSeqNum);

 // Check if a packet hasn't been removed from instMap in too long.
 // Panics if a deadlock is detected and returns nothing otherwise.
@@ -88,7 +94,9 @@
 // which need responses. This data structure assumes the sequence  
number

 // is monotonically increasing (which is true for CU class) in order to
 // issue packets in age order.
-std::map instMap;
+std::map instMap;
+
+std::map instPktsRemaining;
 };

 class CoalescedRequest
@@ -389,6 +397,8 @@

 virtual RubyRequestType getRequestType(PacketPtr pkt);

+GPUDynInstPtr getDynInst(PacketPtr pkt) const;
+
 // Attempt to remove a packet from the uncoalescedTable and coalesce
 // with a previous request from the same instruction. If there is no
 // previous instruction and the max number of outstanding requests has

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[gem5-dev] Change in gem5/gem5[develop]: configs: Fix typo in apu_se.py

2020-09-25 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35175 )



Change subject: configs: Fix typo in apu_se.py
..

configs: Fix typo in apu_se.py

Change parser.add_options to parser.add_option

Change-Id: I8b0235a1bf9e01e915dec71d85b9da02c477eb34
---
M configs/example/apu_se.py
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/configs/example/apu_se.py b/configs/example/apu_se.py
index 077ce4c..2e24079 100644
--- a/configs/example/apu_se.py
+++ b/configs/example/apu_se.py
@@ -174,7 +174,7 @@
   help="number of physical banks per LDS module")
 parser.add_option("--ldsBankConflictPenalty", type="int", default=1,
   help="number of cycles per LDS bank conflict")
-parser.add_options("--lds-size", type="int", default=65536,
+parser.add_option("--lds-size", type="int", default=65536,
help="Size of the LDS in bytes")
 parser.add_option('--fast-forward-pseudo-op', action='store_true',
   help = 'fast forward using kvm until the m5_switchcpu'

--
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Gerrit-PatchSet: 1
Gerrit-Owner: Matthew Poremba 
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[gem5-dev] Change in gem5/gem5[release-staging-v20.1.0.0]: configs: Set kvm_map in DRAMInterface in Ruby.py

2020-09-25 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35095 )


Change subject: configs: Set kvm_map in DRAMInterface in Ruby.py
..

configs: Set kvm_map in DRAMInterface in Ruby.py

The kvm_map parameter from AbstractMemory has been moved from MemCtrl
(formerly DRAMCtrl) to DRAMInterface. Assign it to DRAMInterface
instead.

Change-Id: I4508aefcf5eb859d9ffe05c81d85a1b84ee0a196
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35095
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M configs/ruby/Ruby.py
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index 622771a..86d5748 100644
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -136,7 +136,7 @@
 mem_ctrl = m5.objects.MemCtrl(dram = dram_intf)

 if options.access_backing_store:
-mem_ctrl.kvm_map=False
+dram_intf.kvm_map=False

 mem_ctrls.append(mem_ctrl)
 dir_ranges.append(mem_ctrl.dram.range)

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Gerrit-Change-Id: I4508aefcf5eb859d9ffe05c81d85a1b84ee0a196
Gerrit-Change-Number: 35095
Gerrit-PatchSet: 2
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
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Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: configs: Set kvm_map in DRAMInterface in Ruby.py

2020-09-24 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35095 )



Change subject: configs: Set kvm_map in DRAMInterface in Ruby.py
..

configs: Set kvm_map in DRAMInterface in Ruby.py

The kvm_map parameter from AbstractMemory has been moved from MemCtrl
(formerly DRAMCtrl) to DRAMInterface. Assign it to DRAMInterface
instead.

Change-Id: I4508aefcf5eb859d9ffe05c81d85a1b84ee0a196
---
M configs/ruby/Ruby.py
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index 622771a..86d5748 100644
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -136,7 +136,7 @@
 mem_ctrl = m5.objects.MemCtrl(dram = dram_intf)

 if options.access_backing_store:
-mem_ctrl.kvm_map=False
+dram_intf.kvm_map=False

 mem_ctrls.append(mem_ctrl)
 dir_ranges.append(mem_ctrl.dram.range)

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[gem5-dev] Change in gem5/gem5[develop]: configs,gpu-compute: Fixes to connect gmTokenPort

2020-09-24 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35096 )



Change subject: configs,gpu-compute: Fixes to connect gmTokenPort
..

configs,gpu-compute: Fixes to connect gmTokenPort

When the TokenPort was moved from the GCN3 staging branch to develop the
TokenPort was changes from being the port connecting the ComputeUnit to
Ruby's vector memory port to a sideband port which inhibits requests to
Ruby's vector memory port. As such, it needs to be explicitly connected
as a new port. This changes the getPort method in ComputeUnit to be
aware of the port as well as modifying the example config to connect to
TCPs.

The iteration to connect in the config file was modified since it was
not properly connecting to TCPs each time and Ruby.py does not
explicitly return a list of each MachineType.

Change-Id: Ia70a6756b2af54d95e94d19bec5d8aadd3c2d5c0
---
M configs/example/apu_se.py
M src/gpu-compute/compute_unit.hh
2 files changed, 13 insertions(+), 3 deletions(-)



diff --git a/configs/example/apu_se.py b/configs/example/apu_se.py
index 077ce4c..1391a22 100644
--- a/configs/example/apu_se.py
+++ b/configs/example/apu_se.py
@@ -174,7 +174,7 @@
   help="number of physical banks per LDS module")
 parser.add_option("--ldsBankConflictPenalty", type="int", default=1,
   help="number of cycles per LDS bank conflict")
-parser.add_options("--lds-size", type="int", default=65536,
+parser.add_option("--lds-size", type="int", default=65536,
help="Size of the LDS in bytes")
 parser.add_option('--fast-forward-pseudo-op', action='store_true',
   help = 'fast forward using kvm until the m5_switchcpu'
@@ -566,6 +566,16 @@
- options.num_scalar_cache
 gpu_port_idx = gpu_port_idx - options.num_cp * 2

+# Connect token ports. For this we need to search through the list of all
+# sequencers, since the TCP coalescers will not necessarily be first. Only
+# TCP coalescers use a token port for back pressure.
+token_port_idx = 0
+for i in range(len(system.ruby._cpu_ports)):
+if type(system.ruby._cpu_ports[i]).__name__ == "VIPERCoalescer":
+system.cpu[shader_idx].CUs[token_port_idx].gmTokenPort = \
+system.ruby._cpu_ports[i].gmTokenPort
+token_port_idx += 1
+
 wavefront_size = options.wf_size
 for i in range(n_cu):
 # The pipeline issues wavefront_size number of uncoalesced requests
@@ -573,8 +583,6 @@
 for j in range(wavefront_size):
 system.cpu[shader_idx].CUs[i].memory_port[j] = \
   system.ruby._cpu_ports[gpu_port_idx].slave[j]
-system.cpu[shader_idx].CUs[i].gmTokenPort = \
-system.ruby._cpu_ports[gpu_port_idx].gmTokenPort
 gpu_port_idx += 1

 for i in range(n_cu):
diff --git a/src/gpu-compute/compute_unit.hh  
b/src/gpu-compute/compute_unit.hh

index fe2091d..2df4807 100644
--- a/src/gpu-compute/compute_unit.hh
+++ b/src/gpu-compute/compute_unit.hh
@@ -1015,6 +1015,8 @@
 return sqcTLBPort;
 } else if (if_name == "ldsPort") {
 return ldsPort;
+} else if (if_name == "gmTokenPort") {
+return gmTokenPort;
 } else {
 return ClockedObject::getPort(if_name, idx);
 }

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[gem5-dev] Change in gem5/gem5[develop]: misc: Use VPtr in hsa_driver.cc

2020-08-31 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33655 )


Change subject: misc: Use VPtr in hsa_driver.cc
..

misc: Use VPtr in hsa_driver.cc

This change updates HSADriver::allocateQueue to take in a ThreadContext
pointer as opposed to a PortProxy ref. This allows the TypedBufferArg
to be replaced with VPtr.

This also fixes building GCN3_X86

Change-Id: I1fea26b10c7344daf54a0cb05337e961f834a5fd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33655
Reviewed-by: Matt Sinclair 
Reviewed-by: Gabe Black 
Reviewed-by: Matthew Poremba 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/dev/hsa/hsa_driver.cc
M src/dev/hsa/hsa_driver.hh
M src/gpu-compute/gpu_compute_driver.cc
3 files changed, 4 insertions(+), 6 deletions(-)

Approvals:
  Matthew Poremba: Looks good to me, approved
  Gabe Black: Looks good to me, but someone else must approve
  Matt Sinclair: Looks good to me, but someone else must approve; Looks  
good to me, approved

  kokoro: Regressions pass



diff --git a/src/dev/hsa/hsa_driver.cc b/src/dev/hsa/hsa_driver.cc
index a1215c4..3b27149 100644
--- a/src/dev/hsa/hsa_driver.cc
+++ b/src/dev/hsa/hsa_driver.cc
@@ -101,10 +101,9 @@
  * be mapped into that page.
  */
 void
-HSADriver::allocateQueue(PortProxy _proxy, Addr ioc_buf)
+HSADriver::allocateQueue(ThreadContext *tc, Addr ioc_buf)
 {
-TypedBufferArg args(ioc_buf);
-args.copyIn(mem_proxy);
+VPtr args(ioc_buf, tc);

 if (queueId >= 0x1000) {
 fatal("%s: Exceeded maximum number of HSA queues allowed\n",  
name());

@@ -115,5 +114,4 @@
 hsa_pp.setDeviceQueueDesc(args->read_pointer_address,
   args->ring_base_address, args->queue_id,
   args->ring_size);
-args.copyOut(mem_proxy);
 }
diff --git a/src/dev/hsa/hsa_driver.hh b/src/dev/hsa/hsa_driver.hh
index abf79ab..19982f7 100644
--- a/src/dev/hsa/hsa_driver.hh
+++ b/src/dev/hsa/hsa_driver.hh
@@ -74,7 +74,7 @@
 HSADevice *device;
 uint32_t queueId;

-void allocateQueue(PortProxy _proxy, Addr ioc_buf);
+void allocateQueue(ThreadContext *tc, Addr ioc_buf);
 };

 #endif // __DEV_HSA_HSA_DRIVER_HH__
diff --git a/src/gpu-compute/gpu_compute_driver.cc  
b/src/gpu-compute/gpu_compute_driver.cc

index 6bdb314..b4d65ce6 100644
--- a/src/gpu-compute/gpu_compute_driver.cc
+++ b/src/gpu-compute/gpu_compute_driver.cc
@@ -71,7 +71,7 @@
   {
 DPRINTF(GPUDriver, "ioctl: AMDKFD_IOC_CREATE_QUEUE\n");

-allocateQueue(virt_proxy, ioc_buf);
+allocateQueue(tc, ioc_buf);

 DPRINTF(GPUDriver, "Creating queue %d\n", queueId);
   }

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Gerrit-Change-Id: I1fea26b10c7344daf54a0cb05337e961f834a5fd
Gerrit-Change-Number: 33655
Gerrit-PatchSet: 2
Gerrit-Owner: Kyle Roarty 
Gerrit-Reviewer: Alexandru Duțu 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Anthony Gutierrez 
Gerrit-CC: Bradford Beckmann 
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Make DMASequencer aware of Atomics

2020-08-29 Thread Matthew Poremba (Gerrit) via gem5-dev
gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9775fc110bb99a1740089746f0d1b3deb124b9f5
Gerrit-Change-Number: 33716
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Gerrit-Owner: Matthew Poremba 
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[gem5-dev] Change in gem5/gem5[develop]: arch-mips: Remove old TypeBufferArg call

2020-08-07 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32414 )



Change subject: arch-mips: Remove old TypeBufferArg call
..

arch-mips: Remove old TypeBufferArg call

TypeBufferArg was replaced by VPtr so this call is no longer needed.
This fixes the MIPS build / nightly build.

Change-Id: I3880229fa0ad87fad1ca35c136e12efc6c36ceda
---
M src/arch/mips/linux/process.cc
1 file changed, 0 insertions(+), 1 deletion(-)



diff --git a/src/arch/mips/linux/process.cc b/src/arch/mips/linux/process.cc
index 8f1ec16..600d053 100644
--- a/src/arch/mips/linux/process.cc
+++ b/src/arch/mips/linux/process.cc
@@ -127,7 +127,6 @@
 // SSI_IEEE_FP_CONTROL
 ConstVPtr fpcr(bufPtr, tc);
 // I don't think this exactly matches the HW FPCR
-fpcr.copyIn(tc->getVirtProxy());
  
DPRINTFR(SyscallVerbose, "sys_setsysinfo(SSI_IEEE_FP_CONTROL): "

" setting FPCR to 0x%x\n", letoh(*fpcr));
 return 0;

--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Getter/setter for atomic ops in WriteMask

2020-07-24 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31474 )


Change subject: mem-ruby: Getter/setter for atomic ops in WriteMask
..

mem-ruby: Getter/setter for atomic ops in WriteMask

Adding getter and setter methods for getting and setting the atomic ops
in the WriteMask class. This allows for message types with WriteMasks to
get or set the atomic ops without explicitly modifying the constructor
for the message type. This will beused by the DMASequencer which uses the
SequencerMsg type where the constructor is auto generated via SLICC.

Change-Id: I71787d294c1b89547618e9a13e386b65bb3e1021
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31474
Reviewed-by: Bobby R. Bruce 
Reviewed-by: Anthony Gutierrez 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/mem/ruby/common/WriteMask.hh
1 file changed, 18 insertions(+), 3 deletions(-)

Approvals:
  Anthony Gutierrez: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/ruby/common/WriteMask.hh  
b/src/mem/ruby/common/WriteMask.hh

index 0ba6989..6a0a041 100644
--- a/src/mem/ruby/common/WriteMask.hh
+++ b/src/mem/ruby/common/WriteMask.hh
@@ -40,6 +40,8 @@
 class WriteMask
 {
   public:
+typedef std::vector> AtomicOpVector;
+
 WriteMask()
   : mSize(RubySystem::getBlockSizeBytes()), mMask(mSize, false),
 mAtomic(false)
@@ -53,8 +55,7 @@
   : mSize(size), mMask(mask), mAtomic(false)
 {}

-WriteMask(int size, std::vector ,
-  std::vector > atomicOp)
+WriteMask(int size, std::vector , AtomicOpVector atomicOp)
   : mSize(size), mMask(mask), mAtomic(true), mAtomicOp(atomicOp)
 {}

@@ -184,11 +185,25 @@
 (*fnctr)(p);
 }
 }
+
+const AtomicOpVector&
+getAtomicOps() const
+{
+return mAtomicOp;
+}
+
+void
+setAtomicOps(const AtomicOpVector& atomicOps)
+{
+mAtomic = true;
+mAtomicOp = std::move(atomicOps);
+}
+
   private:
 int mSize;
 std::vector mMask;
 bool mAtomic;
-std::vector > mAtomicOp;
+AtomicOpVector mAtomicOp;
 };

 inline std::ostream&

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Gerrit-Change-Id: I71787d294c1b89547618e9a13e386b65bb3e1021
Gerrit-Change-Number: 31474
Gerrit-PatchSet: 2
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: Tiago Mück 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3,gpu-compute: Fix GCN3 related compiler errors

2020-07-20 Thread Matthew Poremba (Gerrit) via gem5-dev
 typename OpTraits::FloatT neg_half = -0.5;
 std::memcpy((void*)srfData.data(), (void*)_half,
-sizeof(srfData));
+sizeof(neg_half));
 }
 break;
   case REG_POS_ONE:
 {
 typename OpTraits::FloatT pos_one = 1.0;
-std::memcpy(srfData.data(), _one, sizeof(srfData));
+std::memcpy(srfData.data(), _one, sizeof(pos_one));
 }
 break;
   case REG_NEG_ONE:
 {
 typename OpTraits::FloatT neg_one = -1.0;
-std::memcpy(srfData.data(), _one, sizeof(srfData));
+std::memcpy(srfData.data(), _one, sizeof(neg_one));
 }
 break;
   case REG_POS_TWO:
 {
 typename OpTraits::FloatT pos_two = 2.0;
-std::memcpy(srfData.data(), _two, sizeof(srfData));
+std::memcpy(srfData.data(), _two, sizeof(pos_two));
 }
 break;
   case REG_NEG_TWO:
 {
 typename OpTraits::FloatT neg_two = -2.0;
-std::memcpy(srfData.data(), _two, sizeof(srfData));
+std::memcpy(srfData.data(), _two, sizeof(neg_two));
 }
 break;
   case REG_POS_FOUR:
 {
 typename OpTraits::FloatT pos_four = 4.0;
-std::memcpy(srfData.data(), _four,  
sizeof(srfData));
+std::memcpy(srfData.data(), _four,  
sizeof(pos_four));

 }
 break;
   case REG_NEG_FOUR:
 {
 typename OpTraits::FloatT neg_four = -4.0;
 std::memcpy((void*)srfData.data(), (void*)_four ,
-sizeof(srfData));
+sizeof(neg_four));
 }
 break;
 case REG_PI:
@@ -614,10 +624,10 @@

 if (sizeof(DataType) == sizeof(ScalarRegF64)) {
 std::memcpy((void*)srfData.data(),
-(void*)_u64, sizeof(srfData));
+(void*)_u64, sizeof(pi_u64));
 } else {
 std::memcpy((void*)srfData.data(),
-(void*)_u32, sizeof(srfData));
+(void*)_u32, sizeof(pi_u32));
 }
 }
 break;
diff --git a/src/gpu-compute/gpu_compute_driver.cc  
b/src/gpu-compute/gpu_compute_driver.cc

index 287c2a1..6bdb314 100644
--- a/src/gpu-compute/gpu_compute_driver.cc
+++ b/src/gpu-compute/gpu_compute_driver.cc
@@ -267,6 +267,7 @@
   {
 warn("unimplemented ioctl:  
AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU\n");

   }
+  break;
 case AMDKFD_IOC_ALLOC_MEMORY_OF_SCRATCH:
   {
 warn("unimplemented ioctl:  
AMDKFD_IOC_ALLOC_MEMORY_OF_SCRATCH\n");


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Gerrit-Change-Number: 31154
Gerrit-PatchSet: 7
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Getter/setter for atomic ops in WriteMask

2020-07-16 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31474 )



Change subject: mem-ruby: Getter/setter for atomic ops in WriteMask
..

mem-ruby: Getter/setter for atomic ops in WriteMask

Adding getter and setter methods for getting and setting the atomic ops
in the WriteMask class. This allows for message types with WriteMasks to
get or set the atomic ops without explicitly modifying the constructor
for the message type. This will beused by the DMASequencer which uses the
SequencerMsg type where the constructor is auto generated via SLICC.

Change-Id: I71787d294c1b89547618e9a13e386b65bb3e1021
---
M src/mem/ruby/common/WriteMask.hh
1 file changed, 18 insertions(+), 3 deletions(-)



diff --git a/src/mem/ruby/common/WriteMask.hh  
b/src/mem/ruby/common/WriteMask.hh

index 0ba6989..6a0a041 100644
--- a/src/mem/ruby/common/WriteMask.hh
+++ b/src/mem/ruby/common/WriteMask.hh
@@ -40,6 +40,8 @@
 class WriteMask
 {
   public:
+typedef std::vector> AtomicOpVector;
+
 WriteMask()
   : mSize(RubySystem::getBlockSizeBytes()), mMask(mSize, false),
 mAtomic(false)
@@ -53,8 +55,7 @@
   : mSize(size), mMask(mask), mAtomic(false)
 {}

-WriteMask(int size, std::vector ,
-  std::vector > atomicOp)
+WriteMask(int size, std::vector , AtomicOpVector atomicOp)
   : mSize(size), mMask(mask), mAtomic(true), mAtomicOp(atomicOp)
 {}

@@ -184,11 +185,25 @@
 (*fnctr)(p);
 }
 }
+
+const AtomicOpVector&
+getAtomicOps() const
+{
+return mAtomicOp;
+}
+
+void
+setAtomicOps(const AtomicOpVector& atomicOps)
+{
+mAtomic = true;
+mAtomicOp = std::move(atomicOps);
+}
+
   private:
 int mSize;
 std::vector mMask;
 bool mAtomic;
-std::vector > mAtomicOp;
+AtomicOpVector mAtomicOp;
 };

 inline std::ostream&

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[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3,gpu-compute: Fix various GCC9 errors

2020-07-09 Thread Matthew Poremba (Gerrit) via gem5-dev
c/gpu-compute/gpu_compute_driver.cc  
b/src/gpu-compute/gpu_compute_driver.cc

index 287c2a1..6bdb314 100644
--- a/src/gpu-compute/gpu_compute_driver.cc
+++ b/src/gpu-compute/gpu_compute_driver.cc
@@ -267,6 +267,7 @@
   {
 warn("unimplemented ioctl:  
AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU\n");

   }
+  break;
 case AMDKFD_IOC_ALLOC_MEMORY_OF_SCRATCH:
   {
 warn("unimplemented ioctl:  
AMDKFD_IOC_ALLOC_MEMORY_OF_SCRATCH\n");


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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Support device memories

2020-07-01 Thread Matthew Poremba (Gerrit) via gem5-dev
alWrite(pkt);
 }
-if (m_abs_cntrl_vec[i]->getDMASequencer()) {
+if (cntrl->getDMASequencer()) {
 num_functional_writes +=
- 
m_abs_cntrl_vec[i]->getDMASequencer()->functionalWrite(pkt);

+cntrl->getDMASequencer()->functionalWrite(pkt);
 }
 }

diff --git a/src/mem/ruby/system/RubySystem.hh  
b/src/mem/ruby/system/RubySystem.hh

index 2407072..7ce5ce0 100644
--- a/src/mem/ruby/system/RubySystem.hh
+++ b/src/mem/ruby/system/RubySystem.hh
@@ -35,6 +35,8 @@
 #ifndef __MEM_RUBY_SYSTEM_RUBYSYSTEM_HH__
 #define __MEM_RUBY_SYSTEM_RUBYSYSTEM_HH__

+#include 
+
 #include "base/callback.hh"
 #include "base/output.hh"
 #include "mem/packet.hh"
@@ -53,6 +55,7 @@
 typedef RubySystemParams Params;
 RubySystem(const Params *p);
 ~RubySystem();
+const Params *params() const { return (const Params *)_params; }

 // config accessors
 static int getRandomization() { return m_randomization; }
@@ -86,12 +89,15 @@
 void unserialize(CheckpointIn ) override;
 void drainResume() override;
 void process();
+void init() override;
 void startup() override;
 bool functionalRead(Packet *ptr);
 bool functionalWrite(Packet *ptr);

 void registerNetwork(Network*);
 void registerAbstractController(AbstractController*);
+void registerMachineID(const MachineID& mach_id, Network* network);
+void registerMasterIDs();

 bool eventQueueEmpty() { return eventq->empty(); }
 void enqueueRubyEvent(Tick tick)
@@ -135,6 +141,10 @@
 std::vector m_abs_cntrl_vec;
 Cycles m_start_cycle;

+std::unordered_map machineToNetwork;
+std::unordered_map masterToNetwork;
+std::unordered_map>  
netCntrls;

+
   public:
 Profiler* m_profiler;
 CacheRecorder* m_cache_recorder;
diff --git a/src/mem/ruby/system/RubySystem.py  
b/src/mem/ruby/system/RubySystem.py

index 1ce4871..347896f 100644
--- a/src/mem/ruby/system/RubySystem.py
+++ b/src/mem/ruby/system/RubySystem.py
@@ -25,6 +25,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 from m5.params import *
+from m5.proxy import *
 from m5.objects.ClockedObject import ClockedObject
 from m5.objects.SimpleMemory import *

@@ -41,6 +42,7 @@
 "number of bits that a memory address requires");

 phys_mem = Param.SimpleMemory(NULL, "")
+system = Param.System(Parent.any, "system object")

 access_backing_store = Param.Bool(False, "Use phys_mem as the  
functional \

 store and only use ruby for timing.")
diff --git a/src/mem/slicc/symbols/StateMachine.py  
b/src/mem/slicc/symbols/StateMachine.py

index 2e9700f..987f3b5 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -558,6 +558,7 @@
 m_machineID.type = MachineType_${ident};
 m_machineID.num = m_version;
 m_num_controllers++;
+p->ruby_system->registerAbstractController(this);

 m_in_ports = $num_in_ports;
 ''')
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 6e5975e..7057a97 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -418,6 +418,31 @@
 }

 void
+System::addDeviceMemory(MasterID masterId, AbstractMemory *deviceMemory)
+{
+if (!deviceMemMap.count(masterId)) {
+deviceMemMap.insert(std::make_pair(masterId, deviceMemory));
+}
+}
+
+bool
+System::isDeviceMemAddr(PacketPtr pkt) const
+{
+const MasterID& mid = pkt->masterId();
+
+return (deviceMemMap.count(mid) &&
+deviceMemMap.at(mid)->getAddrRange().contains(pkt->getAddr()));
+}
+
+AbstractMemory *
+System::getDeviceMemory(MasterID mid) const
+{
+panic_if(!deviceMemMap.count(mid),
+ "No device memory found for MasterID %d\n", mid);
+return deviceMemMap.at(mid);
+}
+
+void
 System::drainResume()
 {
 totalNumInsts = 0;
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 72734f8..9480821 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -98,6 +98,9 @@
 std::list liveEvents;
 SystemPort _systemPort;

+// Map of memory address ranges for devices with their own backing  
stores

+std::unordered_map deviceMemMap;
+
   public:

 class Threads
@@ -354,6 +357,25 @@
 bool isMemAddr(Addr addr) const;

 /**
+ * Add a physical memory range for a device. The ranges added here will
+ * be considered a non-PIO memory address if the masterId of the packet
+ * and range match something in the device memory map.
+ */
+void addDeviceMemory(MasterID masterID, AbstractMemory *deviceMemory);
+
+/**
+ * Similar to isMemAddr but for devices. Checks if a physical address
+ * of the packet match an address range of a device corresponding to  
the

+ * MasterId of the request.
+ */
+    bool isDeviceMemAddr(PacketPtr pkt) const;
+
+/**
+ * Return a pointer

[gem5-dev] Change in gem5/gem5[develop]: sim: Initialize stackSize and stackMin in MemState

2020-06-19 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30394 )


Change subject: sim: Initialize stackSize and stackMin in MemState
..

sim: Initialize stackSize and stackMin in MemState

Initialize _stackSize and _stackMin to the maximum stack size values.
The are setup in each arch's Process::initState and may be uninitialized
until then. If a stack fixup occurs before these are setup, addresses
which are not in the stack might be allocated on the stack. This
prevents that until they are initialized in Process::initState. If an
access occurs before that with these initial values, the stack fixup
will simply allocate a page of memory in the stack space. However, it
will not print the typical info messages about growing the stack during
this time.

Change-Id: I9f9316734f4bf1f773fc538922e83b867731c684
JIRA: https://gem5.atlassian.net/browse/GEM5-629
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30394
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Gabe Black 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/sim/mem_state.cc
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/mem_state.cc b/src/sim/mem_state.cc
index bfee9da..bcfab78 100644
--- a/src/sim/mem_state.cc
+++ b/src/sim/mem_state.cc
@@ -43,7 +43,8 @@
Addr mmap_end)
 : _ownerProcess(owner),
   _pageBytes(owner->system->getPageBytes()), _brkPoint(brk_point),
-  _stackBase(stack_base), _maxStackSize(max_stack_size),
+  _stackBase(stack_base), _stackSize(max_stack_size),
+  _maxStackSize(max_stack_size), _stackMin(stack_base -  
max_stack_size),

   _nextThreadStackBase(next_thread_stack_base),
   _mmapEnd(mmap_end), _endBrkPoint(brk_point)
 {

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Gerrit-Branch: develop
Gerrit-Change-Id: I9f9316734f4bf1f773fc538922e83b867731c684
Gerrit-Change-Number: 30394
Gerrit-PatchSet: 2
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim: Initialize stackSize and stackMin in MemState

2020-06-17 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30394 )



Change subject: sim: Initialize stackSize and stackMin in MemState
..

sim: Initialize stackSize and stackMin in MemState

Initialize _stackSize and _stackMin to the maximum stack size values.
The are setup in each arch's Process::initState and may be uninitialized
until then. If a stack fixup occurs before these are setup, addresses
which are not in the stack might be allocated on the stack. This
prevents that until they are initialized in Process::initState. If an
access occurs before that with these initial values, the stack fixup
will simply allocate a page of memory in the stack space. However, it
will not print the typical info messages about growing the stack during
this time.

Change-Id: I9f9316734f4bf1f773fc538922e83b867731c684
JIRA: https://gem5.atlassian.net/browse/GEM5-629
---
M src/sim/mem_state.cc
1 file changed, 2 insertions(+), 1 deletion(-)



diff --git a/src/sim/mem_state.cc b/src/sim/mem_state.cc
index bfee9da..bcfab78 100644
--- a/src/sim/mem_state.cc
+++ b/src/sim/mem_state.cc
@@ -43,7 +43,8 @@
Addr mmap_end)
 : _ownerProcess(owner),
   _pageBytes(owner->system->getPageBytes()), _brkPoint(brk_point),
-  _stackBase(stack_base), _maxStackSize(max_stack_size),
+  _stackBase(stack_base), _stackSize(max_stack_size),
+  _maxStackSize(max_stack_size), _stackMin(stack_base -  
max_stack_size),

   _nextThreadStackBase(next_thread_stack_base),
   _mmapEnd(mmap_end), _endBrkPoint(brk_point)
 {

--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Allow MachineID to be unordered key

2020-06-08 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/29652 )


Change subject: mem-ruby: Allow MachineID to be unordered key
..

mem-ruby: Allow MachineID to be unordered key

Define an std::hash function so that MachineID may be used as a key
type for unordered STL containers.

Change-Id: Ibc3bc78149c69683207d8967542fa6e8d545f75c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29652
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Bobby R. Bruce 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/mem/ruby/common/MachineID.hh
1 file changed, 10 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/ruby/common/MachineID.hh  
b/src/mem/ruby/common/MachineID.hh

index 64082d7..3ef7b88 100644
--- a/src/mem/ruby/common/MachineID.hh
+++ b/src/mem/ruby/common/MachineID.hh
@@ -67,6 +67,16 @@
 return (obj1.type != obj2.type || obj1.num != obj2.num);
 }

+namespace std {
+template<>
+struct hash {
+inline size_t operator()(const MachineID& id) const {
+size_t hval = MachineType_base_level(id.type) << 16 | id.num;
+return hval;
+}
+};
+}
+
 // Output operator declaration
 std::ostream& operator<<(std::ostream& out, const MachineID& obj);


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Gerrit-Change-Number: 29652
Gerrit-PatchSet: 2
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: mem: Support device memory with any address range

2020-05-28 Thread Matthew Poremba (Gerrit) via gem5-dev
 typedef RubySystemParams Params;
 RubySystem(const Params *p);
 ~RubySystem();
+const Params *params() const { return (const Params *)_params; }

 // config accessors
 static int getRandomization() { return m_randomization; }
@@ -92,6 +95,8 @@

 void registerNetwork(Network*);
 void registerAbstractController(AbstractController*);
+void registerMachineID(const MachineID& mach_id, Network* network);
+void registerMasterIDs();

 bool eventQueueEmpty() { return eventq->empty(); }
 void enqueueRubyEvent(Tick tick)
@@ -135,6 +140,10 @@
 std::vector m_abs_cntrl_vec;
 Cycles m_start_cycle;

+std::unordered_map machineToNetwork;
+std::unordered_map masterToNetwork;
+std::unordered_map>  
netCntrls;

+
   public:
 Profiler* m_profiler;
 CacheRecorder* m_cache_recorder;
diff --git a/src/mem/ruby/system/RubySystem.py  
b/src/mem/ruby/system/RubySystem.py

index 1ce4871..347896f 100644
--- a/src/mem/ruby/system/RubySystem.py
+++ b/src/mem/ruby/system/RubySystem.py
@@ -25,6 +25,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 from m5.params import *
+from m5.proxy import *
 from m5.objects.ClockedObject import ClockedObject
 from m5.objects.SimpleMemory import *

@@ -41,6 +42,7 @@
 "number of bits that a memory address requires");

 phys_mem = Param.SimpleMemory(NULL, "")
+system = Param.System(Parent.any, "system object")

 access_backing_store = Param.Bool(False, "Use phys_mem as the  
functional \

 store and only use ruby for timing.")
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 0bae99a..93d986c 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -357,6 +357,35 @@
 }

 void
+System::addDeviceMemory(MasterID masterId, AddrRange range,
+PhysicalMemory *deviceMemory)
+{
+// Remove the interleaving bits to prevent addresses from not matching.
+// Right now the device can only have one address range.
+if (!deviceMemMap.count(masterId)) {
+AddrRange flat_range(range.start(), range.end());
+DeviceMemInfo dmi{flat_range, deviceMemory};
+deviceMemMap.emplace(masterId, dmi);
+}
+}
+
+bool
+System::isDeviceMemAddr(PacketPtr pkt) const
+{
+const MasterID& mid = pkt->masterId();
+
+return (deviceMemMap.count(mid) &&
+deviceMemMap.at(mid).addrRange.contains(pkt->getAddr()));
+}
+
+PhysicalMemory *
+System::getDeviceMemory(MasterID mid) const
+{
+return deviceMemMap.count(mid) ? deviceMemMap.at(mid).backingStore
+   : nullptr;
+}
+
+void
 System::drainResume()
 {
 totalNumInsts = 0;
diff --git a/src/sim/system.hh b/src/sim/system.hh
index fa59765..287ceb3 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -97,6 +97,18 @@
 std::list liveEvents;
 SystemPort _systemPort;

+// Map of memory address ranges for devices with their own backing  
stores

+struct DeviceMemInfo
+{
+AddrRange addrRange;
+PhysicalMemory *backingStore;
+
+DeviceMemInfo(AddrRange r, PhysicalMemory *p)
+: addrRange(r), backingStore(p) { }
+};
+
+std::unordered_map deviceMemMap;
+
   public:

 void init() override;
@@ -243,6 +255,26 @@
 bool isMemAddr(Addr addr) const;

 /**
+ * Add a physical memory range for a device. The ranges added here will
+ * be considered a non-PIO memory address if the masterId of the packet
+ * and range match something in the device memory map.
+ */
+void addDeviceMemory(MasterID masterID, AddrRange range,
+ PhysicalMemory *deviceMemory = nullptr);
+
+/**
+ * Similar to isMemAddr but for devices. Checks if a physical address
+ * of the packet match an address range of a device corresponding to  
the

+ * MasterId of the request.
+ */
+bool isDeviceMemAddr(PacketPtr pkt) const;
+
+    /**
+ * Return a pointer to the device memory.
+ */
+PhysicalMemory *getDeviceMemory(MasterID masterID) const;
+
+/**
  * Get the architecture.
  */
 Arch getArch() const { return Arch::TheISA; }

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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Allow MachineID to be unordered key

2020-05-28 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/29652 )



Change subject: mem-ruby: Allow MachineID to be unordered key
..

mem-ruby: Allow MachineID to be unordered key

Define an std::hash function so that MachineID may be used as a key
type for unordered STL containers.

Change-Id: Ibc3bc78149c69683207d8967542fa6e8d545f75c
---
M src/mem/ruby/common/MachineID.hh
1 file changed, 10 insertions(+), 0 deletions(-)



diff --git a/src/mem/ruby/common/MachineID.hh  
b/src/mem/ruby/common/MachineID.hh

index 64082d7..3ef7b88 100644
--- a/src/mem/ruby/common/MachineID.hh
+++ b/src/mem/ruby/common/MachineID.hh
@@ -67,6 +67,16 @@
 return (obj1.type != obj2.type || obj1.num != obj2.num);
 }

+namespace std {
+template<>
+struct hash {
+inline size_t operator()(const MachineID& id) const {
+size_t hval = MachineType_base_level(id.type) << 16 | id.num;
+return hval;
+}
+};
+}
+
 // Output operator declaration
 std::ostream& operator<<(std::ostream& out, const MachineID& obj);


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[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: misc: Fixed GCN3_X86/HSAIL_X86 compilation errors

2020-05-19 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/29305 )



Change subject: misc: Fixed GCN3_X86/HSAIL_X86 compilation errors
..

misc: Fixed GCN3_X86/HSAIL_X86 compilation errors

GCN3_X86 and HSAIL_X86 fail to compile. This patch enables compilation.

Issue-on: https://gem5.atlassian.net/browse/GEM5-556
  https://gem5.atlassian.net/browse/GEM5-561

Change-Id: Ib0882dcc013ac097d0d5ab9c0ca401ea00391616
---
M src/dev/hsa/hsa_device.cc
M src/dev/hsa/hsa_driver.cc
M src/dev/hsa/hsa_packet_processor.cc
3 files changed, 5 insertions(+), 31 deletions(-)



diff --git a/src/dev/hsa/hsa_device.cc b/src/dev/hsa/hsa_device.cc
index c23639e..78ec8e8 100644
--- a/src/dev/hsa/hsa_device.cc
+++ b/src/dev/hsa/hsa_device.cc
@@ -102,9 +102,8 @@
  * grab context zero.
  */
 auto process = sys->getThreadContext(0)->getProcessPtr();
-auto mem_state = process->memState;

-if (!mem_state->translate(vaddr, paddr)) {
+if (!process->pTable->translate(vaddr, paddr)) {
 fatal("failed translation: vaddr 0x%x\n", vaddr);
 }
 }
diff --git a/src/dev/hsa/hsa_driver.cc b/src/dev/hsa/hsa_driver.cc
index 08e1db3..3f5c8eb 100644
--- a/src/dev/hsa/hsa_driver.cc
+++ b/src/dev/hsa/hsa_driver.cc
@@ -87,32 +87,8 @@
  * Now map this virtual address to our PIO doorbell interface
  * in the page tables (non-cacheable).
  */
-mem_state->map(start, device->hsaPacketProc().pioAddr, length, false);
+process->pTable->map(start, device->hsaPacketProc().pioAddr,
+ length, false);
 DPRINTF(HSADriver, "amdkfd doorbell mapped to %xp\n", start);
 return start;
 }
-
-/**
- * Forward relevant parameters to packet processor; queueID
- * is used to link doorbell. The queueIDs are not re-used
- * in current implementation, and we allocate only one page
- * (4096 bytes) for doorbells, so check if this queue ID can
- * be mapped into that page.
- */
-void
-HSADriver::allocateQueue(const SETranslatingPortProxy _proxy, Addr  
ioc_buf)

-{
-TypedBufferArg args(ioc_buf);
-args.copyIn(mem_proxy);
-
-if (VOID_PTR_ADD32(0, queueId) >= (void*)0x1000) {
-fatal("%s: Exceeded maximum number of HSA queues allowed\n",  
name());

-}
-
-args->queue_id = queueId++;
-auto _pp = device->hsaPacketProc();
-hsa_pp.setDeviceQueueDesc(args->read_pointer_address,
-  args->ring_base_address, args->queue_id,
-  args->ring_size);
-args.copyOut(mem_proxy);
-}
diff --git a/src/dev/hsa/hsa_packet_processor.cc  
b/src/dev/hsa/hsa_packet_processor.cc

index ad59de5..5fa0fbe 100644
--- a/src/dev/hsa/hsa_packet_processor.cc
+++ b/src/dev/hsa/hsa_packet_processor.cc
@@ -127,7 +127,7 @@
   "%s: write of size %d to reg-offset %d (0x%x)\n",
   __FUNCTION__, pkt->getSize(), daddr, daddr);

-uint32_t doorbell_reg = pkt->get();
+uint32_t doorbell_reg = pkt->getLE();

 DPRINTF(HSAPacketProcessor,
 "%s: write data 0x%x to offset %d (0x%x)\n",
@@ -152,9 +152,8 @@
 // new extensions, it will likely be wrong to just arbitrarily grab  
context

 // zero.
 auto process = sys->getThreadContext(0)->getProcessPtr();
-auto mem_state = process->memState;

-if (!mem_state->translate(vaddr, paddr))
+if (!process->pTable->translate(vaddr, paddr))
 fatal("failed translation: vaddr 0x%x\n", vaddr);
 }


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[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: sim: Fixes for mremap

2020-05-13 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28948 )


Change subject: sim: Fixes for mremap
..

sim: Fixes for mremap

Remapping memory was trying to map old pages to the same new page and
calling MemState mapRegion unnecessarily. Properly increment the new
page address and remove the redundant mapRegion as remapRegion covers
its functionality.

JIRA: https://gem5.atlassian.net/browse/GEM5-475
Change-Id: Ie360755cfe488b09cbd87cd0ce525b11ac446b51
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28948
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/sim/mem_state.cc
M src/sim/syscall_emul.hh
2 files changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/mem_state.cc b/src/sim/mem_state.cc
index 42d3781..f998fff 100644
--- a/src/sim/mem_state.cc
+++ b/src/sim/mem_state.cc
@@ -369,6 +369,7 @@
  new_start_addr);

 start_addr += _pageBytes;
+new_start_addr += _pageBytes;

 /**
  * The regions need to always be page-aligned otherwise the while
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 5bd9f54..290c48e 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1177,7 +1177,6 @@

 warn("returning %08p as start\n", new_start);
 p->memState->remapRegion(start, new_start, old_length);
-p->memState->mapRegion(new_start, new_length, "remapped");
 return new_start;
 }
 }

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Gerrit-Change-Number: 28948
Gerrit-PatchSet: 2
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Brandon Potter 
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[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: sim: Fixes for mremap

2020-05-12 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28948 )



Change subject: sim: Fixes for mremap
..

sim: Fixes for mremap

Remapping memory was trying to map old pages to the same new page and
calling MemState mapRegion unnecessarily. Properly increment the new
page address and remove the redundant mapRegion as remapRegion covers
its functionality.

JIRA: https://gem5.atlassian.net/browse/GEM5-475
Change-Id: Ie360755cfe488b09cbd87cd0ce525b11ac446b51
---
M src/sim/mem_state.cc
M src/sim/syscall_emul.hh
2 files changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/sim/mem_state.cc b/src/sim/mem_state.cc
index 42d3781..f998fff 100644
--- a/src/sim/mem_state.cc
+++ b/src/sim/mem_state.cc
@@ -369,6 +369,7 @@
  new_start_addr);

 start_addr += _pageBytes;
+new_start_addr += _pageBytes;

 /**
  * The regions need to always be page-aligned otherwise the while
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 5bd9f54..290c48e 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1177,7 +1177,6 @@

 warn("returning %08p as start\n", new_start);
 p->memState->remapRegion(start, new_start, old_length);
-p->memState->mapRegion(new_start, new_length, "remapped");
 return new_start;
 }
 }

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[gem5-dev] Change in gem5/gem5[develop]: sim: Fixes for mremap

2020-05-12 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28907 )



Change subject: sim: Fixes for mremap
..

sim: Fixes for mremap

Remapping memory was trying to map old pages to the same new page and
calling MemState mapRegion unnecessarily. Properly increment the new
page address and remove the redudnant mapRegion as remapRegion covers
its functionality.

Change-Id: Ie360755cfe488b09cbd87cd0ce525b11ac446b51
---
M src/sim/mem_state.cc
M src/sim/syscall_emul.hh
2 files changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/sim/mem_state.cc b/src/sim/mem_state.cc
index 42d3781..f998fff 100644
--- a/src/sim/mem_state.cc
+++ b/src/sim/mem_state.cc
@@ -369,6 +369,7 @@
  new_start_addr);

 start_addr += _pageBytes;
+new_start_addr += _pageBytes;

 /**
  * The regions need to always be page-aligned otherwise the while
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 5bd9f54..290c48e 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1177,7 +1177,6 @@

 warn("returning %08p as start\n", new_start);
 p->memState->remapRegion(start, new_start, old_length);
-p->memState->mapRegion(new_start, new_length, "remapped");
 return new_start;
 }
 }

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[gem5-dev] Change in gem5/gem5[develop]: gpu-compute,mem-ruby: Refactor GPU coalescer

2020-05-11 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27429 )


Change subject: gpu-compute,mem-ruby: Refactor GPU coalescer
..

gpu-compute,mem-ruby: Refactor GPU coalescer

Remove the read/write tables and coalescing table and introduce a two
levels of tables for uncoalesced and coalesced packets. Tokens are
granted to GPU instructions to place in uncoalesced table. If tokens
are available, the operation always succeeds such that the 'Aliased'
status is never returned. Coalesced accesses are placed in the
coalesced table while requests are outstanding. Requests to the same
address are added as targets to the table similar to how MSHRs
operate.

Change-Id: I44983610307b638a97472db3576d0a30df2de600
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27429
Reviewed-by: Bradford Beckmann 
Reviewed-by: Jason Lowe-Power 
Maintainer: Bradford Beckmann 
Tested-by: kokoro 
---
M src/gpu-compute/GPU.py
M src/gpu-compute/compute_unit.cc
M src/gpu-compute/compute_unit.hh
M src/gpu-compute/global_memory_pipeline.cc
M src/gpu-compute/global_memory_pipeline.hh
M src/gpu-compute/wavefront.cc
M src/mem/ruby/system/GPUCoalescer.cc
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/ruby/system/GPUCoalescer.py
M src/mem/ruby/system/VIPERCoalescer.cc
10 files changed, 572 insertions(+), 643 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve
  Bradford Beckmann: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/gpu-compute/GPU.py b/src/gpu-compute/GPU.py
index fee0254..7eaf65f 100644
--- a/src/gpu-compute/GPU.py
+++ b/src/gpu-compute/GPU.py
@@ -129,6 +129,8 @@
   "memory pipeline's queues")
 local_mem_queue_size = Param.Int(256, "Number of entries in the local "
   "memory pipeline's queues")
+max_cu_tokens = Param.Int(4, "Maximum number of tokens, i.e., the  
number"\
+" of instructions that can be sent to  
coalescer")

 ldsBus = Bridge() # the bridge between the CU and its LDS
 ldsPort = MasterPort("The port that goes to the LDS")
 localDataStore = Param.LdsState("the LDS for this CU")
diff --git a/src/gpu-compute/compute_unit.cc  
b/src/gpu-compute/compute_unit.cc

index 59bc6a0..cd880d6 100644
--- a/src/gpu-compute/compute_unit.cc
+++ b/src/gpu-compute/compute_unit.cc
@@ -74,9 +74,9 @@
 req_tick_latency(p->mem_req_latency * p->clk_domain->clockPeriod()),
 resp_tick_latency(p->mem_resp_latency * p->clk_domain->clockPeriod()),
 _masterId(p->system->getMasterId(this, "ComputeUnit")),
-lds(*p->localDataStore), _cacheLineSize(p->system->cacheLineSize()),
-globalSeqNum(0), wavefrontSize(p->wfSize),
-kernelLaunchInst(new KernelLaunchStaticInst())
+lds(*p->localDataStore), gmTokenPort(name() + ".gmTokenPort", this),
+_cacheLineSize(p->system->cacheLineSize()), globalSeqNum(0),
+wavefrontSize(p->wfSize), kernelLaunchInst(new  
KernelLaunchStaticInst())

 {
 /**
  * This check is necessary because std::bitset only provides conversion
@@ -139,6 +139,10 @@

 memPort.resize(wfSize());

+// Setup tokens for slave ports. The number of tokens in memSlaveTokens
+// is the total token count for the entire vector port (i.e., this CU).
+memPortTokens = new TokenManager(p->max_cu_tokens);
+
 // resize the tlbPort vectorArray
 int tlbPort_width = perLaneTLB ? wfSize() : 1;
 tlbPort.resize(tlbPort_width);
@@ -612,6 +616,8 @@
 vectorAluInstAvail.resize(numSIMDs, false);
 shrMemInstAvail = 0;
 glbMemInstAvail = 0;
+
+gmTokenPort.setTokenManager(memPortTokens);
 }

 bool
diff --git a/src/gpu-compute/compute_unit.hh  
b/src/gpu-compute/compute_unit.hh

index a023cb2..49713e9 100644
--- a/src/gpu-compute/compute_unit.hh
+++ b/src/gpu-compute/compute_unit.hh
@@ -51,6 +51,7 @@
 #include "gpu-compute/schedule_stage.hh"
 #include "gpu-compute/scoreboard_check_stage.hh"
 #include "mem/port.hh"
+#include "mem/token_port.hh"
 #include "sim/clocked_object.hh"

 static const int MAX_REGS_FOR_NON_VEC_MEM_INST = 1;
@@ -415,6 +416,26 @@

 CUExitCallback *cuExitCallback;

+class GMTokenPort : public TokenMasterPort
+{
+  public:
+GMTokenPort(const std::string& name, SimObject *owner,
+PortID id = InvalidPortID)
+: TokenMasterPort(name, owner, id)
+{ }
+~GMTokenPort() { }
+
+  protected:
+bool recvTimingResp(PacketPtr) { return false; }
+void recvReqRetry() { }
+};
+
+// Manager for the number of tokens available to this compute unit to
+// send global memory request packets to the coalescer this is only  
used

+// between global memory pipe and TCP coalescer.
+TokenManager *memPortTokens;
+GMTokenPort gmTokenPort;
+
 /** 

[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: mem: Defer deletion of respQueue.front() in DRAMCtrl

2020-05-11 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28808 )


Change subject: mem: Defer deletion of respQueue.front() in DRAMCtrl
..

mem: Defer deletion of respQueue.front() in DRAMCtrl

The front() of respQueue was being deleted before the last usuage of
dram_pkt (which points to the same object) causing random crashes.

Change-Id: I89862d10599dc0d1a50717dac8ed9298b4d74a3d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28808
Reviewed-by: Nikos Nikoleris 
Maintainer: Nikos Nikoleris 
Tested-by: kokoro 
---
M src/mem/dram_ctrl.cc
1 file changed, 3 insertions(+), 1 deletion(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc
index 0a8479e..5f0fcc7 100644
--- a/src/mem/dram_ctrl.cc
+++ b/src/mem/dram_ctrl.cc
@@ -716,7 +716,7 @@
 accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency);
 }

-delete respQueue.front();
+assert(respQueue.front() == dram_pkt);
 respQueue.pop_front();

 if (!respQueue.empty()) {
@@ -738,6 +738,8 @@
 }
 }

+delete dram_pkt;
+
 // We have made a location in the queue available at this point,
 // so if there is a read that was forced to wait, retry now
 if (retryRdReq) {

--
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Gerrit-Change-Id: I89862d10599dc0d1a50717dac8ed9298b4d74a3d
Gerrit-Change-Number: 28808
Gerrit-PatchSet: 3
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: Wendy Elsasser 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: mem: Defer deletion of respQueue.front() in DRAMCtrl

2020-05-08 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28808 )



Change subject: mem: Defer deletion of respQueue.front() in DRAMCtrl
..

mem: Defer deletion of respQueue.front() in DRAMCtrl

The front() of respQueue was being deleted before the last usuage of
dram_pkt (which points to the same object) causing random crashes.

Change-Id: I89862d10599dc0d1a50717dac8ed9298b4d74a3d
---
M src/mem/dram_ctrl.cc
1 file changed, 2 insertions(+), 1 deletion(-)



diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc
index 0a8479e..20b779b 100644
--- a/src/mem/dram_ctrl.cc
+++ b/src/mem/dram_ctrl.cc
@@ -716,7 +716,6 @@
 accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency);
 }

-delete respQueue.front();
 respQueue.pop_front();

 if (!respQueue.empty()) {
@@ -738,6 +737,8 @@
 }
 }

+delete dram_pkt;
+
 // We have made a location in the queue available at this point,
 // so if there is a read that was forced to wait, retry now
 if (retryRdReq) {

--
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[gem5-dev] Change in gem5/gem5[develop]: mem: Remove infinite queue between Ruby and memory

2020-04-30 Thread Matthew Poremba (Gerrit) via gem5-dev
MemoryPort(const std::string& _name, SimpleMemory& _memory);

   protected:
+bool tryTiming(PacketPtr pkt) override;
 Tick recvAtomic(PacketPtr pkt) override;
 Tick recvAtomicBackdoor(
 PacketPtr pkt, MemBackdoorPtr &_backdoor) override;
@@ -182,6 +183,7 @@
 void init() override;

   protected:
+bool tryTiming(PacketPtr pkt);
 Tick recvAtomic(PacketPtr pkt);
 Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &_backdoor);
 void recvFunctional(PacketPtr pkt);
diff --git a/src/mem/xbar.cc b/src/mem/xbar.cc
index 9920216..2d300e5 100644
--- a/src/mem/xbar.cc
+++ b/src/mem/xbar.cc
@@ -174,6 +174,13 @@

 template 
 bool
+BaseXBar::Layer::layerBusy() const
+{
+return (state == BUSY || waitingForPeer != NULL);
+}
+
+template 
+bool
 BaseXBar::Layer::tryTiming(SrcType* src_port)
 {
 // if we are in the retry state, we will not see anything but the
@@ -185,7 +192,7 @@
 // first we see if the layer is busy, next we check if the
 // destination port is already engaged in a transaction waiting
 // for a retry from the peer
-if (state == BUSY || waitingForPeer != NULL) {
+if (layerBusy()) {
 // the port should not be waiting already
 assert(std::find(waitingForLayer.begin(), waitingForLayer.end(),
  src_port) == waitingForLayer.end());
diff --git a/src/mem/xbar.hh b/src/mem/xbar.hh
index 4488f74..05fa7c9 100644
--- a/src/mem/xbar.hh
+++ b/src/mem/xbar.hh
@@ -148,6 +148,9 @@

 void occupyLayer(Tick until);

+/** Check if layer is busy */
+bool layerBusy() const;
+
 /**
  * Send a retry to the port at the head of waitingForLayer. The
  * caller must ensure that the list is not empty.

--
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[gem5-dev] Change in gem5/gem5[develop]: configs: Add missing requestToMemory MessageBuffers

2020-04-28 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28187 )


Change subject: configs: Add missing requestToMemory MessageBuffers
..

configs: Add missing requestToMemory MessageBuffers

In commit 53b6e21 two protocol config files were missed when the new
requestToMemory MessageBuffers were added. This fixes the issue such
that all Ruby protocols are working again.

Change-Id: Iaa04c792eaf6d659ba13c19f003e7e31b71ffdb4
JIRA: https://gem5.atlassian.net/browse/GEM5-468
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28187
Reviewed-by: Bobby R. Bruce 
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Ciro Santilli 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M configs/ruby/MESI_Three_Level.py
M configs/ruby/MOESI_AMD_Base.py
2 files changed, 3 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Ciro Santilli: Looks good to me, but someone else must approve
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/ruby/MESI_Three_Level.py  
b/configs/ruby/MESI_Three_Level.py

index c05dca3..fdebea4 100644
--- a/configs/ruby/MESI_Three_Level.py
+++ b/configs/ruby/MESI_Three_Level.py
@@ -229,6 +229,7 @@
 dir_cntrl.responseToDir.slave = ruby_system.network.master
 dir_cntrl.responseFromDir = MessageBuffer()
 dir_cntrl.responseFromDir.master = ruby_system.network.slave
+dir_cntrl.requestToMemory = MessageBuffer()
 dir_cntrl.responseFromMemory = MessageBuffer()

 for i, dma_port in enumerate(dma_ports):
diff --git a/configs/ruby/MOESI_AMD_Base.py b/configs/ruby/MOESI_AMD_Base.py
index 5b2d912..aa9dd50 100644
--- a/configs/ruby/MOESI_AMD_Base.py
+++ b/configs/ruby/MOESI_AMD_Base.py
@@ -277,6 +277,8 @@

 dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
 dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True)
+
+dir_cntrl.requestToMemory = MessageBuffer()
 dir_cntrl.responseFromMemory = MessageBuffer()

 exec("system.dir_cntrl%d = dir_cntrl" % i)

--
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Gerrit-Change-Number: 28187
Gerrit-PatchSet: 2
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Bobby R. Bruce 
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[gem5-dev] Change in gem5/gem5[develop]: configs: Add missing requestToMemory MessageBuffers

2020-04-24 Thread Matthew Poremba (Gerrit) via gem5-dev
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28187 )



Change subject: configs: Add missing requestToMemory MessageBuffers
..

configs: Add missing requestToMemory MessageBuffers

In commit 53b6e21 two protocol config files were missed when the new
requestToMemory MessageBuffers were added. This fixes the issue such
that all Ruby protocols are working again.

Change-Id: Iaa04c792eaf6d659ba13c19f003e7e31b71ffdb4
JIRA: https://gem5.atlassian.net/browse/GEM5-468
---
M configs/ruby/MESI_Three_Level.py
M configs/ruby/MOESI_AMD_Base.py
2 files changed, 3 insertions(+), 0 deletions(-)



diff --git a/configs/ruby/MESI_Three_Level.py  
b/configs/ruby/MESI_Three_Level.py

index c05dca3..fdebea4 100644
--- a/configs/ruby/MESI_Three_Level.py
+++ b/configs/ruby/MESI_Three_Level.py
@@ -229,6 +229,7 @@
 dir_cntrl.responseToDir.slave = ruby_system.network.master
 dir_cntrl.responseFromDir = MessageBuffer()
 dir_cntrl.responseFromDir.master = ruby_system.network.slave
+dir_cntrl.requestToMemory = MessageBuffer()
 dir_cntrl.responseFromMemory = MessageBuffer()

 for i, dma_port in enumerate(dma_ports):
diff --git a/configs/ruby/MOESI_AMD_Base.py b/configs/ruby/MOESI_AMD_Base.py
index 5b2d912..aa9dd50 100644
--- a/configs/ruby/MOESI_AMD_Base.py
+++ b/configs/ruby/MOESI_AMD_Base.py
@@ -277,6 +277,8 @@

 dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
 dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True)
+
+dir_cntrl.requestToMemory = MessageBuffer()
 dir_cntrl.responseFromMemory = MessageBuffer()

 exec("system.dir_cntrl%d = dir_cntrl" % i)

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[gem5-dev] Change in gem5/gem5[develop]: sim: Use off_t for mmap offset arguments

2020-04-17 Thread Matthew Poremba (Gerrit)
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27367 )


Change subject: sim: Use off_t for mmap offset arguments
..

sim: Use off_t for mmap offset arguments

The GuestABI used to call the system-calls infers the size of values
read from the registers based on the function signature of the system
call. For mmap this was causing offset to be truncated to a 32-bit
value. In the GPUComputeDriver mmap, the offset must be a 64-bit
value. This fixes a bug where the doorbell memory was not setup and
causing GPU applications to fail.

Change-Id: I75d9b32c0470d1907c68826ef81cf6cd46f60ea7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27367
Tested-by: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Tested-by: kokoro 
Reviewed-by: Matthew Poremba 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/arch/x86/linux/linux.hh
M src/sim/syscall_emul.hh
2 files changed, 20 insertions(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Matthew Poremba: Looks good to me, approved
  kokoro: Regressions pass
  Gem5 Cloud Project GCB service account: Regressions pass



diff --git a/src/arch/x86/linux/linux.hh b/src/arch/x86/linux/linux.hh
index e373daf..4705123 100644
--- a/src/arch/x86/linux/linux.hh
+++ b/src/arch/x86/linux/linux.hh
@@ -190,6 +190,14 @@

 static const int NUM_OPEN_FLAGS;

+//@{
+/// Basic X86_64 Linux types
+typedef uint64_t size_t;
+typedef uint64_t off_t;
+typedef int64_t time_t;
+typedef int64_t clock_t;
+//@}
+
 static const unsigned TGT_MAP_SHARED= 0x1;
 static const unsigned TGT_MAP_PRIVATE   = 0x2;
 static const unsigned TGT_MAP_32BIT = 0x00040;
@@ -318,6 +326,14 @@

 static SyscallFlagTransTable mmapFlagTable[];

+//@{
+/// Basic X86 Linux types
+typedef uint32_t size_t;
+typedef uint32_t off_t;
+typedef int32_t time_t;
+typedef int32_t clock_t;
+//@}
+
 static const unsigned TGT_MAP_SHARED= 0x1;
 static const unsigned TGT_MAP_PRIVATE   = 0x2;
 static const unsigned TGT_MAP_32BIT = 0x00040;
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 11561a6..e5444b1 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1642,8 +1642,8 @@
 template 
 SyscallReturn
 mmapFunc(SyscallDesc *desc, ThreadContext *tc,
- Addr start, uint64_t length, int prot, int tgt_flags,
- int tgt_fd, int offset)
+ Addr start, typename OS::size_t length, int prot,
+ int tgt_flags, int tgt_fd, typename OS::off_t offset)
 {
 auto p = tc->getProcessPtr();
 Addr page_bytes = tc->getSystemPtr()->getPageBytes();
@@ -1826,8 +1826,8 @@
 template 
 SyscallReturn
 mmap2Func(SyscallDesc *desc, ThreadContext *tc,
-  Addr start, uint64_t length, int prot, int tgt_flags,
-  int tgt_fd, int offset)
+  Addr start, typename OS::size_t length, int prot,
+  int tgt_flags, int tgt_fd, typename OS::off_t offset)
 {
 return mmapFunc(desc, tc, start, length, prot, tgt_flags,
 tgt_fd, offset *  
tc->getSystemPtr()->getPageBytes());


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I75d9b32c0470d1907c68826ef81cf6cd46f60ea7
Gerrit-Change-Number: 27367
Gerrit-PatchSet: 3
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby, mem-garnet: Multiple networks per RubySystem

2020-04-17 Thread Matthew Poremba (Gerrit)
tLink *simple_link = safe_cast(link);

-m_switches[src]->addOutPort(m_fromNetQueues[dest], routing_table_entry,
-simple_link->m_latency,
+m_switches[src]->addOutPort(m_fromNetQueues[local_dest],
+routing_table_entry,  
simple_link->m_latency,

 simple_link->m_bw_multiplier);
 }

 // From an endpoint node to a switch
 void
-SimpleNetwork::makeExtInLink(NodeID src, SwitchID dest, BasicLink* link,
+SimpleNetwork::makeExtInLink(NodeID global_src, SwitchID dest, BasicLink*  
link,

   const NetDest& routing_table_entry)
 {
-assert(src < m_nodes);
-m_switches[dest]->addInPort(m_toNetQueues[src]);
+assert(globalToLocalMap.count(global_src));
+NodeID local_src = globalToLocalMap[global_src];
+assert(local_src < m_nodes);
+m_switches[dest]->addInPort(m_toNetQueues[local_src]);
 }

 // From a switch to a switch
diff --git a/src/mem/ruby/system/RubySystem.cc  
b/src/mem/ruby/system/RubySystem.cc

index 83fa4c7..5a7fddd 100644
--- a/src/mem/ruby/system/RubySystem.cc
+++ b/src/mem/ruby/system/RubySystem.cc
@@ -80,7 +80,7 @@
 void
 RubySystem::registerNetwork(Network* network_ptr)
 {
-m_network = network_ptr;
+m_networks.push_back(network_ptr);
 }

 void
@@ -94,7 +94,9 @@

 RubySystem::~RubySystem()
 {
-delete m_network;
+for (int i = 0; i < m_networks.size(); ++i) {
+delete m_networks[i];
+}
 delete m_profiler;
 }

@@ -508,7 +510,9 @@
 }
 }

-num_functional_writes += m_network->functionalWrite(pkt);
+for (int i = 0; i < m_networks.size(); ++i) {
+num_functional_writes += m_networks[i]->functionalWrite(pkt);
+}
 DPRINTF(RubySystem, "Messages written = %u\n", num_functional_writes);

 return true;
diff --git a/src/mem/ruby/system/RubySystem.hh  
b/src/mem/ruby/system/RubySystem.hh

index 5d10991..9a0df07 100644
--- a/src/mem/ruby/system/RubySystem.hh
+++ b/src/mem/ruby/system/RubySystem.hh
@@ -130,7 +130,7 @@
 SimpleMemory *m_phys_mem;
 const bool m_access_backing_store;

-Network* m_network;
+std::vector m_networks;
 std::vector m_abs_cntrl_vec;
 Cycles m_start_cycle;


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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Change insertBits in TLB translateFunctional

2020-04-15 Thread Matthew Poremba (Gerrit)
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27827 )


Change subject: arch-x86: Change insertBits in TLB translateFunctional
..

arch-x86: Change insertBits in TLB translateFunctional

x86 TLB::translateFunctional inserts one too many bits from the virtual
address leading to an incorrect physical address occasionally.

Change-Id: I2cc551c496f7ce729ea440ef01a680c0de257269
JIRA: https://gem5.atlassian.net/browse/GEM5-442
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27827
Reviewed-by: Bobby R. Bruce 
Reviewed-by: Gabe Black 
Maintainer: Bobby R. Bruce 
Maintainer: Gabe Black 
Tested-by: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Tested-by: kokoro 
---
M src/arch/x86/tlb.cc
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass
  Gem5 Cloud Project GCB service account: Regressions pass



diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index baeeb66..ceccba8 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -473,7 +473,7 @@
 Fault fault = walker->startFunctional(tc, addr, logBytes, mode);
 if (fault != NoFault)
 return fault;
-paddr = insertBits(addr, logBytes, 0, vaddr);
+paddr = insertBits(addr, logBytes - 1, 0, vaddr);
 } else {
 Process *process = tc->getProcessPtr();
 const auto *pte = process->pTable->lookup(vaddr);

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Gerrit-Branch: develop
Gerrit-Change-Id: I2cc551c496f7ce729ea440ef01a680c0de257269
Gerrit-Change-Number: 27827
Gerrit-PatchSet: 3
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gem5 Cloud Project GCB service account  
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Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Change insertBits in TLB translateFunctional

2020-04-14 Thread Matthew Poremba (Gerrit)
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27827 )



Change subject: arch-x86: Change insertBits in TLB translateFunctional
..

arch-x86: Change insertBits in TLB translateFunctional

x86 TLB::translateFunctional inserts one too many bits from the virtual
address leading to an incorrect physical address occasionally.

Change-Id: I2cc551c496f7ce729ea440ef01a680c0de257269
JIRA: https://gem5.atlassian.net/browse/GEM5-442
---
M src/arch/x86/tlb.cc
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index baeeb66..b652a63 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -473,7 +473,7 @@
 Fault fault = walker->startFunctional(tc, addr, logBytes, mode);
 if (fault != NoFault)
 return fault;
-paddr = insertBits(addr, logBytes, 0, vaddr);
+paddr = insertBits(addr, logBytes-1, 0, vaddr);
 } else {
 Process *process = tc->getProcessPtr();
 const auto *pte = process->pTable->lookup(vaddr);

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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Do not fixup faults in TLB

2020-04-09 Thread Matthew Poremba (Gerrit)
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27507 )


Change subject: arch-x86: Do not fixup faults in TLB
..

arch-x86: Do not fixup faults in TLB

Faults in the TLB ought to cause a page walk. Force that by removing
the fixup in X86 TLB.

This fixes rare race conditions where a timing page walk is
intercepted by a TLB miss which fixes up the fault resulting in
double calls to allocateMem in Process class.

Change-Id: Iaef4d636cd2997144d8bc5012cd7c2a0a97102e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27507
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/arch/x86/tlb.cc
1 file changed, 0 insertions(+), 7 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 53492b0..baeeb66 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -397,13 +397,6 @@
 Process *p = tc->getProcessPtr();
 const EmulationPageTable::Entry *pte =
 p->pTable->lookup(vaddr);
-if (!pte && mode != Execute) {
-// Check if we just need to grow the stack.
-if (p->fixupFault(vaddr)) {
-// If we did, lookup the entry for the new  
page.

-pte = p->pTable->lookup(vaddr);
-}
-}
 if (!pte) {
 return std::make_shared(vaddr, true,  
mode,

true, false);

--
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Gerrit-Change-Number: 27507
Gerrit-PatchSet: 2
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Alexandru Duțu 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Replace SLICC queueMemory calls with enqueue

2020-04-08 Thread Matthew Poremba (Gerrit)
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27427 )


Change subject: mem-ruby: Replace SLICC queueMemory calls with enqueue
..

mem-ruby: Replace SLICC queueMemory calls with enqueue

Calls to queueMemoryRead and queueMemoryWrite do not consider the size
of the queue between ruby directories and DRAMCtrl which causes infinite
buffering in the queued port between the two. This adds a MessageBuffer
in between which uses enqueues in SLICC and is therefore size checked
before any SLICC transaction pushing to the buffer can occur, removing
the infinite buffering between the two.

Change-Id: Iedb9070844e4f6c8532a9c914d126105ec98d0bc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27427
Tested-by: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Tested-by: kokoro 
Reviewed-by: Bradford Beckmann 
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Matt Sinclair 
Maintainer: Bradford Beckmann 
---
M configs/learning_gem5/part3/msi_caches.py
M configs/learning_gem5/part3/ruby_caches_MI_example.py
M configs/ruby/GPU_RfO.py
M configs/ruby/GPU_VIPER.py
M configs/ruby/GPU_VIPER_Baseline.py
M configs/ruby/GPU_VIPER_Region.py
M configs/ruby/MESI_Two_Level.py
M configs/ruby/MI_example.py
M configs/ruby/MOESI_CMP_directory.py
M configs/ruby/MOESI_CMP_token.py
M configs/ruby/MOESI_hammer.py
M src/learning_gem5/part3/MSI-dir.sm
M src/mem/ruby/protocol/MESI_Two_Level-dir.sm
M src/mem/ruby/protocol/MI_example-dir.sm
M src/mem/ruby/protocol/MOESI_AMD_Base-Region-dir.sm
M src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
M src/mem/ruby/protocol/MOESI_AMD_Base-probeFilter.sm
M src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
M src/mem/ruby/protocol/MOESI_CMP_token-dir.sm
M src/mem/ruby/protocol/MOESI_hammer-dir.sm
M src/mem/ruby/protocol/RubySlicc_Defines.sm
M src/mem/ruby/protocol/RubySlicc_MemControl.sm
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/slicc/symbols/StateMachine.py
25 files changed, 445 insertions(+), 172 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bradford Beckmann: Looks good to me, approved; Looks good to me, approved
  Matt Sinclair: Looks good to me, approved
  kokoro: Regressions pass
  Gem5 Cloud Project GCB service account: Regressions pass



diff --git a/configs/learning_gem5/part3/msi_caches.py  
b/configs/learning_gem5/part3/msi_caches.py

index aeacd75..f899426 100644
--- a/configs/learning_gem5/part3/msi_caches.py
+++ b/configs/learning_gem5/part3/msi_caches.py
@@ -214,10 +214,11 @@
 self.forwardToCache = MessageBuffer(ordered = True)
 self.forwardToCache.master = ruby_system.network.slave

-# This is another special message buffer. It is used to send  
replies

-# from memory back to the controller. Any messages received on the
-# memory port (see self.memory above) will be directed to this
-# message buffer.
+# These are other special message buffers. They are used to send
+# requests to memory and responses from memory back to the  
controller.

+# Any messages sent or received on the memory port (see self.memory
+# above) will be directed through these message buffers.
+self.requestToMemory = MessageBuffer()
 self.responseFromMemory = MessageBuffer()

 class MyNetwork(SimpleNetwork):
diff --git a/configs/learning_gem5/part3/ruby_caches_MI_example.py  
b/configs/learning_gem5/part3/ruby_caches_MI_example.py

index 0a7e0d4..29b66a6 100644
--- a/configs/learning_gem5/part3/ruby_caches_MI_example.py
+++ b/configs/learning_gem5/part3/ruby_caches_MI_example.py
@@ -204,6 +204,7 @@
 self.dmaResponseFromDir.master = ruby_system.network.slave
 self.forwardFromDir = MessageBuffer()
 self.forwardFromDir.master = ruby_system.network.slave
+self.requestToMemory = MessageBuffer()
 self.responseFromMemory = MessageBuffer()

 class MyNetwork(SimpleNetwork):
diff --git a/configs/ruby/GPU_RfO.py b/configs/ruby/GPU_RfO.py
index 449c169..cf2fdbd 100644
--- a/configs/ruby/GPU_RfO.py
+++ b/configs/ruby/GPU_RfO.py
@@ -499,6 +499,7 @@

 dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
 dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True)
+dir_cntrl.requestToMemory = MessageBuffer()
 dir_cntrl.responseFromMemory = MessageBuffer()

 exec("system.dir_cntrl%d = dir_cntrl" % i)
diff --git a/configs/ruby/GPU_VIPER.py b/configs/ruby/GPU_VIPER.py
index 2c36426..71238ae 100644
--- a/configs/ruby/GPU_VIPER.py
+++ b/configs/ruby/GPU_VIPER.py
@@ -453,6 +453,7 @@

 dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
 dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True)
+dir_cntrl.requestToMemory = MessageBuffer()
 dir_cntrl.responseFromMemory = 

[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Do not fixup faults in TLB

2020-04-06 Thread Matthew Poremba (Gerrit)
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27507 )



Change subject: arch-x86: Do not fixup faults in TLB
..

arch-x86: Do not fixup faults in TLB

Faults in the TLB ought to cause a page walk. Force that by removing
the fixup in X86 TLB.

This fixes rare race conditions where a timing page walk is
intercepted by a TLB miss which fixes up the fault resulting in
double calls to allocateMem in Process class.

Change-Id: Iaef4d636cd2997144d8bc5012cd7c2a0a97102e5
---
M src/arch/x86/tlb.cc
1 file changed, 0 insertions(+), 7 deletions(-)



diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 53492b0..baeeb66 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -397,13 +397,6 @@
 Process *p = tc->getProcessPtr();
 const EmulationPageTable::Entry *pte =
 p->pTable->lookup(vaddr);
-if (!pte && mode != Execute) {
-// Check if we just need to grow the stack.
-if (p->fixupFault(vaddr)) {
-// If we did, lookup the entry for the new  
page.

-pte = p->pTable->lookup(vaddr);
-}
-}
 if (!pte) {
 return std::make_shared(vaddr, true,  
mode,

true, false);

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[gem5-dev] Change in gem5/gem5[develop]: base, arch-hsail: Fix GPU build

2020-04-03 Thread Matthew Poremba (Gerrit)
ranslation, Mode mode, bool ,

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[gem5-dev] Change in gem5/gem5[develop]: sim: Use off_t for mmap offset arguments

2020-04-01 Thread Matthew Poremba (Gerrit)
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27367 )



Change subject: sim: Use off_t for mmap offset arguments
..

sim: Use off_t for mmap offset arguments

The GuestABI used to call the system-calls infers the size of values
read from the registers based on the function signature of the system
call. For mmap this was causing offset to be truncated to a 32-bit
value. In the GPUComputeDriver mmap, the offset must be a 64-bit
value. This fixes a bug where the doorbell memory was not setup and
causing GPU applications to fail.

Change-Id: I75d9b32c0470d1907c68826ef81cf6cd46f60ea7
---
M src/sim/syscall_emul.hh
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index e1a23a0..a2e0f38 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1643,7 +1643,7 @@
 SyscallReturn
 mmapFunc(SyscallDesc *desc, ThreadContext *tc,
  Addr start, uint64_t length, int prot, int tgt_flags,
- int tgt_fd, int offset)
+ int tgt_fd, off_t offset)
 {
 auto p = tc->getProcessPtr();
 Addr page_bytes = tc->getSystemPtr()->getPageBytes();
@@ -1826,7 +1826,7 @@
 SyscallReturn
 mmap2Func(SyscallDesc *desc, ThreadContext *tc,
   Addr start, uint64_t length, int prot, int tgt_flags,
-  int tgt_fd, int offset)
+  int tgt_fd, off_t offset)
 {
 return mmapFunc(desc, tc, start, length, prot, tgt_flags,
 tgt_fd, offset *  
tc->getSystemPtr()->getPageBytes());


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[gem5-dev] Change in gem5/gem5[develop]: base, arch-hsail: Fix GPU build

2020-03-26 Thread Matthew Poremba (Gerrit)
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27136 )



Change subject: base,arch-hsail: Fix GPU build
..

base,arch-hsail: Fix GPU build

The GPU build is currently broken due to recent changes. This fixes
the build after changes to local access, removal of getSyscallArg,
and creating of AMO header in base.

Change-Id: I43506f6fb0a92a61a50ecb9efa7ee279ecb21d98
---
M src/base/amo.hh
M src/gpu-compute/cl_driver.cc
M src/gpu-compute/gpu_dyn_inst.hh
M src/gpu-compute/gpu_tlb.cc
M src/gpu-compute/gpu_tlb.hh
5 files changed, 17 insertions(+), 17 deletions(-)



diff --git a/src/base/amo.hh b/src/base/amo.hh
index 718b346..44dec8b 100644
--- a/src/base/amo.hh
+++ b/src/base/amo.hh
@@ -35,6 +35,7 @@
 #include 
 #include 
 #include 
+#include 

 struct AtomicOpFunctor
 {
diff --git a/src/gpu-compute/cl_driver.cc b/src/gpu-compute/cl_driver.cc
index d8a4618..ee86017 100644
--- a/src/gpu-compute/cl_driver.cc
+++ b/src/gpu-compute/cl_driver.cc
@@ -105,9 +105,6 @@
 int
 ClDriver::ioctl(ThreadContext *tc, unsigned req, Addr buf_addr)
 {
-int index = 2;
-auto process = tc->getProcessPtr();
-
 switch (req) {
   case HSA_GET_SIZES:
 {
diff --git a/src/gpu-compute/gpu_dyn_inst.hh  
b/src/gpu-compute/gpu_dyn_inst.hh

index a4a6ffb..bee08e3 100644
--- a/src/gpu-compute/gpu_dyn_inst.hh
+++ b/src/gpu-compute/gpu_dyn_inst.hh
@@ -251,31 +251,31 @@
 // when true, call execContinuation when response arrives
 bool useContinuation;

-template AtomicOpFunctor*
+template AtomicOpFunctorPtr
 makeAtomicOpFunctor(c0 *reg0, c0 *reg1)
 {
 if (isAtomicAnd()) {
-return new AtomicOpAnd(*reg0);
+return m5::make_unique>(*reg0);
 } else if (isAtomicOr()) {
-return new AtomicOpOr(*reg0);
+return m5::make_unique>(*reg0);
 } else if (isAtomicXor()) {
-return new AtomicOpXor(*reg0);
+return m5::make_unique>(*reg0);
 } else if (isAtomicCAS()) {
-return new AtomicOpCAS(*reg0, *reg1, cu);
+return m5::make_unique>(*reg0, *reg1, cu);
 } else if (isAtomicExch()) {
-return new AtomicOpExch(*reg0);
+return m5::make_unique>(*reg0);
 } else if (isAtomicAdd()) {
-return new AtomicOpAdd(*reg0);
+return m5::make_unique>(*reg0);
 } else if (isAtomicSub()) {
-return new AtomicOpSub(*reg0);
+return m5::make_unique>(*reg0);
 } else if (isAtomicInc()) {
-return new AtomicOpInc();
+return m5::make_unique>();
 } else if (isAtomicDec()) {
-return new AtomicOpDec();
+return m5::make_unique>();
 } else if (isAtomicMax()) {
-return new AtomicOpMax(*reg0);
+return m5::make_unique>(*reg0);
 } else if (isAtomicMin()) {
-return new AtomicOpMin(*reg0);
+return m5::make_unique>(*reg0);
 } else {
 fatal("Unrecognized atomic operation");
 }
diff --git a/src/gpu-compute/gpu_tlb.cc b/src/gpu-compute/gpu_tlb.cc
index 12fb9aa..2ae40da 100644
--- a/src/gpu-compute/gpu_tlb.cc
+++ b/src/gpu-compute/gpu_tlb.cc
@@ -43,6 +43,7 @@
 #include "arch/x86/pagetable.hh"
 #include "arch/x86/pagetable_walker.hh"
 #include "arch/x86/regs/misc.hh"
+#include "arch/x86/regs/msr.hh"
 #include "arch/x86/x86_traits.hh"
 #include "base/bitfield.hh"
 #include "base/logging.hh"
@@ -426,7 +427,7 @@
 // If this is true, we're dealing with a request
 // to a non-memory address space.
 if (seg == SEGMENT_REG_MS) {
-return translateInt(mode == Read, req, tc);
+return translateInt(mode == Mode::Read, req, tc);
 }

 delayedResponse = false;
diff --git a/src/gpu-compute/gpu_tlb.hh b/src/gpu-compute/gpu_tlb.hh
index 6ed4ba1..dbd3a16 100644
--- a/src/gpu-compute/gpu_tlb.hh
+++ b/src/gpu-compute/gpu_tlb.hh
@@ -175,7 +175,8 @@
  */
 std::vector entryList;

-Fault translateInt(const RequestPtr , ThreadContext *tc);
+Fault translateInt(bool read, const RequestPtr ,
+   ThreadContext *tc);

 Fault translate(const RequestPtr , ThreadContext *tc,
 Translation *translation, Mode mode, bool ,

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[gem5-dev] Change in gem5/gem5[develop]: sim-se: Add special paths for MPI, libnuma, ROCm support

2020-03-25 Thread Matthew Poremba (Gerrit)
-xp  00:00 0 ";
+line << "[" << vma.getName() << "]" << std::endl;
+file_content << line.str();
+}
+
+return file_content.str();
+}
diff --git a/src/sim/mem_state.hh b/src/sim/mem_state.hh
index 42823ce..1ca80da 100644
--- a/src/sim/mem_state.hh
+++ b/src/sim/mem_state.hh
@@ -203,6 +203,11 @@
 paramIn(cp, "mmapEnd", _mmapEnd);
 }

+/**
+ * Print the list of VMAs in a format similar to /proc/self/maps
+ */
+std::string printVmaList();
+
   private:
 /**
  * Owner process of MemState. Used to manipulate page tables.
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 1270855..e1a23a0 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -876,7 +876,9 @@
 int sim_fd = -1;
 std::string used_path;
 std::vector special_paths =
-{ "/proc/meminfo/", "/system/", "/platform/", "/etc/passwd" };
+{ "/proc/meminfo/", "/system/", "/platform/", "/etc/passwd",
+  "/proc/self/maps", "/dev/urandom",
+  "/sys/devices/system/cpu/online" };
 for (auto entry : special_paths) {
     if (startswith(path, entry)) {
 sim_fd = OS::openSpecialFile(abs_path, p, tc);

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[gem5-dev] Change in gem5/gem5[develop]: sim-se: Switch to new MemState API

2020-03-25 Thread Matthew Poremba (Gerrit)
) {
-if (!p->pTable->translate(gen.addr()))
-p->allocateMem(roundDown(gen.addr(), PageBytes),  
PageBytes);

+mem_state->updateBrkRegion(brk_point, new_brk);

-// if the address is already there, zero it out
-else {
-uint8_t zero = 0;
-PortProxy  = tc->getVirtProxy();
-
-// split non-page aligned accesses
-Addr next_page = roundUp(gen.addr(), PageBytes);
-uint32_t size_needed = next_page - gen.addr();
-tp.memsetBlob(gen.addr(), zero, size_needed);
-if (gen.addr() + PageBytes > next_page &&
-next_page < new_brk &&
-p->pTable->translate(next_page)) {
-size_needed = PageBytes - size_needed;
-tp.memsetBlob(next_page, zero, size_needed);
-}
-}
-}
-}
-
-mem_state->setBrkPoint(new_brk);
 DPRINTF_SYSCALL(Verbose, "brk: break point changed to: %#X\n",
 mem_state->getBrkPoint());
+
 return mem_state->getBrkPoint();
 }


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[gem5-dev] Change in gem5/gem5[develop]: sim-se: Update mmap, munmap, mremap to use MemState

2020-03-25 Thread Matthew Poremba (Gerrit)
uint64_t size = std::min((uint64_t)file_stat.st_size - offset,
- length);
-tp.writeBlob(start, pmap, size);
-
-// Cleanup the mmap region before exiting this function.
-munmap(pmap, length);
-
-// Maintain the symbol table for dynamic executables.
-// The loader will call mmap to map the images into its address
-// space and we intercept that here. We can verify that we are
-// executing inside the loader by checking the program counter  
value.
-// XXX: with multiprogrammed workloads or multi-node  
configurations,

-// this will not work since there is a single global symbol table.
-if (p->interpImage.contains(tc->pcState().instAddr())) {
-std::shared_ptr fdep = (*p->fds)[tgt_fd];
-auto ffdp = std::dynamic_pointer_cast(fdep);
-auto process = tc->getProcessPtr();
-ObjectFile *lib = createObjectFile(
-process->checkPathRedirect(
-ffdp->getFileName()));
-
-if (lib) {
-lib->loadAllSymbols(debugSymbolTable,
-lib->buildImage().minAddr(), start);
-}
-}
-
-// Note that we do not zero out the remainder of the mapping. This
-// is done by a real system, but it probably will not affect
-// execution (hopefully).
+std::shared_ptr fdep = (*p->fds)[tgt_fd];
+auto ffdp = std::dynamic_pointer_cast(fdep);
+    region_name = ffdp->getFileName();
 }

+/**
+ * Setup the correct VMA for this region.  The physical pages will be
+ * mapped lazily.
+ */
+p->memState->mapRegion(start, length, region_name, sim_fd, offset);
+
 return start;
 }


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[gem5-dev] Change in gem5/gem5[develop]: sim-se: Extend MemState API to use VMAs

2020-03-25 Thread Matthew Poremba (Gerrit)
tart_addr, Addr length);
+
+/**
+ * Add a new memory region. The region represents a contiguous virtual
+ * address range which can map to physical memory or a host-backed  
file.

+ * Regions which are not file-backed should use -1 for sim_fd and 0 for
+ * offset.
+ *
+ * @param start_addr Starting address of the region.
+ * @param length Size of the region.
+ * @param name Name of region. Optional.
+ * @param sim_fd File descriptor for file-backed regions or -1.
+ * @param offset Offset in file in which region starts.
+ */
+void mapRegion(Addr start_addr, Addr length,
+   const std::string& name="anon", int sim_fd=-1,
+   Addr offset=0);
+
+/**
+ * Unmap a pre-existing region. Depending on the range being unmapped
+ * the resulting new regions will either be split, resized, or
+ * removed completely.
+ *
+ * @param start_addr Starting address of region to unmap.
+ * @param length Size of region to unmap.
+ */
+void unmapRegion(Addr start_addr, Addr length);
+
+/**
+ * Remap a pre-existing region. This changes the virtual address
+ * range of the region. This will result in regions being expanded
+ * if there is overlap with another region or simply moving the range
+ * otherwise.
+ *
+ * @param start_addr Start address of region being remapped.
+ * @param new_start_addr New start address of the region.
+ * @param length Length of the newly remapped region.
+ */
+void remapRegion(Addr start_addr, Addr new_start_addr, Addr length);
+
+/**
+ * Change the end of a process' program break. This represents the end
+ * of the heap segment of a process.
+ *
+ * @param old_brk Old program break address
+ * @param new_brk New program break address
+ */
+void updateBrkRegion(Addr old_brk, Addr new_brk);
+
+/**
+ * Attempt to fix up a fault at vaddr by allocating a page. The fault
+ * likely occurred because a virtual page which does not have physical
+ * page assignment is being accessed.
+ *
+ * @param vaddr The virtual address which is causing the fault.
+ * @return Whether the fault has been fixed.
+ */
+bool fixupFault(Addr vaddr);
+
+/**
+ * Given the vaddr and size, this method will chunk the allocation into
+ * page granularity and then request physical pages (frames) from the
+ * system object. After retrieving a frame, the method updates the page
+ * table mappings.
+ *
+ * @param vaddr The virtual address in need of a frame allocation.
+ * @param size The size in bytes of the requested mapping.
+ * @param clobber This flag specifies whether mappings in the page  
tables

+ *can be overwritten and replaced with the new mapping.
+ */
+void allocateMem(Addr vaddr, int64_t size, bool clobber = false);
+
 void
 serialize(CheckpointOut ) const override
 {
@@ -113,6 +204,12 @@
 }

   private:
+/**
+ * Owner process of MemState. Used to manipulate page tables.
+ */
+Process * _ownerProcess;
+
+Addr _pageBytes;
 Addr _brkPoint;
 Addr _stackBase;
 Addr _stackSize;
@@ -120,6 +217,25 @@
 Addr _stackMin;
 Addr _nextThreadStackBase;
 Addr _mmapEnd;
+
+/**
+ * Keeps record of the furthest mapped heap location.
+ */
+Addr _endBrkPoint;
+
+/**
+ * The _vmaList member is a list of virtual memory areas in the target
+ * application space that have been allocated by the target. In most
+ * operating systems, lazy allocation is used and these structures (or
+ * equivalent ones) are used to track the valid address ranges.
+ *
+ * This could use a more efficient data structure like an interval
+ * tree, but it is unclear whether the vmas will be modified often  
enough
+ * for the improvement in lookup time to matter. Unmapping VMAs  
currently

+ * modifies the list while iterating so the STL container must either
+ * support this or the unmapping method must be changed.
+     */
+    std::list _vmaList;
 };

 #endif

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[gem5-dev] Change in gem5/gem5[develop]: tests: Add unit tests for Virtual Memory Areas

2020-03-24 Thread Matthew Poremba (Gerrit)
size(), 0x1000);
+EXPECT_DEATH(vma.sliceRegionRight(0x1000), "");
+}
+
+TEST(VMATest, ContractLeftDeath)
+{
+VMA vma(AddrRange(0x1000, 0x2000), 4096);
+EXPECT_EQ(vma.size(), 0x1000);
+EXPECT_DEATH(vma.sliceRegionLeft(0x2000), "");
+}
+
+TEST(VMATest, StrictSuperset)
+{
+VMA vma(AddrRange(0x0, 0x1), 4096);
+AddrRange r1(0x1000, 0x2000);
+AddrRange r2(0x0, 0x2000);
+AddrRange r3(0x9000, 0x11000);
+
+EXPECT_TRUE(vma.isStrictSuperset(r1));
+EXPECT_FALSE(vma.isStrictSuperset(r2));
+EXPECT_FALSE(vma.isStrictSuperset(r3));
+}
+
+TEST(VMATest, ContainsAddr)
+{
+VMA vma(AddrRange(0x0, 0x1000), 4096);
+EXPECT_TRUE(vma.contains(0xCAB));
+}

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[gem5-dev] Change in gem5/gem5[develop]: sim-se: Implement Virtual Memory Area API

2020-03-19 Thread Matthew Poremba (Gerrit)
   }
+
+/**
+ * Remap the virtual memory area starting at new_start.
+ */
+void
+remap(Addr new_start)
+{
+_addrRange = AddrRange(new_start, new_start + _addrRange.size());
+
+DPRINTF(Vma, "Remapping vma start %#x end %#x\n",  
_addrRange.start(),

+_addrRange.end());
+
+sanityCheck();
+}
+
+/**
+ * Check if the virtual memory area has an equivalent buffer on the
+ * host machine.
+ */
+bool hasHostBuf() const { return _origHostBuf != nullptr; }
+
+/**
+ * Copy memory from a buffer which resides on the host machine into a
+ * section of memory on the target.
+ */
+void fillMemPages(Addr start, Addr size, PortProxy ) const;
+
+/**
+ * Returns true if desired range exists within this virtual memory area
+ * and does not include the start and end addresses.
+ */
+bool isStrictSuperset(const AddrRange ) const;
+
+/**
+ * Remove the address range to the right of slice_addr.
+ */
+void sliceRegionRight(Addr slice_addr);
+
+/**
+ * Remove the address range to the left of slice_addr.
+ */
+void sliceRegionLeft(Addr slice_addr);
+
+const std::string& getName() { return _vmaName; }
+
+/**
+ * Defer AddrRange related calls to the AddrRange.
+ */
+Addr size() { return _addrRange.size(); }
+Addr start() { return _addrRange.start(); }
+Addr end() { return _addrRange.end(); }
+
+bool
+mergesWith(const AddrRange& r) const
+{
+return _addrRange.mergesWith(r);
+}
+
+bool
+intersects(const AddrRange& r) const
+{
+return _addrRange.intersects(r);
+}
+
+bool
+isSubset(const AddrRange& r) const
+{
+return _addrRange.isSubset(r);
+}
+
+bool
+contains(const Addr& a) const
+{
+return _addrRange.contains(a);
+}
+
+  private:
+void sanityCheck();
+
+/**
+ * Address range for this virtual memory area.
+ */
+AddrRange _addrRange;
+
+/**
+ * Number of bytes in an OS page.
+ */
+Addr _pageBytes;
+
+/**
+ * The host file backing will be chopped up and reassigned as pages are
+ * mapped, remapped, and unmapped. In addition to the current host
+ * pointer and length, each virtual memory area will also keep a
+ * reference-counted handle to the original host memory. The last  
virtual

+ * memory area to die cleans up the host memory it handles.
+ */
+std::shared_ptr _origHostBuf;
+
+/**
+ * Host buffer ptr for this virtual memory area.
+ */
+void *_hostBuf;
+
+/**
+ * Length of host buffer for this virtual memory area.
+ */
+uint64_t _hostBufLen;
+
+/**
+ * Human-readable name associated with the virtual memory area.
+ * The name is useful for debugging and also exposing vma state through
+ * the psuedo file system (i.e. Linux's /proc/self/maps) to the
+ * application.
+ */
+std::string _vmaName;
+
+/**
+ * MappedFileBuffer is a wrapper around a region of host memory backed  
by a
+ * file. The constructor attempts to map a file from host memory, and  
the
+ * destructor attempts to unmap it.  If there is a problem with the  
host

+ * mapping/unmapping, then we panic.
+ */
+class MappedFileBuffer
+{
+  public:
+MappedFileBuffer(int fd, size_t length, off_t offset);
+~MappedFileBuffer();
+
+void *getBuffer() const { return _buffer; }
+uint64_t getLength() const { return _length; }
+
+  private:
+void *_buffer;   // Host buffer ptr
+size_t _length;   // Length of host ptr
+};
+};
+
+#endif // __SRC_MEM_VMA_HH__

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Gerrit-Change-Number: 25365
Gerrit-PatchSet: 14
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in gem5/gem5[develop]: sim-se: Update mmap, munmap, mremap to use MemState

2020-03-17 Thread Matthew Poremba (Gerrit)
to map the images into its address
-// space and we intercept that here. We can verify that we are
-// executing inside the loader by checking the program counter  
value.
-// XXX: with multiprogrammed workloads or multi-node  
configurations,

-// this will not work since there is a single global symbol table.
-if (p->interpImage.contains(tc->pcState().instAddr())) {
-std::shared_ptr fdep = (*p->fds)[tgt_fd];
-auto ffdp = std::dynamic_pointer_cast(fdep);
-auto process = tc->getProcessPtr();
-ObjectFile *lib = createObjectFile(
-process->checkPathRedirect(
-ffdp->getFileName()));
-
-if (lib) {
-lib->loadAllSymbols(debugSymbolTable,
-lib->buildImage().minAddr(), start);
-}
-}
-
-// Note that we do not zero out the remainder of the mapping. This
-// is done by a real system, but it probably will not affect
-// execution (hopefully).
+std::shared_ptr fdep = (*p->fds)[tgt_fd];
+auto ffdp = std::dynamic_pointer_cast(fdep);
+    region_name = ffdp->getFileName();
 }

+/**
+ * Setup the correct VMA for this region.  The physical pages will be
+ * mapped lazily.
+ */
+p->memState->mapRegion(start, length, region_name, sim_fd, offset);
+
 return start;
 }


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[gem5-dev] Change in gem5/gem5[develop]: base: Fix build with protobuf

2020-02-18 Thread Matthew Poremba (Gerrit)
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25503 )



Change subject: base: Fix build with protobuf
..

base: Fix build with protobuf

Change-Id: I7f1e98d3a8ff6f56c9acf078700bb7a9dd09a1eb
---
M src/arch/arm/nativetrace.cc
M src/base/remote_gdb.cc
M src/dev/net/i8254xGBe.cc
3 files changed, 5 insertions(+), 11 deletions(-)



diff --git a/src/arch/arm/nativetrace.cc b/src/arch/arm/nativetrace.cc
index 0a0a250..e2a1175 100644
--- a/src/arch/arm/nativetrace.cc
+++ b/src/arch/arm/nativetrace.cc
@@ -165,8 +165,7 @@

 errorFound = true;

-#ifndef NDEBUG
-const char *vergence = "  ";
+const char * M5_VAR_USED vergence = "  ";
 if (oldMatch && !newMatch) {
 vergence = "<>";
 } else if (!oldMatch && newMatch) {
@@ -195,7 +194,6 @@
   nState.oldState[i],  
nState.newState[i],
   mState.oldState[i],  
mState.newState[i]);

 }
-#endif
 }
 }
 if (errorFound) {
diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index 7c8241a..026a9a0 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -297,7 +297,7 @@
 GdbAccWp = '4',
 };

-#ifndef NDEBUG
+#if TRACING_ON==1
 const char *
 break_type(char c)
 {
diff --git a/src/dev/net/i8254xGBe.cc b/src/dev/net/i8254xGBe.cc
index 55e8c51..6f678be 100644
--- a/src/dev/net/i8254xGBe.cc
+++ b/src/dev/net/i8254xGBe.cc
@@ -1023,9 +1023,7 @@
 }


-#ifndef NDEBUG
-int oldCp = cachePnt;
-#endif
+int M5_VAR_USED oldCp = cachePnt;

 cachePnt += curFetching;
 assert(cachePnt <= descLen());
@@ -1058,10 +1056,8 @@

 igbe->anBegin(annSmWb, "Finish Writeback");

-long  curHead = descHead();
-#ifndef NDEBUG
-long oldHead = curHead;
-#endif
+long curHead = descHead();
+long M5_VAR_USED oldHead = curHead;

 for (int x = 0; x < wbOut; x++) {
 assert(usedCache.size());

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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add used attribute to pauth_helpers asserts

2020-02-18 Thread Matthew Poremba (Gerrit)
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25364 )


Change subject: arch-arm: Add used attribute to pauth_helpers asserts
..

arch-arm: Add used attribute to pauth_helpers asserts

Adding M5_VAR_USED attribute to variables in pauth_helpers so that
gem5.fast builds.

Change-Id: I45dd70ea2e921f7ce68ea52147abdd40da99f37e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25364
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/pauth_helpers.cc
1 file changed, 2 insertions(+), 3 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/pauth_helpers.cc b/src/arch/arm/pauth_helpers.cc
index 892a414..1c83d77 100644
--- a/src/arch/arm/pauth_helpers.cc
+++ b/src/arch/arm/pauth_helpers.cc
@@ -113,9 +113,8 @@
 Fault
 ArmISA::trapPACUse(ThreadContext *tc, ExceptionLevel target_el)
 {
-ExceptionLevel curr_el = currEL(tc);
 assert(ArmSystem::haveEL(tc, target_el) &&
-   target_el != EL0 && (target_el >= curr_el));
+   target_el != EL0 && (target_el >= currEL(tc)));

 switch (target_el) {
case EL2:
@@ -149,7 +148,7 @@
 if (upperAndLowerRange(tc, el)) {
 ExceptionLevel s1_el = s1TranslationRegime(tc, el);
 assert (s1_el == EL1 || s1_el == EL2);
-if (s1TranslationRegime(tc, el) == EL1) {
+if (s1_el == EL1) {
 // EL1 translation regime registers
 TCR tcr = tc->readMiscReg(MISCREG_TCR_EL1);
 if (data) {

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Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in gem5/gem5[develop]: sim-se: Extend MemState API to use VMAs

2020-02-17 Thread Matthew Poremba (Gerrit)
Table(np->pTable.get());

 np->memState = memState;
 } else {
diff --git a/src/sim/process.hh b/src/sim/process.hh
index 6183bcc..64b0698 100644
--- a/src/sim/process.hh
+++ b/src/sim/process.hh
@@ -178,7 +178,7 @@
 // flag for using the process as a thread which shares page tables
 bool useForClone;

-EmulationPageTable *pTable;
+std::shared_ptr pTable;

 SETranslatingPortProxy initVirtMem; // memory proxy for initial image  
load



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[gem5-dev] Change in gem5/gem5[develop]: sim-se: Implement Virtual Memory Area API

2020-02-13 Thread Matthew Poremba (Gerrit)
 IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Michael LeBeane
+ */
+
+#ifndef SRC_MEM_VMA_HH
+#define SRC_MEM_VMA_HH
+
+#include 
+
+#include "arch/isa_traits.hh"
+#include "base/addr_range.hh"
+#include "base/mapped_file_buffer.hh"
+#include "base/types.hh"
+#include "debug/Vma.hh"
+#include "mem/se_translating_port_proxy.hh"
+
+class VMA
+{
+  public:
+VMA(Addr sa, Addr len, int fd, Addr off, std::string vma_name)
+: _addrRange(sa, sa + len), _origHostBuf(nullptr),
+  _hostBuf(nullptr), _hostBufLen(0), _vmaName(vma_name)
+{
+DPRINTF(Vma, "Creating vma start %p len %p end %p\n",
+sa, len, sa + len);
+
+if (fd != -1) {
+_origHostBuf = std::make_shared(fd, len,  
off);

+_hostBuf = _origHostBuf->buf;
+_hostBufLen = _origHostBuf->len;
+}
+
+sanityCheck();
+}
+
+/**
+ * Remap the virtual memory area starting at new_start.
+ */
+void remap(Addr new_start)
+{
+_addrRange = AddrRange(new_start, new_start + _addrRange.size());
+
+DPRINTF(Vma, "Remapping vma start %p end %p\n", _addrRange.start(),
+_addrRange.end());
+
+sanityCheck();
+}
+
+/**
+ * Check if the virtual memory area has an equivalent buffer on the
+ * host machine.
+ */
+bool hasHostBuf() const { return _origHostBuf != nullptr; }
+
+/**
+ * Copy memory from a buffer which resides on the host machine into a
+ * section of memory on the target.
+ */
+void fillMemPages(Addr start, Addr size,
+  SETranslatingPortProxy ) const;
+
+/**
+ * Returns true if desired range exists within this virtual memory area
+ * and does not include the start and end addresses.
+ */
+bool isStrictSuperset(const AddrRange ) const;
+
+/**
+ * Remove the address range to the right of slice_addr.
+ */
+void sliceRegionRight(Addr slice_addr);
+
+/**
+ * Remove the address range to the left of slice_addr.
+ */
+void sliceRegionLeft(Addr slice_addr);
+
+std::string getName() { return _vmaName; }
+
+/**
+ * Defer AddrRange related calls to the AddrRange.
+ */
+Addr size() { return _addrRange.size(); }
+Addr start() { return _addrRange.start(); }
+Addr end() { return _addrRange.end(); }
+
+bool mergesWith(const AddrRange& r) const
+{ return _addrRange.mergesWith(r); }
+
+bool intersects(const AddrRange& r) const
+{ return _addrRange.intersects(r); }
+
+bool isSubset(const AddrRange& r) const
+{ return _addrRange.isSubset(r); }
+
+bool contains(const Addr& a) const
+{ return _addrRange.contains(a); }
+
+  private:
+void sanityCheck();
+
+AddrRange _addrRange;
+
+/**
+ * The host file backing will be chopped up and reassigned as pages are
+ * mapped, remapped, and unmapped. In addition to the current host
+ * pointer and length, each virtual memory area will also keep a
+ * reference-counted handle to the original host memory. The last  
virtual

+ * memory area to die cleans up the host memory it handles.
+ */
+std::shared_ptr _origHostBuf;
+
+/**
+ * Host buffer ptr for this virtual memory area.
+ */
+char *_hostBuf;
+
+/**
+ * Length of host buffer for this virtual memory area.
+ */
+Addr _hostBufLen;
+
+/**
+ * Human-readable name associated with the virtual memory area.
+ * The name is useful for debugging and also exposing vma state through
+ * the psuedo file system (i.e. Linux's /proc/self/maps) to the
+ * application.
+ */
+std::string _vmaName;
+};
+
+#endif

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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add used attribute to pauth_helpers asserts

2020-02-13 Thread Matthew Poremba (Gerrit)
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25364 )



Change subject: arch-arm: Add used attribute to pauth_helpers asserts
..

arch-arm: Add used attribute to pauth_helpers asserts

Adding M5_VAR_USED attribute to variables in pauth_helpers so that
gem5.fast builds.

Change-Id: I45dd70ea2e921f7ce68ea52147abdd40da99f37e
---
M src/arch/arm/pauth_helpers.cc
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/arch/arm/pauth_helpers.cc b/src/arch/arm/pauth_helpers.cc
index c08e818..106f3c5 100644
--- a/src/arch/arm/pauth_helpers.cc
+++ b/src/arch/arm/pauth_helpers.cc
@@ -115,7 +115,7 @@
 Fault
 ArmISA::trapPACUse(ThreadContext *tc, ExceptionLevel target_el)
 {
-ExceptionLevel curr_el = currEL(tc);
+ExceptionLevel M5_VAR_USED curr_el = currEL(tc);
 assert(ArmSystem::haveEL(tc, target_el) &&
target_el != EL0 && (target_el >= curr_el));

@@ -149,7 +149,7 @@
 // 1xxx0... with TBI0=0 and TBI1=1 and 0xxx1 with TBI1=0 and  
TBI0=1


 if (upperAndLowerRange(tc, el)) {
-ExceptionLevel s1_el = s1TranslationRegime(tc, el);
+ExceptionLevel M5_VAR_USED s1_el = s1TranslationRegime(tc, el);
 assert (s1_el == EL1 || s1_el == EL2);
 if (s1TranslationRegime(tc, el) == EL1) {
 // EL1 translation regime registers

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[gem5-dev] Change in gem5/gem5[develop]: sim-se: Add special paths for MPI, libnuma, ROCm support

2020-02-13 Thread Matthew Poremba (Gerrit)
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25367 )



Change subject: sim-se: Add special paths for MPI, libnuma, ROCm support
..

sim-se: Add special paths for MPI, libnuma, ROCm support

Add new pseudo files which are read by various runtime libraries including
MPI, libnuma, and ROCm. New paths include /proc/self/maps, /dev/urandom,
and /sys/devices/system/cpu/online.

Change-Id: I00a82788cff9d6f4f16fc56230b18be9b76c4015
---
M src/kern/linux/linux.cc
M src/kern/linux/linux.hh
M src/sim/syscall_emul.hh
3 files changed, 60 insertions(+), 1 deletion(-)



diff --git a/src/kern/linux/linux.cc b/src/kern/linux/linux.cc
index e499776..c37daa1 100644
--- a/src/kern/linux/linux.cc
+++ b/src/kern/linux/linux.cc
@@ -35,8 +35,10 @@

 #include "cpu/base.hh"
 #include "debug/SyscallVerbose.hh"
+#include "sim/mem_state.hh"
 #include "sim/process.hh"
 #include "sim/system.hh"
+#include "sim/vma.hh"

 int
 Linux::openSpecialFile(std::string path, Process *process,
@@ -55,6 +57,15 @@
 } else if (path.compare(0, 11, "/etc/passwd") == 0) {
 data = Linux::etcPasswd(process, tc);
 matched = true;
+} else if (path.compare(0, 15, "/proc/self/maps") == 0) {
+data = Linux::procSelfMaps(process, tc);
+matched = true;
+} else if (path.compare(0, 30, "/sys/devices/system/cpu/online") == 0)  
{

+data = Linux::cpuOnline(process, tc);
+matched = true;
+} else if (path.compare(0, 12 ,"/dev/urandom") == 0) {
+data = Linux::devRandom(process, tc);
+matched = true;
 }

 if (matched) {
@@ -87,3 +98,47 @@
 return csprintf("gem5-user:x:1000:1000:gem5-user,,,:%s:/bin/bash\n",
 process->tgtCwd);
 }
+
+std::string
+Linux::procSelfMaps(Process *process, ThreadContext *tc)
+{
+std::stringstream file_content;
+auto memState = process->getMemState();
+
+for (auto vma : memState->vmaList()) {
+std::stringstream line;
+line << std::hex << vma.start() << "-";
+line << std::hex << vma.end() << " ";
+line << "r-xp  00:00 0 ";
+line << "[" << vma.getName() << "]" << std::endl;
+file_content << line.str();
+}
+
+return file_content.str();
+}
+
+std::string
+Linux::cpuOnline(Process *process, ThreadContext *tc)
+{
+return csprintf("0-%d\n",
+tc->getSystemPtr()->numContexts() - 1);
+}
+
+std::string
+Linux::devRandom(Process *process, ThreadContext *tc)
+{
+DPRINTFR(SyscallVerbose,
+ "%d: %s: open: generating urandom\n",
+ curTick(), tc->getCpuPtr()->name());
+std::stringstream line;
+int seed = 1234;
+srand(0);
+int max = 1E5;
+for (int i = 0; i  (rand()) /
+(static_cast  (RAND_MAX/seed));
+
+line << (char)rand_fl;
+}
+return line.str();
+}
diff --git a/src/kern/linux/linux.hh b/src/kern/linux/linux.hh
index 9325301..c855d57 100644
--- a/src/kern/linux/linux.hh
+++ b/src/kern/linux/linux.hh
@@ -236,7 +236,9 @@
ThreadContext *tc);
 static std::string procMeminfo(Process *process, ThreadContext *tc);
 static std::string etcPasswd(Process *process, ThreadContext *tc);
+static std::string procSelfMaps(Process *process, ThreadContext *tc);
 static std::string cpuOnline(Process *process, ThreadContext *tc);
+static std::string devRandom(Process *process, ThreadContext *tc);

 // For futex system call
 static const unsigned TGT_FUTEX_WAIT= 0;
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 53b86e2..1ce5351 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -911,7 +911,9 @@
 int sim_fd = -1;
 std::string used_path;
 std::vector special_paths =
-{ "/proc/meminfo/", "/system/", "/platform/", "/etc/passwd" };
+{ "/proc/meminfo/", "/system/", "/platform/", "/etc/passwd",
+  "/proc/self/maps", "/dev/urandom",
+  "/sys/devices/system/cpu/online" };
 for (auto entry : special_paths) {
 if (startswith(path, entry)) {
 sim_fd = OS::openSpecialFile(abs_path, p, tc);

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[gem5-dev] Change in gem5/gem5[master]: arch-x86: Don't free PTW state with inflight requests

2019-07-22 Thread Matthew Poremba (Gerrit)
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/19568 )


Change subject: arch-x86: Don't free PTW state with inflight requests
..

arch-x86: Don't free PTW state with inflight requests

If a page table walk is squashed, the walker state is being deleted
in the squash code. If there are in flight requests, the deleted
walker state values may be clobbered, leading to undefined behavior.
This adds a squashed boolean to the walker state which is set if a
walk is squashed while requests are still in flight. When packets
for the in flight request return, we check if the walk was squashed
and return that the walk is complete once the number of in flight
requests reaches zero. The walker state is then freed by the PTW.

Change-Id: I57a64b1548b83a8a9e8441fc9d6f33e9842df2b3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19568
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/x86/pagetable_walker.cc
M src/arch/x86/pagetable_walker.hh
2 files changed, 29 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/x86/pagetable_walker.cc  
b/src/arch/x86/pagetable_walker.cc

index 932eb8e..86f140f 100644
--- a/src/arch/x86/pagetable_walker.cc
+++ b/src/arch/x86/pagetable_walker.cc
@@ -205,8 +205,14 @@
 std::make_shared("Squashed Inst"),
 currState->req, currState->tc, currState->mode);

-// delete the current request
-delete currState;
+// delete the current request if there are no inflight packets.
+// if there is something in flight, delete when the packets are
+// received and inflight is zero.
+if (currState->numInflight() == 0) {
+delete currState;
+} else {
+currState->squash();
+}

 // check the next translation request, if it exists
 if (currStates.size())
@@ -597,6 +603,11 @@
 assert(inflight);
 assert(state == Waiting);
 inflight--;
+if (squashed) {
+// if were were squashed, return true once inflight is zero and
+// this WalkerState will be freed there.
+return (inflight == 0);
+}
 if (pkt->isRead()) {
 // should not have a pending read it we also had one outstanding
 assert(!read);
@@ -678,6 +689,12 @@
 }
 }

+unsigned
+Walker::WalkerState::numInflight() const
+{
+return inflight;
+}
+
 bool
 Walker::WalkerState::isRetrying()
 {
@@ -697,6 +714,12 @@
 }

 void
+Walker::WalkerState::squash()
+{
+squashed = true;
+}
+
+void
 Walker::WalkerState::retry()
 {
 retrying = false;
diff --git a/src/arch/x86/pagetable_walker.hh  
b/src/arch/x86/pagetable_walker.hh

index 88b8147..73e8924 100644
--- a/src/arch/x86/pagetable_walker.hh
+++ b/src/arch/x86/pagetable_walker.hh
@@ -111,6 +111,7 @@
 bool timing;
 bool retrying;
 bool started;
+bool squashed;
   public:
 WalkerState(Walker * _walker, BaseTLB::Translation  
*_translation,
 const RequestPtr &_req, bool _isFunctional =  
false) :

@@ -118,7 +119,7 @@
 nextState(Ready), inflight(0),
 translation(_translation),
 functional(_isFunctional), timing(false),
-retrying(false), started(false)
+retrying(false), started(false), squashed(false)
 {
 }
 void initState(ThreadContext * _tc, BaseTLB::Mode _mode,
@@ -126,10 +127,12 @@
 Fault startWalk();
 Fault startFunctional(Addr , unsigned );
 bool recvPacket(PacketPtr pkt);
+unsigned numInflight() const;
 bool isRetrying();
 bool wasStarted();
 bool isTiming();
 void retry();
+void squash();
 std::string name() const {return walker->name();}

   private:

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I57a64b1548b83a8a9e8441fc9d6f33e9842df2b3
Gerrit-Change-Number: 19568
Gerrit-PatchSet: 2
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: arch-x86: Don't free PTW state with inflight requests

2019-07-18 Thread Matthew Poremba (Gerrit)
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/19568 )



Change subject: arch-x86: Don't free PTW state with inflight requests
..

arch-x86: Don't free PTW state with inflight requests

If a page table walk is squashed, the walker state is being deleted
in the squash code. If there are in flight requests, the deleted
walker state values may be clobbered, leading to undefined behavior.
This adds a squashed boolean to the walker state which is set if a
walk is squashed while requests are still in flight. When packets
for the in flight request return, we check if the walk was squashed
and return that the walk is complete once the number of in flight
requests reaches zero. The walker state is then freed by the PTW.

Change-Id: I57a64b1548b83a8a9e8441fc9d6f33e9842df2b3
---
M src/arch/x86/pagetable_walker.cc
M src/arch/x86/pagetable_walker.hh
2 files changed, 29 insertions(+), 3 deletions(-)



diff --git a/src/arch/x86/pagetable_walker.cc  
b/src/arch/x86/pagetable_walker.cc

index 932eb8e..86f140f 100644
--- a/src/arch/x86/pagetable_walker.cc
+++ b/src/arch/x86/pagetable_walker.cc
@@ -205,8 +205,14 @@
 std::make_shared("Squashed Inst"),
 currState->req, currState->tc, currState->mode);

-// delete the current request
-delete currState;
+// delete the current request if there are no inflight packets.
+// if there is something in flight, delete when the packets are
+// received and inflight is zero.
+if (currState->numInflight() == 0) {
+delete currState;
+} else {
+currState->squash();
+}

 // check the next translation request, if it exists
 if (currStates.size())
@@ -597,6 +603,11 @@
 assert(inflight);
 assert(state == Waiting);
 inflight--;
+if (squashed) {
+// if were were squashed, return true once inflight is zero and
+// this WalkerState will be freed there.
+return (inflight == 0);
+}
 if (pkt->isRead()) {
 // should not have a pending read it we also had one outstanding
 assert(!read);
@@ -678,6 +689,12 @@
 }
 }

+unsigned
+Walker::WalkerState::numInflight() const
+{
+return inflight;
+}
+
 bool
 Walker::WalkerState::isRetrying()
 {
@@ -697,6 +714,12 @@
 }

 void
+Walker::WalkerState::squash()
+{
+squashed = true;
+}
+
+void
 Walker::WalkerState::retry()
 {
 retrying = false;
diff --git a/src/arch/x86/pagetable_walker.hh  
b/src/arch/x86/pagetable_walker.hh

index 88b8147..73e8924 100644
--- a/src/arch/x86/pagetable_walker.hh
+++ b/src/arch/x86/pagetable_walker.hh
@@ -111,6 +111,7 @@
 bool timing;
 bool retrying;
 bool started;
+bool squashed;
   public:
 WalkerState(Walker * _walker, BaseTLB::Translation  
*_translation,
 const RequestPtr &_req, bool _isFunctional =  
false) :

@@ -118,7 +119,7 @@
 nextState(Ready), inflight(0),
 translation(_translation),
 functional(_isFunctional), timing(false),
-retrying(false), started(false)
+retrying(false), started(false), squashed(false)
 {
 }
 void initState(ThreadContext * _tc, BaseTLB::Mode _mode,
@@ -126,10 +127,12 @@
 Fault startWalk();
 Fault startFunctional(Addr , unsigned );
 bool recvPacket(PacketPtr pkt);
+unsigned numInflight() const;
 bool isRetrying();
 bool wasStarted();
 bool isTiming();
 void retry();
+void squash();
 std::string name() const {return walker->name();}

   private:

--
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[gem5-dev] Change in gem5/gem5[master]: mem: Option to toggle DRAM low-power states

2019-06-06 Thread Matthew Poremba (Gerrit)
 if (isQueueEmpty() && outstandingEvents == 0) {
+if (isQueueEmpty() && outstandingEvents == 0 &&
+memory.enableDRAMPowerdown) {
 // should still be in ACT state since bank still open
 assert(pwrState == PWR_ACT);

@@ -2057,7 +2058,7 @@

 // Force PRE power-down if there are no outstanding commands
 // in Q after refresh.
-} else if (isQueueEmpty()) {
+} else if (isQueueEmpty() && memory.enableDRAMPowerdown) {
 // still have refresh event outstanding but there should
 // be no other events outstanding
 assert(outstandingEvents == 1);
@@ -2328,7 +2329,8 @@
 // will issue refresh immediately upon entry
 if (pwrStatePostRefresh == PWR_PRE_PDN && isQueueEmpty() &&
(memory.drainState() != DrainState::Draining) &&
-   (memory.drainState() != DrainState::Drained)) {
+   (memory.drainState() != DrainState::Drained) &&
+   memory.enableDRAMPowerdown) {
 DPRINTF(DRAMState, "Rank %d bypassing refresh and  
transitioning "

 "to self refresh at %11u tick\n", rank, curTick());
 powerDownSleep(PWR_SREF, curTick());
diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh
index 54826e0..7de0872 100644
--- a/src/mem/dram_ctrl.hh
+++ b/src/mem/dram_ctrl.hh
@@ -1140,6 +1140,9 @@
 /** The time when stats were last reset used to calculate average  
power */

 Tick lastStatsResetTick;

+/** Enable or disable DRAM powerdown states. */
+bool enableDRAMPowerdown;
+
 /**
  * Upstream caches need this packet until true is returned, so
  * hold it for deletion until a subsequent call

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Gerrit-Reviewer: Andreas Sandberg 
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Gerrit-Reviewer: Matthew Poremba 
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[gem5-dev] Change in gem5/gem5[master]: mem: Option to toggle DRAM low-power states

2019-06-06 Thread Matthew Poremba (Gerrit)
Hello Wendy Elsasser, kokoro, Éder F. Zulian, Matt Sinclair, Curtis Dunham,  
Anthony Gutierrez, Xianwei Zhang, Matthias Jung, Nikos Nikoleris,


I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/18548

to look at the new patch set (#2).

Change subject: mem: Option to toggle DRAM low-power states
..

mem: Option to toggle DRAM low-power states

Adding an option to enable DRAM low-power states. The low power
states can have a significant impact on application performance
(sim_ticks) on the order of 2-3x, especially for compute-gpu apps.
The options allows for it to easily be enabled/disabled to compare
performance numbers. The option is disabled by default.

Change-Id: Ib9bddbb792a1a6a4afb5339003472ff8f00a5859
---
M configs/common/MemConfig.py
M configs/common/Options.py
M configs/ruby/Ruby.py
M src/mem/DRAMCtrl.py
M src/mem/dram_ctrl.cc
M src/mem/dram_ctrl.hh
6 files changed, 26 insertions(+), 5 deletions(-)


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Gerrit-Change-Id: Ib9bddbb792a1a6a4afb5339003472ff8f00a5859
Gerrit-Change-Number: 18548
Gerrit-PatchSet: 2
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Curtis Dunham 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: Matthias Jung 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: Wendy Elsasser 
Gerrit-Reviewer: Xianwei Zhang 
Gerrit-Reviewer: kokoro 
Gerrit-Reviewer: Éder F. Zulian 
Gerrit-CC: Andreas Sandberg 
Gerrit-MessageType: newpatchset
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[gem5-dev] Change in gem5/gem5[master]: mem: Option to toggle DRAM low-power states

2019-05-01 Thread Matthew Poremba (Gerrit)
"to self refresh at %11u tick\n", rank, curTick());
 powerDownSleep(PWR_SREF, curTick());
diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh
index 54826e0..8cbb2ba 100644
--- a/src/mem/dram_ctrl.hh
+++ b/src/mem/dram_ctrl.hh
@@ -1140,6 +1140,9 @@
 /** The time when stats were last reset used to calculate average  
power */

 Tick lastStatsResetTick;

+/** Enable or disable DRAM powerdown states. */
+bool disableDRAMPowerdown;
+
 /**
  * Upstream caches need this packet until true is returned, so
  * hold it for deletion until a subsequent call

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[gem5-dev] Change in public/gem5[master]: mem: Add unified queue to DRAMCtrl

2018-02-14 Thread Matthew Poremba (Gerrit)
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/8302



Change subject: mem: Add unified queue to DRAMCtrl
..

mem: Add unified queue to DRAMCtrl

Add optional unified queue to the DRAMCtrl to serve as a front end queue
for flow control. This prevents needing individual flot control for both
read and write queues by exposing only one queue at the slave side. This
makes flow control more generic and simplistic.

Change-Id: I1fde4c8da2a51688979d148d9124fb0e22be5c5b
---
M src/mem/DRAMCtrl.py
M src/mem/dram_ctrl.cc
M src/mem/dram_ctrl.hh
3 files changed, 168 insertions(+), 2 deletions(-)



diff --git a/src/mem/DRAMCtrl.py b/src/mem/DRAMCtrl.py
index 3145751..92d25cc 100644
--- a/src/mem/DRAMCtrl.py
+++ b/src/mem/DRAMCtrl.py
@@ -76,6 +76,14 @@
 # bus in front of the controller for multiple ports
 port = SlavePort("Slave port")

+# the unified queue holds all incoming memory requests to help with
+# flow control and is searched by the memory controller when it's
+# read or write queues have free space available
+use_unified_buffer = Param.Bool(False, "Should we use a unified  
buffer?")

+unified_buffer_size = Param.Unsigned(100, "Number of total requests")
+unified_search_depth = Param.Unsigned(16, "Maximum number of entries "
+ "to search when looking for new requests")
+
 # the basic configuration of the controller architecture, note
 # that each entry corresponds to a burst for the specific DRAM
 # configuration (e.g. x32 with burst length 8 is 32 bytes) and not
diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc
index 62de18d..b1fff15 100644
--- a/src/mem/dram_ctrl.cc
+++ b/src/mem/dram_ctrl.cc
@@ -78,6 +78,9 @@
 bankGroupsPerRank(p->bank_groups_per_rank),
 bankGroupArch(p->bank_groups_per_rank > 0),
 banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0),
+useUnifiedBuffer(p->use_unified_buffer),
+unifiedBufferSize(p->unified_buffer_size),
+unifiedSearchDepth(p->unified_search_depth),
 readBufferSize(p->read_buffer_size),
 writeBufferSize(p->write_buffer_size),
 writeHighThreshold(writeBufferSize * p->write_high_thresh_perc /  
100.0),

@@ -271,6 +274,67 @@
 return latency;
 }

+void
+DRAMCtrl::processUnifiedQueue()
+{
+// Fast path if there is nothing to do
+if (unifiedQueue.empty()) {
+return;
+}
+
+// See how many reads and writes we can issue
+int read_queue_space = readBufferSize
+ - (readQueue.size() + respQueue.size());
+int write_queue_space = writeBufferSize - writeQueue.size();
+int search_count = 0;
+
+for (auto iter = unifiedQueue.begin();
+ iter != unifiedQueue.end(); ++iter) {
+// Emulate a maximum number of requests we can search per cycle
+if (++search_count > unifiedSearchDepth) {
+break;
+}
+
+PacketPtr pkt = (*iter);
+unsigned size = pkt->getSize();
+unsigned offset = pkt->getAddr() & (burstSize - 1);
+unsigned int dram_pkt_count = divCeil(offset + size, burstSize);
+
+// Look for as many requests up to the maximum search depth. Note
+// that write merging and read serviings by write queue are not
+// handled here and left to the split read and write queues.
+if (pkt->isRead() && read_queue_space >= dram_pkt_count) {
+DPRINTF(DRAM, "Read addr %lld moved from unified queue\n",
+pkt->getAddr());
+inUnifiedQueue.erase(burstAlign(pkt->getAddr()));
+unifiedPending.insert(burstAlign(pkt->getAddr()));
+iter = unifiedQueue.erase(iter);
+read_queue_space -= dram_pkt_count;
+issueTimingReq(pkt);
+} else if (pkt->isWrite() && write_queue_space >= dram_pkt_count) {
+DPRINTF(DRAM, "Write addr %lld moved from unified queue\n",
+pkt->getAddr());
+inUnifiedQueue.erase(burstAlign(pkt->getAddr()));
+unifiedPending.insert(burstAlign(pkt->getAddr()));
+iter = unifiedQueue.erase(iter);
+write_queue_space -= dram_pkt_count;
+issueTimingReq(pkt);
+}
+
+// make sure we don't enqueue too many requests or invalid types
+DPRINTF(DRAM, "Unified queue occupancy is %d of %d\n",
+unifiedQueueOccupancy(), unifiedBufferSize);
+assert(unifiedQueueOccupancy() <= unifiedBufferSize);
+assert(pkt->isRead() || pkt->isWrite());
+}
+}
+
+int
+DRAMCtrl::unifiedQueueOccupancy()
+{
+return unifiedQueue.size() + unifiedPending.size();
+}
+
 bool
 DRAMCtrl::readQueueFull(unsigned int neededEntries) const
 {
@@ -594,7 +658,51 @@
 }
 prevArrival = curTick();

+// If we are using a unified buffer, place requests in it and
+// check if space is 

[gem5-dev] Change in public/gem5[master]: ruby: Replace SLICC queueMemory calls with enqueue

2018-02-14 Thread Matthew Poremba (Gerrit)
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/8301



Change subject: ruby: Replace SLICC queueMemory calls with enqueue
..

ruby: Replace SLICC queueMemory calls with enqueue

Calls to queueMemoryRead and queueMemoryWrite do not consider the size
of the queue between ruby directories and DRAMCtrl which causes infinite
buffering in the queued port between the two. This adds a MessageBuffer
in between which uses enqueues in SLICC and is therefore size checked
before any SLICC transaction pushing to the buffer can occur, removing
the infinite buffering between the two.

Change-Id: I655b157be29e71abf06c7a6a8c1ef9c738e1ca54
---
M configs/ruby/GPU_RfO.py
M configs/ruby/GPU_VIPER.py
M configs/ruby/GPU_VIPER_Baseline.py
M configs/ruby/GPU_VIPER_Region.py
M configs/ruby/MESI_Two_Level.py
M configs/ruby/MI_example.py
M configs/ruby/MOESI_CMP_directory.py
M configs/ruby/MOESI_CMP_token.py
M configs/ruby/MOESI_hammer.py
M src/mem/protocol/MESI_Two_Level-dir.sm
M src/mem/protocol/MI_example-dir.sm
M src/mem/protocol/MOESI_AMD_Base-Region-dir.sm
M src/mem/protocol/MOESI_AMD_Base-dir.sm
M src/mem/protocol/MOESI_AMD_Base-probeFilter.sm
M src/mem/protocol/MOESI_CMP_directory-dir.sm
M src/mem/protocol/MOESI_CMP_token-dir.sm
M src/mem/protocol/MOESI_hammer-dir.sm
M src/mem/protocol/RubySlicc_Defines.sm
M src/mem/protocol/RubySlicc_MemControl.sm
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/slicc/symbols/StateMachine.py
22 files changed, 408 insertions(+), 160 deletions(-)



diff --git a/configs/ruby/GPU_RfO.py b/configs/ruby/GPU_RfO.py
index f900a48..728bddb 100644
--- a/configs/ruby/GPU_RfO.py
+++ b/configs/ruby/GPU_RfO.py
@@ -504,6 +504,7 @@

 dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
 dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True)
+dir_cntrl.requestToMemory = MessageBuffer()
 dir_cntrl.responseFromMemory = MessageBuffer()

 exec("system.dir_cntrl%d = dir_cntrl" % i)
diff --git a/configs/ruby/GPU_VIPER.py b/configs/ruby/GPU_VIPER.py
index 36ef9f5..74d4b50 100644
--- a/configs/ruby/GPU_VIPER.py
+++ b/configs/ruby/GPU_VIPER.py
@@ -458,6 +458,7 @@

 dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
 dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True)
+dir_cntrl.requestToMemory = MessageBuffer()
 dir_cntrl.responseFromMemory = MessageBuffer()

 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
diff --git a/configs/ruby/GPU_VIPER_Baseline.py  
b/configs/ruby/GPU_VIPER_Baseline.py

index df3c60a..a13a482 100644
--- a/configs/ruby/GPU_VIPER_Baseline.py
+++ b/configs/ruby/GPU_VIPER_Baseline.py
@@ -436,6 +436,7 @@

 dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
 dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True)
+dir_cntrl.requestToMemory = MessageBuffer()
 dir_cntrl.responseFromMemory = MessageBuffer()

 exec("system.dir_cntrl%d = dir_cntrl" % i)
diff --git a/configs/ruby/GPU_VIPER_Region.py  
b/configs/ruby/GPU_VIPER_Region.py

index 239624d..96316a6 100644
--- a/configs/ruby/GPU_VIPER_Region.py
+++ b/configs/ruby/GPU_VIPER_Region.py
@@ -715,6 +715,7 @@

 dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
 dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True)
+dir_cntrl.requestToMemory = MessageBuffer()
 dir_cntrl.responseFromMemory = MessageBuffer()

 exec("system.dir_cntrl%d = dir_cntrl" % i)
diff --git a/configs/ruby/MESI_Two_Level.py b/configs/ruby/MESI_Two_Level.py
index 844c62a..921858b 100644
--- a/configs/ruby/MESI_Two_Level.py
+++ b/configs/ruby/MESI_Two_Level.py
@@ -183,6 +183,7 @@
 dir_cntrl.responseToDir.slave = ruby_system.network.master
 dir_cntrl.responseFromDir = MessageBuffer()
 dir_cntrl.responseFromDir.master = ruby_system.network.slave
+dir_cntrl.requestToMemory = MessageBuffer()
 dir_cntrl.responseFromMemory = MessageBuffer()


diff --git a/configs/ruby/MI_example.py b/configs/ruby/MI_example.py
index eb881e5..ed0eedc 100644
--- a/configs/ruby/MI_example.py
+++ b/configs/ruby/MI_example.py
@@ -140,6 +140,7 @@
 dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave
 dir_cntrl.forwardFromDir = MessageBuffer()
 dir_cntrl.forwardFromDir.master = ruby_system.network.slave
+dir_cntrl.requestToMemory = MessageBuffer()
 dir_cntrl.responseFromMemory = MessageBuffer()


diff --git a/configs/ruby/MOESI_CMP_directory.py  
b/configs/ruby/MOESI_CMP_directory.py

index cbb061d..ec66d06 100644
--- a/configs/ruby/MOESI_CMP_directory.py
+++ b/configs/ruby/MOESI_CMP_directory.py
@@ -177,6 +177,7 @@
 dir_cntrl.responseFromDir.master = ruby_system.network.slave
 dir_cntrl.forwardFromDir = MessageBuffer()
 dir_cntrl.forwardFromDir.master = 

[gem5-dev] Change in public/gem5[master]: ruby: Refactor GPU coalescer

2018-02-14 Thread Matthew Poremba (Gerrit)

Hello Jason Lowe-Power,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/4180

to look at the new patch set (#2).

Change subject: ruby: Refactor GPU coalescer
..

ruby: Refactor GPU coalescer

Remove the read/write tables and coalescing table and introduce a two
levels of tables for uncoalesced and coalesced packets. Tokens are
granted to GPU instructions to place in uncoalesced table. If tokens
are available, the operation always succeeds such that the 'Aliased'
status is never returned. Coalesced accesses are placed in the
coalesced table while requests are outstanding. Requests to the same
address are added as targets to the table similar to how MSHRs
operate.

Change-Id: I37654091f18d137a40e7fdb0694a4ec4c77b1c1d
---
M configs/ruby/GPU_RfO.py
M configs/ruby/GPU_VIPER.py
M configs/ruby/GPU_VIPER_Baseline.py
M configs/ruby/GPU_VIPER_Region.py
M src/gpu-compute/GPU.py
M src/gpu-compute/compute_unit.cc
M src/gpu-compute/compute_unit.hh
M src/gpu-compute/global_memory_pipeline.cc
M src/gpu-compute/global_memory_pipeline.hh
M src/gpu-compute/wavefront.cc
M src/mem/SConscript
M src/mem/port.hh
M src/mem/ruby/system/GPUCoalescer.cc
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/ruby/system/GPUCoalescer.py
M src/mem/ruby/system/RubyPort.cc
M src/mem/ruby/system/RubyPort.hh
M src/mem/ruby/system/VIPERCoalescer.cc
A src/mem/token_port.cc
A src/mem/token_port.hh
20 files changed, 798 insertions(+), 654 deletions(-)


--
To view, visit https://gem5-review.googlesource.com/4180
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I37654091f18d137a40e7fdb0694a4ec4c77b1c1d
Gerrit-Change-Number: 4180
Gerrit-PatchSet: 2
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-CC: Matt Poremba 
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[gem5-dev] Change in public/gem5[master]: mem: Use token ports on DRAMCtrl side of system

2018-02-14 Thread Matthew Poremba (Gerrit)
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/8303



Change subject: mem: Use token ports on DRAMCtrl side of system
..

mem: Use token ports on DRAMCtrl side of system

When interfacing with Ruby, MessageBuffers between AbstractController
and DRAMCtrl do resource checking to ensure finite buffering. Currently
checking of resources is not possible with queued ports, leading to
hidden infinite buffering around Ruby directories and memory. This
reuses the token port class designed for the GPUCoalescer to provide
resource checking at the directory. Currently this support only resource
checking for request from directory to memory.

Change-Id: I3423b819ea4e2d6c33d3bdd11f20b3d7cd7e7e3e
---
M src/mem/dram_ctrl.cc
M src/mem/dram_ctrl.hh
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/ruby/slicc_interface/AbstractController.hh
4 files changed, 78 insertions(+), 41 deletions(-)



diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc
index b1fff15..6df9350 100644
--- a/src/mem/dram_ctrl.cc
+++ b/src/mem/dram_ctrl.cc
@@ -66,6 +66,7 @@
 busStateNext(READ),
 nextReqEvent([this]{ processNextReqEvent(); }, name()),
 respondEvent([this]{ processRespondEvent(); }, name()),
+backendEvent([this]{ processBackendEvent(); }, name()),
 deviceSize(p->device_size),
 deviceBusWidth(p->device_bus_width), burstLength(p->burst_length),
 deviceRowBufferSize(p->device_rowbuffer_size),
@@ -228,6 +229,10 @@
 assert(columnsPerStripe <= columnsPerRowBuffer);
 }
 }
+
+// Setup the initial token count. Use the size of the unified buffer
+// as the maximum number of requests the master can send.
+port.sendTokens(unifiedBufferSize);
 }

 void
@@ -282,12 +287,7 @@
 return;
 }

-// See how many reads and writes we can issue
-int read_queue_space = readBufferSize
- - (readQueue.size() + respQueue.size());
-int write_queue_space = writeBufferSize - writeQueue.size();
 int search_count = 0;
-
 for (auto iter = unifiedQueue.begin();
  iter != unifiedQueue.end(); ++iter) {
 // Emulate a maximum number of requests we can search per cycle
@@ -303,21 +303,19 @@
 // Look for as many requests up to the maximum search depth. Note
 // that write merging and read serviings by write queue are not
 // handled here and left to the split read and write queues.
-if (pkt->isRead() && read_queue_space >= dram_pkt_count) {
+if (pkt->isRead() && !readQueueFull(dram_pkt_count)) {
 DPRINTF(DRAM, "Read addr %lld moved from unified queue\n",
 pkt->getAddr());
 inUnifiedQueue.erase(burstAlign(pkt->getAddr()));
 unifiedPending.insert(burstAlign(pkt->getAddr()));
 iter = unifiedQueue.erase(iter);
-read_queue_space -= dram_pkt_count;
 issueTimingReq(pkt);
-} else if (pkt->isWrite() && write_queue_space >= dram_pkt_count) {
+} else if (pkt->isWrite() && !writeQueueFull(dram_pkt_count)) {
 DPRINTF(DRAM, "Write addr %lld moved from unified queue\n",
 pkt->getAddr());
 inUnifiedQueue.erase(burstAlign(pkt->getAddr()));
 unifiedPending.insert(burstAlign(pkt->getAddr()));
 iter = unifiedQueue.erase(iter);
-write_queue_space -= dram_pkt_count;
 issueTimingReq(pkt);
 }

@@ -996,6 +994,9 @@
 unifiedPending.erase(burstAlign(pkt->getAddr()));
 }

+// Done with a request. Send back a token.
+port.sendTokens(1);
+
 bool needsResponse = pkt->needsResponse();
 // do the actual memory access which also turns the packet into a
 // response
@@ -1016,7 +1017,17 @@

 // queue the packet in the response queue to be sent out after
 // the static latency has passed
-port.schedTimingResp(pkt, response_time, true);
+if (response_time == curTick()) {
+port.sendTimingResp(pkt);
+} else {
+backendMap[response_time].push_back(pkt);
+
+if (!backendEvent.scheduled()) {
+schedule(backendEvent, response_time);
+} else if (response_time < backendEvent.when()) {
+reschedule(backendEvent, response_time);
+}
+}
 } else {
 // @todo the packet is going to be deleted, and the DRAMPacket
 // is still having a pointer to it
@@ -1029,6 +1040,25 @@
 }

 void
+DRAMCtrl::processBackendEvent()
+{
+DPRINTF(DRAM, "Processing backend event\n");
+
+std::deque& backendQueue = backendMap.begin()->second;
+PacketPtr pkt = backendQueue.front();
+backendQueue.pop_front();
+if (backendQueue.empty()) {
+backendMap.erase(backendMap.begin());
+}
+
+port.sendTimingResp(pkt);
+
+if 

[gem5-dev] Change in public/gem5[master]: ruby: Refactor GPU coalescer

2017-07-20 Thread Matthew Poremba (Gerrit)
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/4180



Change subject: ruby: Refactor GPU coalescer
..

ruby: Refactor GPU coalescer

Remove the read/write tables and coalescing table and introduce a two
levels of tables for uncoalesced and coalesced packets. Tokens are
granted to GPU instructions to place in uncoalesced table. If tokens
are available, the operation always succeeds such that the 'Aliased'
status is never returned. Coalesced accesses are placed in the
coalesced table while requests are outstanding. Requests to the same
address are added as targets to the table similar to how MSHRs
operate.

Change-Id: I37654091f18d137a40e7fdb0694a4ec4c77b1c1d
---
M configs/ruby/GPU_RfO.py
M configs/ruby/GPU_VIPER.py
M configs/ruby/GPU_VIPER_Baseline.py
M configs/ruby/GPU_VIPER_Region.py
M src/gpu-compute/GPU.py
M src/gpu-compute/compute_unit.cc
M src/gpu-compute/compute_unit.hh
M src/gpu-compute/global_memory_pipeline.cc
M src/gpu-compute/global_memory_pipeline.hh
M src/gpu-compute/wavefront.cc
M src/mem/SConscript
M src/mem/port.hh
M src/mem/ruby/system/GPUCoalescer.cc
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/ruby/system/GPUCoalescer.py
M src/mem/ruby/system/RubyPort.cc
M src/mem/ruby/system/RubyPort.hh
M src/mem/ruby/system/VIPERCoalescer.cc
A src/mem/token_port.cc
A src/mem/token_port.hh
20 files changed, 799 insertions(+), 654 deletions(-)



diff --git a/configs/ruby/GPU_RfO.py b/configs/ruby/GPU_RfO.py
index 71e21d9..a52ff3d 100644
--- a/configs/ruby/GPU_RfO.py
+++ b/configs/ruby/GPU_RfO.py
@@ -170,6 +170,8 @@
 self.coalescer.max_outstanding_requests = options.simds_per_cu * \
   options.wfs_per_simd * \
   options.wf_size
+self.coalescer.max_coalesces_per_cycle = \
+options.max_coalesces_per_cycle

 self.sequencer = RubySequencer()
 self.sequencer.version = self.seqCount()
@@ -436,6 +438,8 @@
   help="tcp size")
 parser.add_option("--tcc-dir-factor", type='int', default=4,
   help="TCCdir size = factor *(TCPs + TCC)")
+parser.add_option("--max-coalesces-per-cycle", type="int", default=1,
+  help="Maximum insts that may coalesce in a cycle");

 def create_system(options, full_system, system, dma_devices, ruby_system):
 if buildEnv['PROTOCOL'] != 'GPU_RfO':
diff --git a/configs/ruby/GPU_VIPER.py b/configs/ruby/GPU_VIPER.py
index e4ba180..36ef9f5 100644
--- a/configs/ruby/GPU_VIPER.py
+++ b/configs/ruby/GPU_VIPER.py
@@ -154,6 +154,8 @@
 self.coalescer.ruby_system = ruby_system
 self.coalescer.support_inst_reqs = False
 self.coalescer.is_cpu_sequencer = False
+self.coalescer.max_coalesces_per_cycle = \
+options.max_coalesces_per_cycle

 self.sequencer = RubySequencer()
 self.sequencer.version = self.seqCount()
@@ -387,6 +389,9 @@
   help = "tcp size")
 parser.add_option("--tcp-assoc", type = 'int', default = 16,
   help = "tcp assoc")
+parser.add_option("--max-coalesces-per-cycle", type="int", default=1,
+  help="Maximum insts that may coalesce in a cycle");
+
 parser.add_option("--noL1", action = "store_true", default = False,
   help = "bypassL1")

diff --git a/configs/ruby/GPU_VIPER_Baseline.py  
b/configs/ruby/GPU_VIPER_Baseline.py

index 978d4cc..df3c60a 100644
--- a/configs/ruby/GPU_VIPER_Baseline.py
+++ b/configs/ruby/GPU_VIPER_Baseline.py
@@ -154,6 +154,8 @@
 self.coalescer.ruby_system = ruby_system
 self.coalescer.support_inst_reqs = False
 self.coalescer.is_cpu_sequencer = False
+self.coalescer.max_coalesces_per_cycle = \
+options.max_coalesces_per_cycle

 self.sequencer = RubySequencer()
 self.sequencer.version = self.seqCount()
@@ -365,6 +367,9 @@
   help = "tcc assoc")
 parser.add_option("--tcp-size", type = 'string', default = '16kB',
   help = "tcp size")
+parser.add_option("--max-coalesces-per-cycle", type="int", default=1,
+  help="Maximum insts that may coalesce in a cycle");
+
 parser.add_option("--sampler-sets", type = "int", default = 1024)
 parser.add_option("--sampler-assoc", type = "int", default = 16)
 parser.add_option("--sampler-counter", type = "int", default = 512)
diff --git a/configs/ruby/GPU_VIPER_Region.py  
b/configs/ruby/GPU_VIPER_Region.py

index 8b59c04..239624d 100644
--- a/configs/ruby/GPU_VIPER_Region.py
+++ b/configs/ruby/GPU_VIPER_Region.py
@@ -155,6 +155,8 @@
 self.coalescer.ruby_system = ruby_system
 self.coalescer.support_inst_reqs = False
 self.coalescer.is_cpu_sequencer = False
+