[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: base,sim: allow m5writeFile with stdout/stderr.

2020-05-08 Thread Nils Asmussen (Gerrit) via gem5-dev
Nils Asmussen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28727 )


Change subject: base,sim: allow m5writeFile with stdout/stderr.
..

base,sim: allow m5writeFile with stdout/stderr.

If m5writeFile opens stdout/stderr, no file is registered in
OutputDirectory and thus we don't want to search for it on close.

In order to write multiple times to stdout/stderr in a reasonable way,
we also want to prevent seeking. Thus, don't seek if the offset is 0, in
which case this would be a noop anyway (we just opened the file without
append).

Finally, it is helpful for debugging if the stream is flushed on every
write.

Change-Id: I102f82dcd2c63420b6f3fe55d67f03c62349e69d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28727
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/base/output.cc
M src/sim/pseudo_inst.cc
2 files changed, 11 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/output.cc b/src/base/output.cc
index ec94a13..47b8aa7 100644
--- a/src/base/output.cc
+++ b/src/base/output.cc
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2015 ARM Limited
+ * Copyright (c) 2020 Barkhausen Institut
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -142,6 +143,11 @@
 void
 OutputDirectory::close(OutputStream *file)
 {
+if (file ==  || file == ) {
+file->stream()->flush();
+return;
+}
+
 auto i = files.find(file->name());
 if (i == files.end())
 fatal("Attempted to close an unregistred file stream");
diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index c65fdc0..b11a5a4 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2010-2012, 2015, 2017 ARM Limited
+ * Copyright (c) 2020 Barkhausen Institut
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -425,8 +426,10 @@
 if (!os)
 panic("could not open file %s\n", filename);

-// seek to offset
-os->seekp(offset);
+if (offset != 0) {
+// seek to offset
+os->seekp(offset);
+}

 // copy out data and write to file
 char *buf = new char[len];

--
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Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v20.0.0.0
Gerrit-Change-Id: I102f82dcd2c63420b6f3fe55d67f03c62349e69d
Gerrit-Change-Number: 28727
Gerrit-PatchSet: 2
Gerrit-Owner: Nils Asmussen 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nils Asmussen 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: arch-riscv,tests: merged changes from RISCV-test upstream repo.

2020-05-06 Thread Nils Asmussen (Gerrit) via gem5-dev
Nils Asmussen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28729 )



Change subject: arch-riscv,tests: merged changes from RISCV-test upstream  
repo.

..

arch-riscv,tests: merged changes from RISCV-test upstream repo.

Change-Id: Ied7c34fedc99657e667bddaf3f3521e5a8f96a6e
---
M tests/test-progs/asmtest/src/riscv/env/encoding.h
M tests/test-progs/asmtest/src/riscv/env/p/riscv_test.h
M tests/test-progs/asmtest/src/riscv/env/v/entry.S
M tests/test-progs/asmtest/src/riscv/env/v/riscv_test.h
M tests/test-progs/asmtest/src/riscv/env/v/vm.c
M tests/test-progs/asmtest/src/riscv/isa/macros/scalar/test_macros.h
M tests/test-progs/asmtest/src/riscv/isa/rv64mi/access.S
M tests/test-progs/asmtest/src/riscv/isa/rv64mi/breakpoint.S
M tests/test-progs/asmtest/src/riscv/isa/rv64mi/illegal.S
M tests/test-progs/asmtest/src/riscv/isa/rv64si/Makefrag
M tests/test-progs/asmtest/src/riscv/isa/rv64si/csr.S
M tests/test-progs/asmtest/src/riscv/isa/rv64si/dirty.S
A tests/test-progs/asmtest/src/riscv/isa/rv64si/icache-alias.S
M tests/test-progs/asmtest/src/riscv/isa/rv64si/ma_fetch.S
M tests/test-progs/asmtest/src/riscv/isa/rv64si/scall.S
M tests/test-progs/asmtest/src/riscv/isa/rv64ua/lrsc.S
M tests/test-progs/asmtest/src/riscv/isa/rv64uc/Makefrag
M tests/test-progs/asmtest/src/riscv/isa/rv64ud/fmin.S
M tests/test-progs/asmtest/src/riscv/isa/rv64ud/structural.S
M tests/test-progs/asmtest/src/riscv/isa/rv64uf/fmin.S
M tests/test-progs/asmtest/src/riscv/isa/rv64ui/jalr.S
M tests/test-progs/asmtest/src/riscv/isa/rv64ui/sll.S
M tests/test-progs/asmtest/src/riscv/isa/rv64ui/slli.S
M tests/test-progs/asmtest/src/riscv/isa/rv64ui/slliw.S
M tests/test-progs/asmtest/src/riscv/isa/rv64ui/sllw.S
M tests/test-progs/asmtest/src/riscv/isa/rv64ui/sra.S
M tests/test-progs/asmtest/src/riscv/isa/rv64ui/sraiw.S
M tests/test-progs/asmtest/src/riscv/isa/rv64ui/sraw.S
M tests/test-progs/asmtest/src/riscv/isa/rv64ui/srl.S
M tests/test-progs/asmtest/src/riscv/isa/rv64ui/srli.S
M tests/test-progs/asmtest/src/riscv/isa/rv64ui/srliw.S
M tests/test-progs/asmtest/src/riscv/isa/rv64ui/srlw.S
32 files changed, 1,781 insertions(+), 165 deletions(-)



diff --git a/tests/test-progs/asmtest/src/riscv/env/encoding.h  
b/tests/test-progs/asmtest/src/riscv/env/encoding.h

index c109ce1..769b0d0 100644
--- a/tests/test-progs/asmtest/src/riscv/env/encoding.h
+++ b/tests/test-progs/asmtest/src/riscv/env/encoding.h
@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+/* See LICENSE for license details. */

 #ifndef RISCV_CSR_ENCODING_H
 #define RISCV_CSR_ENCODING_H
@@ -12,7 +12,7 @@
 #define MSTATUS_HPIE0x0040
 #define MSTATUS_MPIE0x0080
 #define MSTATUS_SPP 0x0100
-#define MSTATUS_HPP 0x0600
+#define MSTATUS_VS  0x0600
 #define MSTATUS_MPP 0x1800
 #define MSTATUS_FS  0x6000
 #define MSTATUS_XS  0x00018000
@@ -32,6 +32,7 @@
 #define SSTATUS_UPIE0x0010
 #define SSTATUS_SPIE0x0020
 #define SSTATUS_SPP 0x0100
+#define SSTATUS_VS  0x0600
 #define SSTATUS_FS  0x6000
 #define SSTATUS_XS  0x00018000
 #define SSTATUS_SUM 0x0004
@@ -40,6 +41,9 @@
 #define SSTATUS_UXL 0x0003
 #define SSTATUS64_SD0x8000

+#define USTATUS_UIE 0x0001
+#define USTATUS_UPIE0x0010
+
 #define DCSR_XDEBUGVER  (3U<<30)
 #define DCSR_NDRESET(1<<29)
 #define DCSR_FULLRESET  (1<<28)
@@ -95,12 +99,15 @@
 #define MCONTROL_MATCH_MASK_LOW  4
 #define MCONTROL_MATCH_MASK_HIGH 5

+#define MIP_USIP(1 << IRQ_U_SOFT)
 #define MIP_SSIP(1 << IRQ_S_SOFT)
 #define MIP_HSIP(1 << IRQ_H_SOFT)
 #define MIP_MSIP(1 << IRQ_M_SOFT)
+#define MIP_UTIP(1 << IRQ_U_TIMER)
 #define MIP_STIP(1 << IRQ_S_TIMER)
 #define MIP_HTIP(1 << IRQ_H_TIMER)
 #define MIP_MTIP(1 << IRQ_M_TIMER)
+#define MIP_UEIP(1 << IRQ_U_EXT)
 #define MIP_SEIP(1 << IRQ_S_EXT)
 #define MIP_HEIP(1 << IRQ_H_EXT)
 #define MIP_MEIP(1 << IRQ_M_EXT)
@@ -138,12 +145,15 @@
 #define PMP_NA4   0x10
 #define PMP_NAPOT 0x18

+#define IRQ_U_SOFT   0
 #define IRQ_S_SOFT   1
 #define IRQ_H_SOFT   2
 #define IRQ_M_SOFT   3
+#define IRQ_U_TIMER  4
 #define IRQ_S_TIMER  5
 #define IRQ_H_TIMER  6
 #define IRQ_M_TIMER  7
+#define IRQ_U_EXT8
 #define IRQ_S_EXT9
 #define IRQ_H_EXT10
 #define IRQ_M_EXT11
@@ -156,16 +166,16 @@
 #define EXT_IO_BASE0x4000
 #define DRAM_BASE  0x8000

-// page table entry (PTE) fields
-#define PTE_V 0x001 // Valid
-#define PTE_R 0x002 // Read
-#define PTE_W 0x004 // Write
-#define PTE_X 0x008 // Execute
-#define PTE_U 0x010 // User
-#define PTE_G 0x020 // Global
-#define PTE_A 0x040 // 

[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: base,sim: allow m5writeFile with stdout/stderr.

2020-05-06 Thread Nils Asmussen (Gerrit) via gem5-dev
Nils Asmussen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28727 )



Change subject: base,sim: allow m5writeFile with stdout/stderr.
..

base,sim: allow m5writeFile with stdout/stderr.

If m5writeFile opens stdout/stderr, no file is registered in
OutputDirectory and thus we don't want to search for it on close.

In order to write multiple times to stdout/stderr in a reasonable way,
we also want to prevent seeking. Thus, don't seek if the offset is 0, in
which case this would be a noop anyway (we just opened the file without
append).

Finally, it is helpful for debugging if the stream is flushed on every
write.

Change-Id: I102f82dcd2c63420b6f3fe55d67f03c62349e69d
---
M src/base/output.cc
M src/sim/pseudo_inst.cc
2 files changed, 11 insertions(+), 2 deletions(-)



diff --git a/src/base/output.cc b/src/base/output.cc
index ec94a13..47b8aa7 100644
--- a/src/base/output.cc
+++ b/src/base/output.cc
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2015 ARM Limited
+ * Copyright (c) 2020 Barkhausen Institut
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -142,6 +143,11 @@
 void
 OutputDirectory::close(OutputStream *file)
 {
+if (file ==  || file == ) {
+file->stream()->flush();
+return;
+}
+
 auto i = files.find(file->name());
 if (i == files.end())
 fatal("Attempted to close an unregistred file stream");
diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index c65fdc0..b11a5a4 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2010-2012, 2015, 2017 ARM Limited
+ * Copyright (c) 2020 Barkhausen Institut
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -425,8 +426,10 @@
 if (!os)
 panic("could not open file %s\n", filename);

-// seek to offset
-os->seekp(offset);
+if (offset != 0) {
+// seek to offset
+os->seekp(offset);
+}

 // copy out data and write to file
 char *buf = new char[len];

--
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Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v20.0.0.0
Gerrit-Change-Id: I102f82dcd2c63420b6f3fe55d67f03c62349e69d
Gerrit-Change-Number: 28727
Gerrit-PatchSet: 1
Gerrit-Owner: Nils Asmussen 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: arch-riscv,tests: run p tests.

2020-05-06 Thread Nils Asmussen (Gerrit) via gem5-dev
-p-, $(rv32ud_sc_tests))
-#rv32ud_ps_tests = $(addprefix rv32ud-ps-, $(rv32ud_sc_tests))
+rv64mi_p_tests = $(addprefix rv64mi-p-, $(rv64mi_sc_tests))

 spike_tests += $(rv64mi_p_tests)
diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64mi/illegal.S  
b/tests/test-progs/asmtest/src/riscv/isa/rv64mi/illegal.S

index 5531570..41097f5 100644
--- a/tests/test-progs/asmtest/src/riscv/isa/rv64mi/illegal.S
+++ b/tests/test-progs/asmtest/src/riscv/isa/rv64mi/illegal.S
@@ -40,8 +40,9 @@
   andi t0, t0, 1
   beqz t0, msip
   csrsi mstatus, MSTATUS_MIE
-1:
-  j 1b
+# TODO we don't have a timer yet, so just skip the test
+# 1:
+#   j 1b
 msip:
   csrw mtvec, s0

diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64si/Makefrag  
b/tests/test-progs/asmtest/src/riscv/isa/rv64si/Makefrag

index c4a5564..f01a332 100644
--- a/tests/test-progs/asmtest/src/riscv/isa/rv64si/Makefrag
+++ b/tests/test-progs/asmtest/src/riscv/isa/rv64si/Makefrag
@@ -12,6 +12,5 @@
sbreak \

 rv64si_p_tests = $(addprefix rv64si-p-, $(rv64si_sc_tests))
-#rv64si_ps_tests = $(addprefix rv64si-ps-, $(rv64si_sc_tests))

 spike_tests += $(rv64si_p_tests)

--
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Gerrit-Change-Id: I0f0e6d6c20210a02411aac0b8d4e85c27f0d904d
Gerrit-Change-Number: 28730
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[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: arch-riscv,tests: run v tests.

2020-05-06 Thread Nils Asmussen (Gerrit) via gem5-dev
Nils Asmussen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28731 )



Change subject: arch-riscv,tests: run v tests.
..

arch-riscv,tests: run v tests.

This commit enables the v tests (using virtual memory) in the test
suite. As for the p tests, success/failure is reported by m5writefile to
a dedicated file. Additionally, failed asserts are reported via the
m5writefile to stdout.

Change-Id: I4fcb8b9cdf0d58460fb90de869fba8c6c8c428a1
---
M tests/test-progs/asmtest/src/riscv/Makefile
M tests/test-progs/asmtest/src/riscv/env/v/vm.c
2 files changed, 24 insertions(+), 16 deletions(-)



diff --git a/tests/test-progs/asmtest/src/riscv/Makefile  
b/tests/test-progs/asmtest/src/riscv/Makefile

index 7b54251..4a22ae5 100644
--- a/tests/test-progs/asmtest/src/riscv/Makefile
+++ b/tests/test-progs/asmtest/src/riscv/Makefile
@@ -55,6 +55,11 @@
 	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(src_dir)/../env/ps  
-I$(src_dir)/macros/scalar -I$(src_dir)/macros/mt  
-T$(src_dir)/../env/ps/link.ld $$< -o $(bin_dir)/$$@

 $(1)_ps_env_tests += $$($(1)_ps_tests)

+$$($(1)_v_tests): $(1)-v-%: $(1)/%.S
+   mkdir -p $(bin_dir)
+	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -DENTROPY=0x$$(shell echo \$$@ |  
md5sum | cut -c 1-7) -std=gnu99 -O2 -I$(src_dir)/../env/v  
-I$(src_dir)/macros/scalar -T$(src_dir)/../env/v/link.ld  
$(src_dir)/../env/v/entry.S $(src_dir)/../env/v/*.c $$< -o $(bin_dir)/$$@

+$(1)_v_env_tests += $$($(1)_v_tests)
+
 $(1)_tests_dump = $$(addsuffix .dump, $$($(1)_tests))

 $(1): $$($(1)_tests_dump)
@@ -80,15 +85,18 @@

 p_env_tests_dump = $(addsuffix .dump, $(p_env_tests))
 ps_env_tests_dump = $(addsuffix .dump, $(ps_env_tests))
+v_env_tests_dump = $(addsuffix .dump, $(v_env_tests))

 #
 # Targets

-all:   p ps
+all:   p ps v
 # build tests with p environment
 p: $(p_env_tests_dump)
 # build tests with ps environment
 ps:$(ps_env_tests_dump)
+# build tests with v environment
+v: $(v_env_tests_dump)

 #
 # Clean up
diff --git a/tests/test-progs/asmtest/src/riscv/env/v/vm.c  
b/tests/test-progs/asmtest/src/riscv/env/v/vm.c

index 6bf05f7..5352dca 100644
--- a/tests/test-progs/asmtest/src/riscv/env/v/vm.c
+++ b/tests/test-progs/asmtest/src/riscv/env/v/vm.c
@@ -17,47 +17,47 @@
 void trap_entry();
 void pop_tf(trapframe_t*);

-volatile uint64_t tohost;
-volatile uint64_t fromhost;
-
-static void do_tohost(uint64_t tohost_value)
-{
-  while (tohost)
-fromhost = 0;
-  tohost = tohost_value;
-}
-
 #define pa2kva(pa) ((void*)(pa) - DRAM_BASE - MEGAPAGE_SIZE)
 #define uva2kva(pa) ((void*)(pa) - MEGAPAGE_SIZE)

 #define flush_page(addr) asm volatile ("sfence.vma %0" : : "r"  
(addr) : "memory")


+static const char *stdoutFile = "stdout";
+static const char *exitcodeFile = "exitcode";
+
 static uint64_t lfsr63(uint64_t x)
 {
   uint64_t bit = (x ^ (x >> 1)) & 1;
   return (x >> 1) | (bit << 62);
 }

-static void cputchar(int x)
+static void cputchar(const char *file, int x)
 {
-  do_tohost(0x0101 | (unsigned char)x);
+  volatile char c = x;
+  register word_t a0 asm("a0") = (uintptr_t)();
+  register word_t a1 asm("a1") = 1;
+  register word_t a2 asm("a2") = 0;
+  register word_t a3 asm("a3") = (uintptr_t)file;
+  asm volatile (".long 0x9E7B" : : "r"(a0), "r"(a1), "r"(a2), "r"(a3));
 }

 static void cputstring(const char* s)
 {
   while (*s)
-cputchar(*s++);
+cputchar(stdoutFile, *s++);
 }

 static void terminate(int code)
 {
-  do_tohost(code);
+  cputchar(exitcodeFile, code >> 1);
+  register word_t a0 asm("a0") = 0;
+  asm volatile (".long 0x427B" : : "r"(a0));
   while (1);
 }

 void wtf()
 {
-  terminate(841);
+  terminate(255 << 1);
 }

 #define stringify1(x) #x

--
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[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: arch-riscv,tests: added .gitignore.

2020-05-06 Thread Nils Asmussen (Gerrit) via gem5-dev
Nils Asmussen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28728 )



Change subject: arch-riscv,tests: added .gitignore.
..

arch-riscv,tests: added .gitignore.

Change-Id: I4377468acf906fbe1f3ca2baa5f0c2aa2941b501
---
A tests/test-progs/asmtest/.gitignore
1 file changed, 2 insertions(+), 0 deletions(-)



diff --git a/tests/test-progs/asmtest/.gitignore  
b/tests/test-progs/asmtest/.gitignore

new file mode 100644
index 000..84ff6ec
--- /dev/null
+++ b/tests/test-progs/asmtest/.gitignore
@@ -0,0 +1,2 @@
+bin/*
+dump/*

--
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Gerrit-Change-Number: 28728
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: be prepared for CSR changes during PT walk.

2020-05-01 Thread Nils Asmussen (Gerrit) via gem5-dev
addr & mask(e->logBytes));
+}
+
 Fault
 TLB::doTranslate(const RequestPtr , ThreadContext *tc,
  Translation *translation, Mode mode, bool )
@@ -281,7 +288,9 @@
 assert(e != nullptr);
 }

-Fault fault = checkPermissions(tc, vaddr, mode, e->pte);
+STATUS status = tc->readMiscReg(MISCREG_STATUS);
+PrivilegeMode pmode = getMemPriv(tc, mode);
+Fault fault = checkPermissions(status, pmode, vaddr, mode, e->pte);
 if (fault != NoFault) {
 // if we want to write and it isn't writable, do a page table walk
 // again to update the dirty flag.
diff --git a/src/arch/riscv/tlb.hh b/src/arch/riscv/tlb.hh
index a7e8d61..7ed6628 100644
--- a/src/arch/riscv/tlb.hh
+++ b/src/arch/riscv/tlb.hh
@@ -88,7 +88,7 @@
 void flushAll() override;
 void demapPage(Addr vaddr, uint64_t asn) override;

-Fault checkPermissions(ThreadContext *tc, Addr vaddr,
+Fault checkPermissions(STATUS status, PrivilegeMode pmode, Addr vaddr,
Mode mode, PTESv39 pte);
 Fault createPagefault(Addr vaddr, Mode mode);

@@ -100,8 +100,7 @@

 void regStats() override;

-Fault doTranslate(const RequestPtr , ThreadContext *tc,
-  Translation *translation, Mode mode, bool );
+Addr translateWithTLB(Addr vaddr, uint16_t asid, Mode mode);

 Fault translateAtomic(const RequestPtr ,
   ThreadContext *tc, Mode mode) override;
@@ -122,6 +121,8 @@

 Fault translate(const RequestPtr , ThreadContext *tc,
 Translation *translation, Mode mode, bool );
+Fault doTranslate(const RequestPtr , ThreadContext *tc,
+  Translation *translation, Mode mode, bool );
 };

 }

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Gerrit-Project: public/gem5
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Gerrit-Change-Id: I8c184c7ae7dd44d78e881bb5ec8d430dd480849c
Gerrit-Change-Number: 28447
Gerrit-PatchSet: 2
Gerrit-Owner: Nils Asmussen 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nils Asmussen 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: misc: added news on RISC-V to RELEASE-NOTES.md.

2020-05-01 Thread Nils Asmussen (Gerrit) via gem5-dev
Nils Asmussen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28448 )


Change subject: misc: added news on RISC-V to RELEASE-NOTES.md.
..

misc: added news on RISC-V to RELEASE-NOTES.md.

Change-Id: I9b60cd2f533e6d4ce677e8a9b7bb5a5698e51c61
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28448
Maintainer: Bobby R. Bruce 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
---
M RELEASE-NOTES.md
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/RELEASE-NOTES.md b/RELEASE-NOTES.md
index 1a679dd..6f80906 100644
--- a/RELEASE-NOTES.md
+++ b/RELEASE-NOTES.md
@@ -8,3 +8,4 @@
 * The m5 utility has been revamped with a new build system based on scons,  
tests, and updated and more consistent feature support.
 * Robust support for marshalling data from a function call inside the  
simulation to a function within gem5 using a predefined set of rules.
 * Workload configuration pulled out into its own object, simplifying the  
System object and making workload configuration more modular and flexible.
+* Sv39 paging has been added to the RISC-V ISA, bringing gem5 close to  
running Linux on RISC-V.


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Gerrit-Change-Number: 28448
Gerrit-PatchSet: 2
Gerrit-Owner: Nils Asmussen 
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: be prepared for CSR changes during PT walk.

2020-05-01 Thread Nils Asmussen (Gerrit) via gem5-dev
e, e->pte);
+STATUS status = tc->readMiscReg(MISCREG_STATUS);
+PrivilegeMode pmode = getMemPriv(tc, mode);
+Fault fault = checkPermissions(status, pmode, vaddr, mode, e->pte);
 if (fault != NoFault) {
 // if we want to write and it isn't writable, do a page table walk
 // again to update the dirty flag.
diff --git a/src/arch/riscv/tlb.hh b/src/arch/riscv/tlb.hh
index a7e8d61..7ed6628 100644
--- a/src/arch/riscv/tlb.hh
+++ b/src/arch/riscv/tlb.hh
@@ -88,7 +88,7 @@
 void flushAll() override;
 void demapPage(Addr vaddr, uint64_t asn) override;

-Fault checkPermissions(ThreadContext *tc, Addr vaddr,
+Fault checkPermissions(STATUS status, PrivilegeMode pmode, Addr vaddr,
Mode mode, PTESv39 pte);
 Fault createPagefault(Addr vaddr, Mode mode);

@@ -100,8 +100,7 @@

 void regStats() override;

-Fault doTranslate(const RequestPtr , ThreadContext *tc,
-  Translation *translation, Mode mode, bool );
+Addr translateWithTLB(Addr vaddr, uint16_t asid, Mode mode);

 Fault translateAtomic(const RequestPtr ,
   ThreadContext *tc, Mode mode) override;
@@ -122,6 +121,8 @@

 Fault translate(const RequestPtr , ThreadContext *tc,
 Translation *translation, Mode mode, bool );
+Fault doTranslate(const RequestPtr , ThreadContext *tc,
+  Translation *translation, Mode mode, bool );
 };

 }

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[gem5-dev] Change in gem5/gem5[develop]: misc: added news on RISC-V to RELEASE-NOTES.md.

2020-05-01 Thread Nils Asmussen (Gerrit) via gem5-dev
Nils Asmussen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28448 )



Change subject: misc: added news on RISC-V to RELEASE-NOTES.md.
..

misc: added news on RISC-V to RELEASE-NOTES.md.

Change-Id: I9b60cd2f533e6d4ce677e8a9b7bb5a5698e51c61
---
M RELEASE-NOTES.md
1 file changed, 1 insertion(+), 0 deletions(-)



diff --git a/RELEASE-NOTES.md b/RELEASE-NOTES.md
index 1a679dd..6f80906 100644
--- a/RELEASE-NOTES.md
+++ b/RELEASE-NOTES.md
@@ -8,3 +8,4 @@
 * The m5 utility has been revamped with a new build system based on scons,  
tests, and updated and more consistent feature support.
 * Robust support for marshalling data from a function call inside the  
simulation to a function within gem5 using a predefined set of rules.
 * Workload configuration pulled out into its own object, simplifying the  
System object and making workload configuration more modular and flexible.
+* Sv39 paging has been added to the RISC-V ISA, bringing gem5 close to  
running Linux on RISC-V.


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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: make uret,sret,mret SerializeAfter,NonSpeculative.

2020-04-29 Thread Nils Asmussen (Gerrit) via gem5-dev
Nils Asmussen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25656 )


Change subject: arch-riscv: make uret,sret,mret  
SerializeAfter,NonSpeculative.

..

arch-riscv: make uret,sret,mret SerializeAfter,NonSpeculative.

These instructions potentially change the privilege level, upon which
the execution of other instructions depends. For that reason, we need to
make *ret SerializeAfter and we also don't want to execute them
speculatively.

Change-Id: If3b5ba6ec3b4102d53c51cf723eba5d5da3eaa2f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25656
Tested-by: kokoro 
Tested-by: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass
  Gem5 Cloud Project GCB service account: Regressions pass



diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 9e65ecf..35d08ec 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -1775,7 +1775,7 @@
 status.upie = 1;
 xc->setMiscReg(MISCREG_STATUS, status);
 NPC = xc->readMiscReg(MISCREG_UEPC);
-}}, IsReturn);
+}}, IsSerializeAfter, IsNonSpeculative, IsReturn);
 }
 0x8: decode RS2 {
 0x2: sret({{
@@ -1796,7 +1796,7 @@
 xc->setMiscReg(MISCREG_STATUS, status);
 NPC = xc->readMiscReg(MISCREG_SEPC);
 }
-}}, IsReturn);
+}}, IsSerializeAfter, IsNonSpeculative, IsReturn);
 0x5: wfi({{
 STATUS status =  
xc->readMiscReg(MISCREG_STATUS);

 auto pm = (PrivilegeMode)xc->readMiscReg(
@@ -1835,7 +1835,7 @@
 xc->setMiscReg(MISCREG_STATUS, status);
 NPC = xc->readMiscReg(MISCREG_MEPC);
 }
-}}, IsReturn);
+}}, IsSerializeAfter, IsNonSpeculative, IsReturn);
 }
 }
 format CSROp {

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Gerrit-Change-Number: 25656
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Gerrit-Owner: Nils Asmussen 
Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nils Asmussen 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: let FPU instructions fault if status.FS = off.

2020-04-29 Thread Nils Asmussen (Gerrit) via gem5-dev
f", machInst);
+
 %(op_decl)s;
 %(op_rd)s;
 if (fault == NoFault) {

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Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Bobby R. Bruce 
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: make accesses to CSRs SerializeAfter.

2020-04-29 Thread Nils Asmussen (Gerrit) via gem5-dev
Nils Asmussen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25655 )


Change subject: arch-riscv: make accesses to CSRs SerializeAfter.
..

arch-riscv: make accesses to CSRs SerializeAfter.

According to page 57 in the RISC-V manual, CSR accesses "need to be
performed in program order with respect to those instructions whose
execution behavior is affected by the state of the accessed CSR".

Thus, we need to make them SerializeAfter to ensure that the following
instructions are executed with the potential changes to the CSR. In
theory, we could be smarter here by only considering write accesses to
CSRs and considering the following instructions, but for now we simply
serialize for every CSR access.

Change-Id: I69391fccaec31c34d944c55bac2f04d37947ebfe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25655
Tested-by: kokoro 
Tested-by: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 6 insertions(+), 6 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass
  Gem5 Cloud Project GCB service account: Regressions pass



diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 8dad14c..9e65ecf 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -1842,27 +1842,27 @@
 0x1: csrrw({{
 Rd = data;
 data = Rs1;
-}}, IsNonSpeculative, No_OpClass);
+}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
 0x2: csrrs({{
 Rd = data;
 data |= Rs1;
-}}, IsNonSpeculative, No_OpClass);
+}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
 0x3: csrrc({{
 Rd = data;
 data &= ~Rs1;
-}}, IsNonSpeculative, No_OpClass);
+}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
 0x5: csrrwi({{
 Rd = data;
 data = uimm;
-}}, IsNonSpeculative, No_OpClass);
+}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
 0x6: csrrsi({{
 Rd = data;
 data |= uimm;
-}}, IsNonSpeculative, No_OpClass);
+}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
 0x7: csrrci({{
 Rd = data;
 data &= ~uimm;
-}}, IsNonSpeculative, No_OpClass);
+}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
 }
 }


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Gerrit-Change-Number: 25655
Gerrit-PatchSet: 11
Gerrit-Owner: Nils Asmussen 
Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: respect IALIGN, influenced by toggling 'c' extension.

2020-04-29 Thread Nils Asmussen (Gerrit) via gem5-dev
Nils Asmussen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25658 )


Change subject: arch-riscv: respect IALIGN, influenced by toggling 'c'  
extension.

..

arch-riscv: respect IALIGN, influenced by toggling 'c' extension.

According to the privileged ISA spec, SEPC[0]/MEPC[0] reads always 0
and SEPC[1]/MEPC[1] reads 0 if the compressed extension is disabled.

Additionally, the compressed extension can only be disabled if the next
instruction is 4-byte aligned.

Change-Id: I590c05e4000b59a5ba283f47933f7a92959d8e38
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25658
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/arch/riscv/isa.cc
M src/arch/riscv/registers.hh
2 files changed, 25 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index a2fbd80..b6137fe 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -283,6 +283,18 @@
  
tc->getCpuPtr()->getInterruptController(tc->threadId()));

 return ic->readIE();
 }
+  case MISCREG_SEPC:
+  case MISCREG_MEPC:
+{
+auto misa = readMiscRegNoEffect(MISCREG_ISA);
+auto val = readMiscRegNoEffect(misc_reg);
+// if compressed instructions are disabled, epc[1] is set to 0
+if ((misa & ISA_EXT_C_MASK) == 0)
+return mbits(val, 63, 2);
+// epc[0] is always 0
+else
+return mbits(val, 63, 1);
+}
   default:
 // Try reading HPM counters
 // As a placeholder, all HPM counters are just cycle counters
@@ -347,6 +359,17 @@
 setMiscRegNoEffect(misc_reg, new_val);
 }
 break;
+  case MISCREG_ISA:
+{
+auto cur_val = readMiscRegNoEffect(misc_reg);
+// only allow to disable compressed instructions
+// if the following instruction is 4-byte aligned
+if ((val & ISA_EXT_C_MASK) == 0 &&
+bits(tc->pcState().npc(), 2, 0) != 0)
+val |= cur_val & ISA_EXT_C_MASK;
+setMiscRegNoEffect(misc_reg, val);
+}
+break;
   case MISCREG_STATUS:
 {
 // SXL and UXL are hard-wired to 64 bit
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index d5c05a2..9b899e3 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -2,6 +2,7 @@
  * Copyright (c) 2013 ARM Limited
  * Copyright (c) 2014-2015 Sven Karlsson
  * Copyright (c) 2019 Yifei Liu
+ * Copyright (c) 2020 Barkhausen Institut
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -646,6 +647,7 @@

 const RegVal ISA_MXL_MASK = 3ULL << MXL_OFFSET;
 const RegVal ISA_EXT_MASK = mask(26);
+const RegVal ISA_EXT_C_MASK = 1UL << ('c' - 'a');
 const RegVal MISA_MASK = ISA_MXL_MASK | ISA_EXT_MASK;

 const RegVal STATUS_SD_MASK = 1ULL << ((sizeof(uint64_t) * 8) - 1);

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Gerrit-Branch: develop
Gerrit-Change-Id: I590c05e4000b59a5ba283f47933f7a92959d8e38
Gerrit-Change-Number: 25658
Gerrit-PatchSet: 10
Gerrit-Owner: Nils Asmussen 
Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nils Asmussen 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: report that we don't have debugging support.

2020-04-29 Thread Nils Asmussen (Gerrit) via gem5-dev
Nils Asmussen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25659 )


Change subject: arch-riscv: report that we don't have debugging support.
..

arch-riscv: report that we don't have debugging support.

According to the debugging spec (page 47), a debugger can test which
triggers are enabled by writing 0 to TSELECT and reading it back. If a
different value is read, the trigger is not supported.

Therefore, we currently always set a different value to indicate that
we do not support any triggers.

Change-Id: If222e913c4517adb2da4f6f0ffeedb4e4808a586
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25659
Tested-by: kokoro 
Tested-by: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/arch/riscv/isa.cc
1 file changed, 10 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass
  Gem5 Cloud Project GCB service account: Regressions pass



diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index b6137fe..ac26230 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -200,6 +200,9 @@
   (1ULL << FS_OFFSET);
 miscRegFile[MISCREG_MCOUNTEREN] = 0x7;
 miscRegFile[MISCREG_SCOUNTEREN] = 0x7;
+// don't set it to zero; software may try to determine the supported
+// triggers, starting at zero. simply set a different value here.
+miscRegFile[MISCREG_TSELECT] = 1;
 }

 bool
@@ -359,6 +362,13 @@
 setMiscRegNoEffect(misc_reg, new_val);
 }
 break;
+  case MISCREG_TSELECT:
+{
+// we don't support debugging, so always set a different  
value

+// than written
+setMiscRegNoEffect(misc_reg, val + 1);
+}
+break;
   case MISCREG_ISA:
 {
 auto cur_val = readMiscRegNoEffect(misc_reg);

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Gerrit-Change-Number: 25659
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Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Bobby R. Bruce 
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Gerrit-Reviewer: Nils Asmussen 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fault on mstatus accesses from lower privilege modes.

2020-04-29 Thread Nils Asmussen (Gerrit) via gem5-dev
Nils Asmussen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25652 )


Change subject: arch-riscv: fault on mstatus accesses from lower privilege  
modes.

..

arch-riscv: fault on mstatus accesses from lower privilege modes.

Change-Id: If2e35445770eaa52f5af6f9ef02fb5e11bef8da4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25652
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/arch/riscv/isa/formats/standard.isa
1 file changed, 13 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/riscv/isa/formats/standard.isa  
b/src/arch/riscv/isa/formats/standard.isa

index 0412151..d80c671 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -2,6 +2,7 @@

 // Copyright (c) 2015 RISC-V Foundation
 // Copyright (c) 2016-2017 The University of Virginia
+// Copyright (c) 2020 Barkhausen Institut
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -306,6 +307,18 @@
 olddata = xc->readMiscReg(MISCREG_FFLAGS) |
   (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
 break;
+  case CSR_MSTATUS: {
+auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
+if (pm != PrivilegeMode::PRV_M) {
+std::string error = csprintf(
+"MSTATUS is only accessibly in machine mode\n");
+fault = make_shared(error, machInst);
+olddata = 0;
+} else {
+olddata = xc->readMiscReg(CSRData.at(csr).physIndex);
+}
+break;
+  }
   default:
 if (CSRData.find(csr) != CSRData.end()) {
 olddata = xc->readMiscReg(CSRData.at(csr).physIndex);

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Gerrit-Change-Number: 25652
Gerrit-PatchSet: 11
Gerrit-Owner: Nils Asmussen 
Gerrit-Reviewer: Alec Roelke 
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fault according to status.{TVM,TSK,TW}.

2020-04-29 Thread Nils Asmussen (Gerrit) via gem5-dev
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I38dddadb3373d2156b8fc57eabff861a062021cf
Gerrit-Change-Number: 25654
Gerrit-PatchSet: 11
Gerrit-Owner: Nils Asmussen 
Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: ignore writes to SXL/UXL fields in status register.

2020-04-29 Thread Nils Asmussen (Gerrit) via gem5-dev
Nils Asmussen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25651 )


Change subject: arch-riscv: ignore writes to SXL/UXL fields in status  
register.

..

arch-riscv: ignore writes to SXL/UXL fields in status register.

We currently only support SXL=UXL=2 (64 bit). These fields are WARL,
so that we have to make sure that no other value can be set.

Change-Id: I62ddc7d68b8c31ca655ba1ccee7a294912f46b09
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25651
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/arch/riscv/isa.cc
1 file changed, 9 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 754ff85..a2fbd80 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -347,6 +347,15 @@
 setMiscRegNoEffect(misc_reg, new_val);
 }
 break;
+  case MISCREG_STATUS:
+{
+// SXL and UXL are hard-wired to 64 bit
+auto cur = readMiscRegNoEffect(misc_reg);
+val &= ~(STATUS_SXL_MASK | STATUS_UXL_MASK);
+val |= cur & (STATUS_SXL_MASK | STATUS_UXL_MASK);
+setMiscRegNoEffect(misc_reg, val);
+}
+break;
   default:
 setMiscRegNoEffect(misc_reg, val);
 }

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Gerrit-Change-Number: 25651
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Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gem5 Cloud Project GCB service account  
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Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: added dummy implementation of wfi instruction.

2020-04-29 Thread Nils Asmussen (Gerrit) via gem5-dev
Nils Asmussen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25653 )


Change subject: arch-riscv: added dummy implementation of wfi instruction.
..

arch-riscv: added dummy implementation of wfi instruction.

Change-Id: I7ca86f57c7d794bf544e34e747875049a3f29d6a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25653
Tested-by: kokoro 
Tested-by: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass
  Gem5 Cloud Project GCB service account: Regressions pass



diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 04f0319..8706155 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -1794,6 +1794,9 @@
 NPC = xc->readMiscReg(MISCREG_SEPC);
 }
 }}, IsReturn);
+0x5: wfi({{
+// don't do anything for now
+}}, No_OpClass);
 }
 0x9: sfence_vma({{
 xc->tcBase()->getITBPtr()->demapPage(Rs1, Rs2);

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Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

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Gerrit-Reviewer: Nils Asmussen 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: added (un)serialization of miscRegFile.

2020-04-29 Thread Nils Asmussen (Gerrit) via gem5-dev
Nils Asmussen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25650 )


Change subject: arch-riscv: added (un)serialization of miscRegFile.
..

arch-riscv: added (un)serialization of miscRegFile.

Change-Id: I127dbf4a6bb4a144eaee05a87495830dce82eb58
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25650
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
2 files changed, 18 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 3f1a7e1..754ff85 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -39,6 +39,7 @@
 #include "arch/riscv/registers.hh"
 #include "base/bitfield.hh"
 #include "cpu/base.hh"
+#include "debug/Checkpoint.hh"
 #include "debug/RiscvMisc.hh"
 #include "params/RiscvISA.hh"
 #include "sim/core.hh"
@@ -352,6 +353,20 @@
 }
 }

+void
+ISA::serialize(CheckpointOut ) const
+{
+DPRINTF(Checkpoint, "Serializing Riscv Misc Registers\n");
+SERIALIZE_CONTAINER(miscRegFile);
+}
+
+void
+ISA::unserialize(CheckpointIn )
+{
+DPRINTF(Checkpoint, "Unserializing Riscv Misc Registers\n");
+UNSERIALIZE_CONTAINER(miscRegFile);
+}
+
 }

 RiscvISA::ISA *
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 9d34242..c56c45b 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -92,6 +92,9 @@

 void startup(ThreadContext *tc) {}

+void serialize(CheckpointOut ) const;
+void unserialize(CheckpointIn );
+
 /// Explicitly import the otherwise hidden startup
 using BaseISA::startup;


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I127dbf4a6bb4a144eaee05a87495830dce82eb58
Gerrit-Change-Number: 25650
Gerrit-PatchSet: 10
Gerrit-Owner: Nils Asmussen 
Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Bobby R. Bruce 
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Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: added TLB and page table walker.

2020-04-29 Thread Nils Asmussen (Gerrit) via gem5-dev
Nils Asmussen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25647 )


Change subject: arch-riscv: added TLB and page table walker.
..

arch-riscv: added TLB and page table walker.

That is, RISC-V has now a TLB and page table walker for Sv39 paging
according to the privileged ISA 1.11.

Both the TLB and PT walker are based on x86 (the code duplication of the
page table walkers will be reduced by a separate commit).

Change-Id: I5e29683bdd40c0d32c06e4d75a8382bf313f2086
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25647
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/riscv/RiscvTLB.py
M src/arch/riscv/SConscript
M src/arch/riscv/bare_metal/fs_workload.cc
M src/arch/riscv/pagetable.cc
M src/arch/riscv/pagetable.hh
A src/arch/riscv/pagetable_walker.cc
A src/arch/riscv/pagetable_walker.hh
M src/arch/riscv/tlb.cc
M src/arch/riscv/tlb.hh
9 files changed, 1,326 insertions(+), 404 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/riscv/RiscvTLB.py b/src/arch/riscv/RiscvTLB.py
index 4bcaf67..884b71f 100644
--- a/src/arch/riscv/RiscvTLB.py
+++ b/src/arch/riscv/RiscvTLB.py
@@ -1,6 +1,7 @@
 # -*- mode:python -*-

 # Copyright (c) 2007 MIPS Technologies, Inc.
+# Copyright (c) 2020 Barkhausen Institut
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -26,13 +27,25 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from m5.SimObject import SimObject
 from m5.params import *
+from m5.proxy import *

 from m5.objects.BaseTLB import BaseTLB
+from m5.objects.ClockedObject import ClockedObject
+
+class RiscvPagetableWalker(ClockedObject):
+type = 'RiscvPagetableWalker'
+cxx_class = 'RiscvISA::Walker'
+cxx_header = 'arch/riscv/pagetable_walker.hh'
+port = MasterPort("Port for the hardware table walker")
+system = Param.System(Parent.any, "system object")
+num_squash_per_cycle = Param.Unsigned(4,
+"Number of outstanding walks that can be squashed per cycle")

 class RiscvTLB(BaseTLB):
 type = 'RiscvTLB'
 cxx_class = 'RiscvISA::TLB'
 cxx_header = 'arch/riscv/tlb.hh'
 size = Param.Int(64, "TLB size")
+walker = Param.RiscvPagetableWalker(\
+RiscvPagetableWalker(), "page table walker")
diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript
index 74217cf..8a363f5 100644
--- a/src/arch/riscv/SConscript
+++ b/src/arch/riscv/SConscript
@@ -2,6 +2,7 @@

 # Copyright (c) 2013 ARM Limited
 # Copyright (c) 2014 Sven Karlsson
+# Copyright (c) 2020 Barkhausen Institut
 # All rights reserved
 #
 # The license below extends only to copyright in the software and shall
@@ -49,6 +50,7 @@
 Source('locked_mem.cc')
 Source('process.cc')
 Source('pagetable.cc')
+Source('pagetable_walker.cc')
 Source('remote_gdb.cc')
 Source('stacktrace.cc')
 Source('tlb.cc')
@@ -64,7 +66,9 @@
 SimObject('RiscvTLB.py')

 DebugFlag('RiscvMisc')
-DebugFlag('RiscvTLB')
+DebugFlag('TLBVerbose')
+DebugFlag('PageTableWalker', \
+  "Page table walker state machine debugging")

 # Add in files generated by the ISA description.
 ISADesc('isa/main.isa')
diff --git a/src/arch/riscv/bare_metal/fs_workload.cc  
b/src/arch/riscv/bare_metal/fs_workload.cc

index cea98e8..a82d1df 100644
--- a/src/arch/riscv/bare_metal/fs_workload.cc
+++ b/src/arch/riscv/bare_metal/fs_workload.cc
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2018 TU Dresden
+ * Copyright (c) 2020 Barkhausen Institut
  * All rights reserved
  *
  * Redistribution and use in source and binary forms, with or without
@@ -60,6 +61,11 @@

 warn_if(!bootloader->buildImage().write(system->physProxy),
 "Could not load sections to memory.");
+
+for (auto *tc: system->threadContexts) {
+RiscvISA::Reset().invoke(tc);
+tc->activate();
+}
 }

 } // namespace RiscvISA
diff --git a/src/arch/riscv/pagetable.cc b/src/arch/riscv/pagetable.cc
index 3291d8a..9e4fef0 100644
--- a/src/arch/riscv/pagetable.cc
+++ b/src/arch/riscv/pagetable.cc
@@ -1,6 +1,7 @@
 /*
  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  * Copyright (c) 2007 MIPS Technologies, Inc.
+ * Copyright (c) 2020 Barkhausen Institut
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -29,47 +30,32 @@

 #include "arch/riscv/pagetable.hh"

+#include "arch/riscv/isa_traits.hh"
 #include "sim/serialize.hh"

 namespace RiscvISA
 {

 void
-PTE::serialize(CheckpointOut ) const
+TlbEntry::serialize(CheckpointOut ) const
 {
-SERIALIZE_SCALAR(Mask);
-SERIALIZE_SCALAR(VPN);
+SERIALIZE_SCALAR(paddr);
+

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: show names of MiscRegs on accesses.

2020-04-29 Thread Nils Asmussen (Gerrit) via gem5-dev
   = "TDATA1",
+[MISCREG_TDATA2]= "TDATA2",
+[MISCREG_TDATA3]= "TDATA3",
+[MISCREG_DCSR]  = "DCSR",
+[MISCREG_DPC]   = "DPC",
+[MISCREG_DSCRATCH]  = "DSCRATCH",
+
+[MISCREG_MEDELEG]   = "MEDELEG",
+[MISCREG_MIDELEG]   = "MIDELEG",
+[MISCREG_MTVEC] = "MTVEC",
+[MISCREG_MCOUNTEREN]= "MCOUNTEREN",
+[MISCREG_MSCRATCH]  = "MSCRATCH",
+[MISCREG_MEPC]  = "MEPC",
+[MISCREG_MCAUSE]= "MCAUSE",
+[MISCREG_MTVAL] = "MTVAL",
+[MISCREG_PMPCFG0]   = "PMPCFG0",
+// pmpcfg1 rv32 only
+[MISCREG_PMPCFG2]   = "PMPCFG2",
+// pmpcfg3 rv32 only
+[MISCREG_PMPADDR00] = "PMPADDR00",
+[MISCREG_PMPADDR01] = "PMPADDR01",
+[MISCREG_PMPADDR02] = "PMPADDR02",
+[MISCREG_PMPADDR03] = "PMPADDR03",
+[MISCREG_PMPADDR04] = "PMPADDR04",
+[MISCREG_PMPADDR05] = "PMPADDR05",
+[MISCREG_PMPADDR06] = "PMPADDR06",
+[MISCREG_PMPADDR07] = "PMPADDR07",
+[MISCREG_PMPADDR08] = "PMPADDR08",
+[MISCREG_PMPADDR09] = "PMPADDR09",
+[MISCREG_PMPADDR10] = "PMPADDR10",
+[MISCREG_PMPADDR11] = "PMPADDR11",
+[MISCREG_PMPADDR12] = "PMPADDR12",
+[MISCREG_PMPADDR13] = "PMPADDR13",
+[MISCREG_PMPADDR14] = "PMPADDR14",
+[MISCREG_PMPADDR15] = "PMPADDR15",
+
+[MISCREG_SEDELEG]   = "SEDELEG",
+[MISCREG_SIDELEG]   = "SIDELEG",
+[MISCREG_STVEC] = "STVEC",
+[MISCREG_SCOUNTEREN]= "SCOUNTEREN",
+[MISCREG_SSCRATCH]  = "SSCRATCH",
+[MISCREG_SEPC]  = "SEPC",
+[MISCREG_SCAUSE]= "SCAUSE",
+[MISCREG_STVAL] = "STVAL",
+[MISCREG_SATP]  = "SATP",
+
+[MISCREG_UTVEC] = "UTVEC",
+[MISCREG_USCRATCH]  = "USCRATCH",
+[MISCREG_UEPC]  = "UEPC",
+[MISCREG_UCAUSE]= "UCAUSE",
+[MISCREG_UTVAL] = "UTVAL",
+[MISCREG_FFLAGS]= "FFLAGS",
+    [MISCREG_FRM]   = "FRM",
+}};
+
 ISA::ISA(Params *p) : BaseISA(p)
 {
 miscRegFile.resize(NumMiscRegs);
@@ -105,8 +232,8 @@
 panic("Illegal CSR index %#x\n", misc_reg);
 return -1;
 }
-DPRINTF(RiscvMisc, "Reading MiscReg %d: %#llx.\n", misc_reg,
-miscRegFile[misc_reg]);
+DPRINTF(RiscvMisc, "Reading MiscReg %s (%d): %#x.\n",
+MiscRegNames[misc_reg], misc_reg, miscRegFile[misc_reg]);
 return miscRegFile[misc_reg];
 }

@@ -180,7 +307,8 @@
 // Illegal CSR
 panic("Illegal CSR index %#x\n", misc_reg);
 }
-DPRINTF(RiscvMisc, "Setting MiscReg %d to %#x.\n", misc_reg, val);
+DPRINTF(RiscvMisc, "Setting MiscReg %s (%d) to %#x.\n",
+MiscRegNames[misc_reg], misc_reg, val);
 miscRegFile[misc_reg] = val;
 }


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Gerrit-Project: public/gem5
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Gerrit-Change-Id: Icd53d5524a5d5daf3e50f253cdda56341663f26e
Gerrit-Change-Number: 25649
Gerrit-PatchSet: 10
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Gerrit-Reviewer: Gabe Black 
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Gerrit-Reviewer: Nils Asmussen 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: cpu,configs: let RISC-V use the PT walker cache.

2020-04-29 Thread Nils Asmussen (Gerrit) via gem5-dev
Nils Asmussen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26988 )


Change subject: cpu,configs: let RISC-V use the PT walker cache.
..

cpu,configs: let RISC-V use the PT walker cache.

Change-Id: I19b1dd9e3c55c433c897988d36e6715017273c66
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26988
Tested-by: kokoro 
Tested-by: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M configs/common/CacheConfig.py
M configs/common/Caches.py
M src/cpu/BaseCPU.py
3 files changed, 8 insertions(+), 5 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass
  Gem5 Cloud Project GCB service account: Regressions pass



diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index 91087fb..05c38e0 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -1,4 +1,5 @@
 # Copyright (c) 2012-2013, 2015-2016 ARM Limited
+# Copyright (c) 2020 Barkhausen Institut
 # All rights reserved
 #
 # The license below extends only to copyright in the software and shall
@@ -79,7 +80,7 @@
 dcache_class, icache_class, l2_cache_class, walk_cache_class = \
 L1_DCache, L1_ICache, L2Cache, None

-if buildEnv['TARGET_ISA'] == 'x86':
+if buildEnv['TARGET_ISA'] in ['x86', 'riscv']:
 walk_cache_class = PageTableWalkerCache

 # Set the cache line size of the system
@@ -181,7 +182,7 @@
 # on these names.  For simplicity, we would advise configuring
 # it to use this naming scheme; if this isn't possible, change
 # the names below.
-if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
+if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']:
 system.cpu[i].addPrivateSplitL1Caches(
 ExternalCache("cpu%d.icache" % i),
 ExternalCache("cpu%d.dcache" % i),
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 123fea4..77213e8 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -1,4 +1,5 @@
 # Copyright (c) 2012 ARM Limited
+# Copyright (c) 2020 Barkhausen Institut
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -92,7 +93,7 @@
 tgts_per_mshr = 12

 # the x86 table walker actually writes to the table-walker cache
-if buildEnv['TARGET_ISA'] == 'x86':
+if buildEnv['TARGET_ISA'] in ['x86', 'riscv']:
 is_read_only = False
 else:
 is_read_only = True
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 53652bf..67d95d0 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -1,4 +1,5 @@
 # Copyright (c) 2012-2013, 2015-2017 ARM Limited
+# Copyright (c) 2020 Barkhausen Institut
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -181,7 +182,7 @@
 dcache_port = MasterPort("Data Port")
 _cached_ports = ['icache_port', 'dcache_port']

-if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
+if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']:
 _cached_ports += ["itb.walker.port", "dtb.walker.port"]

 _uncached_slave_ports = []
@@ -216,7 +217,7 @@
 self.icache_port = ic.cpu_side
 self.dcache_port = dc.cpu_side
 self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
-if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
+if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']:
 if iwc and dwc:
 self.itb_walker_cache = iwc
 self.dtb_walker_cache = dwc

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I19b1dd9e3c55c433c897988d36e6715017273c66
Gerrit-Change-Number: 26988
Gerrit-PatchSet: 10
Gerrit-Owner: Nils Asmussen 
Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nils Asmussen 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: implement RemoteGDB::acc for FS mode.

2020-04-29 Thread Nils Asmussen (Gerrit) via gem5-dev
Nils Asmussen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26985 )


Change subject: arch-riscv: implement RemoteGDB::acc for FS mode.
..

arch-riscv: implement RemoteGDB::acc for FS mode.

Change-Id: I78b37db43fbb16d4dafa74294117e8beba62f903
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26985
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/arch/riscv/remote_gdb.cc
1 file changed, 22 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/riscv/remote_gdb.cc b/src/arch/riscv/remote_gdb.cc
index 16b4585..7da666d 100644
--- a/src/arch/riscv/remote_gdb.cc
+++ b/src/arch/riscv/remote_gdb.cc
@@ -2,6 +2,7 @@
  * Copyright 2015 LabWare
  * Copyright 2014 Google, Inc.
  * Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2020 Barkhausen Institut
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -133,7 +134,9 @@

 #include 

+#include "arch/riscv/pagetable_walker.hh"
 #include "arch/riscv/registers.hh"
+#include "arch/riscv/tlb.hh"
 #include "cpu/thread_state.hh"
 #include "debug/GDBAcc.hh"
 #include "mem/page_table.hh"
@@ -150,7 +153,25 @@
 bool
 RemoteGDB::acc(Addr va, size_t len)
 {
-panic_if(FullSystem, "acc not implemented for RISCV FS!");
+if (FullSystem)
+{
+TLB *tlb = dynamic_cast(context()->getDTBPtr());
+unsigned logBytes;
+Addr paddr = va;
+
+PrivilegeMode pmode = tlb->getMemPriv(context(), BaseTLB::Read);
+SATP satp = context()->readMiscReg(MISCREG_SATP);
+if (pmode != PrivilegeMode::PRV_M &&
+satp.mode != AddrXlateMode::BARE) {
+Walker *walker = tlb->getWalker();
+Fault fault = walker->startFunctional(
+context(), paddr, logBytes, BaseTLB::Read);
+if (fault != NoFault)
+return false;
+}
+return true;
+}
+
 return context()->getProcessPtr()->pTable->lookup(va) != nullptr;
 }


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Gerrit-Branch: develop
Gerrit-Change-Id: I78b37db43fbb16d4dafa74294117e8beba62f903
Gerrit-Change-Number: 26985
Gerrit-PatchSet: 9
Gerrit-Owner: Nils Asmussen 
Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nils Asmussen 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fixed read of {M,S,U}TVEC.

2020-04-29 Thread Nils Asmussen (Gerrit) via gem5-dev
Nils Asmussen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25648 )


Change subject: arch-riscv: fixed read of {M,S,U}TVEC.
..

arch-riscv: fixed read of {M,S,U}TVEC.

As stated in 4.1.4 of the privileged ISA manual, the BASE field in the
STVEC register contains the bits [SXLEN-1:2] of the base address, not
the base address shifted left by 2.

Change-Id: I799ec0dc1cbd7b271b91b53adb033a5d1ca3306f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25648
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/arch/riscv/faults.cc
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index 2296992..2ef8df4 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -130,7 +130,7 @@
 tc->setMiscReg(MISCREG_STATUS, status);

 // Set PC to fault handler address
-Addr addr = tc->readMiscReg(tvec) >> 2;
+Addr addr = mbits(tc->readMiscReg(tvec), 63, 2);
 if (isInterrupt() && bits(tc->readMiscReg(tvec), 1, 0) == 1)
 addr += 4 * _code;
 pcState.set(addr);

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I799ec0dc1cbd7b271b91b53adb033a5d1ca3306f
Gerrit-Change-Number: 25648
Gerrit-PatchSet: 10
Gerrit-Owner: Nils Asmussen 
Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nils Asmussen 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: implement sfence.vma to flush TLBs.

2020-04-29 Thread Nils Asmussen (Gerrit) via gem5-dev
C);
-}
-}}, IsReturn);
-0x302: mret({{
+NPC = xc->readMiscReg(MISCREG_UEPC);
+}}, IsReturn);
+}
+0x8: decode RS2 {
+0x2: sret({{
+if (xc->readMiscReg(MISCREG_PRV) == PRV_U) {
+fault = make_shared(
+"sret in user mode", machInst);
+NPC = NPC;
+} else {
+STATUS status = xc->readMiscReg(
+MISCREG_STATUS);
+xc->setMiscReg(MISCREG_PRV, status.spp);
+status.sie = status.spie;
+status.spie = 1;
+status.spp = PRV_U;
+xc->setMiscReg(MISCREG_STATUS, status);
+NPC = xc->readMiscReg(MISCREG_SEPC);
+}
+}}, IsReturn);
+}
+0x9: sfence_vma({{
+xc->tcBase()->getITBPtr()->demapPage(Rs1, Rs2);
+xc->tcBase()->getDTBPtr()->demapPage(Rs1, Rs2);
+}}, IsNonSpeculative, IsSerializeAfter, No_OpClass);
+0x18: mret({{
 if (xc->readMiscReg(MISCREG_PRV) != PRV_M) {
 fault = make_shared(
 "mret at lower privilege",  
machInst);


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Gerrit-Change-Id: I424123d3c94c9673269f922cd6755f0bbf5b6cc0
Gerrit-Change-Number: 26984
Gerrit-PatchSet: 9
Gerrit-Owner: Nils Asmussen 
Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nils Asmussen 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs: added bare metal FS support for RISC-V.

2020-04-29 Thread Nils Asmussen (Gerrit) via gem5-dev
Nils Asmussen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26989 )


Change subject: configs: added bare metal FS support for RISC-V.
..

configs: added bare metal FS support for RISC-V.

Change-Id: Id412186d868680b9af97503a5337fc394fd84f68
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26989
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M configs/common/FSConfig.py
M configs/example/fs.py
2 files changed, 31 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 7fc5557..d49ad78 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -1,4 +1,5 @@
 # Copyright (c) 2010-2012, 2015-2019 ARM Limited
+# Copyright (c) 2020 Barkhausen Institut
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -48,6 +49,7 @@

 # Populate to reflect supported os types per target ISA
 os_types = { 'mips'  : [ 'linux' ],
+ 'riscv' : [ 'linux' ], # TODO that's a lie
  'sparc' : [ 'linux' ],
  'x86'   : [ 'linux' ],
  'arm'   : [ 'linux',
@@ -614,6 +616,28 @@
 self.workload.command_line = fillInCmdline(mdesc, cmdline)
 return self

+def makeBareMetalRiscvSystem(mem_mode, mdesc=None, cmdline=None):
+self = System()
+if not mdesc:
+# generic system
+mdesc = SysConfig()
+self.mem_mode = mem_mode
+self.mem_ranges = [AddrRange(mdesc.mem())]
+
+self.workload = RiscvBareMetal()
+
+self.iobus = IOXBar()
+self.membus = MemBus()
+
+self.bridge = Bridge(delay='50ns')
+self.bridge.master = self.iobus.slave
+self.bridge.slave = self.membus.master
+# Sv39 has 56 bit physical addresses; use the upper 8 bit for the IO  
space

+IO_address_space_base = 0x00FF
+self.bridge.ranges = [AddrRange(IO_address_space_base, Addr.max)]
+
+self.system_port = self.membus.slave
+return self

 def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
 self = Root(full_system = full_system)
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 5264aa5..6643d35 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -1,4 +1,5 @@
 # Copyright (c) 2010-2013, 2016, 2019 ARM Limited
+# Copyright (c) 2020 Barkhausen Institut
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -82,6 +83,9 @@
 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0],  
cmdline=cmdline)

 elif buildEnv['TARGET_ISA'] == "sparc":
 test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
+elif buildEnv['TARGET_ISA'] == "riscv":
+test_sys = makeBareMetalRiscvSystem(test_mem_mode, bm[0],
+cmdline=cmdline)
 elif buildEnv['TARGET_ISA'] == "x86":
 test_sys = makeLinuxX86System(test_mem_mode, np, bm[0],  
options.ruby,

   cmdline=cmdline)
@@ -123,7 +127,9 @@
  voltage_domain =
  test_sys.cpu_voltage_domain)

-if options.kernel is not None:
+if buildEnv['TARGET_ISA'] == 'riscv':
+test_sys.workload.bootloader = options.kernel
+elif options.kernel is not None:
 test_sys.workload.object_file = binary(options.kernel)

 if options.script is not None:

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id412186d868680b9af97503a5337fc394fd84f68
Gerrit-Change-Number: 26989
Gerrit-PatchSet: 10
Gerrit-Owner: Nils Asmussen 
Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nils Asmussen 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fixed formatting.

2020-04-29 Thread Nils Asmussen (Gerrit) via gem5-dev
Nils Asmussen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26986 )


Change subject: arch-riscv: fixed formatting.
..

arch-riscv: fixed formatting.

Change-Id: I134993a4aced07e75bf62fec56081b0f9d8fc18c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26986
Tested-by: kokoro 
Tested-by: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/arch/riscv/isa.hh
1 file changed, 3 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass
  Gem5 Cloud Project GCB service account: Regressions pass



diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 4bf0fdb..9d34242 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -4,6 +4,7 @@
  * Copyright (c) 2014 Sven Karlsson
  * Copyright (c) 2016 RISC-V Foundation
  * Copyright (c) 2016 The University of Virginia
+ * Copyright (c) 2020 Barkhausen Institut
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -52,7 +53,8 @@
 namespace RiscvISA
 {

-enum PrivilegeMode {
+enum PrivilegeMode
+{
 PRV_U = 0,
 PRV_S = 1,
 PRV_M = 3

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Gerrit-Change-Id: I134993a4aced07e75bf62fec56081b0f9d8fc18c
Gerrit-Change-Number: 26986
Gerrit-PatchSet: 9
Gerrit-Owner: Nils Asmussen 
Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nils Asmussen 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: make sure only supported modes can be set in SATP.

2020-04-29 Thread Nils Asmussen (Gerrit) via gem5-dev
Nils Asmussen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26983 )


Change subject: arch-riscv: make sure only supported modes can be set in  
SATP.

..

arch-riscv: make sure only supported modes can be set in SATP.

Change-Id: I37c67e491d64bf03d1125e23db28611fa0b16038
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26983
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/arch/riscv/isa.cc
1 file changed, 14 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index ca3358e..a71733b 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -1,6 +1,7 @@
 /*
  * Copyright (c) 2016 RISC-V Foundation
  * Copyright (c) 2016 The University of Virginia
+ * Copyright (c) 2020 Barkhausen Institut
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -34,6 +35,7 @@
 #include 

 #include "arch/riscv/interrupts.hh"
+#include "arch/riscv/pagetable.hh"
 #include "arch/riscv/registers.hh"
 #include "base/bitfield.hh"
 #include "cpu/base.hh"
@@ -204,6 +206,18 @@
 ic->setIE(val);
 }
 break;
+  case MISCREG_SATP:
+{
+// we only support bare and Sv39 mode; setting a different  
mode

+// shall have no effect (see 4.1.12 in priv ISA manual)
+SATP cur_val = readMiscRegNoEffect(misc_reg);
+SATP new_val = val;
+if (new_val.mode != AddrXlateMode::BARE &&
+new_val.mode != AddrXlateMode::SV39)
+new_val.mode = cur_val.mode;
+setMiscRegNoEffect(misc_reg, new_val);
+}
+break;
   default:
 setMiscRegNoEffect(misc_reg, val);
 }

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Gerrit-Change-Id: I37c67e491d64bf03d1125e23db28611fa0b16038
Gerrit-Change-Number: 26983
Gerrit-PatchSet: 9
Gerrit-Owner: Nils Asmussen 
Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
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Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: print information about faults.

2020-03-26 Thread Nils Asmussen (Gerrit)
Nils Asmussen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25646 )


Change subject: arch-riscv: print information about faults.
..

arch-riscv: print information about faults.

Change-Id: Ic69b788d508bab1044b693860c7d942963bed3f9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25646
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/arch/riscv/faults.cc
1 file changed, 5 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index 1d48d85..2296992 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -2,6 +2,7 @@
  * Copyright (c) 2016 RISC-V Foundation
  * Copyright (c) 2016 The University of Virginia
  * Copyright (c) 2018 TU Dresden
+ * Copyright (c) 2020 Barkhausen Institut
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -36,6 +37,7 @@
 #include "arch/riscv/utility.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
+#include "debug/Fault.hh"
 #include "sim/debug.hh"
 #include "sim/full_system.hh"

@@ -53,6 +55,9 @@
 {
 PCState pcState = tc->pcState();

+DPRINTFS(Fault, tc->getCpuPtr(), "Fault (%s) at PC: %s\n",
+ name(), pcState);
+
 if (FullSystem) {
 PrivilegeMode pp = (PrivilegeMode)tc->readMiscReg(MISCREG_PRV);
 PrivilegeMode prv = PRV_M;

--
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Gerrit-Change-Number: 25646
Gerrit-PatchSet: 7
Gerrit-Owner: Nils Asmussen 
Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Gem5 Cloud Project GCB service account  
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Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: added support for pseudo instructions.

2020-03-26 Thread Nils Asmussen (Gerrit)
a/src/arch/riscv/utility.hh b/src/arch/riscv/utility.hh
index 7dcd5e2..32eaff6 100644
--- a/src/arch/riscv/utility.hh
+++ b/src/arch/riscv/utility.hh
@@ -2,6 +2,7 @@
  * Copyright (c) 2013 ARM Limited
  * Copyright (c) 2014-2015 Sven Karlsson
  * Copyright (c) 2018 TU Dresden
+ * Copyright (c) 2020 Barkhausen Institut
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -109,7 +110,14 @@
 inline uint64_t
 getArgument(ThreadContext *tc, int , uint16_t size, bool fp)
 {
-return 0;
+panic_if(fp, "getArgument(): Floating point arguments not  
implemented");
+panic_if(size != 8, "getArgument(): Can only handle 64-bit  
arguments.");

+panic_if(number >= ArgumentRegs.size(),
+ "getArgument(): Don't know how to handle stack arguments");
+
+// The first 8 integer arguments are passed in registers, the rest
+// are passed on the stack.
+return tc->readIntReg(ArgumentRegs[number]);
 }

 inline void

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: make sure only supported modes can be set in SATP.

2020-03-21 Thread Nils Asmussen (Gerrit)
Nils Asmussen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26983 )



Change subject: arch-riscv: make sure only supported modes can be set in  
SATP.

..

arch-riscv: make sure only supported modes can be set in SATP.

Change-Id: I37c67e491d64bf03d1125e23db28611fa0b16038
---
M src/arch/riscv/isa.cc
1 file changed, 14 insertions(+), 0 deletions(-)



diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index ca3358e..a71733b 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -1,6 +1,7 @@
 /*
  * Copyright (c) 2016 RISC-V Foundation
  * Copyright (c) 2016 The University of Virginia
+ * Copyright (c) 2020 Barkhausen Institut
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -34,6 +35,7 @@
 #include 

 #include "arch/riscv/interrupts.hh"
+#include "arch/riscv/pagetable.hh"
 #include "arch/riscv/registers.hh"
 #include "base/bitfield.hh"
 #include "cpu/base.hh"
@@ -204,6 +206,18 @@
 ic->setIE(val);
 }
 break;
+  case MISCREG_SATP:
+{
+// we only support bare and Sv39 mode; setting a different  
mode

+// shall have no effect (see 4.1.12 in priv ISA manual)
+SATP cur_val = readMiscRegNoEffect(misc_reg);
+SATP new_val = val;
+if (new_val.mode != AddrXlateMode::BARE &&
+new_val.mode != AddrXlateMode::SV39)
+new_val.mode = cur_val.mode;
+setMiscRegNoEffect(misc_reg, new_val);
+}
+break;
   default:
 setMiscRegNoEffect(misc_reg, val);
 }

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv, configs: add support for the walker cache.

2020-03-21 Thread Nils Asmussen (Gerrit)
Nils Asmussen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26988 )



Change subject: arch-riscv,configs: add support for the walker cache.
..

arch-riscv,configs: add support for the walker cache.

Change-Id: I19b1dd9e3c55c433c897988d36e6715017273c66
---
M configs/common/CacheConfig.py
M configs/common/Caches.py
M src/cpu/BaseCPU.py
3 files changed, 8 insertions(+), 5 deletions(-)



diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index 91087fb..05c38e0 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -1,4 +1,5 @@
 # Copyright (c) 2012-2013, 2015-2016 ARM Limited
+# Copyright (c) 2020 Barkhausen Institut
 # All rights reserved
 #
 # The license below extends only to copyright in the software and shall
@@ -79,7 +80,7 @@
 dcache_class, icache_class, l2_cache_class, walk_cache_class = \
 L1_DCache, L1_ICache, L2Cache, None

-if buildEnv['TARGET_ISA'] == 'x86':
+if buildEnv['TARGET_ISA'] in ['x86', 'riscv']:
 walk_cache_class = PageTableWalkerCache

 # Set the cache line size of the system
@@ -181,7 +182,7 @@
 # on these names.  For simplicity, we would advise configuring
 # it to use this naming scheme; if this isn't possible, change
 # the names below.
-if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
+if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']:
 system.cpu[i].addPrivateSplitL1Caches(
 ExternalCache("cpu%d.icache" % i),
 ExternalCache("cpu%d.dcache" % i),
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 123fea4..77213e8 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -1,4 +1,5 @@
 # Copyright (c) 2012 ARM Limited
+# Copyright (c) 2020 Barkhausen Institut
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -92,7 +93,7 @@
 tgts_per_mshr = 12

 # the x86 table walker actually writes to the table-walker cache
-if buildEnv['TARGET_ISA'] == 'x86':
+if buildEnv['TARGET_ISA'] in ['x86', 'riscv']:
 is_read_only = False
 else:
 is_read_only = True
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 53652bf..67d95d0 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -1,4 +1,5 @@
 # Copyright (c) 2012-2013, 2015-2017 ARM Limited
+# Copyright (c) 2020 Barkhausen Institut
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -181,7 +182,7 @@
 dcache_port = MasterPort("Data Port")
 _cached_ports = ['icache_port', 'dcache_port']

-if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
+if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']:
 _cached_ports += ["itb.walker.port", "dtb.walker.port"]

 _uncached_slave_ports = []
@@ -216,7 +217,7 @@
 self.icache_port = ic.cpu_side
 self.dcache_port = dc.cpu_side
 self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
-if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
+if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']:
 if iwc and dwc:
 self.itb_walker_cache = iwc
 self.dtb_walker_cache = dwc

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: removed unused files.

2020-03-21 Thread Nils Asmussen (Gerrit)
OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __ARCH_RISCV_BARE_METAL_SYSTEM_HH__
-#define __ARCH_RISCV_BARE_METAL_SYSTEM_HH__
-
-#include "arch/riscv/system.hh"
-#include "params/BareMetalRiscvSystem.hh"
-
-class BareMetalRiscvSystem : public RiscvSystem
-{
-  protected:
-ObjectFile* bootloader;
-
-  public:
-typedef BareMetalRiscvSystemParams Params;
-BareMetalRiscvSystem(Params *p);
-~BareMetalRiscvSystem();
-
-// initialize the system
-virtual void initState();
-};
-
-#endif // __ARCH_RISCV_BARE_METAL_SYSTEM_HH__
-

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fixed formatting.

2020-03-21 Thread Nils Asmussen (Gerrit)
Nils Asmussen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26986 )



Change subject: arch-riscv: fixed formatting.
..

arch-riscv: fixed formatting.

Change-Id: I134993a4aced07e75bf62fec56081b0f9d8fc18c
---
M src/arch/riscv/isa.hh
1 file changed, 3 insertions(+), 1 deletion(-)



diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 4bf0fdb..9d34242 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -4,6 +4,7 @@
  * Copyright (c) 2014 Sven Karlsson
  * Copyright (c) 2016 RISC-V Foundation
  * Copyright (c) 2016 The University of Virginia
+ * Copyright (c) 2020 Barkhausen Institut
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -52,7 +53,8 @@
 namespace RiscvISA
 {

-enum PrivilegeMode {
+enum PrivilegeMode
+{
 PRV_U = 0,
 PRV_S = 1,
 PRV_M = 3

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: implement sfence.vma to flush TLBs.

2020-03-21 Thread Nils Asmussen (Gerrit)
 if (xc->readMiscReg(MISCREG_PRV) == PRV_U) {
+fault = make_shared(
+"sret in user mode", machInst);
+NPC = NPC;
+} else {
+STATUS status = xc->readMiscReg(
+MISCREG_STATUS);
+xc->setMiscReg(MISCREG_PRV, status.spp);
+status.sie = status.spie;
+status.spie = 1;
+status.spp = PRV_U;
+xc->setMiscReg(MISCREG_STATUS, status);
+NPC = xc->readMiscReg(MISCREG_SEPC);
+}
+}}, IsReturn);
+}
+0x9: sfence_vma({{
+xc->tcBase()->getITBPtr()->demapPage(Rs1, Rs2);
+xc->tcBase()->getDTBPtr()->demapPage(Rs1, Rs2);
+}}, IsNonSpeculative, IsSerializeAfter, No_OpClass);
+0x18: mret({{
 if (xc->readMiscReg(MISCREG_PRV) != PRV_M) {
 fault = make_shared(
 "mret at lower privilege",  
machInst);


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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv, configs: added bare metal FS support.

2020-03-21 Thread Nils Asmussen (Gerrit)
Nils Asmussen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26989 )



Change subject: arch-riscv,configs: added bare metal FS support.
..

arch-riscv,configs: added bare metal FS support.

Change-Id: Id412186d868680b9af97503a5337fc394fd84f68
---
M configs/common/FSConfig.py
M configs/example/fs.py
2 files changed, 31 insertions(+), 1 deletion(-)



diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 3ae00ad..f03e514 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -1,4 +1,5 @@
 # Copyright (c) 2010-2012, 2015-2019 ARM Limited
+# Copyright (c) 2020 Barkhausen Institut
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -48,6 +49,7 @@

 # Populate to reflect supported os types per target ISA
 os_types = { 'mips'  : [ 'linux' ],
+ 'riscv' : [ 'linux' ], # TODO that's a lie
  'sparc' : [ 'linux' ],
  'x86'   : [ 'linux' ],
  'arm'   : [ 'linux',
@@ -626,6 +628,28 @@
 self.workload.command_line = fillInCmdline(mdesc, cmdline)
 return self

+def makeBareMetalRiscvSystem(mem_mode, mdesc=None, cmdline=None):
+self = RiscvSystem()
+if not mdesc:
+# generic system
+mdesc = SysConfig()
+self.mem_mode = mem_mode
+self.mem_ranges = [AddrRange(mdesc.mem())]
+
+self.workload = RiscvBareMetal()
+
+self.iobus = IOXBar()
+self.membus = MemBus()
+
+self.bridge = Bridge(delay='50ns')
+self.bridge.master = self.iobus.slave
+self.bridge.slave = self.membus.master
+# Sv39 has 56 bit physical addresses; use the upper 8 bit for the IO  
space

+IO_address_space_base = 0x00FF
+self.bridge.ranges = [AddrRange(IO_address_space_base, Addr.max)]
+
+self.system_port = self.membus.slave
+return self

 def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
 self = Root(full_system = full_system)
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 5264aa5..6643d35 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -1,4 +1,5 @@
 # Copyright (c) 2010-2013, 2016, 2019 ARM Limited
+# Copyright (c) 2020 Barkhausen Institut
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -82,6 +83,9 @@
 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0],  
cmdline=cmdline)

 elif buildEnv['TARGET_ISA'] == "sparc":
 test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
+elif buildEnv['TARGET_ISA'] == "riscv":
+test_sys = makeBareMetalRiscvSystem(test_mem_mode, bm[0],
+cmdline=cmdline)
 elif buildEnv['TARGET_ISA'] == "x86":
 test_sys = makeLinuxX86System(test_mem_mode, np, bm[0],  
options.ruby,

   cmdline=cmdline)
@@ -123,7 +127,9 @@
  voltage_domain =
  test_sys.cpu_voltage_domain)

-if options.kernel is not None:
+if buildEnv['TARGET_ISA'] == 'riscv':
+test_sys.workload.bootloader = options.kernel
+elif options.kernel is not None:
 test_sys.workload.object_file = binary(options.kernel)

 if options.script is not None:

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: implement RemoteGDB::acc for FS mode.

2020-03-21 Thread Nils Asmussen (Gerrit)
Nils Asmussen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26985 )



Change subject: arch-riscv: implement RemoteGDB::acc for FS mode.
..

arch-riscv: implement RemoteGDB::acc for FS mode.

Change-Id: I78b37db43fbb16d4dafa74294117e8beba62f903
---
M src/arch/riscv/remote_gdb.cc
1 file changed, 22 insertions(+), 1 deletion(-)



diff --git a/src/arch/riscv/remote_gdb.cc b/src/arch/riscv/remote_gdb.cc
index 16b4585..7da666d 100644
--- a/src/arch/riscv/remote_gdb.cc
+++ b/src/arch/riscv/remote_gdb.cc
@@ -2,6 +2,7 @@
  * Copyright 2015 LabWare
  * Copyright 2014 Google, Inc.
  * Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2020 Barkhausen Institut
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -133,7 +134,9 @@

 #include 

+#include "arch/riscv/pagetable_walker.hh"
 #include "arch/riscv/registers.hh"
+#include "arch/riscv/tlb.hh"
 #include "cpu/thread_state.hh"
 #include "debug/GDBAcc.hh"
 #include "mem/page_table.hh"
@@ -150,7 +153,25 @@
 bool
 RemoteGDB::acc(Addr va, size_t len)
 {
-panic_if(FullSystem, "acc not implemented for RISCV FS!");
+if (FullSystem)
+{
+TLB *tlb = dynamic_cast(context()->getDTBPtr());
+unsigned logBytes;
+Addr paddr = va;
+
+PrivilegeMode pmode = tlb->getMemPriv(context(), BaseTLB::Read);
+SATP satp = context()->readMiscReg(MISCREG_SATP);
+if (pmode != PrivilegeMode::PRV_M &&
+satp.mode != AddrXlateMode::BARE) {
+Walker *walker = tlb->getWalker();
+Fault fault = walker->startFunctional(
+context(), paddr, logBytes, BaseTLB::Read);
+if (fault != NoFault)
+return false;
+}
+return true;
+}
+
 return context()->getProcessPtr()->pTable->lookup(va) != nullptr;
 }


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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv, tests: run p tests.

2020-02-24 Thread Nils Asmussen (Gerrit)
_tests += $(rv64si_p_tests)

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: report that we don't have debugging support.

2020-02-24 Thread Nils Asmussen (Gerrit)
Nils Asmussen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25659 )



Change subject: arch-riscv: report that we don't have debugging support.
..

arch-riscv: report that we don't have debugging support.

According to the debugging spec (page 47), a debugger can test which
triggers are enabled by writing 0 to TSELECT and reading it back. If a
different value is read, the trigger is not supported.

Therefore, we currently always set a different value to indicate that
we do not support any triggers.

Change-Id: If222e913c4517adb2da4f6f0ffeedb4e4808a586
---
M src/arch/riscv/isa.cc
1 file changed, 10 insertions(+), 0 deletions(-)



diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 9c5e302..2c5ef14 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -205,6 +205,9 @@
   (1ULL << FS_OFFSET);
 miscRegFile[MISCREG_MCOUNTEREN] = 0x7;
 miscRegFile[MISCREG_SCOUNTEREN] = 0x7;
+// don't set it to zero; software may try to determine the supported
+// triggers, starting at zero. simply set a different value here.
+miscRegFile[MISCREG_TSELECT] = 1;
 }

 bool
@@ -364,6 +367,13 @@
 setMiscRegNoEffect(misc_reg, new_val);
 }
 break;
+  case MISCREG_TSELECT:
+{
+// we don't support debugging, so always set a different  
value

+// than written
+setMiscRegNoEffect(misc_reg, val + 1);
+}
+break;
   case MISCREG_ISA:
 {
 auto cur_val = readMiscRegNoEffect(misc_reg);

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv, tests: improved run-tests.py.

2020-02-24 Thread Nils Asmussen (Gerrit)
u_type
 job_names.append(test_name)
-job_cmds.append([gem5_bin,
- '-d', 'm5out/' + test_name,
- '--listener-mode', 'off',
- config,
- '-m', str(args.max_tick),
- '--cpu-type', model,
- '-n', str(args.num_cpus),
- '-c', test_dir + '/' + test,
- '--ruby' if args.ruby else '--caches',
-])
+job_cmds.append([test, args.cpu_type])
+  else:
+for model in cpu_models:
+  test_name = test + '-' + model
+  job_names.append(test_name)
+  job_cmds.append([test, model])

 # execute all jobs
-job_pool = Pool(processes = n_tests)
-job_outputs = job_pool.map(subprocess.call, job_cmds)
+job_pool = Pool()
+job_outputs = []
+try:
+  total = len(job_cmds)
+  for r in job_pool.imap(run_test, job_cmds):
+job_outputs.append(r)
+print("\rRunning tests... [{}/{}]".format(len(job_outputs), total)),
+sys.stdout.flush()
+  print("\rRunning tests... [{}/{}]".format(len(job_outputs), total))
+except KeyboardInterrupt:
+  job_pool.terminate()
+  job_pool.join()
 job_pool.close()

-# process job outputs
-file = open(test_summary_out, "w")
+if args.test is None:
+  # process job outputs
+  file = open(test_summary_out, "w")

-job_outputs = zip(job_names, job_outputs)
-for entry in job_outputs:
-  # a negative return value indicates that the job was terminated
-  # by a signal
-  # a positive return value indicates that the job exited with a return
-  # value
-  if entry[1] < 0:
-file.write("%-50s failed - signal = %d\n" % (entry[0], -1 * entry[1]))
-  elif entry[1] > 0:
-file.write("%-50s failed - status = %d\n" % (entry[0], entry[1]))
-  else:
-file.write("%-50s passed\n" % (entry[0]))
+  job_outputs = zip(job_names, job_outputs)
+  for entry in job_outputs:
+# a negative return value indicates that the job was terminated
+# by a signal
+# a positive return value indicates that the job exited with a return
+# value
+if entry[1] < 0:
+  file.write("%-50s failed - signal = %d\n" % (entry[0], -1 *  
entry[1]))

+elif entry[1] > 0:
+  file.write("%-50s failed - status = %d\n" % (entry[0], entry[1]))
+else:
+  file.write("%-50s passed\n" % (entry[0]))

-file.close()
+  file.close()
+else:
+  print("\nResults:")
+  print(zip(job_names, job_outputs))

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fault on mstatus accesses from lower privilege modes.

2020-02-24 Thread Nils Asmussen (Gerrit)
Nils Asmussen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25652 )



Change subject: arch-riscv: fault on mstatus accesses from lower privilege  
modes.

..

arch-riscv: fault on mstatus accesses from lower privilege modes.

Change-Id: If2e35445770eaa52f5af6f9ef02fb5e11bef8da4
---
M src/arch/riscv/isa/formats/standard.isa
1 file changed, 13 insertions(+), 0 deletions(-)



diff --git a/src/arch/riscv/isa/formats/standard.isa  
b/src/arch/riscv/isa/formats/standard.isa

index a6c6e1c..7ec9484 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -2,6 +2,7 @@

 // Copyright (c) 2015 RISC-V Foundation
 // Copyright (c) 2016-2017 The University of Virginia
+// Copyright (c) 2020 Barkhausen Institut
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -304,6 +305,18 @@
 olddata = xc->readMiscReg(MISCREG_FFLAGS) |
   (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
 break;
+  case CSR_MSTATUS: {
+auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
+if (pm != PrivilegeMode::PRV_M) {
+std::string error = csprintf(
+"MSTATUS is only accessibly in machine mode\n");
+fault = make_shared(error, machInst);
+olddata = 0;
+}
+else
+olddata = xc->readMiscReg(CSRData.at(csr).physIndex);
+break;
+  }
   default:
 if (CSRData.find(csr) != CSRData.end()) {
 olddata = xc->readMiscReg(CSRData.at(csr).physIndex);

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: added fullsystem support.

2020-02-24 Thread Nils Asmussen (Gerrit)
Nils Asmussen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25647 )



Change subject: arch-riscv: added fullsystem support.
..

arch-riscv: added fullsystem support.

That is, RISC-V has now a TLB and page table walker for Sv39 paging
according to the privileged ISA 1.11. Additionally, the instruction
sfence.vma is implemented to invalidate TLB entries accordingly.

The page table walker and parts of the TLB are based on x86 (the code
duplication of the page table walkers will be reduced by a separate
commit).

Change-Id: I5e29683bdd40c0d32c06e4d75a8382bf313f2086
---
M configs/common/CacheConfig.py
M configs/common/Caches.py
M configs/common/FSConfig.py
M configs/example/fs.py
M src/arch/riscv/RiscvTLB.py
M src/arch/riscv/SConscript
M src/arch/riscv/insts/standard.cc
M src/arch/riscv/insts/standard.hh
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/pagetable.cc
M src/arch/riscv/pagetable.hh
A src/arch/riscv/pagetable_walker.cc
A src/arch/riscv/pagetable_walker.hh
M src/arch/riscv/remote_gdb.cc
M src/arch/riscv/tlb.cc
M src/arch/riscv/tlb.hh
A src/arch/riscv/vtophys.cc
M src/arch/riscv/vtophys.hh
M src/cpu/BaseCPU.py
21 files changed, 1,488 insertions(+), 424 deletions(-)



diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index ff2f0da..bf8e376 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -1,4 +1,5 @@
 # Copyright (c) 2012-2013, 2015-2016 ARM Limited
+# Copyright (c) 2020 Barkhausen Institut
 # All rights reserved
 #
 # The license below extends only to copyright in the software and shall
@@ -79,7 +80,7 @@
 dcache_class, icache_class, l2_cache_class, walk_cache_class = \
 L1_DCache, L1_ICache, L2Cache, None

-if buildEnv['TARGET_ISA'] == 'x86':
+if buildEnv['TARGET_ISA'] in ['x86', 'riscv']:
 walk_cache_class = PageTableWalkerCache

 # Set the cache line size of the system
@@ -181,7 +182,7 @@
 # on these names.  For simplicity, we would advise configuring
 # it to use this naming scheme; if this isn't possible, change
 # the names below.
-if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
+if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']:
 system.cpu[i].addPrivateSplitL1Caches(
 ExternalCache("cpu%d.icache" % i),
 ExternalCache("cpu%d.dcache" % i),
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 123fea4..77213e8 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -1,4 +1,5 @@
 # Copyright (c) 2012 ARM Limited
+# Copyright (c) 2020 Barkhausen Institut
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -92,7 +93,7 @@
 tgts_per_mshr = 12

 # the x86 table walker actually writes to the table-walker cache
-if buildEnv['TARGET_ISA'] == 'x86':
+if buildEnv['TARGET_ISA'] in ['x86', 'riscv']:
 is_read_only = False
 else:
 is_read_only = True
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index c200e61..fa7a86d 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -1,4 +1,5 @@
 # Copyright (c) 2010-2012, 2015-2019 ARM Limited
+# Copyright (c) 2020 Barkhausen Institut
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -48,6 +49,7 @@

 # Populate to reflect supported os types per target ISA
 os_types = { 'mips'  : [ 'linux' ],
+ 'riscv' : [ 'linux' ], # TODO that's a lie
  'sparc' : [ 'linux' ],
  'x86'   : [ 'linux' ],
  'arm'   : [ 'linux',
@@ -604,6 +606,26 @@
 self.boot_osflags = fillInCmdline(mdesc, cmdline)
 return self

+def makeBareMetalRiscvSystem(mem_mode, mdesc=None, cmdline=None):
+self = BareMetalRiscvSystem()
+if not mdesc:
+# generic system
+mdesc = SysConfig()
+self.mem_mode = mem_mode
+self.mem_ranges = [AddrRange(mdesc.mem())]
+
+self.iobus = IOXBar()
+self.membus = MemBus()
+
+self.bridge = Bridge(delay='50ns')
+self.bridge.master = self.iobus.slave
+self.bridge.slave = self.membus.master
+# Sv39 has 56 bit physical addresses; use the upper 8 bit for the IO  
space

+IO_address_space_base = 0x00FF
+self.bridge.ranges = [AddrRange(IO_address_space_base, Addr.max)]
+
+self.system_port = self.membus.slave
+return self

 def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
 self = Root(full_system = full_system)
diff --git a/configs/example/fs.py b/configs/example/fs.py
index bf68325..f3627f8 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -1,4 +1,5 @@
 # Copyright (c) 2010-2013, 2016, 2019 ARM Limited
+# 

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: added (un)serialization of miscRegFile.

2020-02-24 Thread Nils Asmussen (Gerrit)
Nils Asmussen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25650 )



Change subject: arch-riscv: added (un)serialization of miscRegFile.
..

arch-riscv: added (un)serialization of miscRegFile.

Change-Id: I127dbf4a6bb4a144eaee05a87495830dce82eb58
---
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
2 files changed, 18 insertions(+), 0 deletions(-)



diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index ba03f34..cfdea22 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -39,6 +39,7 @@
 #include "arch/riscv/registers.hh"
 #include "base/bitfield.hh"
 #include "cpu/base.hh"
+#include "debug/Checkpoint.hh"
 #include "debug/RiscvMisc.hh"
 #include "params/RiscvISA.hh"
 #include "sim/core.hh"
@@ -357,6 +358,20 @@
 }
 }

+void
+ISA::serialize(CheckpointOut ) const
+{
+DPRINTF(Checkpoint, "Serializing Riscv Misc Registers\n");
+SERIALIZE_CONTAINER(miscRegFile);
+}
+
+void
+ISA::unserialize(CheckpointIn )
+{
+DPRINTF(Checkpoint, "Unserializing Riscv Misc Registers\n");
+UNSERIALIZE_CONTAINER(miscRegFile);
+}
+
 }

 RiscvISA::ISA *
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 9d34242..c56c45b 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -92,6 +92,9 @@

 void startup(ThreadContext *tc) {}

+void serialize(CheckpointOut ) const;
+void unserialize(CheckpointIn );
+
 /// Explicitly import the otherwise hidden startup
 using BaseISA::startup;


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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv, tests: merged changes from RISCV-test upstream repo.

2020-02-24 Thread Nils Asmussen (Gerrit)
ff );


+  # Verify that shifts ignore top 32 (using true 64-bit values)
+
+  TEST_RR_OP( 44, sraw, 0x12345678, 0x12345678, 0 );
+  TEST_RR_OP( 45, sraw, 0x01234567, 0x12345678, 4 );
+  TEST_RR_OP( 46, sraw, 0x92345678, 0x92345678, 0 );
+  TEST_RR_OP( 47, sraw, 0xf9234567, 0x92345678, 4 );
+
   #-
   # Source/Destination tests
   #-
diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64ui/srl.S  
b/tests/test-progs/asmtest/src/riscv/isa/rv64ui/srl.S

index c1e936a..5ee223f 100644
--- a/tests/test-progs/asmtest/src/riscv/isa/rv64ui/srl.S
+++ b/tests/test-progs/asmtest/src/riscv/isa/rv64ui/srl.S
@@ -38,7 +38,7 @@
   TEST_SRL( 15, 0x21212121, 14 );
   TEST_SRL( 16, 0x21212121, 31 );

-  # Verify that shifts only use bottom five bits
+  # Verify that shifts only use bottom six(rv64) or five(rv32) bits

   TEST_RR_OP( 17, srl, 0x21212121, 0x21212121,  
0xffc0 );
   TEST_RR_OP( 18, srl, 0x10909090, 0x21212121,  
0xffc1 );
diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64ui/srli.S  
b/tests/test-progs/asmtest/src/riscv/isa/rv64ui/srli.S

index 88ee8d2..3522957 100644
--- a/tests/test-progs/asmtest/src/riscv/isa/rv64ui/srli.S
+++ b/tests/test-progs/asmtest/src/riscv/isa/rv64ui/srli.S
@@ -17,26 +17,26 @@
   # Arithmetic tests
   #-

-#define TEST_SRL(n, v, a) \
+#define TEST_SRLI(n, v, a) \
   TEST_IMM_OP(n, srli, ((v) & ((1 << (__riscv_xlen-1) << 1) - 1)) >> (a),  
v, a)


-  TEST_SRL( 2,  0x8000, 0  );
-  TEST_SRL( 3,  0x8000, 1  );
-  TEST_SRL( 4,  0x8000, 7  );
-  TEST_SRL( 5,  0x8000, 14 );
-  TEST_SRL( 6,  0x8001, 31 );
+  TEST_SRLI( 2,  0x8000, 0  );
+  TEST_SRLI( 3,  0x8000, 1  );
+  TEST_SRLI( 4,  0x8000, 7  );
+  TEST_SRLI( 5,  0x8000, 14 );
+  TEST_SRLI( 6,  0x8001, 31 );

-  TEST_SRL( 7,  0x, 0  );
-  TEST_SRL( 8,  0x, 1  );
-  TEST_SRL( 9,  0x, 7  );
-  TEST_SRL( 10, 0x, 14 );
-  TEST_SRL( 11, 0x, 31 );
+  TEST_SRLI( 7,  0x, 0  );
+  TEST_SRLI( 8,  0x, 1  );
+  TEST_SRLI( 9,  0x, 7  );
+  TEST_SRLI( 10, 0x, 14 );
+  TEST_SRLI( 11, 0x, 31 );

-  TEST_SRL( 12, 0x21212121, 0  );
-  TEST_SRL( 13, 0x21212121, 1  );
-  TEST_SRL( 14, 0x21212121, 7  );
-  TEST_SRL( 15, 0x21212121, 14 );
-  TEST_SRL( 16, 0x21212121, 31 );
+  TEST_SRLI( 12, 0x21212121, 0  );
+  TEST_SRLI( 13, 0x21212121, 1  );
+  TEST_SRLI( 14, 0x21212121, 7  );
+  TEST_SRLI( 15, 0x21212121, 14 );
+  TEST_SRLI( 16, 0x21212121, 31 );

   #-
   # Source/Destination tests
diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64ui/srliw.S  
b/tests/test-progs/asmtest/src/riscv/isa/rv64ui/srliw.S

index a8b9fd7..471042f 100644
--- a/tests/test-progs/asmtest/src/riscv/isa/rv64ui/srliw.S
+++ b/tests/test-progs/asmtest/src/riscv/isa/rv64ui/srliw.S
@@ -35,6 +35,13 @@
   TEST_IMM_OP( 15, srliw, 0x8484, 0x21212121, 14 );
   TEST_IMM_OP( 16, srliw, 0x, 0x21212121, 31 );

+  # Verify that shifts ignore top 32 (using true 64-bit values)
+
+  TEST_IMM_OP( 44, srliw, 0x12345678, 0x12345678, 0 );
+  TEST_IMM_OP( 45, srliw, 0x01234567, 0x12345678, 4 );
+  TEST_IMM_OP( 46, srliw, 0x92345678, 0x92345678, 0 );
+  TEST_IMM_OP( 47, srliw, 0x09234567, 0x92345678, 4 );
+
   #-
   # Source/Destination tests
   #-
diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64ui/srlw.S  
b/tests/test-progs/asmtest/src/riscv/isa/rv64ui/srlw.S

index 24a492a..f0d1dae 100644
--- a/tests/test-progs/asmtest/src/riscv/isa/rv64ui/srlw.S
+++ b/tests/test-progs/asmtest/src/riscv/isa/rv64ui/srlw.S
@@ -43,6 +43,13 @@
   TEST_RR_OP( 20, srlw, 0x8484, 0x21212121,  
0xffee );
   TEST_RR_OP( 21, srlw, 0x, 0x21212121,  
0x );


+  # Verify that shifts ignore top 32 (using true 64-bit values)
+
+  TEST_RR_OP( 44, srlw, 0x12345678, 0x12345678, 0 );
+  TEST_RR_OP( 45, srlw, 0x01234567, 0x12345678, 4 );
+  TEST_RR_OP( 46, srlw, 0x92345678, 0x92345678, 0 );
+  TEST_RR_OP( 47, srlw, 0x09234567, 0x000092345678, 4 );
+
   #-
   # Sou

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: make accesses to CSRs SerializeAfter.

2020-02-24 Thread Nils Asmussen (Gerrit)
Nils Asmussen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25655 )



Change subject: arch-riscv: make accesses to CSRs SerializeAfter.
..

arch-riscv: make accesses to CSRs SerializeAfter.

According to page 57 in the RISC-V manual, CSR accesses "need to be
performed in program order with respect to those instructions whose
execution behavior is affected by the state of the accessed CSR".

Thus, we need to make them SerializeAfter to ensure that the following
instructions are executed with the potential changes to the CSR. In
theory, we could be smarter here by only considering write accesses to
CSRs and considering the following instructions, but for now we simply
serialize for every CSR access.

Change-Id: I69391fccaec31c34d944c55bac2f04d37947ebfe
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 6 insertions(+), 6 deletions(-)



diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 474e432..5de3eee 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -1842,27 +1842,27 @@
 0x1: csrrw({{
 Rd = data;
 data = Rs1;
-}}, IsNonSpeculative, No_OpClass);
+}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
 0x2: csrrs({{
 Rd = data;
 data |= Rs1;
-}}, IsNonSpeculative, No_OpClass);
+}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
 0x3: csrrc({{
 Rd = data;
 data &= ~Rs1;
-}}, IsNonSpeculative, No_OpClass);
+}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
 0x5: csrrwi({{
 Rd = data;
 data = uimm;
-}}, IsNonSpeculative, No_OpClass);
+}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
 0x6: csrrsi({{
 Rd = data;
 data |= uimm;
-}}, IsNonSpeculative, No_OpClass);
+}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
 0x7: csrrci({{
 Rd = data;
 data &= ~uimm;
-}}, IsNonSpeculative, No_OpClass);
+}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
 }
 }


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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv, tests: added .gitignore.

2020-02-24 Thread Nils Asmussen (Gerrit)
Nils Asmussen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25704 )



Change subject: arch-riscv,tests: added .gitignore.
..

arch-riscv,tests: added .gitignore.

Change-Id: I4377468acf906fbe1f3ca2baa5f0c2aa2941b501
---
A tests/test-progs/asmtest/.gitignore
1 file changed, 3 insertions(+), 0 deletions(-)



diff --git a/tests/test-progs/asmtest/.gitignore  
b/tests/test-progs/asmtest/.gitignore

new file mode 100644
index 000..efe07d4
--- /dev/null
+++ b/tests/test-progs/asmtest/.gitignore
@@ -0,0 +1,3 @@
+bin/*
+dump/*
+src/riscv/test-summary.out

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[gem5-dev] Change in gem5/gem5[develop]: tests: call sys.exit() on failure in Simulation::run.

2020-02-24 Thread Nils Asmussen (Gerrit)
Nils Asmussen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25662 )



Change subject: tests: call sys.exit() on failure in Simulation::run.
..

tests: call sys.exit() on failure in Simulation::run.

This patch is required for the p and v tests in the RISC-V test suite
to report success/failure.

Change-Id: Ic84255fc545f531402700c864010b4542d059c77
---
M configs/common/Simulation.py
1 file changed, 2 insertions(+), 0 deletions(-)



diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py
index eadc8de..da70086 100644
--- a/configs/common/Simulation.py
+++ b/configs/common/Simulation.py
@@ -1,4 +1,5 @@
 # Copyright (c) 2012-2013 ARM Limited
+# Copyright (c) 2020 Barkhausen Institut
 # All rights reserved
 #
 # The license below extends only to copyright in the software and shall
@@ -730,3 +731,4 @@

 if exit_event.getCode() != 0:
 print("Simulated exit code not 0! Exit code is",  
exit_event.getCode())

+sys.exit(exit_event.getCode())

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[gem5-dev] Change in gem5/gem5[develop]: base, sim: allow m5writeFile with stdout/stderr.

2020-02-24 Thread Nils Asmussen (Gerrit)
Nils Asmussen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25661 )



Change subject: base,sim: allow m5writeFile with stdout/stderr.
..

base,sim: allow m5writeFile with stdout/stderr.

If m5writeFile opens stdout/stderr, no file is registered in
OutputDirectory and thus we don't want to search for it on close.

In order to write multiple times to stdout/stderr in a reasonable way,
we also want to prevent seeking. Thus, don't seek if the offset is 0, in
which case this would be a noop anyway (we just opened the file without
append).

Finally, it is helpful for debugging if the stream is flushed on every
write.

Change-Id: I102f82dcd2c63420b6f3fe55d67f03c62349e69d
---
M src/base/output.cc
M src/sim/pseudo_inst.cc
2 files changed, 11 insertions(+), 2 deletions(-)



diff --git a/src/base/output.cc b/src/base/output.cc
index ec94a13..47b8aa7 100644
--- a/src/base/output.cc
+++ b/src/base/output.cc
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2015 ARM Limited
+ * Copyright (c) 2020 Barkhausen Institut
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -142,6 +143,11 @@
 void
 OutputDirectory::close(OutputStream *file)
 {
+if (file ==  || file == ) {
+file->stream()->flush();
+return;
+}
+
 auto i = files.find(file->name());
 if (i == files.end())
 fatal("Attempted to close an unregistred file stream");
diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index 3c369b0..c169d0d 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2010-2012, 2015, 2017 ARM Limited
+ * Copyright (c) 2020 Barkhausen Institut
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -413,8 +414,10 @@
 if (!os)
 panic("could not open file %s\n", filename);

-// seek to offset
-os->seekp(offset);
+if (offset != 0) {
+// seek to offset
+os->seekp(offset);
+}

 // copy out data and write to file
 char *buf = new char[len];

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv, arch-x86: moved common code into generic walker class.

2020-02-24 Thread Nils Asmussen (Gerrit)
Nils Asmussen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25660 )



Change subject: arch-riscv,arch-x86: moved common code into generic walker  
class.

..

arch-riscv,arch-x86: moved common code into generic walker class.

The basic structure of the page table walker, that is, loading PTEs in
multiple steps until the leaf PTE is found, support multiple walks at
the same time, handling sends and receives of packets, supporting timing
and functional walks, etc. is generic. Therefore, I've moved this code
into the generic ISA as a base class for the RISC-V and X86 page table
walker. Unfortunately, the ARM PT walker is very different, so that it
does not take advantage of the generic PT walker.

The ISA-specific page table walker only needs to implement the setup
of the walk, each step of the walk, and a couple of helper methods.

Change-Id: I45b7e8a365b32b49f1c34a5501f6b4b0d015d74e
---
M src/arch/generic/BaseTLB.py
M src/arch/generic/SConscript
A src/arch/generic/pagetable_walker.cc
A src/arch/generic/pagetable_walker.hh
M src/arch/riscv/RiscvTLB.py
M src/arch/riscv/SConscript
M src/arch/riscv/pagetable_walker.cc
M src/arch/riscv/pagetable_walker.hh
M src/arch/riscv/tlb.cc
M src/arch/x86/SConscript
M src/arch/x86/X86TLB.py
M src/arch/x86/pagetable_walker.cc
M src/arch/x86/pagetable_walker.hh
13 files changed, 820 insertions(+), 992 deletions(-)



diff --git a/src/arch/generic/BaseTLB.py b/src/arch/generic/BaseTLB.py
index 02776e6..7f5f53e 100644
--- a/src/arch/generic/BaseTLB.py
+++ b/src/arch/generic/BaseTLB.py
@@ -1,5 +1,6 @@
 # Copyright (c) 2008 The Hewlett-Packard Development Company
 # Copyright (c) 2018 Metempsy Technology Consulting
+# Copyright (c) 2020 Barkhausen Institut
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -26,7 +27,20 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 from m5.params import *
+from m5.proxy import *
+
 from m5.SimObject import SimObject
+from m5.objects.ClockedObject import ClockedObject
+
+class BasePagetableWalker(ClockedObject):
+type = 'BasePagetableWalker'
+cxx_class = 'BaseWalker'
+cxx_header = 'arch/generic/pagetable_walker.hh'
+abstract = True
+port = MasterPort("Port for the hardware table walker")
+system = Param.System(Parent.any, "system object")
+num_squash_per_cycle = Param.Unsigned(4,
+"Number of outstanding walks that can be squashed per cycle")

 class BaseTLB(SimObject):
 type = 'BaseTLB'
diff --git a/src/arch/generic/SConscript b/src/arch/generic/SConscript
index e3c2567..bc8811e 100644
--- a/src/arch/generic/SConscript
+++ b/src/arch/generic/SConscript
@@ -1,4 +1,5 @@
 # Copyright (c) 2016 ARM Limited
+# Copyright (c) 2020 Barkhausen Institut
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -48,5 +49,7 @@
 SimObject('BaseTLB.py')
 SimObject('ISACommon.py')

+DebugFlag('PageTableWalker', "Page table walker state machine debugging")
 DebugFlag('TLB')
 Source('pseudo_inst.cc')
+Source('pagetable_walker.cc')
diff --git a/src/arch/generic/pagetable_walker.cc  
b/src/arch/generic/pagetable_walker.cc

new file mode 100644
index 000..e6266b6
--- /dev/null
+++ b/src/arch/generic/pagetable_walker.cc
@@ -0,0 +1,418 @@
+/*
+ * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2020 Barkhausen Institut
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this 

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv, tests: run v tests.

2020-02-24 Thread Nils Asmussen (Gerrit)
Nils Asmussen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25707 )



Change subject: arch-riscv,tests: run v tests.
..

arch-riscv,tests: run v tests.

This commit enables the v tests (using virtual memory) in the test
suite. As for the p tests, success/failure is reported by pseudo
instructions. Additionally, failed asserts are reported via the
m5writeFile pseudo instruction.

Change-Id: I4fcb8b9cdf0d58460fb90de869fba8c6c8c428a1
---
M tests/test-progs/asmtest/src/riscv/Makefile
M tests/test-progs/asmtest/src/riscv/env/v/vm.c
2 files changed, 22 insertions(+), 13 deletions(-)



diff --git a/tests/test-progs/asmtest/src/riscv/Makefile  
b/tests/test-progs/asmtest/src/riscv/Makefile

index 7b54251..4a22ae5 100644
--- a/tests/test-progs/asmtest/src/riscv/Makefile
+++ b/tests/test-progs/asmtest/src/riscv/Makefile
@@ -55,6 +55,11 @@
 	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(src_dir)/../env/ps  
-I$(src_dir)/macros/scalar -I$(src_dir)/macros/mt  
-T$(src_dir)/../env/ps/link.ld $$< -o $(bin_dir)/$$@

 $(1)_ps_env_tests += $$($(1)_ps_tests)

+$$($(1)_v_tests): $(1)-v-%: $(1)/%.S
+   mkdir -p $(bin_dir)
+	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -DENTROPY=0x$$(shell echo \$$@ |  
md5sum | cut -c 1-7) -std=gnu99 -O2 -I$(src_dir)/../env/v  
-I$(src_dir)/macros/scalar -T$(src_dir)/../env/v/link.ld  
$(src_dir)/../env/v/entry.S $(src_dir)/../env/v/*.c $$< -o $(bin_dir)/$$@

+$(1)_v_env_tests += $$($(1)_v_tests)
+
 $(1)_tests_dump = $$(addsuffix .dump, $$($(1)_tests))

 $(1): $$($(1)_tests_dump)
@@ -80,15 +85,18 @@

 p_env_tests_dump = $(addsuffix .dump, $(p_env_tests))
 ps_env_tests_dump = $(addsuffix .dump, $(ps_env_tests))
+v_env_tests_dump = $(addsuffix .dump, $(v_env_tests))

 #
 # Targets

-all:   p ps
+all:   p ps v
 # build tests with p environment
 p: $(p_env_tests_dump)
 # build tests with ps environment
 ps:$(ps_env_tests_dump)
+# build tests with v environment
+v: $(v_env_tests_dump)

 #
 # Clean up
diff --git a/tests/test-progs/asmtest/src/riscv/env/v/vm.c  
b/tests/test-progs/asmtest/src/riscv/env/v/vm.c

index df302b4..51a9938 100644
--- a/tests/test-progs/asmtest/src/riscv/env/v/vm.c
+++ b/tests/test-progs/asmtest/src/riscv/env/v/vm.c
@@ -17,16 +17,6 @@
 void trap_entry();
 void pop_tf(trapframe_t*);

-volatile uint64_t tohost;
-volatile uint64_t fromhost;
-
-static void do_tohost(uint64_t tohost_value)
-{
-  while (tohost)
-fromhost = 0;
-  tohost = tohost_value;
-}
-
 #define pa2kva(pa) ((void*)(pa) - DRAM_BASE - MEGAPAGE_SIZE)
 #define uva2kva(pa) ((void*)(pa) - MEGAPAGE_SIZE)

@@ -40,7 +30,13 @@

 static void cputchar(int x)
 {
-  do_tohost(0x0101 | (unsigned char)x);
+  static const char *fileAddr = "stdout";
+  char c = x;
+  register word_t a0 asm("a0") = (uintptr_t)();
+  register word_t a1 asm("a1") = 1;
+  register word_t a2 asm("a2") = 0;
+  register word_t a3 asm("a3") = (uintptr_t)fileAddr;
+  asm volatile (".long 0x9E7B" : : "r"(a0), "r"(a1), "r"(a2), "r"(a3));
 }

 static void cputstring(const char* s)
@@ -51,7 +47,12 @@

 static void terminate(int code)
 {
-  do_tohost(code);
+  register word_t a0 asm("a0") = 0;
+  register word_t a1 asm("a1") = code >> 1;
+  if(code == 1)
+asm volatile (".long 0x427B" : : "r"(a0));
+  else
+asm volatile (".long 0x447B" : : "r"(a0), "r"(a1));
   while (1);
 }


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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: let FPU instructions fault if status.FS = off.

2020-02-24 Thread Nils Asmussen (Gerrit)
Nils Asmussen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25657 )



Change subject: arch-riscv: let FPU instructions fault if status.FS = off.
..

arch-riscv: let FPU instructions fault if status.FS = off.

These checks are required for some tests in the RISC-V test suite.
However, actually we also need to set the INITIAL/CLEAN/DIRTY flags
accordingly, which is not done yet.

Change-Id: If5d6ac22069b51a57b6353cd6d45b77ee51a4d55
---
M src/arch/riscv/isa.hh
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/fp.isa
3 files changed, 43 insertions(+), 0 deletions(-)



diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index c56c45b..73df087 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -60,6 +60,14 @@
 PRV_M = 3
 };

+enum FSMode
+{
+OFF = 0,
+INITIAL = 1,
+CLEAN = 2,
+DIRTY = 3,
+};
+
 class ISA : public BaseISA
 {
   protected:
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 4f0a90a..ad19393 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -50,6 +50,11 @@
 0x1: c_fld({{
 offset = CIMM3 << 3 | CIMM2 << 6;
 }}, {{
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (status.fs == FSMode::OFF)
+fault = make_shared("FPU is off",
+  machInst);
+
 Fp2_bits = Mem;
 }}, {{
 EA = Rp1 + offset;
@@ -75,6 +80,11 @@
 0x5: c_fsd({{
 offset = CIMM3 << 3 | CIMM2 << 6;
 }}, {{
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (status.fs == FSMode::OFF)
+fault = make_shared("FPU is off",
+  machInst);
+
 Mem = Fp2_bits;
 }}, {{
 EA = Rp1 + offset;
@@ -390,9 +400,19 @@
 0x01: decode FUNCT3 {
 format Load {
 0x2: flw({{
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (status.fs == FSMode::OFF)
+fault = make_shared("FPU is off",
+  machInst);
+
 Fd_bits = (uint64_t)Mem_uw;
 }}, inst_flags=FloatMemReadOp);
 0x3: fld({{
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (status.fs == FSMode::OFF)
+fault = make_shared("FPU is off",
+  machInst);
+
 Fd_bits = Mem;
 }}, inst_flags=FloatMemReadOp);
 }
@@ -484,9 +504,19 @@
 0x09: decode FUNCT3 {
 format Store {
 0x2: fsw({{
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (status.fs == FSMode::OFF)
+fault = make_shared("FPU is off",
+  machInst);
+
 Mem_uw = (uint32_t)Fs2_bits;
 }}, inst_flags=FloatMemWriteOp);
 0x3: fsd({{
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (status.fs == FSMode::OFF)
+fault = make_shared("FPU is off",
+  machInst);
+
 Mem_ud = Fs2_bits;
 }}, inst_flags=FloatMemWriteOp);
 }
diff --git a/src/arch/riscv/isa/formats/fp.isa  
b/src/arch/riscv/isa/formats/fp.isa

index e383db8..cb2a90c 100644
--- a/src/arch/riscv/isa/formats/fp.isa
+++ b/src/arch/riscv/isa/formats/fp.isa
@@ -2,6 +2,7 @@

 // Copyright (c) 2015 Riscv Developers
 // Copyright (c) 2016-2017 The University of Virginia
+// Copyright (c) 2020 Barkhausen Institut
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -37,6 +38,10 @@
 {
 Fault fault = NoFault;

+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (status.fs == FSMode::OFF)
+fault = make_shared("FPU is off", machInst);
+
 %(op_decl)s;
 %(op_rd)s;
 if (fault == NoFault) {

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: respect IALIGN, influenced by toggling 'c' extension.

2020-02-24 Thread Nils Asmussen (Gerrit)
Nils Asmussen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25658 )



Change subject: arch-riscv: respect IALIGN, influenced by toggling 'c'  
extension.

..

arch-riscv: respect IALIGN, influenced by toggling 'c' extension.

According to the privileged ISA spec, SEPC[0]/MEPC[0] reads always 0
and SEPC[1]/MEPC[1] reads 0 if the compressed extension is disabled.

Additionally, the compressed extension can only be disabled if the next
instruction is 4-byte aligned.

Change-Id: I590c05e4000b59a5ba283f47933f7a92959d8e38
---
M src/arch/riscv/isa.cc
M src/arch/riscv/registers.hh
2 files changed, 25 insertions(+), 0 deletions(-)



diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 5c1af29..9c5e302 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -288,6 +288,18 @@
  
tc->getCpuPtr()->getInterruptController(tc->threadId()));

 return ic->readIE();
 }
+  case MISCREG_SEPC:
+  case MISCREG_MEPC:
+{
+auto misa = readMiscRegNoEffect(MISCREG_ISA);
+RegVal val = readMiscRegNoEffect(misc_reg);
+// epc[0] is always 0
+val &= ~static_cast(0x1);
+// if compressed instructions are disabled, epc[1] is set to 0
+if ((misa & ISA_EXT_C_MASK) == 0)
+val &= ~static_cast(0x2);
+return val;
+}
   default:
 // Try reading HPM counters
 // As a placeholder, all HPM counters are just cycle counters
@@ -352,6 +364,17 @@
 setMiscRegNoEffect(misc_reg, new_val);
 }
 break;
+  case MISCREG_ISA:
+{
+auto cur_val = readMiscRegNoEffect(misc_reg);
+// only allow to disable compressed instructions
+// if the following instruction is 4-byte aligned
+if ((val & ISA_EXT_C_MASK) == 0 &&
+(tc->pcState().npc() & 0x3) != 0)
+val |= cur_val & ISA_EXT_C_MASK;
+setMiscRegNoEffect(misc_reg, val);
+}
+break;
   case MISCREG_STATUS:
 {
 // these bits are hard-wired
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index d5c05a2..9b899e3 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -2,6 +2,7 @@
  * Copyright (c) 2013 ARM Limited
  * Copyright (c) 2014-2015 Sven Karlsson
  * Copyright (c) 2019 Yifei Liu
+ * Copyright (c) 2020 Barkhausen Institut
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -646,6 +647,7 @@

 const RegVal ISA_MXL_MASK = 3ULL << MXL_OFFSET;
 const RegVal ISA_EXT_MASK = mask(26);
+const RegVal ISA_EXT_C_MASK = 1UL << ('c' - 'a');
 const RegVal MISA_MASK = ISA_MXL_MASK | ISA_EXT_MASK;

 const RegVal STATUS_SD_MASK = 1ULL << ((sizeof(uint64_t) * 8) - 1);

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: make uret, sret, mret SerializeAfter, NonSpeculative.

2020-02-24 Thread Nils Asmussen (Gerrit)
Nils Asmussen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25656 )



Change subject: arch-riscv: make uret,sret,mret  
SerializeAfter,NonSpeculative.

..

arch-riscv: make uret,sret,mret SerializeAfter,NonSpeculative.

These instructions potentially change the privilege level, upon which
the execution of other instructions depends. For that reason, we need to
make *ret SerializeAfter and we also don't want to execute them
speculatively.

Change-Id: If3b5ba6ec3b4102d53c51cf723eba5d5da3eaa2f
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 3 insertions(+), 3 deletions(-)



diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 5de3eee..4f0a90a 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -1775,7 +1775,7 @@
 status.upie = 1;
 xc->setMiscReg(MISCREG_STATUS, status);
 NPC = xc->readMiscReg(MISCREG_UEPC);
-}}, IsReturn);
+}}, IsSerializeAfter, IsNonSpeculative, IsReturn);
 }
 0x8: decode RS2 {
 0x2: sret({{
@@ -1796,7 +1796,7 @@
 xc->setMiscReg(MISCREG_STATUS, status);
 NPC = xc->readMiscReg(MISCREG_SEPC);
 }
-}}, IsReturn);
+}}, IsSerializeAfter, IsNonSpeculative, IsReturn);
 0x5: wfi({{
 STATUS status =  
xc->readMiscReg(MISCREG_STATUS);

 auto pm = (PrivilegeMode)xc->readMiscReg(
@@ -1835,7 +1835,7 @@
 xc->setMiscReg(MISCREG_STATUS, status);
 NPC = xc->readMiscReg(MISCREG_MEPC);
 }
-}}, IsReturn);
+}}, IsSerializeAfter, IsNonSpeculative, IsReturn);
 }
 }
 format CSROp {

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fixed read of {M, S, U}TVEC.

2020-02-24 Thread Nils Asmussen (Gerrit)
Nils Asmussen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25648 )



Change subject: arch-riscv: fixed read of {M,S,U}TVEC.
..

arch-riscv: fixed read of {M,S,U}TVEC.

As stated in 4.1.4 of the privileged ISA manual, the BASE field in the
STVEC register contains the bits [SXLEN-1:2] of the base address, not
the base address shifted left by 2.

Change-Id: I799ec0dc1cbd7b271b91b53adb033a5d1ca3306f
---
M src/arch/riscv/faults.cc
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index 9311925..47edbe7 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -130,7 +130,7 @@
 tc->setMiscReg(MISCREG_STATUS, status);

 // Set PC to fault handler address
-Addr addr = tc->readMiscReg(tvec) >> 2;
+Addr addr = tc->readMiscReg(tvec) & ~static_cast(0x3);
 if (isInterrupt() && bits(tc->readMiscReg(tvec), 1, 0) == 1)
 addr += 4 * _code;
 pcState.set(addr);

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: show names of MiscRegs on accesses.

2020-02-24 Thread Nils Asmussen (Gerrit)
Nils Asmussen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25649 )



Change subject: arch-riscv: show names of MiscRegs on accesses.
..

arch-riscv: show names of MiscRegs on accesses.

Printing the number of the MiscRegs makes it hard to debug problems.
Therefore, this commit adds a name table and prints the name of the
register.

Change-Id: Icd53d5524a5d5daf3e50f253cdda56341663f26e
---
M src/arch/riscv/isa.cc
1 file changed, 136 insertions(+), 3 deletions(-)



diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 861b19c..ba03f34 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -47,8 +47,140 @@
 namespace RiscvISA
 {

+const char *MiscRegNames[] = {
+"PRV",
+"ISA",
+"VENDORID",
+"ARCHID",
+"IMPID",
+"HARTID",
+"STATUS",
+"IP",
+"IE",
+"CYCLE",
+"TIME",
+"INSTRET",
+"HPMCOUNTER03",
+"HPMCOUNTER04",
+"HPMCOUNTER05",
+"HPMCOUNTER06",
+"HPMCOUNTER07",
+"HPMCOUNTER08",
+"HPMCOUNTER09",
+"HPMCOUNTER10",
+"HPMCOUNTER11",
+"HPMCOUNTER12",
+"HPMCOUNTER13",
+"HPMCOUNTER14",
+"HPMCOUNTER15",
+"HPMCOUNTER16",
+"HPMCOUNTER17",
+"HPMCOUNTER18",
+"HPMCOUNTER19",
+"HPMCOUNTER20",
+"HPMCOUNTER21",
+"HPMCOUNTER22",
+"HPMCOUNTER23",
+"HPMCOUNTER24",
+"HPMCOUNTER25",
+"HPMCOUNTER26",
+"HPMCOUNTER27",
+"HPMCOUNTER28",
+"HPMCOUNTER29",
+"HPMCOUNTER30",
+"HPMCOUNTER31",
+"HPMEVENT03",
+"HPMEVENT04",
+"HPMEVENT05",
+"HPMEVENT06",
+"HPMEVENT07",
+"HPMEVENT08",
+"HPMEVENT09",
+"HPMEVENT10",
+"HPMEVENT11",
+"HPMEVENT12",
+"HPMEVENT13",
+"HPMEVENT14",
+"HPMEVENT15",
+"HPMEVENT16",
+"HPMEVENT17",
+"HPMEVENT18",
+"HPMEVENT19",
+"HPMEVENT20",
+"HPMEVENT21",
+"HPMEVENT22",
+"HPMEVENT23",
+"HPMEVENT24",
+"HPMEVENT25",
+"HPMEVENT26",
+"HPMEVENT27",
+"HPMEVENT28",
+"HPMEVENT29",
+"HPMEVENT30",
+"HPMEVENT31",
+"TSELECT",
+"TDATA1",
+"TDATA2",
+"TDATA3",
+"DCSR",
+"DPC",
+"DSCRATCH",
+
+"MEDELEG",
+"MIDELEG",
+"MTVEC",
+"MCOUNTEREN",
+"MSCRATCH",
+"MEPC",
+"MCAUSE",
+"MTVAL",
+"PMPCFG0",
+// pmpcfg1 rv32 only
+"PMPCFG2",
+// pmpcfg3 rv32 only
+"PMPADDR00",
+"PMPADDR01",
+"PMPADDR02",
+"PMPADDR03",
+"PMPADDR04",
+"PMPADDR05",
+"PMPADDR06",
+"PMPADDR07",
+"PMPADDR08",
+"PMPADDR09",
+"PMPADDR10",
+"PMPADDR11",
+"PMPADDR12",
+"PMPADDR13",
+"PMPADDR14",
+"PMPADDR15",
+
+"SEDELEG",
+"SIDELEG",
+"STVEC",
+"SCOUNTEREN",
+"SSCRATCH",
+"SEPC",
+"SCAUSE",
+"STVAL",
+"SATP",
+
+"UTVEC",
+"USCRATCH",
+"UEPC",
+"UCAUSE",
+"UTVAL",
+"FFLAGS",
+"FRM",
+};
+
 ISA::ISA(Params *p) : BaseISA(p)
 {
+static_assert(
+sizeof(MiscRegNames) / sizeof(MiscRegNames[0]) == NumMiscRegs,
+    "MiscRegNames not in sync with NumMiscRegs"
+);
+
 miscRegFile.resize(NumMiscRegs);
 clear();
 }
@@ -105,8 +237,8 @@
 panic("Illegal CSR index %#x\n", misc_reg);
 return -1;
 }
-DPRINTF(RiscvMisc, "Reading MiscReg %d: %#llx.\n", misc_reg,
-miscRegFile[misc_reg]);
+DPRINTF(RiscvMisc, "Reading MiscReg %s (%d): %#llx.\n",
+MiscRegNames[misc_reg], misc_reg, miscRegFile[misc_reg]);
 return miscRegFile[misc_reg];
 }

@@ -180,7 +312,8 @@
 // Illegal CSR
 panic("Illegal CSR index %#x\n", misc_reg);
 }
-DPRINTF(RiscvMisc, "Setting MiscReg %d to %#x.\n", misc_reg, val);
+DPRINTF(RiscvMisc, "Setting MiscReg %s (%d) to %#x.\n",
+MiscRegNames[misc_reg], misc_reg, val);
 miscRegFile[misc_reg] = val;
 }


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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: added support for pseudo instructions.

2020-02-24 Thread Nils Asmussen (Gerrit)
PseudoOp",
+   { "code": m5panicCode },
+   ["IsNonSpeculative"])
+header_output += BasicDeclare.subst(m5panicIop)
+decoder_output += BasicConstructor.subst(m5panicIop)
+exec_output += BasicExecute.subst(m5panicIop)
+
+m5workbeginCode = '''
+PseudoInst::workbegin(xc->tcBase(), a0, a1);
+'''
+
+m5workbeginIop =  
InstObjParams("m5workbegin", "M5workbegin", "PseudoOp",

+   { "code": m5workbeginCode },
+   ["IsNonSpeculative"])
+header_output += BasicDeclare.subst(m5workbeginIop)
+decoder_output += BasicConstructor.subst(m5workbeginIop)
+exec_output += BasicExecute.subst(m5workbeginIop)
+
+m5workendCode = '''
+PseudoInst::workend(xc->tcBase(), a0, a1);
+'''
+
+m5workendIop = InstObjParams("m5workend", "M5workend", "PseudoOp",
+ { "code": m5workendCode },
+ ["IsNonSpeculative"])
+header_output += BasicDeclare.subst(m5workendIop)
+decoder_output += BasicConstructor.subst(m5workendIop)
+exec_output += BasicExecute.subst(m5workendIop)
+}};
+
+def format M5ops() {{
+decode_block = '''
+{
+const uint32_t m5func = bits(machInst, 31, 25);
+switch(m5func) {
+case M5OP_ARM: return new Arm(machInst);
+case M5OP_QUIESCE: return new Quiesce(machInst);
+case M5OP_QUIESCE_NS: return new QuiesceNs(machInst);
+case M5OP_QUIESCE_CYCLE: return new QuiesceCycles(machInst);
+case M5OP_QUIESCE_TIME: return new QuiesceTime(machInst);
+case M5OP_RPNS: return new Rpns(machInst);
+case M5OP_WAKE_CPU: return new WakeCPU(machInst);
+case M5OP_EXIT: return new M5exit(machInst);
+case M5OP_FAIL: return new M5fail(machInst);
+case M5OP_LOAD_SYMBOL: return new Loadsymbol(machInst);
+case M5OP_INIT_PARAM: return new Initparam(machInst);
+case M5OP_RESET_STATS: return new Resetstats(machInst);
+case M5OP_DUMP_STATS: return new Dumpstats(machInst);
+case M5OP_DUMP_RESET_STATS: return new  
Dumpresetstats(machInst);

+case M5OP_CHECKPOINT: return new M5checkpoint(machInst);
+case M5OP_WRITE_FILE: return new M5writefile(machInst);
+case M5OP_READ_FILE: return new M5readfile(machInst);
+case M5OP_DEBUG_BREAK: return new M5break(machInst);
+case M5OP_SWITCH_CPU: return new M5switchcpu(machInst);
+case M5OP_ADD_SYMBOL: return new M5addsymbol(machInst);
+case M5OP_PANIC: return new M5panic(machInst);
+case M5OP_WORK_BEGIN: return new M5workbegin(machInst);
+case M5OP_WORK_END: return new M5workend(machInst);
+default: return new Unknown(machInst);
+}
+   }
+   '''
+}};
diff --git a/src/arch/riscv/isa/includes.isa  
b/src/arch/riscv/isa/includes.isa

index 2d355ba..9db8c9e 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -2,6 +2,7 @@

 // Copyright (c) 2015 RISC-V Foundation
 // Copyright (c) 2016 The University of Virginia
+// Copyright (c) 2020 Barkhausen Institut
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -42,6 +43,7 @@
 #include "arch/riscv/insts/amo.hh"
 #include "arch/riscv/insts/compressed.hh"
 #include "arch/riscv/insts/mem.hh"
+#include "arch/riscv/insts/pseudo.hh"
 #include "arch/riscv/insts/standard.hh"
 #include "arch/riscv/insts/static_inst.hh"
 #include "arch/riscv/insts/unknown.hh"
@@ -57,6 +59,8 @@
 #include 
 #include 

+#include 
+
 #include "arch/riscv/decoder.hh"
 #include "arch/riscv/faults.hh"
 #include "arch/riscv/tlb.hh"
@@ -90,6 +94,7 @@
 #include "mem/request.hh"
 #include "sim/eventq.hh"
 #include "sim/full_system.hh"
+#include "sim/pseudo_inst.hh"
 #include "sim/sim_events.hh"
 #include "sim/sim_exit.hh"
 #include "sim/system.hh"
diff --git a/src/arch/riscv/isa/operands.isa  
b/src/arch/riscv/isa/operands.isa

index 7c80b8a..41e0a4b 100644
--- a/src/arch/riscv/isa/operands.isa
+++ b/src/arch/riscv/isa/operands.isa
@@ -2,6 +2,7 @@

 // Copyright (c) 2015 RISC-V Foundation
 // Copyright (c) 2016 The University of Virginia
+// Copyright (c) 2020 Barkhausen Institut
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -53,6 +54,11 @@
 'ra': ('IntReg', 'ud', 'ReturnAddrReg', 'IsInteger', 1),
 'sp': ('IntReg', 'ud', 'StackPointerReg', 'IsInteger', 2),

+'a0': ('IntReg', 'ud', '10', 'IsInteger', 1),
+'a1': ('IntReg', 'ud', '11', 'IsInteger', 2),
+'a2': ('IntReg', 'ud', '12', 'IsInteger', 3),
+'a3': ('IntReg', 'ud', '13', 'IsInteger', 4),
+
 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 1),
 'Fd_bits': ('FloatReg', 'ud', 'FD', 'IsFloating', 1),
 'Fs1': ('FloatReg', 'df', 'FS1', 'IsFloating', 2),

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fault according to status.{TVM, TSK, TW}.

2020-02-24 Thread Nils Asmussen (Gerrit)
ttings


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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: ignore writes to SXL/UXL fields in status register.

2020-02-24 Thread Nils Asmussen (Gerrit)
Nils Asmussen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25651 )



Change subject: arch-riscv: ignore writes to SXL/UXL fields in status  
register.

..

arch-riscv: ignore writes to SXL/UXL fields in status register.

We currently only support SXL=UXL=2 (64 bit). These fields are WARL,
so that we have to make sure that no other value can be set.

Change-Id: I62ddc7d68b8c31ca655ba1ccee7a294912f46b09
---
M src/arch/riscv/isa.cc
1 file changed, 9 insertions(+), 0 deletions(-)



diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index cfdea22..5c1af29 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -352,6 +352,15 @@
 setMiscRegNoEffect(misc_reg, new_val);
 }
 break;
+  case MISCREG_STATUS:
+{
+// these bits are hard-wired
+RegVal cur = readMiscRegNoEffect(misc_reg);
+val &= ~(STATUS_SXL_MASK | STATUS_UXL_MASK);
+val |= cur & (STATUS_SXL_MASK | STATUS_UXL_MASK);
+setMiscRegNoEffect(misc_reg, val);
+}
+break;
   default:
 setMiscRegNoEffect(misc_reg, val);
 }

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: added dummy implementation of wfi instruction.

2020-02-24 Thread Nils Asmussen (Gerrit)
Nils Asmussen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25653 )



Change subject: arch-riscv: added dummy implementation of wfi instruction.
..

arch-riscv: added dummy implementation of wfi instruction.

Change-Id: I7ca86f57c7d794bf544e34e747875049a3f29d6a
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 3 insertions(+), 0 deletions(-)



diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 1e726a3..41aa9c9 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -1794,6 +1794,9 @@
 NPC = xc->readMiscReg(MISCREG_SEPC);
 }
 }}, IsReturn);
+   0x5: wfi({{
+   // don't do anything for now
+   }}, No_OpClass);
 }
 0x9: sfence_vma({{
 xc->tcBase()->getITBPtr()->demapPage(Rs1, Rs2);

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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: print information about faults.

2020-02-24 Thread Nils Asmussen (Gerrit)
Nils Asmussen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25646 )



Change subject: arch-riscv: print information about faults.
..

arch-riscv: print information about faults.

Change-Id: Ic69b788d508bab1044b693860c7d942963bed3f9
---
M src/arch/riscv/faults.cc
1 file changed, 5 insertions(+), 0 deletions(-)



diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index df8c0ae..9311925 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -2,6 +2,7 @@
  * Copyright (c) 2016 RISC-V Foundation
  * Copyright (c) 2016 The University of Virginia
  * Copyright (c) 2018 TU Dresden
+ * Copyright (c) 2020 Barkhausen Institut
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -36,6 +37,7 @@
 #include "arch/riscv/utility.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
+#include "debug/Fault.hh"
 #include "sim/debug.hh"
 #include "sim/full_system.hh"

@@ -53,6 +55,9 @@
 {
 PCState pcState = tc->pcState();

+DPRINTFS(Fault, tc->getCpuPtr(), "Fault (%s) at PC: %s\n",
+ name(), pcState);
+
 if (FullSystem) {
 PrivilegeMode pp = (PrivilegeMode)tc->readMiscReg(MISCREG_PRV);
 PrivilegeMode prv = PRV_M;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic69b788d508bab1044b693860c7d942963bed3f9
Gerrit-Change-Number: 25646
Gerrit-PatchSet: 1
Gerrit-Owner: Nils Asmussen 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: make MicroUopSetPCCPSR SerializeAfter

2020-02-04 Thread Nils Asmussen (Gerrit)
Nils Asmussen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/24943 )


Change subject: arch-arm: make MicroUopSetPCCPSR SerializeAfter
..

arch-arm: make MicroUopSetPCCPSR SerializeAfter

Updating CPSR needs to be SerializeAfter to ensure that all following
instructions are executed with the new CPSR. Otherwise, for example,
the following instructions will access the banked registers from the
previous mode.

The missing IsSerializeAfter had the consequence that the instruction
rfe (return from exception) did not work correctly with the DerivO3CPU
model.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-303

Change-Id: I999623c0fc92cfcd4c3550b9cb34e8564a92e3e6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24943
Reviewed-by: Gabe Black 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/isa/insts/macromem.isa
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Gabe Black: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/isa/insts/macromem.isa  
b/src/arch/arm/isa/insts/macromem.isa

index 251e5c2..d9eea19 100644
--- a/src/arch/arm/isa/insts/macromem.isa
+++ b/src/arch/arm/isa/insts/macromem.isa
@@ -691,7 +691,7 @@
  'MicroSetPCCPSR',
  {'code': setPCCPSRDecl,
   'predicate_test': predicateTest},
- ['IsMicroop'])
+ ['IsMicroop', 'IsSerializeAfter'])

 header_output = MicroIntImmDeclare.subst(microAddiUopIop) + \
 MicroIntImmDeclare.subst(microAddXiUopIop) + \

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I999623c0fc92cfcd4c3550b9cb34e8564a92e3e6
Gerrit-Change-Number: 24943
Gerrit-PatchSet: 4
Gerrit-Owner: Nils Asmussen 
Gerrit-Assignee: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nils Asmussen 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: make SetPCCPRS microop SerializeAfter

2020-01-30 Thread Nils Asmussen (Gerrit)
Nils Asmussen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/24943 )



Change subject: arch-arm: make SetPCCPRS microop SerializeAfter
..

arch-arm: make SetPCCPRS microop SerializeAfter

Updating CPRS needs to be SerializeAfter to ensure that all following
instructions are executed with the new CPRS. Otherwise, for example,
the following instructions will access the banked register from the
previous mode.

The missing SerializeAfter had the consequence that the instruction rfe
(return from exception) did not work correctly with the DerivO3CPU
model.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-303

Change-Id: I999623c0fc92cfcd4c3550b9cb34e8564a92e3e6
---
M src/arch/arm/isa/insts/macromem.isa
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/arch/arm/isa/insts/macromem.isa  
b/src/arch/arm/isa/insts/macromem.isa

index 251e5c2..d9eea19 100644
--- a/src/arch/arm/isa/insts/macromem.isa
+++ b/src/arch/arm/isa/insts/macromem.isa
@@ -691,7 +691,7 @@
  'MicroSetPCCPSR',
  {'code': setPCCPSRDecl,
   'predicate_test': predicateTest},
- ['IsMicroop'])
+ ['IsMicroop', 'IsSerializeAfter'])

 header_output = MicroIntImmDeclare.subst(microAddiUopIop) + \
 MicroIntImmDeclare.subst(microAddXiUopIop) + \

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I999623c0fc92cfcd4c3550b9cb34e8564a92e3e6
Gerrit-Change-Number: 24943
Gerrit-PatchSet: 1
Gerrit-Owner: Nils Asmussen 
Gerrit-MessageType: newchange
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