[gem5-dev] changeset in gem5: mem: Add rank-wise refresh to the DRAM contro...

changeset bb665366cc00 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=bb665366cc00 description: mem: Add rank-wise refresh to the DRAM controller This patch adds rank-wise refresh to the controller, as opposed to the channel-wide refresh currently in

[gem5-dev] changeset in gem5: mem: Fix a bug in the DRAM controller arbitra...

changeset 471d390943f0 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=471d390943f0 description: mem: Fix a bug in the DRAM controller arbitration Fix a minor issue that affects multi-rank systems. diffstat: src/mem/dram_ctrl.cc | 12 +--- 1 files

[gem5-dev] changeset in gem5: mem: Add a GDDR5 DRAM config

changeset e1a853349529 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=e1a853349529 description: mem: Add a GDDR5 DRAM config This patch adds a first cut GDDR5 config to accommodate the users combining gem5 and GPUSim. The config is based on a SK

[gem5-dev] changeset in gem5: mem: Add missig timing and current parameters...

changeset f958ccec628f in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=f958ccec628f description: mem: Add missig timing and current parameters to DRAM configs This patch adds missing timing and current parameters to the existing DRAM configs. These

[gem5-dev] changeset in gem5: mem: Remove DRAMSim2 DDR3 configuration

changeset 025a459edb87 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=025a459edb87 description: mem: Remove DRAMSim2 DDR3 configuration This patch prunes the DDR3 config that was initially created to match the default config of DRAMSim2. The config