[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Removed invalid transition from MOESI_CMP dir

2020-04-15 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27848 )



Change subject: mem-ruby: Removed invalid transition from MOESI_CMP dir
..

mem-ruby: Removed invalid transition from MOESI_CMP dir

When memory data is received we always have a valid directory
entry or are in a transient state.

Change-Id: I0e9120e320c157fd306909458cbc446275a4f738
Signed-off-by: Tiago Mück 
---
M src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm  
b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm

index e8d0863..6f868b4 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
@@ -905,7 +905,7 @@
 j_popIncomingUnblockQueue;
   }

-  transition({I, S, O, M, IS, SS, OO, MO, MM, MI, MIS, OS, OSS},  
Memory_Data) {
+  transition({S, O, M, IS, SS, OO, MO, MM, MI, MIS, OS, OSS}, Memory_Data)  
{

 d_sendDataMsg;
 q_popMemQueue;
   }

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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Deallocating unused entries in MOESI_CMP dir

2020-04-15 Thread Tiago Mück (Gerrit)
return Directory_State_to_permission(State:I);
+  }
 }
-
 DPRINTF(RubySlicc, "AccessPermission_NotPresent\n");
 return AccessPermission:NotPresent;
   }

   void setAccessPermission(Addr addr, State state) {
 if (directory.isPresent(addr)) {
-   
getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));

+  Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
+  if (is_valid(dir_entry)) {
+dir_entry.changePermission(Directory_State_to_permission(state));
+  } else {
+assert(state == State:I);
+  }
 }
   }

@@ -319,6 +346,14 @@

   // Actions

+  action(allocDirEntry, "alloc", desc="Allocate directory entry") {
+allocateDirectoryEntry(address);
+  }
+
+  action(deallocDirEntry, "dealloc", desc="Deallocate directory entry") {
+deallocateDirectoryEntry(address);
+  }
+
   action(a_sendWriteBackAck, "a", desc="Send writeback ack to requestor") {
 peek(requestQueue_in, RequestMsg) {
   enqueue(responseNetwork_out, ResponseMsg, directory_latency) {
@@ -600,16 +635,19 @@

   // TRANSITIONS
   transition(I, GETX, MM) {
+allocDirEntry;
 qf_queueMemoryFetchRequest;
 i_popIncomingRequestQueue;
   }

   transition(I, DMA_READ, XI_M) {
+allocDirEntry;
 qf_queueMemoryFetchRequest;
 i_popIncomingRequestQueue;
   }

   transition(I, DMA_WRITE, XI_U) {
+allocDirEntry;
 qw_queueMemoryWBFromDMARequest;
 a_sendDMAAck;  // ack count may be zero
 i_popIncomingRequestQueue;
@@ -617,12 +655,14 @@

   transition(XI_M, Memory_Data, I) {
 d_sendDataMsg;  // ack count may be zero
+deallocDirEntry;
 q_popMemQueue;
   }

   transition(XI_U, Exclusive_Unblock, I) {
 cc_clearSharers;
 c_clearOwner;
+deallocDirEntry;
 j_popIncomingUnblockQueue;
   }

@@ -647,6 +687,7 @@
   }

   transition(I, GETS, IS) {
+allocDirEntry;
 qf_queueMemoryFetchRequest;
 i_popIncomingRequestQueue;
   }
@@ -812,6 +853,7 @@
 c_clearOwner;
 cc_clearSharers;
 qw_queueMemoryWBFromCacheRequest;
+deallocDirEntry;
 i_popIncomingRequestQueue;
   }

@@ -846,6 +888,7 @@
   transition(MI, Clean_Writeback, I) {
 c_clearOwner;
 cc_clearSharers;
+deallocDirEntry;
 i_popIncomingRequestQueue;
   }


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[gem5-dev] Change in gem5/gem5[develop]: cpu-minor: fix store-release issuing

2020-03-26 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27135 )



Change subject: cpu-minor: fix store-release issuing
..

cpu-minor: fix store-release issuing

Store with release flag are treated like store conditionals and are not
bufferable. Also they are only sent when the store buffer is empty to
satisfy the release semantics.

Change-Id: I253ec5ecd39901b14d0dc8efbc82cf7e4b07f08f
Signed-off-by: Tiago Mück 
---
M src/cpu/minor/lsq.cc
1 file changed, 12 insertions(+), 2 deletions(-)



diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc
index e50d498..e4a9dc0 100644
--- a/src/cpu/minor/lsq.cc
+++ b/src/cpu/minor/lsq.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014,2017-2018 ARM Limited
+ * Copyright (c) 2013-2014,2017-2018,2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -1029,10 +1029,11 @@

 bool is_load = request->isLoad;
 bool is_llsc = request->request->isLLSC();
+bool is_release = request->request->isRelease();
 bool is_swap = request->request->isSwap();
 bool is_atomic = request->request->isAtomic();
 bool bufferable = !(request->request->isStrictlyOrdered() ||
-is_llsc || is_swap || is_atomic);
+is_llsc || is_swap || is_atomic || is_release);

 if (is_load) {
 if (numStoresInTransfers != 0) {
@@ -1050,6 +1051,15 @@
 }
 }

+// Process store conditionals or store release after all previous
+// stores are completed
+if (((!is_load && is_llsc) || is_release) &&
+!storeBuffer.isDrained()) {
+DPRINTF(MinorMem, "Memory access needs to wait for store buffer"
+  " to drain\n");
+return;
+}
+
 /* Check if this is the head instruction (and so must be executable as
  *  its stream sequence number was checked above) for loads which must
  *  not be speculatively issued and stores which must be issued here */

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[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: fix store-release issuing

2020-03-26 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27134 )



Change subject: cpu-o3: fix store-release issuing
..

cpu-o3: fix store-release issuing

Requests from stores with release semantics are only issued when they
are at the head of the store queue.

Change-Id: I19fbceb5ee057d3aa70175cbeec6b9b466334e8c
Signed-off-by: Tiago Mück 
---
M src/cpu/o3/lsq_unit_impl.hh
1 file changed, 16 insertions(+), 1 deletion(-)



diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index f7fb3fe..7383c6f 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -1,6 +1,6 @@

 /*
- * Copyright (c) 2010-2014, 2017-2019 ARM Limited
+ * Copyright (c) 2010-2014, 2017-2020 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -753,6 +753,21 @@

 DynInstPtr inst = storeWBIt->instruction();
 LSQRequest* req = storeWBIt->request();
+
+// Process store conditionals or store release after all previous
+// stores are completed
+if ((req->mainRequest()->isLLSC() ||
+ req->mainRequest()->isRelease()) &&
+ (storeWBIt.idx() != storeQueue.head())) {
+DPRINTF(LSQUnit, "Store idx:%i PC:%s to Addr:%#x "
+"[sn:%lli] is %s%s and not head of the queue\n",
+storeWBIt.idx(), inst->pcState(),
+req->request()->getPaddr(), inst->seqNum,
+req->mainRequest()->isLLSC() ? "SC" : "",
+req->mainRequest()->isRelease() ? "/Release" : "");
+break;
+}
+
 storeWBIt->committed() = true;

 assert(!inst->memData);

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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Using acquire/release memory flags

2020-03-26 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27133 )



Change subject: arch-arm: Using acquire/release memory flags
..

arch-arm: Using acquire/release memory flags

Appends the acquire/release memory flags for the instructions with those
semantics.

Change-Id: I9d1e12c6ced511f2ff7a1006c27ae9014965e044
Signed-off-by: Tiago Mück 
---
M src/arch/arm/isa/insts/ldr.isa
M src/arch/arm/isa/insts/ldr64.isa
M src/arch/arm/isa/insts/str.isa
M src/arch/arm/isa/insts/str64.isa
4 files changed, 12 insertions(+), 4 deletions(-)



diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index dc1d650..d828fcf 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2010-2011,2019 ARM Limited
+// Copyright (c) 2010-2011,2019-2020 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -182,6 +182,7 @@
 self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
+self.memFlags.append("Request::ACQUIRE")

 # Disambiguate the class name for different flavors of loads
 if self.flavor != "normal":
@@ -256,6 +257,7 @@
 self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
+self.memFlags.append("Request::ACQUIRE")

 def emit(self):
 # Address computation code
diff --git a/src/arch/arm/isa/insts/ldr64.isa  
b/src/arch/arm/isa/insts/ldr64.isa

index 4f12509..fc4f34f 100644
--- a/src/arch/arm/isa/insts/ldr64.isa
+++ b/src/arch/arm/isa/insts/ldr64.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2011-2014, 2017, 2019 ARM Limited
+// Copyright (c) 2011-2014, 2017, 2019-2020 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -94,6 +94,8 @@
 self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
+self.memFlags.append("Request::ACQUIRE")
+
 if self.flavor in ("acex", "exclusive", "exp", "acexp"):
 self.memFlags.append("Request::LLSC")

diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa
index f542478..e99f6ad 100644
--- a/src/arch/arm/isa/insts/str.isa
+++ b/src/arch/arm/isa/insts/str.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2010-2011,2017,2019 ARM Limited
+// Copyright (c) 2010-2011,2017,2019-2020 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -190,6 +190,7 @@
 self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
+self.memFlags.append("Request::RELEASE")

 # Disambiguate the class name for different flavors of stores
 if self.flavor != "normal":
@@ -271,6 +272,7 @@
 self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
+self.memFlags.append("Request::RELEASE")

 # Disambiguate the class name for different flavors of stores
 if self.flavor != "normal":
diff --git a/src/arch/arm/isa/insts/str64.isa  
b/src/arch/arm/isa/insts/str64.isa

index 22d1456..7ad1cad 100644
--- a/src/arch/arm/isa/insts/str64.isa
+++ b/src/arch/arm/isa/insts/str64.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2011-2013,2017,2019 ARM Limited
+// Copyright (c) 2011-2013,2017,2019-2020 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -82,6 +82,8 @@
 self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
+self.memFlags.append("Request::RELEASE")
+
 if self.flavor in ("relex", "exclusive", "exp", "relexp"):
 self.instFlags.append("IsStoreConditional")
 self.memFlags.append("Request::LLSC")

--
To

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: MemDepUnit tracks load-acquire/store-release

2020-03-26 Thread Tiago Mück (Gerrit)
,9 @@
 }
 }

+// for load-acquire store-release that could also be a barrier
+_insertBarrier(inst);
+
 if (inst->isStore() || inst->isAtomic()) {
 DPRINTF(MemDepUnit, "Inserting store/atomic PC %s [sn:%lli].\n",
 inst->pcState(), inst->seqNum);
@@ -298,26 +353,16 @@
 } else {
 panic("Unknown type! (most likely a barrier).");
 }
+
+// for load-acquire store-release that could also be a barrier
+_insertBarrier(inst);
 }

 template 
 void
 MemDepUnit::insertBarrier(const DynInstPtr _inst)
 {
-InstSeqNum barr_sn = barr_inst->seqNum;
-// Memory barriers block loads and stores, write barriers only stores.
-if (barr_inst->isMemBarrier()) {
-loadBarrier = true;
-loadBarrierSN = barr_sn;
-storeBarrier = true;
-storeBarrierSN = barr_sn;
-DPRINTF(MemDepUnit, "Inserted a memory barrier %s SN:%lli\n",
-barr_inst->pcState(),barr_sn);
-} else if (barr_inst->isWriteBarrier()) {
-storeBarrier = true;
-storeBarrierSN = barr_sn;
-DPRINTF(MemDepUnit, "Inserted a write barrier\n");
-}
+_insertBarrier(barr_inst);

 ThreadID tid = barr_inst->threadNumber;

@@ -325,7 +370,7 @@

 // Add the MemDepEntry to the hash.
 memDepHash.insert(
-std::pair(barr_sn, inst_entry));
+std::pair(barr_inst->seqNum,  
inst_entry));

 #ifdef DEBUG
 MemDepEntry::memdep_insert++;
 #endif
@@ -348,7 +393,7 @@

 inst_entry->regsReady = true;

-if (inst_entry->memDepReady) {
+if (inst_entry->memDeps == 0) {
 DPRINTF(MemDepUnit, "Instruction has its memory "
 "dependencies resolved, adding it to the ready list.\n");

@@ -422,6 +467,9 @@
 #ifdef DEBUG
 MemDepEntry::memdep_erase++;
 #endif
+
+// Check barrier
+_completeBarrier(inst);
 }

 template 
@@ -430,19 +478,6 @@
 {
 wakeDependents(inst);
 completed(inst);
-
-InstSeqNum barr_sn = inst->seqNum;
-DPRINTF(MemDepUnit, "barrier completed: %s SN:%lli\n", inst->pcState(),
-inst->seqNum);
-if (inst->isMemBarrier()) {
-if (loadBarrierSN == barr_sn)
-loadBarrier = false;
-if (storeBarrierSN == barr_sn)
-storeBarrier = false;
-} else if (inst->isWriteBarrier()) {
-if (storeBarrierSN == barr_sn)
-storeBarrier = false;
-}
 }

 template 
@@ -469,10 +504,13 @@
 "[sn:%lli].\n",
 woken_inst->inst->seqNum);

-if (woken_inst->regsReady && !woken_inst->squashed) {
+assert(woken_inst->memDeps > 0);
+woken_inst->memDeps -= 1;
+
+if ((woken_inst->memDeps == 0) &&
+woken_inst->regsReady &&
+!woken_inst->squashed) {
 moveToReady(woken_inst);
-} else {
-woken_inst->memDepReady = true;
 }
 }

@@ -507,11 +545,9 @@
 DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
 (*squash_it)->seqNum);

-if ((*squash_it)->seqNum == loadBarrierSN)
-  loadBarrier = false;
+    loadBarrierSNs.erase((*squash_it)->seqNum);

-if ((*squash_it)->seqNum == storeBarrierSN)
-  storeBarrier = false;
+storeBarrierSNs.erase((*squash_it)->seqNum);

 hash_it = memDepHash.find((*squash_it)->seqNum);


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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Add functionalReadBuffers to AbstractController

2019-10-21 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/22020 )



Change subject: mem-ruby: Add functionalReadBuffers to AbstractController
..

mem-ruby: Add functionalReadBuffers to AbstractController

Forwards a functional read accesses to all message buffers, similar to
functionalWriteBuffers.

Change-Id: I54b0ba16aab84575e4c9d6102f6c519b309aa95b
Signed-off-by: Tiago Mück 
---
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/slicc/symbols/StateMachine.py
2 files changed, 37 insertions(+), 0 deletions(-)



diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh  
b/src/mem/ruby/slicc_interface/AbstractController.hh

index 2007026..eff49ed 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -111,6 +111,7 @@

 //! These functions are used by ruby system to read/write the data  
blocks

 //! that exist with in the controller.
+virtual bool functionalReadBuffers(PacketPtr&) = 0;
 virtual void functionalRead(const Addr , PacketPtr) = 0;
 void functionalMemoryRead(PacketPtr);
 //! The return value indicates the number of messages written with the
diff --git a/src/mem/slicc/symbols/StateMachine.py  
b/src/mem/slicc/symbols/StateMachine.py

index a92e078..a7e7c4d 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2019 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
 # Copyright (c) 2009 The Hewlett-Packard Development Company
 # Copyright (c) 2013 Advanced Micro Devices, Inc.
@@ -312,6 +324,7 @@
 Sequencer* getCPUSequencer() const;
 GPUCoalescer* getGPUCoalescer() const;

+bool functionalReadBuffers(PacketPtr&);
 int functionalWriteBuffers(PacketPtr&);

 void countTransition(${ident}_State state, ${ident}_Event event);
@@ -1029,6 +1042,29 @@
 }
 ''')

+# Function for functional reads to messages buffered in the  
controller

+code('''
+bool
+$c_ident::functionalReadBuffers(PacketPtr& pkt)
+{
+''')
+for var in self.objects:
+vtype = var.type
+if vtype.isBuffer:
+vid = "m_%s_ptr" % var.ident
+code('if ($vid->functionalRead(pkt)) return true;')
+
+for var in self.config_parameters:
+vtype = var.type_ast.type
+if vtype.isBuffer:
+vid = "m_%s_ptr" % var.ident
+code('if ($vid->functionalRead(pkt)) return true;')
+
+code('''
+return false;
+}
+''')
+
 code.write(path, "%s.cc" % c_ident)

 def printCWakeup(self, path, includes):

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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: SimpleNetwork implementation of functional reads

2019-10-21 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/22021 )



Change subject: mem-ruby: SimpleNetwork implementation of functional reads
..

mem-ruby: SimpleNetwork implementation of functional reads

Change-Id: Id362d992cbf178f15294f0a5e9060a1de2beb394
Signed-off-by: Tiago Mück 
---
M src/mem/ruby/network/simple/SimpleNetwork.cc
M src/mem/ruby/network/simple/Switch.cc
2 files changed, 33 insertions(+), 2 deletions(-)



diff --git a/src/mem/ruby/network/simple/SimpleNetwork.cc  
b/src/mem/ruby/network/simple/SimpleNetwork.cc

index 56f948f..9168f65 100644
--- a/src/mem/ruby/network/simple/SimpleNetwork.cc
+++ b/src/mem/ruby/network/simple/SimpleNetwork.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
  * All rights reserved.
  *
@@ -186,9 +198,12 @@
 SimpleNetwork::functionalRead(Packet *pkt)
 {
 for (unsigned int i = 0; i < m_switches.size(); i++) {
-if (m_switches[i]->functionalRead(pkt)) {
+if (m_switches[i]->functionalRead(pkt))
 return true;
-}
+}
+for (unsigned int i = 0; i < m_int_link_buffers.size(); ++i) {
+if (m_int_link_buffers[i]->functionalRead(pkt))
+return true;
 }

 return false;
diff --git a/src/mem/ruby/network/simple/Switch.cc  
b/src/mem/ruby/network/simple/Switch.cc

index 7cc635d..004694b 100644
--- a/src/mem/ruby/network/simple/Switch.cc
+++ b/src/mem/ruby/network/simple/Switch.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
  * All rights reserved.
  *
@@ -174,6 +186,10 @@
 bool
 Switch::functionalRead(Packet *pkt)
 {
+for (unsigned int i = 0; i < m_port_buffers.size(); ++i) {
+if (m_port_buffers[i]->functionalRead(pkt))
+return true;
+}
 return false;
 }


--
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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Allow MessageBuffer functional reads

2019-10-21 Thread Tiago Mück (Gerrit)
eview.googlesource.com/c/public/gem5/+/22019
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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Fix Ruby handling of functional requests

2019-10-21 Thread Tiago Mück (Gerrit)
::functionalWrite(func_pkt);
+
+RequestTable::iterator write = m_writeRequestTable.begin();
+RequestTable::iterator write_end = m_writeRequestTable.end();
+for (; write != write_end; ++write) {
+SequencerRequest* request = write->second;
+if (request->functionalWrite(func_pkt))
+++num_written;
+}
+
+return num_written;
+}
+
 void Sequencer::resetStats()
 {
 m_latencyHist.reset();
diff --git a/src/mem/ruby/system/Sequencer.hh  
b/src/mem/ruby/system/Sequencer.hh

index 33fd530..9c379a6 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
  * All rights reserved.
  *
@@ -50,6 +62,15 @@
  Cycles _issue_time)
 : pkt(_pkt), m_type(_m_type), issue_time(_issue_time)
 {}
+
+bool functionalWrite(Packet *func_pkt)
+{
+// Follow-up on RubyRequest::functionalWrite
+// This makes sure the hitCallback won't overrite the value we
+// expect to find
+assert(func_pkt->isWrite());
+return func_pkt->trySatisfyFunctional(pkt);
+}
 };

 std::ostream& operator<<(std::ostream& out, const SequencerRequest& obj);
@@ -101,6 +122,8 @@
 void invalidateSC(Addr address);
 int coreId() const { return m_coreId; }

+virtual int functionalWrite(Packet *func_pkt) override;
+
 void recordRequestType(SequencerRequestType requestType);
 Stats::Histogram& getOutstandReqHist() { return m_outstandReqHist; }

diff --git a/src/mem/slicc/symbols/StateMachine.py  
b/src/mem/slicc/symbols/StateMachine.py

index a7e7c4d..bef5398 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -322,6 +322,7 @@

 void recordCacheTrace(int cntrl, CacheRecorder* tr);
 Sequencer* getCPUSequencer() const;
+DMASequencer* getDMASequencer() const;
 GPUCoalescer* getGPUCoalescer() const;

 bool functionalReadBuffers(PacketPtr&);
@@ -696,6 +697,12 @@
 assert(param.pointer)
 seq_ident = "m_%s_ptr" % param.ident

+dma_seq_ident = "NULL"
+for param in self.config_parameters:
+if param.ident == "dma_sequencer":
+assert(param.pointer)
+dma_seq_ident = "m_%s_ptr" % param.ident
+
 coal_ident = "NULL"
 for param in self.config_parameters:
 if param.ident == "coalescer":
@@ -724,6 +731,28 @@
 }
 ''')

+if dma_seq_ident != "NULL":
+code('''
+DMASequencer*
+$c_ident::getDMASequencer() const
+{
+if (NULL != $dma_seq_ident) {
+return $dma_seq_ident;
+} else {
+return NULL;
+}
+}
+''')
+else:
+code('''
+
+DMASequencer*
+$c_ident::getDMASequencer() const
+{
+return NULL;
+}
+''')
+
 if coal_ident != "NULL":
     code('''
 GPUCoalescer*

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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: NetDest static allocation of bitmasks

2019-10-18 Thread Tiago Mück (Gerrit)
..8437de2 100644
--- a/src/mem/ruby/common/NetDest.hh
+++ b/src/mem/ruby/common/NetDest.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
  * All rights reserved.
  *
@@ -29,11 +41,12 @@
 #ifndef __MEM_RUBY_COMMON_NETDEST_HH__
 #define __MEM_RUBY_COMMON_NETDEST_HH__

+#include 
 #include 
 #include 

-#include "mem/ruby/common/Set.hh"
 #include "mem/ruby/common/MachineID.hh"
+#include "mem/ruby/common/Set.hh"

 // NetDest specifies the network destination of a Message
 class NetDest
@@ -49,10 +62,10 @@
 ~NetDest()
 { }

-void add(MachineID newElement);
+void add(const MachineID );
 void addNetDest(const NetDest& netDest);
 void setNetDest(MachineType machine, const Set& set);
-void remove(MachineID oldElement);
+void remove(const MachineID );
 void removeNetDest(const NetDest& netDest);
 void clear();
 void broadcast();
@@ -74,7 +87,7 @@

 bool isSuperset(const NetDest& test) const;
 bool isSubset(const NetDest& test) const { return  
test.isSuperset(*this); }

-bool isElement(MachineID element) const;
+bool isElement(const MachineID ) const;
 bool isBroadcast() const;
 bool isEmpty() const;

@@ -84,11 +97,10 @@
 MachineID smallestElement() const;
 MachineID smallestElement(MachineType machine) const;

-void resize();
 int getSize() const { return m_bits.size(); }

 // get element for a index
-NodeID elementAt(MachineID index);
+NodeID elementAt(const MachineID );

 void print(std::ostream& out) const;

@@ -96,7 +108,7 @@
 // returns a value >= MachineType_base_level("this machine")
 // and < MachineType_base_level("next highest machine")
 int
-vecIndex(MachineID m) const
+vecIndex(const MachineID ) const
 {
 int vec_index = MachineType_base_level(m.type);
 assert(vec_index < m_bits.size());
@@ -105,7 +117,7 @@

 NodeID bitIndex(NodeID index) const { return index; }

-std::vector m_bits;  // a vector of bit vectors - i.e. Sets
+std::array  m_bits;  // a vector of bit vectors
 };

 inline std::ostream&

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[gem5-dev] Change in gem5/gem5[master]: dev-arm: Check for gem5 extensions in GicV2

2019-10-18 Thread Tiago Mück (Gerrit)
Tiago Mück has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/19288 )


Change subject: dev-arm: Check for gem5 extensions in GicV2
..

dev-arm: Check for gem5 extensions in GicV2

Using GicV2 without setting the gem5_extensions parameter in a
config  with more than 8 is not allowed to prevent overflow of
the 8-bit mask.

Change-Id: I780c6985e8f44ed780b4f74f9a27805124e23a7b
Signed-off-by: Tiago Mück 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19288
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/dev/arm/gic_v2.hh
1 file changed, 6 insertions(+), 3 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh
index f9b66b8..4104140 100644
--- a/src/dev/arm/gic_v2.hh
+++ b/src/dev/arm/gic_v2.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
+ * Copyright (c) 2010, 2013, 2015-2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -309,8 +309,11 @@
 if (gem5ExtensionsEnabled) {
 ctx_mask = ctx;
 } else {
-// convert the CPU id number into a bit mask
-ctx_mask = power(2, ctx);
+fatal_if(ctx >= 8,
+"%s requires the gem5_extensions parameter to support "
+"more than 8 cores\n", name());
+// convert the CPU id number into a bit mask
+ctx_mask = 1 << ctx;
 }
 return ctx_mask;
 } else {

--
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Gerrit-Change-Number: 19288
Gerrit-PatchSet: 2
Gerrit-Owner: Tiago Mück 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Tiago Mück 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: removed unused checkCoherence

2019-10-18 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/21924 )



Change subject: mem-ruby: removed unused checkCoherence
..

mem-ruby: removed unused checkCoherence

Change-Id: I108b95513f2828470fe70bad5f136b0721598582
Signed-off-by: Tiago Mück 
---
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/system/GPUCoalescer.cc
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/ruby/system/Sequencer.cc
M src/mem/ruby/system/Sequencer.hh
5 files changed, 0 insertions(+), 20 deletions(-)



diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm  
b/src/mem/ruby/protocol/RubySlicc_Types.sm

index 99931bc..2c0404d 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -124,7 +124,6 @@
   void writeCallback(Addr, DataBlock, bool, MachineType,
  Cycles, Cycles, Cycles);

-  void checkCoherence(Addr);
   void evictionCallback(Addr);
   void recordRequestType(SequencerRequestType);
   bool checkResourceAvailable(CacheResourceType, Addr);
@@ -144,7 +143,6 @@
  Cycles, Cycles, Cycles);
   void writeCallback(Addr, MachineType, DataBlock,
  Cycles, Cycles, Cycles, bool);
-  void checkCoherence(Addr);
   void evictionCallback(Addr);
   void recordCPReadCallBack(MachineID, MachineID);
   void recordCPWriteCallBack(MachineID, MachineID);
@@ -165,7 +163,6 @@
  Cycles, Cycles, Cycles, bool);
   void invCallback(Addr);
   void wbCallback(Addr);
-  void checkCoherence(Addr);
   void evictionCallback(Addr);
 }

diff --git a/src/mem/ruby/system/GPUCoalescer.cc  
b/src/mem/ruby/system/GPUCoalescer.cc

index 61ee2ae..e7d2cb6 100644
--- a/src/mem/ruby/system/GPUCoalescer.cc
+++ b/src/mem/ruby/system/GPUCoalescer.cc
@@ -978,13 +978,6 @@
 << "]";
 }

-// this can be called from setState whenever coherence permissions are
-// upgraded when invoked, coherence violations will be checked for the
-// given block
-void
-GPUCoalescer::checkCoherence(Addr addr)
-{
-}

 void
 GPUCoalescer::recordRequestType(SequencerRequestType requestType) {
diff --git a/src/mem/ruby/system/GPUCoalescer.hh  
b/src/mem/ruby/system/GPUCoalescer.hh

index 56f81c6..2d5604f 100644
--- a/src/mem/ruby/system/GPUCoalescer.hh
+++ b/src/mem/ruby/system/GPUCoalescer.hh
@@ -178,7 +178,6 @@
 bool empty() const;

 void print(std::ostream& out) const;
-void checkCoherence(Addr address);

 void markRemoved();
 void removeRequest(GPUCoalescerRequest* request);
diff --git a/src/mem/ruby/system/Sequencer.cc  
b/src/mem/ruby/system/Sequencer.cc

index 9d317aa..5604356 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -679,14 +679,6 @@
 << "]";
 }

-// this can be called from setState whenever coherence permissions are
-// upgraded when invoked, coherence violations will be checked for the
-// given block
-void
-Sequencer::checkCoherence(Addr addr)
-{
-}
-
 void
 Sequencer::recordRequestType(SequencerRequestType requestType) {
 DPRINTF(RubyStats, "Recorded statistic: %s\n",
diff --git a/src/mem/ruby/system/Sequencer.hh  
b/src/mem/ruby/system/Sequencer.hh

index 33fd530..8b48ae1 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -94,7 +94,6 @@
 { deschedule(deadlockCheckEvent); }

 void print(std::ostream& out) const;
-void checkCoherence(Addr address);

 void markRemoved();
 void evictionCallback(Addr address);

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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: fix possible MOESI_CMP deadlock

2019-10-18 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/21929 )



Change subject: mem-ruby: fix possible MOESI_CMP deadlock
..

mem-ruby: fix possible MOESI_CMP deadlock

Freeing the L2 block only after local invalidates are acked in the OLSF
state may lead to a deadlock.

Change-Id: Ia4b60e5bc9e2d3315b874a8c6616478db6eb38c1
Signed-off-by: Tiago Mück 
---
M src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
1 file changed, 3 insertions(+), 3 deletions(-)



diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm  
b/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm

index 8b6643e..ed91821 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
@@ -1912,6 +1912,9 @@
 i_allocateTBE;
 t_recordFwdXID;
 ee_sendLocalInv;
+gg_clearLocalSharers;
+checkCacheNoSharersNoOwner;
+rr_deallocateL2CacheBlock;
 m_popRequestQueue;
   }

@@ -1923,10 +1926,7 @@

   transition(OLSF, All_Acks, I) {
 c_sendDataFromTBEToFwdGETX;
-gg_clearLocalSharers;
 s_deallocateTBE;
-checkCacheNoSharersNoOwner;
-rr_deallocateL2CacheBlock;
 n_popTriggerQueue;
 wa_wakeUpDependents;
   }

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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Missing transition in MOESI_CMP_directory

2019-10-18 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/21925 )



Change subject: mem-ruby: Missing transition in MOESI_CMP_directory
..

mem-ruby: Missing transition in MOESI_CMP_directory

Change-Id: I3aa9cd0230c141128ef5bddc728775b1ea6bbe14
Signed-off-by: Tiago Mück 
---
M src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm  
b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm

index 85e7946..39de654 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
@@ -663,7 +663,7 @@
 i_popIncomingRequestQueue;
   }

-  transition({I, S}, PUTO) {
+  transition({I, S}, {PUTO, PUTO_SHARERS}) {
 b_sendWriteBackNack;
 i_popIncomingRequestQueue;
   }

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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Add deallocate to DirectoryMemory

2019-10-18 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/21920 )



Change subject: mem-ruby: Add deallocate to DirectoryMemory
..

mem-ruby: Add deallocate to DirectoryMemory

Change-Id: Ib261ec8b302b55e539d8e13064957170412b752c
Signed-off-by: Tiago Mück 
---
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/structures/DirectoryMemory.cc
M src/mem/ruby/structures/DirectoryMemory.hh
3 files changed, 33 insertions(+), 2 deletions(-)



diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm  
b/src/mem/ruby/protocol/RubySlicc_Types.sm

index fd76289..99931bc 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved.
@@ -181,6 +193,7 @@
 structure (DirectoryMemory, external = "yes") {
   AbstractCacheEntry allocate(Addr, AbstractCacheEntry);
   AbstractCacheEntry lookup(Addr);
+  void deallocate(Addr);
   bool isPresent(Addr);
   void invalidateBlock(Addr);
   void recordRequestType(DirectoryRequestType);
diff --git a/src/mem/ruby/structures/DirectoryMemory.cc  
b/src/mem/ruby/structures/DirectoryMemory.cc

index d9da058..c878ee8 100644
--- a/src/mem/ruby/structures/DirectoryMemory.cc
+++ b/src/mem/ruby/structures/DirectoryMemory.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017 ARM Limited
+ * Copyright (c) 2017,2019 ARM Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -129,6 +129,7 @@

 idx = mapAddressToLocalIdx(address);
 assert(idx < m_num_entries);
+assert(m_entries[idx] == NULL);
 entry->changePermission(AccessPermission_Read_Only);
 m_entries[idx] = entry;

@@ -136,6 +137,20 @@
 }

 void
+DirectoryMemory::deallocate(Addr address)
+{
+assert(isPresent(address));
+uint64_t idx;
+DPRINTF(RubyCache, "Removing entry for address: %#x\n", address);
+
+idx = mapAddressToLocalIdx(address);
+assert(idx < m_num_entries);
+assert(m_entries[idx] != NULL);
+delete m_entries[idx];
+m_entries[idx] = NULL;
+}
+
+void
 DirectoryMemory::print(ostream& out) const
 {
 }
diff --git a/src/mem/ruby/structures/DirectoryMemory.hh  
b/src/mem/ruby/structures/DirectoryMemory.hh

index f879b29..3dd0e95 100644
--- a/src/mem/ruby/structures/DirectoryMemory.hh
+++ b/src/mem/ruby/structures/DirectoryMemory.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017 ARM Limited
+ * Copyright (c) 2017,2019 ARM Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -79,6 +79,9 @@
 AbstractCacheEntry *lookup(Addr address);
 AbstractCacheEntry *allocate(Addr address, AbstractCacheEntry*  
new_entry);


+// Explicitly free up this address
+void deallocate(Addr address);
+
 void print(std::ostream& out) const;
 void recordRequestType(DirectoryRequestType requestType);


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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: fix MOESI_CMP_directory functional reads

2019-10-18 Thread Tiago Mück (Gerrit)
emoryWBFromCacheRequest;
 i_popIncomingRequestQueue;
   }

+  transition(WBS, Memory_Ack, S) {
+clearWBAck;
+w_deallocateTBE;
+q_popMemQueue;
+  }
+
   transition(OSS, Clean_Writeback, S) {
 c_moveOwnerToSharer;
 i_popIncomingRequestQueue;
@@ -901,15 +1008,26 @@
 i_popIncomingRequestQueue;
   }

-  transition({MI, MIS}, Unblock, M) {
-j_popIncomingUnblockQueue;
+  //transition({MI, MIS}, Unblock, M) {
+  //  j_popIncomingUnblockQueue;
+  //}
+
+  //transition({OS, OSS}, Unblock, O) {
+  //  j_popIncomingUnblockQueue;
+  //}
+
+  //transition({S, O, M, SS, OO, MI, MIS, OS, OSS}, Memory_Data_Cache) {
+  transition({S, O, M, SS, OO}, Memory_Data_Cache) {
+d_sendDataMsg;
+q_popMemQueue;
   }

-  transition({OS, OSS}, Unblock, O) {
-j_popIncomingUnblockQueue;
+  transition(IS_M, Memory_Data_Cache, IS) {
+d_sendDataMsg;
+q_popMemQueue;
   }

-  transition({S, O, M, IS, SS, OO, MO, MM, MI, MIS, OS, OSS},  
Memory_Data_Cache) {

+  transition(MM_M, Memory_Data_Cache, MM) {
 d_sendDataMsg;
 q_popMemQueue;
   }
@@ -920,8 +1038,4 @@
 q_popMemQueue;
   }

-  transition({I, S, O, M, IS, SS, OO, MO, MM, MI, MIS, OS, OSS, XI_U,  
XI_M, XI_M_U}, Memory_Ack) {

-q_popMemQueue;
-  }
-
 }
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm  
b/src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm

index 1dc0c58..5a52b60 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm
@@ -100,6 +100,7 @@
   }

   AccessPermission getAccessPermission(Addr addr) {
+DPRINTF(RubySlicc, "AccessPermission_NotPresent\n");
 return AccessPermission:NotPresent;
   }

diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-msg.sm  
b/src/mem/ruby/protocol/MOESI_CMP_directory-msg.sm

index 7dc5822..2dd34e4 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-msg.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-msg.sm
@@ -109,9 +109,7 @@

   bool functionalRead(Packet *pkt) {
 // Read only those messages that contain the data
-if (Type == CoherenceRequestType:DMA_READ ||
-Type == CoherenceRequestType:DMA_WRITE ||
-Type == CoherenceRequestType:WRITEBACK_CLEAN_DATA ||
+if (Type == CoherenceRequestType:WRITEBACK_CLEAN_DATA ||
 Type == CoherenceRequestType:WRITEBACK_DIRTY_DATA) {
 return testAndRead(addr, DataBlk, pkt);
 }

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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Fixed MOESI_CMP_directory resource tracking

2019-10-18 Thread Tiago Mück (Gerrit)
comingRequestQueue;
   }

   transition(MIS, Clean_Writeback, S) {
 c_moveOwnerToSharer;
+w_deallocateTBE;
 i_popIncomingRequestQueue;
   }

@@ -999,6 +1024,7 @@
   transition(MI, Clean_Writeback, I) {
 c_clearOwner;
 cc_clearSharers;
+w_deallocateTBE;
 deallocDirEntry;
 i_popIncomingRequestQueue;
   }
@@ -1016,8 +1042,7 @@
   //  j_popIncomingUnblockQueue;
   //}

-  //transition({S, O, M, SS, OO, MI, MIS, OS, OSS}, Memory_Data_Cache) {
-  transition({S, O, M, SS, OO}, Memory_Data_Cache) {
+  transition({S, SS}, Memory_Data_Cache) {
 d_sendDataMsg;
 q_popMemQueue;
   }
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm  
b/src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm

index 5a52b60..c2eb593 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm
@@ -255,6 +255,7 @@
   }

   action(v_allocateTBE, "v", desc="Allocate TBE entry") {
+check_allocate(TBEs);
 TBEs.allocate(address);
 set_tbe(TBEs[address]);
   }

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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: removed checkCoherence from MOESI_CMP_directory

2019-10-18 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/21923 )



Change subject: mem-ruby: removed checkCoherence from MOESI_CMP_directory
..

mem-ruby: removed checkCoherence from MOESI_CMP_directory

The implementation is empty and this is not used by other protocols

Change-Id: Iaed7d6d4b7ef1eb4cd47bdc0710dc9dbb7a86a0c
Signed-off-by: Tiago Mück 
---
M src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
M src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
M src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
3 files changed, 0 insertions(+), 11 deletions(-)



diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm  
b/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm

index b8d8ab4..d7b175c 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
@@ -215,7 +215,6 @@
  ((cache_entry.CacheState != State:O) && (state == State:O)) ) {

 cache_entry.CacheState := state;
-sequencer.checkCoherence(addr);
   }
   else {
 cache_entry.CacheState := state;
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm  
b/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm

index b3a170e..a04f167 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
@@ -523,13 +523,6 @@
 (state == State:SLS)) {
assert(is_valid(cache_entry));
assert(L2cache.isTagPresent(addr));
-
-   if ( ((cache_entry.CacheState != State:M) && (state == State:M)) ||
-   ((cache_entry.CacheState != State:S) && (state == State:S)) ||
-   ((cache_entry.CacheState != State:O) && (state == State:O)) ) {
-// disable Coherence Checker for now
-// sequencer.checkCoherence(addr);
-  }
 } else if ( (state == State:ILS) ||
 (state == State:ILX) ||
 (state == State:ILO) ||
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm  
b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm

index e1c287e..85e7946 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
@@ -155,9 +155,6 @@
 assert(getDirectoryEntry(addr).Sharers.count() == 0);

 directory.deallocate(addr);
-
-// disable coherence checker
-// sequencer.checkCoherence(addr);
   }

   State getState(TBE tbe, Addr addr) {

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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Deallocating unused entries in MOESI_CMP_dir

2019-10-18 Thread Tiago Mück (Gerrit)
assert(dir_entry.WaitingUnblocks == 0);
+}
+
+dir_entry.DirectoryState := state;
+
+  } else {
+assert(state == State:I);
   }
 }
   }

   AccessPermission getAccessPermission(Addr addr) {
 if (directory.isPresent(addr)) {
-  DPRINTF(RubySlicc, "%s\n",  
Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState));
-  return  
Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState);

+  Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
+  if (is_valid(dir_entry)) {
+DPRINTF(RubySlicc, "%s\n",  
Directory_State_to_permission(dir_entry.DirectoryState));

+return Directory_State_to_permission(dir_entry.DirectoryState);
+  } else {
+DPRINTF(RubySlicc, "%s\n", Directory_State_to_permission(State:I));
+return Directory_State_to_permission(State:I);
+  }
 }
-
 DPRINTF(RubySlicc, "AccessPermission_NotPresent\n");
 return AccessPermission:NotPresent;
   }

   void setAccessPermission(Addr addr, State state) {
 if (directory.isPresent(addr)) {
-   
getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));

+  Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
+  if (is_valid(dir_entry)) {
+dir_entry.changePermission(Directory_State_to_permission(state));
+  } else {
+assert(state == State:I);
+  }
 }
   }

@@ -317,6 +344,14 @@

   // Actions

+  action(allocDirEntry, "alloc", desc="Allocate directory entry") {
+allocateDirectoryEntry(address);
+  }
+
+  action(deallocDirEntry, "dealloc", desc="Deallocate directory entry") {
+deallocateDirectoryEntry(address);
+  }
+
   action(a_sendWriteBackAck, "a", desc="Send writeback ack to requestor") {
 peek(requestQueue_in, RequestMsg) {
   enqueue(responseNetwork_out, ResponseMsg, directory_latency) {
@@ -568,16 +603,19 @@

   // TRANSITIONS
   transition(I, GETX, MM) {
+allocDirEntry;
 qf_queueMemoryFetchRequest;
 i_popIncomingRequestQueue;
   }

   transition(I, DMA_READ, XI_M) {
+allocDirEntry;
 qf_queueMemoryFetchRequest;
 i_popIncomingRequestQueue;
   }

   transition(I, DMA_WRITE, XI_U) {
+allocDirEntry;
 qw_queueMemoryWBFromDMARequest;
 a_sendDMAAck;  // ack count may be zero
 i_popIncomingRequestQueue;
@@ -585,12 +623,14 @@

   transition(XI_M, Memory_Data, I) {
 d_sendDataMsg;  // ack count may be zero
+deallocDirEntry;
 q_popMemQueue;
   }

   transition(XI_U, Exclusive_Unblock, I) {
 cc_clearSharers;
 c_clearOwner;
+deallocDirEntry;
 j_popIncomingUnblockQueue;
   }

@@ -615,6 +655,7 @@
   }

   transition(I, GETS, IS) {
+allocDirEntry;
 qf_queueMemoryFetchRequest;
 i_popIncomingRequestQueue;
   }
@@ -780,6 +821,7 @@
 c_clearOwner;
 cc_clearSharers;
 qw_queueMemoryWBFromCacheRequest;
+deallocDirEntry;
 i_popIncomingRequestQueue;
   }

@@ -814,6 +856,7 @@
   transition(MI, Clean_Writeback, I) {
 c_clearOwner;
 cc_clearSharers;
+deallocDirEntry;
 i_popIncomingRequestQueue;
   }

@@ -830,7 +873,7 @@
 j_popIncomingUnblockQueue;
   }

-  transition({I, S, O, M, IS, SS, OO, MO, MM, MI, MIS, OS, OSS},  
Memory_Data) {
+  transition({S, O, M, IS, SS, OO, MO, MM, MI, MIS, OS, OSS}, Memory_Data)  
{

 d_sendDataMsg;
 q_popMemQueue;
   }

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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Fix MOESI_CMP_directory DMA handling

2019-10-18 Thread Tiago Mück (Gerrit)
t a/src/mem/ruby/protocol/RubySlicc_Types.sm  
b/src/mem/ruby/protocol/RubySlicc_Types.sm

index 2c0404d..101b251 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -62,7 +62,11 @@
 }

 external_type(NodeID, default="0", primitive="yes");
-external_type(MachineID);
+
+structure(MachineID, external = "yes", non_obj="yes") {
+  MachineType getType();
+  NodeID getNum();
+}

 structure (Set, external = "yes", non_obj="yes") {
   void setSize(int);

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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Check on PerfectCacheMemory deallocate

2019-10-18 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/21921 )



Change subject: mem-ruby: Check on PerfectCacheMemory deallocate
..

mem-ruby: Check on PerfectCacheMemory deallocate

Allowing deallocate to be called for non-existing blocks may hide
potential bugs.

Change-Id: Ida77e2db1da59d7cdb21d58968e1f17e75eaa6e0
Signed-off-by: Tiago Mück 
---
M src/mem/ruby/structures/PerfectCacheMemory.hh
1 file changed, 14 insertions(+), 1 deletion(-)



diff --git a/src/mem/ruby/structures/PerfectCacheMemory.hh  
b/src/mem/ruby/structures/PerfectCacheMemory.hh

index 363e3e8..9898995 100644
--- a/src/mem/ruby/structures/PerfectCacheMemory.hh
+++ b/src/mem/ruby/structures/PerfectCacheMemory.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
  * All rights reserved.
  *
@@ -138,7 +150,8 @@
 inline void
 PerfectCacheMemory::deallocate(Addr address)
 {
-m_map.erase(makeLineAddress(address));
+auto num_erased M5_VAR_USED = m_map.erase(makeLineAddress(address));
+assert(num_erased == 1);
 }

 // Returns with the physical address of the conflicting cache line

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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Support for non-blocking aliased requests

2019-10-08 Thread Tiago Mück (Gerrit)
tatus_BufferFull;
 }

+// Also check if we can enqueue the request
+if (!m_mandatory_q_ptr->areNSlotsAvailable(1, curTick()))
+return RequestStatus_BufferFull;
+
 RubyRequestType primary_type = RubyRequestType_NULL;
 RubyRequestType secondary_type = RubyRequestType_NULL;

@@ -656,7 +727,7 @@

 template 
 std::ostream &
-operator<<(ostream , const std::unordered_map )
+operator<<(ostream , const std::unordered_multimap )
 {
 auto i = map.begin();
 auto end = map.end();
diff --git a/src/mem/ruby/system/Sequencer.hh  
b/src/mem/ruby/system/Sequencer.hh

index 33fd530..076a122 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
  * All rights reserved.
  *
@@ -83,6 +95,22 @@
   const Cycles forwardRequestTime = Cycles(0),
   const Cycles firstResponseTime = Cycles(0));

+void writeCallback(PacketPtr pkt,
+   DataBlock& data,
+   const bool externalHit = false,
+   const MachineType mach = MachineType_NUM,
+   const Cycles initialRequestTime = Cycles(0),
+   const Cycles forwardRequestTime = Cycles(0),
+   const Cycles firstResponseTime = Cycles(0));
+
+void readCallback(PacketPtr pkt,
+  DataBlock& data,
+  const bool externalHit = false,
+  const MachineType mach = MachineType_NUM,
+  const Cycles initialRequestTime = Cycles(0),
+  const Cycles forwardRequestTime = Cycles(0),
+  const Cycles firstResponseTime = Cycles(0));
+
 RequestStatus makeRequest(PacketPtr pkt);
 bool empty() const;
 int outstandingCount() const { return m_outstanding_count; }
@@ -96,7 +124,6 @@
 void print(std::ostream& out) const;
 void checkCoherence(Addr address);

-void markRemoved();
 void evictionCallback(Addr address);
 void invalidateSC(Addr address);
 int coreId() const { return m_coreId; }
@@ -151,6 +178,20 @@
   private:
 void issueRequest(PacketPtr pkt, RubyRequestType type);

+void writeCallbackImpl(SequencerRequest *req, DataBlock& data,
+   const bool externalHit,
+   const MachineType mach,
+   const Cycles initialRequestTime,
+   const Cycles forwardRequestTime,
+   const Cycles firstResponseTime);
+
+void readCallbackImpl(SequencerRequest *req, DataBlock& data,
+   const bool externalHit,
+   const MachineType mach,
+   const Cycles initialRequestTime,
+   const Cycles forwardRequestTime,
+   const Cycles firstResponseTime);
+
 void hitCallback(SequencerRequest* request, DataBlock& data,
  bool llscSuccess,
  const MachineType mach, const bool externalHit,
@@ -168,6 +209,8 @@
 RequestStatus insertRequest(PacketPtr pkt, RubyRequestType  
request_type);

 bool handleLlsc(Addr address, SequencerRequest* request);

+bool fwdAliased() { return m_aliasing_mode ==  
RubyAliasingType_FORWARD; }

+
 // Private copy constructor and assignment operator
 Sequencer(const Sequencer& obj);
 Sequencer& operator=(const Sequencer& obj);
@@ -186,13 +229,18 @@
 Cycles m_data_cache_hit_latency;
 Cycles m_inst_cache_hit_latency;

-typedef std::unordered_map RequestTable;
+typedef std::unordered_multimap RequestTable;
 RequestTable m_writeRequestTable;
 RequestTable m_readRequestTable;
 // Global outstanding request count, across all request tables
 int m_outstanding_count;
 bool m_deadlock_check_scheduled;

+// Removes requests from a request table
+SequencerRequest* findAndRemoveRequest(Addr addr, RequestTable );
+SequencerRequest* findAndRemoveRequest(PacketPtr pkt, RequestTable  
);

+void markRemoved();
+
 //! Counters for recording aliasing information.
 Stats::Scalar m_store_waiting_on_load;
 Stats::Scalar m_store_waiting_on_store;

--
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[gem5-dev] Change in gem5/gem5[master]: mem-cache: mark block as dirty when handling SW prefetch

2019-07-31 Thread Tiago Mück (Gerrit)
b6bb284dee6545925ce
Gerrit-Change-Number: 19688
Gerrit-PatchSet: 2
Gerrit-Owner: Tiago Mück 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: Tiago Mück 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Giacomo Travaglini 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: mem-cache: mark block as dirty when handling SW prefetch

2019-07-30 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/19688 )



Change subject: mem-cache: mark block as dirty when handling SW prefetch
..

mem-cache: mark block as dirty when handling SW prefetch

This addresses the issue described in
64687ee mem-cache: Mark block as dirty after a SWPrefetchEXResp.

Previous patch misses cases when the prefetch response is ReadExResp or
UpgradeResp. Also, marking the block as dirty in serviceMSHRTargets
instead of in handleFill covers cases when the prefetch is coalesced with
other requests.

Change-Id: I2b377fdd240eb0f09e720b6bb284dee6545925ce
Signed-off-by: Tiago Mück 
---
M src/mem/cache/base.cc
M src/mem/cache/cache.cc
2 files changed, 26 insertions(+), 24 deletions(-)



diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 082650c..0de7f21 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -1409,30 +1409,6 @@
 chatty_assert(!isReadOnly, "Should never see dirty snoop  
response "

   "in read-only cache %s\n", name());

-} else if (pkt->cmd.isSWPrefetch() && pkt->needsWritable()) {
-// All other copies of the block were invalidated and we
-// have an exclusive copy.
-
-// The coherence protocol assumes that if we fetched an
-// exclusive copy of the block, we have the intention to
-// modify it. Therefore the MSHR for the PrefetchExReq has
-// been the point of ordering and this cache has commited
-// to respond to snoops for the block.
-//
-// In most cases this is true anyway - a PrefetchExReq
-// will be followed by a WriteReq. However, if that
-// doesn't happen, the block is not marked as dirty and
-// the cache doesn't respond to snoops that has committed
-// to do so.
-//
-// To avoid deadlocks in cases where there is a snoop
-// between the PrefetchExReq and the expected WriteReq, we
-// proactively mark the block as Dirty.
-
-blk->status |= BlkDirty;
-
-panic_if(!isReadOnly, "Prefetch exclusive requests from  
read-only "

- "cache %s\n", name());
 }
 }

diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index bded746..b054cd4 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -710,6 +710,32 @@

 // Software prefetch handling for cache closest to core
 if (tgt_pkt->cmd.isSWPrefetch()) {
+if (tgt_pkt->needsWritable()) {
+// All other copies of the block were invalidated and  
we

+// have an exclusive copy.
+
+// The coherence protocol assumes that if we fetched an
+// exclusive copy of the block, we have the intention  
to
+// modify it. Therefore the MSHR for the PrefetchExReq  
has
+// been the point of ordering and this cache has  
commited

+// to respond to snoops for the block.
+//
+// In most cases this is true anyway - a PrefetchExReq
+// will be followed by a WriteReq. However, if that
+// doesn't happen, the block is not marked as dirty and
+// the cache doesn't respond to snoops that has  
committed

+// to do so.
+//
+// To avoid deadlocks in cases where there is a snoop
+// between the PrefetchExReq and the expected  
WriteReq, we

+// proactively mark the block as Dirty.
+assert(blk);
+blk->status |= BlkDirty;
+
+panic_if(isReadOnly, "Prefetch exclusive requests  
from "

+"read-only cache %s\n", name());
+}
+
 // a software prefetch would have already been ack'd
 // immediately with dummy data so the core would be able to
 // retire it. This request completes right here, so we

--
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[gem5-dev] Change in gem5/gem5[master]: dev-arm: A9SCU fixup

2019-07-10 Thread Tiago Mück (Gerrit)
Tiago Mück has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/19408 )


Change subject: dev-arm: A9SCU fixup
..

dev-arm: A9SCU fixup

Shifting instead of expensive power.

Change-Id: I164933257db125e18721c5b8bcaf9702030ebf40
Signed-off-by: Tiago Mück 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19408
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/dev/arm/a9scu.cc
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/a9scu.cc b/src/dev/arm/a9scu.cc
index 677101b..20a0c33 100644
--- a/src/dev/arm/a9scu.cc
+++ b/src/dev/arm/a9scu.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2010,2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -73,7 +73,7 @@
 fatal("Too many CPUs (%d) for A9SCU!\n",  
sys->numContexts());

 }
 int smp_bits, core_cnt;
-smp_bits = power(2,sys->numContexts()) - 1;
+smp_bits = (1 << sys->numContexts()) - 1;
 core_cnt = sys->numContexts() - 1;
 pkt->setLE(smp_bits << 4 | core_cnt);
 break;

--
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Gerrit-Change-Number: 19408
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[gem5-dev] Change in gem5/gem5[master]: dev-arm: A9SCU fixup

2019-07-08 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/19408



Change subject: dev-arm: A9SCU fixup
..

dev-arm: A9SCU fixup

Shifting instead of expensive power.

Change-Id: I164933257db125e18721c5b8bcaf9702030ebf40
Signed-off-by: Tiago Mück 
---
M src/dev/arm/a9scu.cc
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/dev/arm/a9scu.cc b/src/dev/arm/a9scu.cc
index 677101b..20a0c33 100644
--- a/src/dev/arm/a9scu.cc
+++ b/src/dev/arm/a9scu.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2010,2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -73,7 +73,7 @@
 fatal("Too many CPUs (%d) for A9SCU!\n",  
sys->numContexts());

 }
 int smp_bits, core_cnt;
-smp_bits = power(2,sys->numContexts()) - 1;
+smp_bits = (1 << sys->numContexts()) - 1;
 core_cnt = sys->numContexts() - 1;
 pkt->setLE(smp_bits << 4 | core_cnt);
 break;

--
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[gem5-dev] Change in gem5/gem5[master]: dev-arm: Check for gem5 extensions in GicV2

2019-06-21 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/19288



Change subject: dev-arm: Check for gem5 extensions in GicV2
..

dev-arm: Check for gem5 extensions in GicV2

Using GicV2 without setting the gem5_extensions parameter in a
config  with more than 8 is not allowed to prevent overflow of
the 8-bit mask.

Change-Id: I780c6985e8f44ed780b4f74f9a27805124e23a7b
Signed-off-by: Tiago Mück 
---
M src/dev/arm/gic_v2.hh
1 file changed, 6 insertions(+), 3 deletions(-)



diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh
index f9b66b8..4104140 100644
--- a/src/dev/arm/gic_v2.hh
+++ b/src/dev/arm/gic_v2.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
+ * Copyright (c) 2010, 2013, 2015-2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -309,8 +309,11 @@
 if (gem5ExtensionsEnabled) {
 ctx_mask = ctx;
 } else {
-// convert the CPU id number into a bit mask
-ctx_mask = power(2, ctx);
+fatal_if(ctx >= 8,
+"%s requires the gem5_extensions parameter to support "
+"more than 8 cores\n", name());
+// convert the CPU id number into a bit mask
+ctx_mask = 1 << ctx;
 }
 return ctx_mask;
 } else {

--
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[gem5-dev] Change in gem5/gem5[master]: misc: dot_writer fixup

2019-06-18 Thread Tiago Mück (Gerrit)
Tiago Mück has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/19208 )


Change subject: misc: dot_writer fixup
..

misc: dot_writer fixup

In large configs the tooltip may be greater then the maximum line
size graphviz supports when parsing the dot file (typically 16k).
Adding '/' causes graphviz to break the string in multiple lines
while parsing and works around this limitation.

Change-Id: I16a0030127de4165080de97f5213309eed9fdeca
Signed-off-by: Tiago Mück 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19208
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/python/m5/util/dot_writer.py
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/python/m5/util/dot_writer.py  
b/src/python/m5/util/dot_writer.py

index 3cec38f..d1fe946 100644
--- a/src/python/m5/util/dot_writer.py
+++ b/src/python/m5/util/dot_writer.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012-2013 ARM Limited
+# Copyright (c) 2012-2013,2019 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -154,7 +154,7 @@
 ini_strings.append(str(param) + "" +
simNode._values[param].ini_str())
 # join all the parameters with an HTML newline
-tooltip = "".join(ini_strings)
+tooltip = "\\".join(ini_strings)

 return pydot.Cluster( \
  full_path, \

--
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[gem5-dev] Change in gem5/gem5[master]: misc: dot_writer fixup

2019-06-14 Thread Tiago Mück (Gerrit)

Hello kokoro, Jason Lowe-Power,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/19208

to look at the new patch set (#2).

Change subject: misc: dot_writer fixup
..

misc: dot_writer fixup

In large configs the tooltip may be greater then the maximum line
size graphviz supports when parsing the dot file (typically 16k).
Adding '/' causes graphviz to break the string in multiple lines
while parsing and works around this limitation.

Change-Id: I16a0030127de4165080de97f5213309eed9fdeca
Signed-off-by: Tiago Mück 
---
M src/python/m5/util/dot_writer.py
1 file changed, 2 insertions(+), 2 deletions(-)


--
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[gem5-dev] Change in gem5/gem5[master]: base: AddrRange does not merge single interleaved ranges

2019-06-13 Thread Tiago Mück (Gerrit)
Tiago Mück has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18788 )


Change subject: base: AddrRange does not merge single interleaved ranges
..

base: AddrRange does not merge single interleaved ranges

AddrRange does not attempt to merge interleaved address ranges if it
has only one of the ranges.

This is needed to allow XBars to accept request targeting only one
part of a interleaved address range. A use case for this would be
modeling distributed LLCs in which a XBar is used solely to
encapsulate the snoop filter of a single LLC slice.

Change-Id: If71c9cf1444ee11916611afb51eab3a4f1d93985
Signed-off-by: Tiago Muck 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18788
Reviewed-by: Nikos Nikoleris 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/base/addr_range.hh
1 file changed, 6 insertions(+), 0 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/addr_range.hh b/src/base/addr_range.hh
index 1d2dc73..cda6ccf 100644
--- a/src/base/addr_range.hh
+++ b/src/base/addr_range.hh
@@ -213,6 +213,11 @@
 _start = ranges.front()._start;
 _end = ranges.front()._end;
 masks = ranges.front().masks;
+intlvMatch = ranges.front().intlvMatch;
+}
+// either merge if got all ranges or keep this equal to the single
+// interleaved range
+if (ranges.size() > 1) {

 if (ranges.size() != (ULL(1) << masks.size()))
 fatal("Got %d ranges spanning %d interleaving bits\n",
@@ -231,6 +236,7 @@
 ++match;
 }
 masks.clear();
+intlvMatch = 0;
 }
 }


--
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Gerrit-Change-Number: 18788
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück 
Gerrit-Assignee: Nikos Nikoleris 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: Tiago Mück 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Andreas Sandberg 
Gerrit-CC: Anthony Gutierrez 
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[gem5-dev] Change in gem5/gem5[master]: sim: Add scheduleInstStop to System

2019-06-12 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/19209



Change subject: sim: Add scheduleInstStop to System
..

sim: Add scheduleInstStop to System

scheduleInstStop schedules an event to stop the simulation when the total
number of simulated instructions by all CPUs reaches the given value.

Change-Id: Iea0222016150988519776ceef53901ccbfd74d41
Signed-off-by: Tiago Mück 
---
M src/sim/System.py
M src/sim/system.cc
M src/sim/system.hh
3 files changed, 30 insertions(+), 3 deletions(-)



diff --git a/src/sim/System.py b/src/sim/System.py
index 9928887..ad8ceb1 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2017 ARM Limited
+# Copyright (c) 2017,2019 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -61,6 +61,14 @@
 PyBindMethod("setMemoryMode"),
 ]

+@cxxMethod
+def scheduleInstStop(self, insts, cause):
+"""
+Schedules an event to stop the simulation when the total number of
+simulated instructions by all CPUs reaches the given value.
+"""
+pass
+
 memories = VectorParam.AbstractMemory(Self.all,
   "All memories in the system")
 mem_mode = Param.MemoryMode('atomic', "The mode the memory system is  
in")

diff --git a/src/sim/system.cc b/src/sim/system.cc
index 7476965..2b2dfc3 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2014,2017-2018 ARM Limited
+ * Copyright (c) 2011-2014,2017-2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -71,6 +71,7 @@
 #include "sim/debug.hh"
 #include "sim/full_system.hh"
 #include "sim/redirect_path.hh"
+#include "sim/sim_events.hh"

 /**
  * To avoid linking errors with LTO, only include the header if we
@@ -475,6 +476,15 @@
 }

 void
+System::scheduleInstStop(Counter insts, const char *cause)
+{
+const Tick now(instEventQueue.getCurTick());
+Event *event(new LocalSimLoopExitEvent(cause, 0));
+
+instEventQueue.schedule(event, now + insts);
+}
+
+void
 System::printSystems()
 {
 ios::fmtflags flags(cerr.flags());
diff --git a/src/sim/system.hh b/src/sim/system.hh
index d7a3b20..1a0f43a 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012, 2014, 2018 ARM Limited
+ * Copyright (c) 2012, 2014, 2018, 2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -607,6 +607,15 @@
 std::map, Tick>  lastWorkItemStarted;
 std::map workItemStats;

+/**
+ * Schedules an event to stop the simulation when the total number of
+ * simulated instructions by all CPUs reaches the given value.
+ *
+ * @param insts Maximum number of simulated instructions
+ * @param cause Description to be passed to the event
+ */
+void scheduleInstStop(Counter insts, const char *cause);
+
 
 //
 // STATIC GLOBAL SYSTEM LIST

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[gem5-dev] Change in gem5/gem5[master]: config: --maxinstsTotal option added

2019-06-12 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/19210



Change subject: config: --maxinstsTotal option added
..

config: --maxinstsTotal option added

--maxinstsTotal stops the simulation when the total number of simulated
instructions reaches the given value. Also updated the --maxinsts help
message for clarification.

Change-Id: Ie0deeccd0f4c698a5cb718f1779042add83227fc
Signed-off-by: Tiago Mück 
---
M configs/common/Options.py
M configs/common/Simulation.py
2 files changed, 10 insertions(+), 2 deletions(-)



diff --git a/configs/common/Options.py b/configs/common/Options.py
index f6fa0d0..f44399d 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2013 ARM Limited
+# Copyright (c) 2013,2019 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -268,6 +268,10 @@
 # Run duration options
 parser.add_option("-I", "--maxinsts", action="store", type="int",
   default=None, help="""Total number of instructions to
+simulate in any thread
+(default: run forever)""")
+parser.add_option("--maxinstsTotal", action="store", type="int",
+  default=None, help="""Total number of instructions to
 simulate (default: run  
forever)""")

 parser.add_option("--work-item-id", action="store", type="int",
   help="the specific work id for exit & checkpointing")
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py
index 56107c1..723cba3 100644
--- a/configs/common/Simulation.py
+++ b/configs/common/Simulation.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012-2013 ARM Limited
+# Copyright (c) 2012-2013,2019 ARM Limited
 # All rights reserved
 #
 # The license below extends only to copyright in the software and shall
@@ -614,6 +614,10 @@
 root.apply_config(options.param)
 m5.instantiate(checkpoint_dir)

+if options.maxinstsTotal:
+testsys.scheduleInstStop(options.maxinstsTotal,
+"the system reached the max instruction  
count")

+
 # Initialization is complete.  If we're not in control of simulation
 # (that is, if we're a slave simulator acting as a component in another
 #  'master' simulator) then we're done here.  The other simulator will

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[gem5-dev] Change in gem5/gem5[master]: misc: dot_writer fixup

2019-06-12 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/19208



Change subject: misc: dot_writer fixup
..

misc: dot_writer fixup

Using multiple lines for the tooltip to avoid having a single string
larger than graphviz YY_BUF_SIZE (typically 16k).

Change-Id: I16a0030127de4165080de97f5213309eed9fdeca
Signed-off-by: Tiago Mück 
---
M src/python/m5/util/dot_writer.py
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/python/m5/util/dot_writer.py  
b/src/python/m5/util/dot_writer.py

index 3cec38f..d1fe946 100644
--- a/src/python/m5/util/dot_writer.py
+++ b/src/python/m5/util/dot_writer.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012-2013 ARM Limited
+# Copyright (c) 2012-2013,2019 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -154,7 +154,7 @@
 ini_strings.append(str(param) + "" +
simNode._values[param].ini_str())
 # join all the parameters with an HTML newline
-tooltip = "".join(ini_strings)
+tooltip = "\\".join(ini_strings)

 return pydot.Cluster( \
  full_path, \

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[gem5-dev] Change in gem5/gem5[master]: base: AddrRange does not merge single interleaved ranges

2019-06-12 Thread Tiago Mück (Gerrit)

Hello Matthew Poremba, Nikos Nikoleris,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/18788

to look at the new patch set (#4).

Change subject: base: AddrRange does not merge single interleaved ranges
..

base: AddrRange does not merge single interleaved ranges

AddrRange does not attempt to merge interleaved address ranges if it
has only one of the ranges.

This is needed to allow XBars to accept request targeting only one
part of a interleaved address range. A use case for this would be
modeling distributed LLCs in which a XBar is used solely to
encapsulate the snoop filter of a single LLC slice.

Change-Id: If71c9cf1444ee11916611afb51eab3a4f1d93985
Signed-off-by: Tiago Muck 
---
M src/base/addr_range.hh
1 file changed, 6 insertions(+), 0 deletions(-)


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Gerrit-Change-Number: 18788
Gerrit-PatchSet: 4
Gerrit-Owner: Tiago Mück 
Gerrit-Assignee: Nikos Nikoleris 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: Tiago Mück 
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[gem5-dev] Change in gem5/gem5[master]: cpu: TrafficGen as BaseCPU

2019-06-11 Thread Tiago Mück (Gerrit)
Tiago Mück has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18416 )


Change subject: cpu: TrafficGen as BaseCPU
..

cpu: TrafficGen as BaseCPU

TrafficGen has additional attributes to behave like a BaseCPU. Python
scripts that expect sim. objects derived from BaseCPU can now be used with
TrafficGen without additional modifications.

Change-Id: Iee848b2ba0ac1851c487b1003da9bd96253d291a
Signed-off-by: Tiago Muck 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18416
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/cpu/testers/traffic_gen/BaseTrafficGen.py
1 file changed, 37 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/testers/traffic_gen/BaseTrafficGen.py  
b/src/cpu/testers/traffic_gen/BaseTrafficGen.py

index 7fd8b30..00fe087 100644
--- a/src/cpu/testers/traffic_gen/BaseTrafficGen.py
+++ b/src/cpu/testers/traffic_gen/BaseTrafficGen.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012, 2016, 2018 ARM Limited
+# Copyright (c) 2012, 2016, 2018, 2019 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -85,3 +85,39 @@
 # Sources for Stream/Substream IDs to apply to requests
 sids = VectorParam.Unsigned([], "StreamIDs to use")
 ssids = VectorParam.Unsigned([], "SubstreamIDs to use")
+
+# These additional parameters allow TrafficGen to be used with scripts
+# that expect a BaseCPU
+cpu_id = Param.Int(-1, "CPU identifier")
+socket_id = Param.Unsigned(0, "Physical Socket identifier")
+numThreads = Param.Unsigned(1, "number of HW thread contexts")
+
+@classmethod
+def memory_mode(cls):
+return 'timing'
+
+@classmethod
+def require_caches(cls):
+return False
+
+def createThreads(self):
+pass
+
+def createInterruptController(self):
+pass
+
+def connectCachedPorts(self, bus):
+if hasattr(self, '_cached_ports') and (len(self._cached_ports) >  
0):

+for p in self._cached_ports:
+exec('self.%s = bus.slave' % p)
+else:
+self.port = bus.slave
+
+def connectAllPorts(self, cached_bus, uncached_bus = None):
+self.connectCachedPorts(cached_bus)
+
+def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
+self.dcache = dc
+self.port = dc.cpu_side
+self._cached_ports = ['dcache.mem_side']
+self._uncached_ports = []

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Gerrit-PatchSet: 2
Gerrit-Owner: Tiago Mück 
Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in gem5/gem5[master]: cpu: Additional TrafficGen stats

2019-06-11 Thread Tiago Mück (Gerrit)
Tiago Mück has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18418 )


Change subject: cpu: Additional TrafficGen stats
..

cpu: Additional TrafficGen stats

Additional stats to keep track of read/write latencies and throughput.

Change-Id: I7684cd33cf68fffdef4ca9c3a6db360a0f531c18
Signed-off-by: Tiago Muck 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18418
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/cpu/testers/traffic_gen/base.cc
M src/cpu/testers/traffic_gen/base.hh
2 files changed, 85 insertions(+), 0 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/testers/traffic_gen/base.cc  
b/src/cpu/testers/traffic_gen/base.cc

index f2385a4..154b1bd 100644
--- a/src/cpu/testers/traffic_gen/base.cc
+++ b/src/cpu/testers/traffic_gen/base.cc
@@ -354,6 +354,51 @@
 retryTicks
 .name(name() + ".retryTicks")
 .desc("Time spent waiting due to back-pressure (ticks)");
+
+bytesRead
+.name(name() + ".bytesRead")
+.desc("Number of bytes read");
+
+bytesWritten
+.name(name() + ".bytesWritten")
+.desc("Number of bytes written");
+
+totalReadLatency
+.name(name() + ".totalReadLatency")
+.desc("Total latency of read requests");
+
+totalWriteLatency
+.name(name() + ".totalWriteLatency")
+.desc("Total latency of write requests");
+
+totalReads
+.name(name() + ".totalReads")
+.desc("Total num of reads");
+
+totalWrites
+.name(name() + ".totalWrites")
+.desc("Total num of writes");
+
+avgReadLatency
+.name(name() + ".avgReadLatency")
+.desc("Avg latency of read requests");
+avgReadLatency = totalReadLatency / totalReads;
+
+avgWriteLatency
+.name(name() + ".avgWriteLatency")
+.desc("Avg latency of write requests");
+avgWriteLatency = totalWriteLatency / totalWrites;
+
+readBW
+.name(name() + ".readBW")
+.desc("Read bandwidth in bytes/s");
+readBW = bytesRead / simSeconds;
+
+writeBW
+.name(name() + ".writeBW")
+.desc("Write bandwidth in bytes/s");
+writeBW = bytesWritten / simSeconds;
+
 }

 std::shared_ptr
@@ -470,6 +515,16 @@

 assert(iter->second <= curTick());

+if (pkt->isWrite()) {
+++totalWrites;
+bytesWritten += pkt->req->getSize();
+totalWriteLatency += curTick() - iter->second;
+} else {
+++totalReads;
+bytesRead += pkt->req->getSize();
+totalReadLatency += curTick() - iter->second;
+}
+
 waitingResp.erase(iter);

 delete pkt;
diff --git a/src/cpu/testers/traffic_gen/base.hh  
b/src/cpu/testers/traffic_gen/base.hh

index 5ffe508..985ab5d 100644
--- a/src/cpu/testers/traffic_gen/base.hh
+++ b/src/cpu/testers/traffic_gen/base.hh
@@ -206,6 +206,36 @@
 /** Reqs waiting for response **/
 std::unordered_map waitingResp;

+/** Count the number of bytes read. */
+Stats::Scalar bytesRead;
+
+/** Count the number of bytes written. */
+Stats::Scalar bytesWritten;
+
+/** Total num of ticks read reqs took to complete  */
+Stats::Scalar totalReadLatency;
+
+/** Total num of ticks write reqs took to complete  */
+Stats::Scalar totalWriteLatency;
+
+/** Count the number reads. */
+Stats::Scalar totalReads;
+
+/** Count the number writes. */
+Stats::Scalar totalWrites;
+
+/** Avg num of ticks each read req took to complete  */
+Stats::Formula avgReadLatency;
+
+/** Avg num of ticks each write reqs took to complete  */
+Stats::Formula avgWriteLatency;
+
+/** Read bandwidth in bytes/s  */
+Stats::Formula readBW;
+
+/** Write bandwidth in bytes/s  */
+Stats::Formula writeBW;
+
   public:
 BaseTrafficGen(const BaseTrafficGenParams* p);


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Gerrit-Change-Number: 18418
Gerrit-PatchSet: 2
Gerrit-Owner: Tiago Mück 
Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in gem5/gem5[master]: cpu: Limit TrafficGen outstanding reqs

2019-06-11 Thread Tiago Mück (Gerrit)
, 2016-2018 ARM Limited
+ * Copyright (c) 2012-2013, 2016-2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -44,6 +44,7 @@

 #include 
 #include 
+#include 

 #include "base/statistics.hh"
 #include "mem/qport.hh"
@@ -93,6 +94,10 @@
  */
 void recvReqRetry();

+void retryReq();
+
+bool recvTimingResp(PacketPtr pkt);
+
 /** Transition to the next generator */
 void transition();

@@ -118,6 +123,8 @@
 /** Time of the next packet. */
 Tick nextPacketTick;

+const int maxOutstandingReqs;
+

 /** Master port specialisation for the traffic generator */
 class TrafficGenPort : public MasterPort
@@ -132,7 +139,8 @@

 void recvReqRetry() { trafficGen.recvReqRetry(); }

-bool recvTimingResp(PacketPtr pkt);
+bool recvTimingResp(PacketPtr pkt)
+{ return trafficGen.recvTimingResp(pkt); }

 void recvTimingSnoopReq(PacketPtr pkt) { }

@@ -161,6 +169,24 @@
 /** Tick when the stalled packet was meant to be sent. */
 Tick retryPktTick;

+/** Set when we blocked waiting for outstanding reqs */
+bool blockedWaitingResp;
+
+/**
+ * Puts this packet in the waitingResp list and returns true if
+ * we are above the maximum number of oustanding requests.
+ */
+bool allocateWaitingRespSlot(PacketPtr pkt)
+{
+assert(waitingResp.find(pkt->req) == waitingResp.end());
+assert(pkt->needsResponse());
+
+waitingResp[pkt->req] = curTick();
+
+return (maxOutstandingReqs > 0) &&
+   (waitingResp.size() > maxOutstandingReqs);
+}
+
 /** Event for scheduling updates */
 EventFunctionWrapper updateEvent;

@@ -177,6 +203,9 @@
 /** Count the time incurred from back-pressure. */
 Stats::Scalar retryTicks;

+/** Reqs waiting for response **/
+std::unordered_map waitingResp;
+
   public:
 BaseTrafficGen(const BaseTrafficGenParams* p);


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[gem5-dev] Change in gem5/gem5[master]: base: AddrRange does not merge single interleaved ranges

2019-05-31 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded a new patch set (#3). (  
https://gem5-review.googlesource.com/c/public/gem5/+/18788 )


Change subject: base: AddrRange does not merge single interleaved ranges
..

base: AddrRange does not merge single interleaved ranges

AddrRange does not attempt to merge interleaved address ranges if it
has only one of the ranges.

This is needed to allow XBars to accept request targeting only one
part of a interleaved address range. A use case for this would be
modeling distributed LLCs in which a XBar is used solely to
encapsulate the snoop filter of a single LLC slice.

Change-Id: If71c9cf1444ee11916611afb51eab3a4f1d93985
Signed-off-by: Tiago Muck 
---
M src/base/addr_range.hh
1 file changed, 6 insertions(+), 1 deletion(-)


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Gerrit-Change-Number: 18788
Gerrit-PatchSet: 3
Gerrit-Owner: Tiago Mück 
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[gem5-dev] Change in gem5/gem5[master]: cpu: Fix rescheduling of progress check events

2019-05-30 Thread Tiago Mück (Gerrit)
Tiago Mück has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18793 )


Change subject: cpu: Fix rescheduling of progress check events
..

cpu: Fix rescheduling of progress check events

noRequestEvent needs to be rescheduled on recvRetry, otherwise the timeout
may be triggered even though packets are being eventually sent.
noResponseEvent scheduling is also fixed. This timeout should not be
active when we are not expecting a response.

Change-Id: If9edb75b5b803caf9f99bf41ea3948b15a3f3d71
Signed-off-by: Tiago Muck 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18793
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/cpu/testers/memtest/memtest.cc
1 file changed, 12 insertions(+), 4 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/testers/memtest/memtest.cc  
b/src/cpu/testers/memtest/memtest.cc

index 93a6ac6..742cf3b 100644
--- a/src/cpu/testers/memtest/memtest.cc
+++ b/src/cpu/testers/memtest/memtest.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015 ARM Limited
+ * Copyright (c) 2015, 2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -120,7 +120,6 @@
 // kick things into action
 schedule(tickEvent, curTick());
 schedule(noRequestEvent, clockEdge(progressCheck));
-schedule(noResponseEvent, clockEdge(progressCheck));
 }

 Port &
@@ -189,8 +188,12 @@
 // the packet will delete the data
 delete pkt;

-// finally shift the response timeout forward
-reschedule(noResponseEvent, clockEdge(progressCheck), true);
+// finally shift the response timeout forward if we are still
+// expecting responses; deschedule it otherwise
+if (outstandingAddrs.size() != 0)
+reschedule(noResponseEvent, clockEdge(progressCheck));
+else if (noResponseEvent.scheduled())
+deschedule(noResponseEvent);
 }

 void
@@ -303,6 +306,10 @@
 } else {
 DPRINTF(MemTest, "Waiting for retry\n");
 }
+
+// Schedule noResponseEvent now if we are expecting a response
+if (!noResponseEvent.scheduled() && (outstandingAddrs.size() != 0))
+schedule(noResponseEvent, clockEdge(progressCheck));
 }

 void
@@ -327,6 +334,7 @@
 retryPkt = nullptr;
 // kick things into action again
 schedule(tickEvent, clockEdge(interval));
+reschedule(noRequestEvent, clockEdge(progressCheck), true);
 }
 }


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[gem5-dev] Change in gem5/gem5[master]: cpu: Fix rescheduling of progress check events

2019-05-29 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded a new patch set (#2). (  
https://gem5-review.googlesource.com/c/public/gem5/+/18793 )


Change subject: cpu: Fix rescheduling of progress check events
..

cpu: Fix rescheduling of progress check events

noRequestEvent needs to be rescheduled on recvRetry, otherwise the timeout
may be triggered even though packets are being eventually sent.
noResponseEvent scheduling is also fixed. This timeout should not be
active when we are not expecting a response.

Change-Id: If9edb75b5b803caf9f99bf41ea3948b15a3f3d71
Signed-off-by: Tiago Muck 
---
M src/cpu/testers/memtest/memtest.cc
1 file changed, 12 insertions(+), 4 deletions(-)


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[gem5-dev] Change in gem5/gem5[master]: mem: Parameterize coherent xbar sanity checks

2019-05-28 Thread Tiago Mück (Gerrit)
ter;

+/** Cycles of snoop response latency.*/
 const Cycles snoopResponseLatency;
+
+/** Maximum number of outstading snoops sanity check*/
+const unsigned int maxOutstandingSnoopCheck;
+
+/** Maximum routing table size sanity check*/
+const unsigned int maxRoutingTableSizeCheck;
+
+/** Is this crossbar the point of coherency? **/
 const bool pointOfCoherency;
+
+/** Is this crossbar the point of unification? **/
 const bool pointOfUnification;

 /**

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[gem5-dev] Change in gem5/gem5[master]: mem: Snoop filter support for large systems

2019-05-28 Thread Tiago Mück (Gerrit)
m.requested, sf_item.holder);

 // The source should have the line
-panic_if(!(sf_item.holder & rsp_mask), "SF value %x.%x does not have "\
- "the line\n", sf_item.requested, sf_item.holder);
+panic_if((sf_item.holder & rsp_mask).none(),
+ "SF value %x.%x does not have the line\n",
+ sf_item.requested, sf_item.holder);

 // The destination should have had a request in
-panic_if(!(sf_item.requested & req_mask), "SF value %x.%x missing "\
+panic_if((sf_item.requested & req_mask).none(), "SF value %x.%x  
missing "\

  "the original request\n",  sf_item.requested, sf_item.holder);

 // If the snoop response has no sharers the line is passed in
@@ -287,7 +291,7 @@
 // @todo Deal with invalidating responses
 sf_item.holder |=  req_mask;
 sf_item.requested &= ~req_mask;
-assert(sf_item.requested | sf_item.holder);
+assert((sf_item.requested | sf_item.holder).any());
 DPRINTF(SnoopFilter, "%s:   new SF value %x.%x\n",
 __func__, sf_item.requested, sf_item.holder);
 }
@@ -359,8 +363,9 @@
 __func__,  sf_item.requested, sf_item.holder);

 // Make sure we have seen the actual request, too
-panic_if(!(sf_item.requested & slave_mask), "SF value %x.%x missing "\
- "request bit\n", sf_item.requested, sf_item.holder);
+panic_if((sf_item.requested & slave_mask).none(),
+ "SF value %x.%x missing request bit\n",
+ sf_item.requested, sf_item.holder);

 sf_item.requested &= ~slave_mask;
 // Update the residency of the cache line.
@@ -376,7 +381,7 @@
 // Any other response implies that a cache above will have the
 // block.
 sf_item.holder |= slave_mask;
-assert(sf_item.holder | sf_item.requested);
+assert((sf_item.holder | sf_item.requested).any());
 }
 DPRINTF(SnoopFilter, "%s:   new SF value %x.%x\n",
 __func__, sf_item.requested, sf_item.holder);
diff --git a/src/mem/snoop_filter.hh b/src/mem/snoop_filter.hh
index 85cc75e..9c06615 100644
--- a/src/mem/snoop_filter.hh
+++ b/src/mem/snoop_filter.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2016 ARM Limited
+ * Copyright (c) 2013-2016,2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -45,6 +45,7 @@
 #ifndef __MEM_SNOOP_FILTER_HH__
 #define __MEM_SNOOP_FILTER_HH__

+#include 
 #include 
 #include 

@@ -86,6 +87,10 @@
  */
 class SnoopFilter : public SimObject {
   public:
+
+// Change for systems with more than 256 ports tracked by this object
+static const int SNOOP_MASK_SIZE = 256;
+
 typedef std::vector SnoopList;

 SnoopFilter (const SnoopFilterParams *p) :
@@ -114,9 +119,9 @@
 }

 // make sure we can deal with this many ports
-fatal_if(id > 8 * sizeof(SnoopMask),
+fatal_if(id > SNOOP_MASK_SIZE,
  "Snoop filter only supports %d snooping ports, got %d\n",
- 8 * sizeof(SnoopMask), id);
+ SNOOP_MASK_SIZE, id);
 }

 /**
@@ -198,13 +203,9 @@

 /**
  * The underlying type for the bitmask we use for tracking. This
- * limits the number of snooping ports supported per crossbar. For
- * the moment it is an uint64_t to offer maximum
- * scalability. However, it is possible to use e.g. a uint16_t or
- * uint32_to slim down the footprint of the hash map (and
- * ultimately improve the simulation performance).
+ * limits the number of snooping ports supported per crossbar.
  */
-typedef uint64_t SnoopMask;
+typedef std::bitset SnoopMask;

 /**
 * Per cache line item tracking a bitmask of SlavePorts who have an
@@ -314,7 +315,7 @@
 {
 SnoopList res;
 for (const auto& p : slavePorts)
-if (port_mask & portToMask(*p))
+if ((port_mask & portToMask(*p)).any())
     res.push_back(p);
 return res;
 }

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I216882300500e2dcb789889756e73a1033271621
Gerrit-Change-Number: 18791
Gerrit-PatchSet: 2
Gerrit-Owner: Tiago Mück 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: Tiago Mück 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: base: Add warn_if_once macro

2019-05-28 Thread Tiago Mück (Gerrit)
Tiago Mück has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18420 )


Change subject: base: Add warn_if_once macro
..

base: Add warn_if_once macro

Change-Id: Ie68f3b07a35ed2e6b0eee20b3b34050542fcdc6c
Signed-off-by: Tiago Muck 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18420
Reviewed-by: Brandon Potter 
Reviewed-by: Daniel Carvalho 
Reviewed-by: Nikos Nikoleris 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/base/logging.hh
1 file changed, 7 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Brandon Potter: Looks good to me, approved
  Nikos Nikoleris: Looks good to me, approved
  Daniel Carvalho: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/logging.hh b/src/base/logging.hh
index 1c504d2..7040037 100644
--- a/src/base/logging.hh
+++ b/src/base/logging.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, 2017 ARM Limited
+ * Copyright (c) 2014, 2017, 2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -231,6 +231,12 @@
 warn(__VA_ARGS__); \
 } while (0)

+#define warn_if_once(cond, ...) \
+do { \
+if ((cond)) \
+warn_once(__VA_ARGS__); \
+} while (0)
+
 /**
  * The chatty assert macro will function like a normal assert, but will  
allow
  * the specification of additional, helpful material to aid debugging why  
the


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Gerrit-Change-Id: Ie68f3b07a35ed2e6b0eee20b3b34050542fcdc6c
Gerrit-Change-Number: 18420
Gerrit-PatchSet: 2
Gerrit-Owner: Tiago Mück 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Daniel Carvalho 
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[gem5-dev] Change in gem5/gem5[master]: mem: Add invalid context id check on LLSC checks

2019-05-22 Thread Tiago Mück (Gerrit)
Tiago Mück has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18792 )


Change subject: mem: Add invalid context id check on LLSC checks
..

mem: Add invalid context id check on LLSC checks

If the request's address is in the LLSC list, its context Id was being
fetched unconditionally, which could cause the assert at
Request::contextId() to fail.

Change-Id: Iae9791f81c8fe9a7fcd842cd8ab7db18f34f2808
Signed-off-by: Tiago Muck 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18792
Reviewed-by: Nikos Nikoleris 
Maintainer: Nikos Nikoleris 
Tested-by: kokoro 
---
M src/mem/abstract_mem.cc
M src/mem/abstract_mem.hh
2 files changed, 8 insertions(+), 3 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/abstract_mem.cc b/src/mem/abstract_mem.cc
index a998530..6870ba3 100644
--- a/src/mem/abstract_mem.cc
+++ b/src/mem/abstract_mem.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012,2017-2018 ARM Limited
+ * Copyright (c) 2010-2012,2017-2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -284,7 +284,10 @@
 DPRINTF(LLSC, "Erasing lock record: context %d addr %#x\n",
 i->contextId, paddr);
 ContextID owner_cid = i->contextId;
-ContextID requester_cid = pkt->req->contextId();
+assert(owner_cid != InvalidContextID);
+ContextID requester_cid = req->hasContextId() ?
+   req->contextId() :
+   InvalidContextID;
 if (owner_cid != requester_cid) {
 ThreadContext* ctx =  
system()->getThreadContext(owner_cid);

 TheISA::globalClearExclusive(ctx);
diff --git a/src/mem/abstract_mem.hh b/src/mem/abstract_mem.hh
index 18d8ee9..8b944b9 100644
--- a/src/mem/abstract_mem.hh
+++ b/src/mem/abstract_mem.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012, 2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -83,6 +83,8 @@
 // check for matching execution context
 bool matchesContext(const RequestPtr ) const
 {
+assert(contextId != InvalidContextID);
+assert(req->hasContextId());
 return (contextId == req->contextId());
 }


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Gerrit-PatchSet: 4
Gerrit-Owner: Tiago Mück 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Nikos Nikoleris 
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[gem5-dev] Change in gem5/gem5[master]: mem: Add invalid context id check on LLSC checks

2019-05-20 Thread Tiago Mück (Gerrit)

Hello kokoro, Daniel Carvalho, Xianwei Zhang, Nikos Nikoleris,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/18792

to look at the new patch set (#3).

Change subject: mem: Add invalid context id check on LLSC checks
..

mem: Add invalid context id check on LLSC checks

If the request's address is in the LLSC list, its context Id was being
fetched unconditionally, which could cause the assert at
Request::contextId() to fail.

Change-Id: Iae9791f81c8fe9a7fcd842cd8ab7db18f34f2808
Signed-off-by: Tiago Muck 
---
M src/mem/abstract_mem.cc
M src/mem/abstract_mem.hh
2 files changed, 8 insertions(+), 3 deletions(-)


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Gerrit-Change-Number: 18792
Gerrit-PatchSet: 3
Gerrit-Owner: Tiago Mück 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: Tiago Mück 
Gerrit-Reviewer: Xianwei Zhang 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[master]: base: AddrRange does not merge single interleaved ranges

2019-05-17 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded a new patch set (#2). (  
https://gem5-review.googlesource.com/c/public/gem5/+/18788 )


Change subject: base: AddrRange does not merge single interleaved ranges
..

base: AddrRange does not merge single interleaved ranges

AddrRange does not attempt to merge interleaved address ranges if it
has only one of the ranges.

Change-Id: If71c9cf1444ee11916611afb51eab3a4f1d93985
Signed-off-by: Tiago Muck 
---
M src/base/addr_range.hh
1 file changed, 6 insertions(+), 1 deletion(-)


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[gem5-dev] Change in gem5/gem5[master]: mem: Add invalid context id check on LLSC checks

2019-05-16 Thread Tiago Mück (Gerrit)

Hello Xianwei Zhang,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/18792

to look at the new patch set (#2).

Change subject: mem: Add invalid context id check on LLSC checks
..

mem: Add invalid context id check on LLSC checks

If the request's address is in the LLSC list, its context Id was being
fetched unconditionally, which could cause the assert at
Request::contextId() to fail.

Change-Id: Iae9791f81c8fe9a7fcd842cd8ab7db18f34f2808
Signed-off-by: Tiago Muck 
---
M src/mem/abstract_mem.cc
M src/mem/abstract_mem.hh
2 files changed, 8 insertions(+), 3 deletions(-)


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Gerrit-Change-Number: 18792
Gerrit-PatchSet: 2
Gerrit-Owner: Tiago Mück 
Gerrit-Reviewer: Tiago Mück 
Gerrit-Reviewer: Xianwei Zhang 
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[gem5-dev] Change in gem5/gem5[master]: misc: Added dot_writer for Ruby's network topology

2019-05-16 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded a new patch set (#3) to the change originally  
created by Giacomo Travaglini. (  
https://gem5-review.googlesource.com/c/public/gem5/+/17548 )


Change subject: misc: Added dot_writer for Ruby's network topology
..

misc: Added dot_writer for Ruby's network topology

Change-Id: Ic71ca7bc2eb4174d70afa368bc9cc987f3df89e9
Signed-off-by: Tiago Muck 
---
M src/python/SConscript
M src/python/m5/simulate.py
A src/python/m5/util/dot_writer_ruby.py
3 files changed, 140 insertions(+), 1 deletion(-)


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Gerrit-Change-Number: 17548
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: Pouya Fotouhi 
Gerrit-Reviewer: Tiago Mück 
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[gem5-dev] Change in gem5/gem5[master]: memtest: Fix rescheduling of progress check events

2019-05-15 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18793



Change subject: memtest: Fix rescheduling of progress check events
..

memtest: Fix rescheduling of progress check events

noRequestEvent needs to be rescheduled on recvRetry, otherwise the timeout
may be triggered even though packets are being eventually sent.
noResponseEvent scheduling is also fixed. This timeout should not be
active when we are not expecting a response.

Change-Id: If9edb75b5b803caf9f99bf41ea3948b15a3f3d71
Signed-off-by: Tiago Muck 
---
M src/cpu/testers/memtest/memtest.cc
1 file changed, 12 insertions(+), 4 deletions(-)



diff --git a/src/cpu/testers/memtest/memtest.cc  
b/src/cpu/testers/memtest/memtest.cc

index 93a6ac6..742cf3b 100644
--- a/src/cpu/testers/memtest/memtest.cc
+++ b/src/cpu/testers/memtest/memtest.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015 ARM Limited
+ * Copyright (c) 2015, 2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -120,7 +120,6 @@
 // kick things into action
 schedule(tickEvent, curTick());
 schedule(noRequestEvent, clockEdge(progressCheck));
-schedule(noResponseEvent, clockEdge(progressCheck));
 }

 Port &
@@ -189,8 +188,12 @@
 // the packet will delete the data
 delete pkt;

-// finally shift the response timeout forward
-reschedule(noResponseEvent, clockEdge(progressCheck), true);
+// finally shift the response timeout forward if we are still
+// expecting responses; deschedule it otherwise
+if (outstandingAddrs.size() != 0)
+reschedule(noResponseEvent, clockEdge(progressCheck));
+else if (noResponseEvent.scheduled())
+deschedule(noResponseEvent);
 }

 void
@@ -303,6 +306,10 @@
 } else {
 DPRINTF(MemTest, "Waiting for retry\n");
 }
+
+// Schedule noResponseEvent now if we are expecting a response
+if (!noResponseEvent.scheduled() && (outstandingAddrs.size() != 0))
+schedule(noResponseEvent, clockEdge(progressCheck));
 }

 void
@@ -327,6 +334,7 @@
 retryPkt = nullptr;
 // kick things into action again
 schedule(tickEvent, clockEdge(interval));
+reschedule(noRequestEvent, clockEdge(progressCheck), true);
 }
 }


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[gem5-dev] Change in gem5/gem5[master]: mem: Add invalid context id check on LLSC checks

2019-05-15 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18792



Change subject: mem: Add invalid context id check on LLSC checks
..

mem: Add invalid context id check on LLSC checks

If the request's address is in the LLSC list, its context Id was being
fetched unconditionally, which could cause the assert at
Request::contextId() to fail.

Change-Id: Iae9791f81c8fe9a7fcd842cd8ab7db18f34f2808
Signed-off-by: Tiago Muck 
---
M src/mem/abstract_mem.cc
1 file changed, 6 insertions(+), 2 deletions(-)



diff --git a/src/mem/abstract_mem.cc b/src/mem/abstract_mem.cc
index a998530..ce40dca 100644
--- a/src/mem/abstract_mem.cc
+++ b/src/mem/abstract_mem.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012,2017-2018 ARM Limited
+ * Copyright (c) 2010-2012,2017-2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -258,6 +258,7 @@

 if (isLLSC) {
 while (i != lockedAddrList.end()) {
+assert(req->hasContextId());
 if (i->addr == paddr && i->matchesContext(req)) {
 // it's a store conditional, and as far as the memory  
system can

 // tell, the requesting context's lock is still valid.
@@ -284,7 +285,10 @@
 DPRINTF(LLSC, "Erasing lock record: context %d addr %#x\n",
 i->contextId, paddr);
 ContextID owner_cid = i->contextId;
-ContextID requester_cid = pkt->req->contextId();
+assert(owner_cid != InvalidContextID);
+ContextID requester_cid = pkt->req->hasContextId()
+   ? pkt->req->contextId()
+   : InvalidContextID;
 if (owner_cid != requester_cid) {
 ThreadContext* ctx =  
system()->getThreadContext(owner_cid);

 TheISA::globalClearExclusive(ctx);

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[gem5-dev] Change in gem5/gem5[master]: mem: Snoop filter support for large systems

2019-05-15 Thread Tiago Mück (Gerrit)
quot;,
+ sf_item.requested, sf_item.holder);

 // The destination should have had a request in
-panic_if(!(sf_item.requested & req_mask), "SF value %x.%x missing "\
+panic_if((sf_item.requested & req_mask).none(), "SF value %x.%x  
missing "\

  "the original request\n",  sf_item.requested, sf_item.holder);

 // If the snoop response has no sharers the line is passed in
@@ -287,7 +291,7 @@
 // @todo Deal with invalidating responses
 sf_item.holder |=  req_mask;
 sf_item.requested &= ~req_mask;
-assert(sf_item.requested | sf_item.holder);
+assert((sf_item.requested | sf_item.holder).any());
 DPRINTF(SnoopFilter, "%s:   new SF value %x.%x\n",
 __func__, sf_item.requested, sf_item.holder);
 }
@@ -359,8 +363,9 @@
 __func__,  sf_item.requested, sf_item.holder);

 // Make sure we have seen the actual request, too
-panic_if(!(sf_item.requested & slave_mask), "SF value %x.%x missing "\
- "request bit\n", sf_item.requested, sf_item.holder);
+panic_if((sf_item.requested & slave_mask).none(),
+ "SF value %x.%x missing request bit\n",
+ sf_item.requested, sf_item.holder);

 sf_item.requested &= ~slave_mask;
 // Update the residency of the cache line.
@@ -376,7 +381,7 @@
 // Any other response implies that a cache above will have the
 // block.
 sf_item.holder |= slave_mask;
-assert(sf_item.holder | sf_item.requested);
+assert((sf_item.holder | sf_item.requested).any());
 }
 DPRINTF(SnoopFilter, "%s:   new SF value %x.%x\n",
 __func__, sf_item.requested, sf_item.holder);
diff --git a/src/mem/snoop_filter.hh b/src/mem/snoop_filter.hh
index 85cc75e..9c06615 100644
--- a/src/mem/snoop_filter.hh
+++ b/src/mem/snoop_filter.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2016 ARM Limited
+ * Copyright (c) 2013-2016,2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -45,6 +45,7 @@
 #ifndef __MEM_SNOOP_FILTER_HH__
 #define __MEM_SNOOP_FILTER_HH__

+#include 
 #include 
 #include 

@@ -86,6 +87,10 @@
  */
 class SnoopFilter : public SimObject {
   public:
+
+// Change for systems with more than 256 ports tracked by this object
+static const int SNOOP_MASK_SIZE = 256;
+
 typedef std::vector SnoopList;

 SnoopFilter (const SnoopFilterParams *p) :
@@ -114,9 +119,9 @@
 }

 // make sure we can deal with this many ports
-fatal_if(id > 8 * sizeof(SnoopMask),
+fatal_if(id > SNOOP_MASK_SIZE,
  "Snoop filter only supports %d snooping ports, got %d\n",
- 8 * sizeof(SnoopMask), id);
+ SNOOP_MASK_SIZE, id);
 }

 /**
@@ -198,13 +203,9 @@

 /**
  * The underlying type for the bitmask we use for tracking. This
- * limits the number of snooping ports supported per crossbar. For
- * the moment it is an uint64_t to offer maximum
- * scalability. However, it is possible to use e.g. a uint16_t or
- * uint32_to slim down the footprint of the hash map (and
- * ultimately improve the simulation performance).
+ * limits the number of snooping ports supported per crossbar.
  */
-typedef uint64_t SnoopMask;
+typedef std::bitset SnoopMask;

 /**
 * Per cache line item tracking a bitmask of SlavePorts who have an
@@ -314,7 +315,7 @@
 {
 SnoopList res;
 for (const auto& p : slavePorts)
-if (port_mask & portToMask(*p))
+if ((port_mask & portToMask(*p)).any())
     res.push_back(p);
 return res;
 }

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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Increase maximum num. of controllers in Ruby

2019-05-15 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18790



Change subject: mem-ruby: Increase maximum num. of controllers in Ruby
..

mem-ruby: Increase maximum num. of controllers in Ruby

Increasing to 256 should be enough for any large-scale system simulatable
by gem5

Change-Id: Iad2d33d5b0cc64a1b7d9d187f12cabbcba113446
Signed-off-by: Tiago Muck 
---
M src/mem/ruby/common/Set.hh
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/mem/ruby/common/Set.hh b/src/mem/ruby/common/Set.hh
index cb01c96..39dd319 100644
--- a/src/mem/ruby/common/Set.hh
+++ b/src/mem/ruby/common/Set.hh
@@ -39,8 +39,8 @@
 #include "base/logging.hh"
 #include "mem/ruby/common/TypeDefines.hh"

-// Change for systems with more than 64 controllers of a particular type.
-const int NUMBER_BITS_PER_SET = 64;
+// Change for systems with more than 256 controllers of a particular type.
+const int NUMBER_BITS_PER_SET = 256;

 class Set
 {

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[gem5-dev] Change in gem5/gem5[master]: mem: Parameterize coherent xbar sanity checks

2019-05-15 Thread Tiago Mück (Gerrit)
of coherency? **/
 const bool pointOfCoherency;
+
+/** Is this crossbar the point of unification? **/
 const bool pointOfUnification;

 /**

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[gem5-dev] Change in gem5/gem5[master]: mem: xbars do not merge single interleaved ranges

2019-05-15 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18788



Change subject: mem: xbars do not merge single interleaved ranges
..

mem: xbars do not merge single interleaved ranges

BaseXBar does not attempt to merge interleaved address ranges if it
has only one of the ranges.

Change-Id: If71c9cf1444ee11916611afb51eab3a4f1d93985
Signed-off-by: Tiago Muck 
---
M src/mem/xbar.cc
1 file changed, 5 insertions(+), 4 deletions(-)



diff --git a/src/mem/xbar.cc b/src/mem/xbar.cc
index de32c0b..a85f7a1 100644
--- a/src/mem/xbar.cc
+++ b/src/mem/xbar.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2015, 2018 ARM Limited
+ * Copyright (c) 2011-2015, 2018, 2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -438,7 +438,7 @@
 // if we already got interleaved ranges that are not
 // part of the same range, then first do a merge
 // before we add the new one
-if (!intlv_ranges.empty() &&
+if ((intlv_ranges.size() > 1) &&
 !intlv_ranges.back().mergesWith(r.first)) {
 DPRINTF(AddrRanges, "-- Merging range from %d  
ranges\n",

 intlv_ranges.size());
@@ -466,7 +466,7 @@

 // if there is still interleaved ranges waiting to be merged,
 // go ahead and do it
-if (!intlv_ranges.empty()) {
+if (intlv_ranges.size() > 1) {
 DPRINTF(AddrRanges, "-- Merging range from %d ranges\n",
 intlv_ranges.size());
 AddrRange merged_range(intlv_ranges);
@@ -475,7 +475,8 @@
 DPRINTF(AddrRanges, "-- Adding merged range %s\n",
 merged_range.to_string());
 }
-}
+} else if (intlv_ranges.size() == 1)
+xbarRanges.push_back(intlv_ranges.front());

 // also check that no range partially intersects with the
 // default range, this has to be done after all ranges are set

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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Cache latencies for MOESI_CMP_dir

2019-05-14 Thread Tiago Mück (Gerrit)
end data and a token from TBE to  
L1 requestor") {

 assert(is_valid(cache_entry));
 peek(L1requestNetwork_in, RequestMsg) {
-  enqueue(responseNetwork_out, ResponseMsg, response_latency) {
+  enqueue(responseNetwork_out, ResponseMsg, cacheResponseLatency()) {
 assert(is_valid(tbe));
 out_msg.addr := address;
 out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
@@ -961,7 +971,7 @@
   action(dd_sendDataToFwdGETX, "dd", desc="send data") {
 assert(is_valid(cache_entry));
 peek(requestNetwork_in, RequestMsg) {
-  enqueue(responseNetwork_out, ResponseMsg, response_latency) {
+  enqueue(responseNetwork_out, ResponseMsg, cacheResponseLatency()) {
 out_msg.addr := address;
 out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 out_msg.Sender := machineID;
@@ -981,7 +991,7 @@
   action(dd_sendDataToFwdGETS, "\dd", desc="send data") {
 assert(is_valid(cache_entry));
 peek(requestNetwork_in, RequestMsg) {
-  enqueue(responseNetwork_out, ResponseMsg, response_latency) {
+  enqueue(responseNetwork_out, ResponseMsg, cacheResponseLatency()) {
 out_msg.addr := address;
 out_msg.Type := CoherenceResponseType:DATA;
 out_msg.Sender := machineID;
@@ -1001,7 +1011,7 @@
   action(dd_sendExclusiveDataToFwdGETS, "\d\d", desc="send data") {
 assert(is_valid(cache_entry));
 peek(requestNetwork_in, RequestMsg) {
-  enqueue(responseNetwork_out, ResponseMsg, response_latency) {
+  enqueue(responseNetwork_out, ResponseMsg, cacheResponseLatency()) {
 out_msg.addr := address;
 out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 out_msg.Sender := machineID;

--
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Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: John Alsop 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: Tiago Mück 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Xianwei Zhang 
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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: MOESI_CMP_dir cleanup

2019-05-14 Thread Tiago Mück (Gerrit)
_TRANSITION_COMMENT(in_msg.Sender);
-}
-responseNetwork_in.recycle(clockEdge(),  
cyclesToTicks(recycle_latency));

-  }
-
   action(st_stallAndWaitL1RequestQueue, "st", desc="Stall and wait on the  
address") {

 stall_and_wait(L1requestNetwork_in, address);
   }
@@ -1617,19 +1599,19 @@
   // TRANSITIONS
   //*

-  transition({II, IFGX, IFGS, ISFGS, IFGXX, IFLXO, OFGX, ILOW, ILOXW,  
ILOSW, ILOSXW, SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO,  
IFLOX, IFLOXX, IFLOSX, OLSXS, IGS, IGM, IGMLS, IGMO, IGMIO, OGMIO, IGMIOF,  
OGMIOF, MM, SS, OO, OI, MI, MII, OLSI, ILSI, SLSS, OLSS, OLSF, IGMIOFS,  
ILOSD, ILOSXD, ILOD, ILXD, ILOXD}, {L1_PUTO, L1_PUTS, L1_PUTS_only,  
L1_PUTX}) {
+  transition({II, IFGX, IFGS, ISFGS, IFGXX, IFLXO, ILOW, ILOXW, ILOSW,  
ILOSXW, SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO, IFLOX,  
IFLOXX, IFLOSX, OLSXS, IGS, IGM, IGMLS, IGMO, IGMIO, OGMIO, IGMIOF, OGMIOF,  
MM, SS, OO, OI, MI, MII, OLSI, ILSI, SLSS, OLSS, OLSF, IGMIOFS, ILOSD,  
ILOSXD, ILOD, ILXD, ILOXD}, {L1_PUTO, L1_PUTS, L1_PUTS_only, L1_PUTX}) {

 st_stallAndWaitL1RequestQueue;
   }

-  transition({II, IFGX, IFGS, ISFGS, IFGXX, IFLXO, OFGX, ILOW, ILOXW,  
ILOSW, ILOSXW, SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO,  
IFLOX, IFLOXX, IFLOSX, OLSXS, IGS, IGM, IGMLS, IGMO, IGMIO, OGMIO, IGMIOF,  
OGMIOF, MM, SS, OO, OI, MI, MII, OLSI, ILSI, SLSS, OLSS, OLSF, IGMIOFS,  
ILOSD, ILOSXD, ILOD, ILXD, ILOXD}, {L1_GETX, L1_GETS}) {
+  transition({II, IFGX, IFGS, ISFGS, IFGXX, IFLXO, ILOW, ILOXW, ILOSW,  
ILOSXW, SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO, IFLOX,  
IFLOXX, IFLOSX, OLSXS, IGS, IGM, IGMLS, IGMO, IGMIO, OGMIO, IGMIOF, OGMIOF,  
MM, SS, OO, OI, MI, MII, OLSI, ILSI, SLSS, OLSS, OLSF, IGMIOFS, ILOSD,  
ILOSXD, ILOD, ILXD, ILOXD}, {L1_GETX, L1_GETS}) {

 st_stallAndWaitL1RequestQueue;
   }

-  transition({IFGX, IFGS, ISFGS, IFGXX, IFLXO, OFGX, ILOW, ILOXW, ILOSW,  
ILOSXW, SLSW, OLSW, ILSW, IW, ILXW, OW, SW, OXW, OLSXW, IFLS, IFLO, IFLOX,  
IFLOXX, IFLOSX,OLSXS,  IGS, IGM, IGMLS, IGMO, MM, SS, OO, OI, MI, MII,  
OLSI, ILSI, SLSS, OLSS, OLSF, IGMIOFS, ILOSD, ILOSXD, ILOD, ILXD, ILOXD},  
L2_Replacement) {
+  transition({IFGX, IFGS, ISFGS, IFGXX, IFLXO, ILOW, ILOXW, ILOSW, ILOSXW,  
SLSW, OLSW, ILSW, IW, ILXW, OW, SW, OXW, OLSXW, IFLS, IFLO, IFLOX, IFLOXX,  
IFLOSX,OLSXS,  IGS, IGM, IGMLS, IGMO, MM, SS, OO, OI, MI, MII, OLSI, ILSI,  
SLSS, OLSS, OLSF, IGMIOFS, ILOSD, ILOSXD, ILOD, ILXD, ILOXD},  
L2_Replacement) {

 zz_recycleL1RequestQueue;
   }

-  transition({IFGX, IFGS, ISFGS, IFGXX, IFLXO, OFGX, ILOW, ILOXW, ILOSW,  
ILOSXW, SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO, IFLOX,  
IFLOXX, IFLOSX,OLSXS, IGS, IGM, MM, SS, OO, SLSS, OLSS, OLSF, IGMIOFS,  
ILOSD, ILOSXD, ILOD, ILXD, ILOXD}, {Fwd_GETX, Fwd_GETS, Fwd_DMA}) {
+  transition({IFGX, IFGS, ISFGS, IFGXX, IFLXO, ILOW, ILOXW, ILOSW, ILOSXW,  
SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO, IFLOX, IFLOXX,  
IFLOSX,OLSXS, IGS, IGM, MM, SS, OO, SLSS, OLSS, OLSF, IGMIOFS, ILOSD,  
ILOSXD, ILOD, ILXD, ILOXD}, {Fwd_GETX, Fwd_GETS, Fwd_DMA}) {

 zz_recycleGlobalRequestQueue;
   }

@@ -1637,7 +1619,7 @@
 zz_recycleGlobalRequestQueue;
   }

-  transition({IFGX, IFGS, ISFGS, IFGXX, IFLXO, OFGX, ILOW, ILOXW, ILOSW,  
ILOSXW, SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO, IFLOX,  
IFLOXX, IFLOSX,OLSXS, MM, SS, OO, SLSS, OLSS, OLSF, IGMIOFS, ILOSD, ILOSXD,  
ILOD, ILXD, ILOXD}, {Inv}) {
+  transition({IFGX, IFGS, ISFGS, IFGXX, IFLXO, ILOW, ILOXW, ILOSW, ILOSXW,  
SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO, IFLOX, IFLOXX,  
IFLOSX,OLSXS, MM, SS, OO, SLSS, OLSS, OLSF, IGMIOFS, ILOSD, ILOSXD, ILOD,  
ILXD, ILOXD}, {Inv}) {

 zz_recycleGlobalRequestQueue;
   }

diff --git a/src/mem/protocol/MOESI_CMP_directory-dir.sm  
b/src/mem/protocol/MOESI_CMP_directory-dir.sm

index f6b880d..f12d166 100644
--- a/src/mem/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm
@@ -69,7 +69,6 @@
 OO, AccessPermission:Busy, desc="Blocked, was in owned";
 MO, AccessPermission:Busy, desc="Blocked, going to owner or maybe  
modified";

 MM, AccessPermission:Busy, desc="Blocked, going to modified";
-MM_DMA, AccessPermission:Busy, desc="Blocked, going to I";

 MI, AccessPermission:Busy, desc="Blocked on a writeback";
 MIS, AccessPermission:Busy, desc="Blocked on a writeback, but don't  
remove from sharers when received";


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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Prevent response stalls on MOESI_CMP_directory

2019-05-14 Thread Tiago Mück (Gerrit)
106,22 +118,6 @@
   out_port(respToDirectory_out, ResponseMsg, respToDir, desc="...");
   out_port(triggerQueue_out, TriggerMsg, triggerQueue, desc="...");

-  in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
-if (dmaRequestQueue_in.isReady(clockEdge())) {
-  peek(dmaRequestQueue_in, SequencerMsg) {
-if (in_msg.Type == SequencerRequestType:LD ) {
-  trigger(Event:ReadRequest, in_msg.LineAddress,
-  TBEs[in_msg.LineAddress]);
-} else if (in_msg.Type == SequencerRequestType:ST) {
-  trigger(Event:WriteRequest, in_msg.LineAddress,
-  TBEs[in_msg.LineAddress]);
-} else {
-  error("Invalid request type");
-}
-  }
-}
-  }
-
   in_port(dmaResponseQueue_in, ResponseMsg, responseFromDir, desc="...") {
 if (dmaResponseQueue_in.isReady(clockEdge())) {
   peek( dmaResponseQueue_in, ResponseMsg) {
@@ -155,6 +151,22 @@
 }
   }

+  in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
+if (dmaRequestQueue_in.isReady(clockEdge())) {
+  peek(dmaRequestQueue_in, SequencerMsg) {
+if (in_msg.Type == SequencerRequestType:LD ) {
+  trigger(Event:ReadRequest, in_msg.LineAddress,
+  TBEs[in_msg.LineAddress]);
+} else if (in_msg.Type == SequencerRequestType:ST) {
+  trigger(Event:WriteRequest, in_msg.LineAddress,
+  TBEs[in_msg.LineAddress]);
+} else {
+  error("Invalid request type");
+}
+  }
+}
+  }
+
   action(s_sendReadRequest, "s", desc="Send a DMA read request to memory")  
{

 peek(dmaRequestQueue_in, SequencerMsg) {
   enqueue(reqToDirectory_out, RequestMsg, request_latency) {
diff --git a/src/mem/protocol/MOESI_CMP_directory-msg.sm  
b/src/mem/protocol/MOESI_CMP_directory-msg.sm

index 5f6f826..7dc5822 100644
--- a/src/mem/protocol/MOESI_CMP_directory-msg.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-msg.sm
@@ -1,5 +1,16 @@
-
 /*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
  * All rights reserved.
  *
@@ -40,11 +51,10 @@
   PUTO,  desc="Put Owned";
   PUTO_SHARERS,  desc="Put Owned, but sharers exist so don't remove  
from sharers list";

   PUTS,  desc="Put Shared";
-  WB_ACK,desc="Writeback ack";
-  WB_ACK_DATA,desc="Writeback ack";
-  WB_NACK,   desc="Writeback neg. ack";
   INV,   desc="Invalidation";
-
+  WRITEBACK_CLEAN_DATA,   desc="Clean writeback (contains data)";
+  WRITEBACK_CLEAN_ACK,desc="Clean writeback (contains no data)";
+  WRITEBACK_DIRTY_DATA,   desc="Dirty writeback (contains data)";
   DMA_READ,  desc="DMA Read";
   DMA_WRITE, desc="DMA Write";
 }
@@ -56,9 +66,9 @@
   DATA_EXCLUSIVE,desc="Data, no processor has a copy";
   UNBLOCK,   desc="Unblock";
   UNBLOCK_EXCLUSIVE, desc="Unblock, we're in E/M";
-  WRITEBACK_CLEAN_DATA,   desc="Clean writeback (contains data)";
-  WRITEBACK_CLEAN_ACK,   desc="Clean writeback (contains no data)";
-  WRITEBACK_DIRTY_DATA,   desc="Dirty writeback (contains data)";
+  WB_ACK,desc="Writeback ack";
+  WB_ACK_DATA,   desc="Writeback ack";
+  WB_NACK,   desc="Writeback neg. ack";
   DMA_ACK,   desc="Ack that a DMA write completed";
 }

@@ -100,7 +110,9 @@
   bool functionalRead(Packet *pkt) {
 // Read only those messages that contain the data
 if (Type == CoherenceRequestType:DMA_READ ||
-Type == CoherenceRequestType:DMA_WRITE) {
+Type == CoherenceRequestType:DMA_WRITE ||
+Type == CoherenceRequestType:WRITEBACK_CLEAN_DATA ||
+Type == CoherenceRequestType:WRITEBACK_DIRTY_DATA) {
 return testAndRead(addr, DataBlk, pkt);
     }
 return false;
@@ -127,9 +139,7 @@
   bool functionalRead(Packet *pkt) {
 // Read only those messages that contain the data
 if (Type == CoherenceResponseType:DATA ||
-Type == CoherenceResponseType:DATA_EXCLUSIVE ||
-Type == CoherenceResponseType:WRITEBACK_CLEAN_DATA ||
-Type == CoherenceRespons

[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Change MOESI_CMP_Dir L2 addressing

2019-05-14 Thread Tiago Mück (Gerrit)
_bits, intToID(0)));
+  out_msg.Destination.add(mapAddressToMachine(address,
+   
MachineType:L2Cache));

   out_msg.DataBlk := cache_entry.DataBlk;
   out_msg.Dirty := cache_entry.Dirty;
   out_msg.Acks := in_msg.Acks;
@@ -614,8 +613,8 @@
   out_msg.Type := CoherenceResponseType:ACK;
   out_msg.Sender := machineID;
   out_msg.SenderMachine := MachineType:L1Cache;
-  out_msg.Destination.add(mapAddressToRange(address,  
MachineType:L2Cache,

-  l2_select_low_bit, l2_select_num_bits, intToID(0)));
+  out_msg.Destination.add(mapAddressToMachine(address,
+   
MachineType:L2Cache));

   out_msg.Acks := 0 - 1; // -1
   out_msg.MessageSize := MessageSizeType:Response_Control;
 }
@@ -629,8 +628,8 @@
   out_msg.Type := CoherenceResponseType:UNBLOCK;
   out_msg.Sender := machineID;
   out_msg.SenderMachine := MachineType:L1Cache;
-  out_msg.Destination.add(mapAddressToRange(address,  
MachineType:L2Cache,

-  l2_select_low_bit, l2_select_num_bits, intToID(0)));
+  out_msg.Destination.add(mapAddressToMachine(address,
+  MachineType:L2Cache));
   out_msg.MessageSize := MessageSizeType:Unblock_Control;
 }
   }
@@ -641,8 +640,8 @@
   out_msg.Type := CoherenceResponseType:UNBLOCK_EXCLUSIVE;
   out_msg.Sender := machineID;
   out_msg.SenderMachine := MachineType:L1Cache;
-  out_msg.Destination.add(mapAddressToRange(address,  
MachineType:L2Cache,

-  l2_select_low_bit, l2_select_num_bits, intToID(0)));
+  out_msg.Destination.add(mapAddressToMachine(address,
+  MachineType:L2Cache));
   out_msg.MessageSize := MessageSizeType:Unblock_Control;
 }
   }
@@ -752,8 +751,8 @@
 out_msg.Type := CoherenceResponseType:DMA_ACK;
 out_msg.Sender := machineID;
 out_msg.SenderMachine := MachineType:L1Cache;
-out_msg.Destination.add(mapAddressToRange(address,  
MachineType:L2Cache,

-  l2_select_low_bit, l2_select_num_bits, intToID(0)));
+out_msg.Destination.add(mapAddressToMachine(address,
+MachineType:L2Cache));
 out_msg.Dirty := false;
 out_msg.Acks := 1;
 out_msg.MessageSize := MessageSizeType:Response_Control;
@@ -785,8 +784,8 @@
   out_msg.Type := CoherenceResponseType:DATA;
   out_msg.Sender := machineID;
   out_msg.SenderMachine := MachineType:L1Cache;
-  out_msg.Destination.add(mapAddressToRange(address,  
MachineType:L2Cache,

-  l2_select_low_bit, l2_select_num_bits, intToID(0)));
+  out_msg.Destination.add(mapAddressToMachine(address,
+   
MachineType:L2Cache));

   out_msg.DataBlk := tbe.DataBlk;
   // out_msg.Dirty := tbe.Dirty;
   out_msg.Dirty := false;
@@ -819,8 +818,8 @@
   out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
   out_msg.Sender := machineID;
   out_msg.SenderMachine := MachineType:L1Cache;
-  out_msg.Destination.add(mapAddressToRange(address,  
MachineType:L2Cache,

-  l2_select_low_bit, l2_select_num_bits, intToID(0)));
+  out_msg.Destination.add(mapAddressToMachine(address,
+   
MachineType:L2Cache));

   out_msg.DataBlk := tbe.DataBlk;
   out_msg.Dirty := tbe.Dirty;
   out_msg.Acks := in_msg.Acks;
@@ -837,8 +836,8 @@
   out_msg.addr := address;
   out_msg.Requestor := machineID;
   out_msg.RequestorMachine := MachineType:L1Cache;
-  out_msg.Destination.add(mapAddressToRange(address,  
MachineType:L2Cache,

-  l2_select_low_bit, l2_select_num_bits, intToID(0)));
+  out_msg.Destination.add(mapAddressToMachine(address,
+  MachineType:L2Cache));
   if (tbe.Dirty) {
 out_msg.Type := CoherenceRequestType:WRITEBACK_DIRTY_DATA;
   } else {

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Gerrit-Change-Id: Ie67999bb977566939432a5045f65dbd2da81816a
Gerrit-Change-Number: 18410
Gerrit-PatchSet: 3
Gerrit-Owner: Tiago Mück 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Do not change blocked msg enqueue info

2019-05-14 Thread Tiago Mück (Gerrit)
Tiago Mück has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18412 )


Change subject: mem-ruby: Do not change blocked msg enqueue info
..

mem-ruby: Do not change blocked msg enqueue info

Updating the message counter and enqueue times when adding blocked
messages back to the queue does not make a lot of sense since these
messages are not new arrivals.
More importantly, this may lead to starvation. See the scenario below:

1) Request A for a blocked line X arrives
2) A is handled; X is blocked so A is stalled
3) Request B for X arrives; Reponse for X arrives
4) Response is handled; X unblocked; A added back to the request queue
5) B is handled ahead of A (since A's arrival was updated);
   X may become blocked again

If new requests keep comming for X, A may will be stalled forever.

Change-Id: Icad79f3f716a870e91cb3455437b8b3c35f130ac
Signed-off-by: Tiago Muck 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18412
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Matthew Poremba 
Maintainer: Jason Lowe-Power 
---
M src/mem/ruby/network/MessageBuffer.cc
1 file changed, 5 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Matthew Poremba: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/ruby/network/MessageBuffer.cc  
b/src/mem/ruby/network/MessageBuffer.cc

index 560b69c..03d1bb0 100644
--- a/src/mem/ruby/network/MessageBuffer.cc
+++ b/src/mem/ruby/network/MessageBuffer.cc
@@ -297,16 +297,18 @@
 MessageBuffer::reanalyzeList(list , Tick schdTick)
 {
 while (!lt.empty()) {
-m_msg_counter++;
 MsgPtr m = lt.front();
-m->setLastEnqueueTime(schdTick);
-m->setMsgCounter(m_msg_counter);
+assert(m->getLastEnqueueTime() <= schdTick);

 m_prio_heap.push_back(m);
 push_heap(m_prio_heap.begin(), m_prio_heap.end(),
   greater());

 m_consumer->scheduleEventAbsolute(schdTick);
+
+DPRINTF(RubyQueue, "Requeue arrival_time: %lld, Message: %s\n",
+schdTick, *(m.get()));
+
 lt.pop_front();
 }
 }

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Gerrit-Branch: master
Gerrit-Change-Id: Icad79f3f716a870e91cb3455437b8b3c35f130ac
Gerrit-Change-Number: 18412
Gerrit-PatchSet: 3
Gerrit-Owner: Tiago Mück 
Gerrit-Reviewer: Bradford Beckmann 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: Tiago Mück 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Unique ranks for MOESI_CMP_dir in ports

2019-05-14 Thread Tiago Mück (Gerrit)
col/MOESI_CMP_directory-dir.sm
@@ -241,7 +241,7 @@

   // ** IN_PORTS **

-  in_port(unblockNetwork_in, ResponseMsg, responseToDir) {
+  in_port(unblockNetwork_in, ResponseMsg, responseToDir, rank=2) {
 if (unblockNetwork_in.isReady(clockEdge())) {
   peek(unblockNetwork_in, ResponseMsg) {
 if (in_msg.Type == CoherenceResponseType:UNBLOCK) {
@@ -268,7 +268,7 @@
 }
   }

-  in_port(requestQueue_in, RequestMsg, requestToDir) {
+  in_port(requestQueue_in, RequestMsg, requestToDir, rank=1) {
 if (requestQueue_in.isReady(clockEdge())) {
   peek(requestQueue_in, RequestMsg) {
 if (in_msg.Type == CoherenceRequestType:GETS) {
@@ -301,7 +301,7 @@
   }

   // off-chip memory request/response is done
-  in_port(memQueue_in, MemoryMsg, responseFromMemory) {
+  in_port(memQueue_in, MemoryMsg, responseFromMemory, rank=0) {
 if (memQueue_in.isReady(clockEdge())) {
   peek(memQueue_in, MemoryMsg) {
 if (in_msg.Type == MemoryRequestType:MEMORY_READ) {
diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm  
b/src/mem/protocol/MOESI_CMP_directory-dma.sm

index 16dc32a..a3a9f63 100644
--- a/src/mem/protocol/MOESI_CMP_directory-dma.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm
@@ -118,7 +118,7 @@
   out_port(respToDirectory_out, ResponseMsg, respToDir, desc="...");
   out_port(triggerQueue_out, TriggerMsg, triggerQueue, desc="...");

-  in_port(dmaResponseQueue_in, ResponseMsg, responseFromDir, desc="...") {
+  in_port(dmaResponseQueue_in, ResponseMsg, responseFromDir, rank=2) {
 if (dmaResponseQueue_in.isReady(clockEdge())) {
   peek( dmaResponseQueue_in, ResponseMsg) {
 if (in_msg.Type == CoherenceResponseType:DMA_ACK) {
@@ -139,7 +139,7 @@
   }

   // Trigger Queue
-  in_port(triggerQueue_in, TriggerMsg, triggerQueue) {
+  in_port(triggerQueue_in, TriggerMsg, triggerQueue, rank=1) {
 if (triggerQueue_in.isReady(clockEdge())) {
   peek(triggerQueue_in, TriggerMsg) {
 if (in_msg.Type == TriggerType:ALL_ACKS) {
@@ -151,7 +151,7 @@
 }
   }

-  in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
+  in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, rank=0) {
 if (dmaRequestQueue_in.isReady(clockEdge())) {
   peek(dmaRequestQueue_in, SequencerMsg) {
 if (in_msg.Type == SequencerRequestType:LD ) {

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Gerrit-Change-Id: Ie8ff660b7450df959292311040aebf802657efcf
Gerrit-Change-Number: 18411
Gerrit-PatchSet: 3
Gerrit-Owner: Tiago Mück 
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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Fix MOESI_CMP_dir debug msg

2019-05-14 Thread Tiago Mück (Gerrit)
Tiago Mück has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18409 )


Change subject: mem-ruby: Fix MOESI_CMP_dir debug msg
..

mem-ruby: Fix MOESI_CMP_dir debug msg

Change-Id: I3fd32bd2e81dbf9a8ea49a43727564b8a9d64767
Signed-off-by: Tiago Muck 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18409
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/mem/protocol/MOESI_CMP_directory-L2cache.sm
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm  
b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm

index 379e609..e006e86 100644
--- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
@@ -626,7 +626,7 @@
   trigger(Event:Data_Exclusive, in_msg.addr,
   getCacheEntry(in_msg.addr), TBEs[in_msg.addr]);
 } else if (in_msg.Type == CoherenceResponseType:UNBLOCK) {
-  DPRINTF(ProtocolTrace, "Received Unblock from L1 addr: %x\n",  
in_msg.addr);
+  DPRINTF(RubySlicc, "Received Unblock from L1 addr: %x\n",  
in_msg.addr);

   trigger(Event:Unblock, in_msg.addr,
   getCacheEntry(in_msg.addr), TBEs[in_msg.addr]);
 } else if (in_msg.Type == CoherenceResponseType:UNBLOCK_EXCLUSIVE)  
{


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Gerrit-Change-Id: I3fd32bd2e81dbf9a8ea49a43727564b8a9d64767
Gerrit-Change-Number: 18409
Gerrit-PatchSet: 3
Gerrit-Owner: Tiago Mück 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: Tiago Mück 
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Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Hit latencies defined by the controllers

2019-05-14 Thread Tiago Mück (Gerrit)
a_cache_hit_latency = p->dcache_hit_latency;
-m_inst_cache_hit_latency = p->icache_hit_latency;
 m_max_outstanding_requests = p->max_outstanding_requests;
 m_deadlock_threshold = p->deadlock_threshold;

@@ -70,8 +68,6 @@
 assert(m_deadlock_threshold > 0);
 assert(m_instCache_ptr != NULL);
 assert(m_dataCache_ptr != NULL);
-assert(m_data_cache_hit_latency > 0);
-assert(m_inst_cache_hit_latency > 0);

 m_runningGarnetStandalone = p->garnet_standalone;
 }
@@ -650,23 +646,12 @@
 printAddress(msg->getPhysicalAddress()),
 RubyRequestType_to_string(secondary_type));

-// The Sequencer currently assesses instruction and data cache hit  
latency

-// for the top-level caches at the beginning of a memory access.
-// TODO: Eventually, this latency should be moved to represent the  
actual

-// cache access latency portion of the memory access. This will require
-// changing cache controller protocol files to assess the latency on  
the

-// access response path.
-Cycles latency(0);  // Initialize to zero to catch misconfigured  
latency

-if (secondary_type == RubyRequestType_IFETCH)
-latency = m_inst_cache_hit_latency;
-else
-latency = m_data_cache_hit_latency;
-
-// Send the message to the cache controller
+Tick latency = cyclesToTicks(
+ 
m_controller->mandatoryQueueLatency(secondary_type));

 assert(latency > 0);

 assert(m_mandatory_q_ptr != NULL);
-m_mandatory_q_ptr->enqueue(msg, clockEdge(), cyclesToTicks(latency));
+m_mandatory_q_ptr->enqueue(msg, clockEdge(), latency);
 }

 template 
diff --git a/src/mem/ruby/system/Sequencer.py  
b/src/mem/ruby/system/Sequencer.py

index 2aede34..47f5146 100644
--- a/src/mem/ruby/system/Sequencer.py
+++ b/src/mem/ruby/system/Sequencer.py
@@ -63,12 +63,7 @@

icache = Param.RubyCache("")
dcache = Param.RubyCache("")
-   # Cache latencies currently assessed at the beginning of each access
-   # NOTE: Setting these values to a value greater than one will result in
-   # O3 CPU pipeline bubbles and negatively impact performance
-   # TODO: Latencies should be migrated into each top-level cache  
controller

-   icache_hit_latency = Param.Cycles(1, "Inst cache hit latency")
-   dcache_hit_latency = Param.Cycles(1, "Data cache hit latency")
+
max_outstanding_requests = Param.Int(16,
"max requests (incl. prefetches) outstanding")
deadlock_threshold = Param.Cycles(50,

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Gerrit-Change-Id: I72e57a7ea49501ef81dc7f591bef14134274647c
Gerrit-Change-Number: 18413
Gerrit-PatchSet: 3
Gerrit-Owner: Tiago Mück 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: John Alsop 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: Tiago Mück 
Gerrit-Reviewer: Xianwei Zhang 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Fix MOESI_CMP_directory blocked line handling

2019-05-09 Thread Tiago Mück (Gerrit)
ponse;
 n_popResponseQueue;
+wa_wakeUpDependents;
   }

   transition(OLS, L1_PUTS, OLSW) {
@@ -2581,16 +2619,19 @@
   transition(OLSXW, {Unblock}, OLSX) {
 gg_clearSharerFromL1Response;
 n_popResponseQueue;
+wa_wakeUpDependents;
   }

   transition(OW, {Unblock}, O) {
 gg_clearSharerFromL1Response;
 n_popResponseQueue;
+wa_wakeUpDependents;
   }

   transition(OXW, {Unblock}, M) {
 gg_clearSharerFromL1Response;
 n_popResponseQueue;
+wa_wakeUpDependents;
   }

   transition(ILX, L1_PUTX, ILXW ) {
@@ -2604,6 +2645,7 @@
 y_copyDirToCacheAndRemove;
 u_writeDataToCache;
 n_popResponseQueue;
+wa_wakeUpDependents;
   }

   // clean writeback
@@ -2613,11 +2655,13 @@
 y_copyDirToCacheAndRemove;
 u_writeDataToCache;
 n_popResponseQueue;
+wa_wakeUpDependents;
   }

   transition(ILXW, Unblock, ILX) {
 // writeback canceled because L1 invalidated
 n_popResponseQueue;
+wa_wakeUpDependents;
   }

   transition(ILSW, L1_WBCLEANDATA, SLS) {
@@ -2626,6 +2670,7 @@
 u_writeDataToCache;
 gg_clearSharerFromL1Response;
 n_popResponseQueue;
+wa_wakeUpDependents;
   }

   transition(IW, L1_WBCLEANDATA, S) {
@@ -2634,7 +2679,7 @@
 u_writeDataToCache;
 gg_clearSharerFromL1Response;
 n_popResponseQueue;
-
+wa_wakeUpDependents;
   }

   // Owner can have dirty data
@@ -2644,6 +2689,7 @@
 gg_clearOwnerFromL1Response;
 u_writeDataToCache;
 n_popResponseQueue;
+wa_wakeUpDependents;
   }

   transition(ILOXW, L1_WBDIRTYDATA, M) {
@@ -2652,6 +2698,7 @@
 gg_clearOwnerFromL1Response;
 u_writeDataToCache;
 n_popResponseQueue;
+wa_wakeUpDependents;
   }

   transition(ILOXW, L1_WBCLEANDATA, M) {
@@ -2660,6 +2707,7 @@
 gg_clearOwnerFromL1Response;
 u_writeDataToCache;
 n_popResponseQueue;
+wa_wakeUpDependents;
   }

   transition(ILOSW, {L1_WBCLEANDATA, L1_WBDIRTYDATA}, OLS) {
@@ -2668,6 +2716,7 @@
 gg_clearOwnerFromL1Response;
 u_writeDataToCache;
 n_popResponseQueue;
+wa_wakeUpDependents;
   }

   transition(ILOSXW, {L1_WBCLEANDATA, L1_WBDIRTYDATA}, OLSX) {
@@ -2676,17 +2725,20 @@
 gg_clearOwnerFromL1Response;
 u_writeDataToCache;
 n_popResponseQueue;
+wa_wakeUpDependents;
   }


   transition(SLSW, {Unblock}, SLS) {
 gg_clearSharerFromL1Response;
 n_popResponseQueue;
+wa_wakeUpDependents;
   }

   transition(OLSW, {Unblock}, OLS) {
 gg_clearSharerFromL1Response;
 n_popResponseQueue;
+wa_wakeUpDependents;
   }


@@ -2787,11 +2839,13 @@
 qq_sendDataFromTBEToMemory;
 s_deallocateTBE;
 m_popRequestQueue;
+wa_wakeUpDependents;
   }

   transition(MII, Writeback_Nack, I) {
 s_deallocateTBE;
 m_popRequestQueue;
+wa_wakeUpDependents;
   }

   transition(OI, Writeback_Nack) {
@@ -2803,17 +2857,20 @@
 qq_sendDataFromTBEToMemory;
 s_deallocateTBE;
 m_popRequestQueue;
+wa_wakeUpDependents;
   }

   transition(MII, Writeback_Ack, I) {
 f_sendUnblock;
 s_deallocateTBE;
 m_popRequestQueue;
+wa_wakeUpDependents;
   }

   transition(ILSI, Writeback_Ack, ILS) {
 f_sendUnblock;
 s_deallocateTBE;
 m_popRequestQueue;
+wa_wakeUpDependents;
   }
 }

--
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Gerrit-Change-Id: I28b8aeacc48919ccf38e69653cd9205a4153514b
Gerrit-Change-Number: 17568
Gerrit-PatchSet: 3
Gerrit-Owner: Tiago Mück 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Bradford Beckmann 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matthew Poremba 
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[gem5-dev] Change in gem5/gem5[master]: base: Add warn_if_once macro

2019-04-26 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18420



Change subject: base: Add warn_if_once macro
..

base: Add warn_if_once macro

Change-Id: Ie68f3b07a35ed2e6b0eee20b3b34050542fcdc6c
Signed-off-by: Tiago Muck 
---
M src/base/logging.hh
1 file changed, 7 insertions(+), 1 deletion(-)



diff --git a/src/base/logging.hh b/src/base/logging.hh
index 1c504d2..7040037 100644
--- a/src/base/logging.hh
+++ b/src/base/logging.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, 2017 ARM Limited
+ * Copyright (c) 2014, 2017, 2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -231,6 +231,12 @@
 warn(__VA_ARGS__); \
 } while (0)

+#define warn_if_once(cond, ...) \
+do { \
+if ((cond)) \
+warn_once(__VA_ARGS__); \
+} while (0)
+
 /**
  * The chatty assert macro will function like a normal assert, but will  
allow
  * the specification of additional, helpful material to aid debugging why  
the


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[gem5-dev] Change in gem5/gem5[master]: base: overloaded operator[] for const Stat::Vector

2019-04-26 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18419



Change subject: base: overloaded operator[] for const Stat::Vector
..

base: overloaded operator[] for const Stat::Vector

Overloaded operator allows fetching individual values from a
const Stat::Vector

Change-Id: I069ea86e9da279f262d5c96fb88bc400eca9146e
Signed-off-by: Tiago Muck 
---
M src/base/statistics.hh
1 file changed, 11 insertions(+), 0 deletions(-)



diff --git a/src/base/statistics.hh b/src/base/statistics.hh
index 8a5420f..085b061 100644
--- a/src/base/statistics.hh
+++ b/src/base/statistics.hh
@@ -1075,6 +1075,17 @@
 }

 /**
+ * Returns a total of a single entry in this vector.
+ * @return The total of a single vector entry.
+ */
+Result
+operator[](off_type i) const
+{
+assert (i >= 0 && i < size());
+return  data(i)->result();
+}
+
+/**
  * @return the number of elements in this vector.
  */
 size_type size() const { return _size; }

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[gem5-dev] Change in gem5/gem5[master]: cpu: Limit TrafficGen outstanding reqs

2019-04-26 Thread Tiago Mück (Gerrit)
"mem/mem_object.hh"
@@ -93,6 +94,10 @@
  */
 void recvReqRetry();

+void retryReq();
+
+bool recvTimingResp(PacketPtr pkt);
+
 /** Transition to the next generator */
 void transition();

@@ -118,6 +123,8 @@
 /** Time of the next packet. */
 Tick nextPacketTick;

+const int maxOutstandingReqs;
+

 /** Master port specialisation for the traffic generator */
 class TrafficGenPort : public MasterPort
@@ -132,7 +139,8 @@

 void recvReqRetry() { trafficGen.recvReqRetry(); }

-bool recvTimingResp(PacketPtr pkt);
+bool recvTimingResp(PacketPtr pkt)
+{ return trafficGen.recvTimingResp(pkt); }

 void recvTimingSnoopReq(PacketPtr pkt) { }

@@ -161,6 +169,24 @@
 /** Tick when the stalled packet was meant to be sent. */
 Tick retryPktTick;

+/** Set when we blocked waiting for outstanding reqs */
+bool blockedWaitingResp;
+
+/**
+ * Puts this packet in the waitingResp list and returns true if
+ * we are above the maximum number of oustanding requests.
+ */
+bool allocateWaitingRespSlot(PacketPtr pkt)
+{
+assert(waitingResp.find(pkt->req) == waitingResp.end());
+assert(pkt->needsResponse());
+
+waitingResp[pkt->req] = curTick();
+
+return (maxOutstandingReqs > 0) &&
+   (waitingResp.size() > maxOutstandingReqs);
+}
+
 /** Event for scheduling updates */
 EventFunctionWrapper updateEvent;

@@ -177,6 +203,9 @@
 /** Count the time incurred from back-pressure. */
 Stats::Scalar retryTicks;

+/** Reqs waiting for response **/
+std::unordered_map waitingResp;
+
   public:
 BaseTrafficGen(const BaseTrafficGenParams* p);


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[gem5-dev] Change in gem5/gem5[master]: cpu: Additional TrafficGen stats

2019-04-26 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18418



Change subject: cpu: Additional TrafficGen stats
..

cpu: Additional TrafficGen stats

Additional stats to keep track of read/write latencies and throughput.

Change-Id: I7684cd33cf68fffdef4ca9c3a6db360a0f531c18
Signed-off-by: Tiago Muck 
---
M src/cpu/testers/traffic_gen/base.cc
M src/cpu/testers/traffic_gen/base.hh
2 files changed, 85 insertions(+), 0 deletions(-)



diff --git a/src/cpu/testers/traffic_gen/base.cc  
b/src/cpu/testers/traffic_gen/base.cc

index 2988e74..e5fe579 100644
--- a/src/cpu/testers/traffic_gen/base.cc
+++ b/src/cpu/testers/traffic_gen/base.cc
@@ -354,6 +354,51 @@
 retryTicks
 .name(name() + ".retryTicks")
 .desc("Time spent waiting due to back-pressure (ticks)");
+
+bytesRead
+.name(name() + ".bytesRead")
+.desc("Number of bytes read");
+
+bytesWritten
+.name(name() + ".bytesWritten")
+.desc("Number of bytes written");
+
+totalReadLatency
+.name(name() + ".totalReadLatency")
+.desc("Total latency of read requests");
+
+totalWriteLatency
+.name(name() + ".totalWriteLatency")
+.desc("Total latency of write requests");
+
+totalReads
+.name(name() + ".totalReads")
+.desc("Total num of reads");
+
+totalWrites
+.name(name() + ".totalWrites")
+.desc("Total num of writes");
+
+avgReadLatency
+.name(name() + ".avgReadLatency")
+.desc("Avg latency of read requests");
+avgReadLatency = totalReadLatency / totalReads;
+
+avgWriteLatency
+.name(name() + ".avgWriteLatency")
+.desc("Avg latency of write requests");
+avgWriteLatency = totalWriteLatency / totalWrites;
+
+readBW
+.name(name() + ".readBW")
+.desc("Read bandwidth in bytes/s");
+readBW = bytesRead / simSeconds;
+
+writeBW
+.name(name() + ".writeBW")
+.desc("Write bandwidth in bytes/s");
+writeBW = bytesWritten / simSeconds;
+
 }

 std::shared_ptr
@@ -470,6 +515,16 @@

 assert(iter->second <= curTick());

+if (pkt->isWrite()) {
+++totalWrites;
+bytesWritten += pkt->req->getSize();
+totalWriteLatency += curTick() - iter->second;
+} else {
+++totalReads;
+bytesRead += pkt->req->getSize();
+totalReadLatency += curTick() - iter->second;
+}
+
 waitingResp.erase(iter);

 delete pkt;
diff --git a/src/cpu/testers/traffic_gen/base.hh  
b/src/cpu/testers/traffic_gen/base.hh

index 1327be0..9e9defa 100644
--- a/src/cpu/testers/traffic_gen/base.hh
+++ b/src/cpu/testers/traffic_gen/base.hh
@@ -206,6 +206,36 @@
 /** Reqs waiting for response **/
 std::unordered_map waitingResp;

+/** Count the number of bytes read. */
+Stats::Scalar bytesRead;
+
+/** Count the number of bytes written. */
+Stats::Scalar bytesWritten;
+
+/** Total num of ticks read reqs took to complete  */
+Stats::Scalar totalReadLatency;
+
+/** Total num of ticks write reqs took to complete  */
+Stats::Scalar totalWriteLatency;
+
+/** Count the number reads. */
+Stats::Scalar totalReads;
+
+/** Count the number writes. */
+Stats::Scalar totalWrites;
+
+/** Avg num of ticks each read req took to complete  */
+Stats::Formula avgReadLatency;
+
+/** Avg num of ticks each write reqs took to complete  */
+Stats::Formula avgWriteLatency;
+
+/** Read bandwidth in bytes/s  */
+Stats::Formula readBW;
+
+/** Write bandwidth in bytes/s  */
+Stats::Formula writeBW;
+
   public:
 BaseTrafficGen(const BaseTrafficGenParams* p);


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[gem5-dev] Change in gem5/gem5[master]: cpu: TrafficGen as BaseCPU

2019-04-26 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18416



Change subject: cpu: TrafficGen as BaseCPU
..

cpu: TrafficGen as BaseCPU

TrafficGen has additional attributes to behave like a BaseCPU. Python
scripts that expect sim. objects derived from BaseCPU can now be used with
TrafficGen without additional modifications.

Change-Id: Iee848b2ba0ac1851c487b1003da9bd96253d291a
Signed-off-by: Tiago Muck 
---
M src/cpu/testers/traffic_gen/BaseTrafficGen.py
1 file changed, 37 insertions(+), 1 deletion(-)



diff --git a/src/cpu/testers/traffic_gen/BaseTrafficGen.py  
b/src/cpu/testers/traffic_gen/BaseTrafficGen.py

index 94e3319..952d91d 100644
--- a/src/cpu/testers/traffic_gen/BaseTrafficGen.py
+++ b/src/cpu/testers/traffic_gen/BaseTrafficGen.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012, 2016, 2018 ARM Limited
+# Copyright (c) 2012, 2016, 2018, 2019 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -85,3 +85,39 @@
 # Sources for Stream/Substream IDs to apply to requests
 sids = VectorParam.Unsigned([], "StreamIDs to use")
 ssids = VectorParam.Unsigned([], "SubstreamIDs to use")
+
+# These additional parameters allow TrafficGen to be used with scripts
+# that expect a BaseCPU
+cpu_id = Param.Int(-1, "CPU identifier")
+socket_id = Param.Unsigned(0, "Physical Socket identifier")
+numThreads = Param.Unsigned(1, "number of HW thread contexts")
+
+@classmethod
+def memory_mode(cls):
+return 'timing'
+
+@classmethod
+def require_caches(cls):
+return False
+
+def createThreads(self):
+pass
+
+def createInterruptController(self):
+pass
+
+def connectCachedPorts(self, bus):
+if hasattr(self, '_cached_ports') and (len(self._cached_ports) >  
0):

+for p in self._cached_ports:
+exec('self.%s = bus.slave' % p)
+else:
+self.port = bus.slave
+
+def connectAllPorts(self, cached_bus, uncached_bus = None):
+self.connectCachedPorts(cached_bus)
+
+def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
+self.dcache = dc
+self.port = dc.cpu_side
+self._cached_ports = ['dcache.mem_side']
+self._uncached_ports = []

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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Hit latencies defined by the controllers

2019-04-26 Thread Tiago Mück (Gerrit)
 != NULL);
-assert(m_data_cache_hit_latency > 0);
-assert(m_inst_cache_hit_latency > 0);

 m_runningGarnetStandalone = p->garnet_standalone;
 }
@@ -650,23 +646,12 @@
 printAddress(msg->getPhysicalAddress()),
 RubyRequestType_to_string(secondary_type));

-// The Sequencer currently assesses instruction and data cache hit  
latency

-// for the top-level caches at the beginning of a memory access.
-// TODO: Eventually, this latency should be moved to represent the  
actual

-// cache access latency portion of the memory access. This will require
-// changing cache controller protocol files to assess the latency on  
the

-// access response path.
-Cycles latency(0);  // Initialize to zero to catch misconfigured  
latency

-if (secondary_type == RubyRequestType_IFETCH)
-latency = m_inst_cache_hit_latency;
-else
-latency = m_data_cache_hit_latency;
-
-// Send the message to the cache controller
+Tick latency = cyclesToTicks(
+ 
m_controller->mandatoryQueueLatency(secondary_type));

 assert(latency > 0);

 assert(m_mandatory_q_ptr != NULL);
-m_mandatory_q_ptr->enqueue(msg, clockEdge(), cyclesToTicks(latency));
+m_mandatory_q_ptr->enqueue(msg, clockEdge(), latency);
 }

 template 
diff --git a/src/mem/ruby/system/Sequencer.py  
b/src/mem/ruby/system/Sequencer.py

index 3546043..5c9dae8 100644
--- a/src/mem/ruby/system/Sequencer.py
+++ b/src/mem/ruby/system/Sequencer.py
@@ -63,12 +63,7 @@

icache = Param.RubyCache("")
dcache = Param.RubyCache("")
-   # Cache latencies currently assessed at the beginning of each access
-   # NOTE: Setting these values to a value greater than one will result in
-   # O3 CPU pipeline bubbles and negatively impact performance
-   # TODO: Latencies should be migrated into each top-level cache  
controller

-   icache_hit_latency = Param.Cycles(1, "Inst cache hit latency")
-   dcache_hit_latency = Param.Cycles(1, "Data cache hit latency")
+
max_outstanding_requests = Param.Int(16,
"max requests (incl. prefetches) outstanding")
deadlock_threshold = Param.Cycles(50,

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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Cache latencies for MOESI_CMP_dir

2019-04-26 Thread Tiago Mück (Gerrit)
t(is_valid(tbe));
 out_msg.addr := address;
 out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
@@ -961,7 +971,7 @@
   action(dd_sendDataToFwdGETX, "dd", desc="send data") {
 assert(is_valid(cache_entry));
 peek(requestNetwork_in, RequestMsg) {
-  enqueue(responseNetwork_out, ResponseMsg, response_latency) {
+  enqueue(responseNetwork_out, ResponseMsg, cacheResponseLatency()) {
 out_msg.addr := address;
 out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 out_msg.Sender := machineID;
@@ -981,7 +991,7 @@
   action(dd_sendDataToFwdGETS, "\dd", desc="send data") {
 assert(is_valid(cache_entry));
 peek(requestNetwork_in, RequestMsg) {
-  enqueue(responseNetwork_out, ResponseMsg, response_latency) {
+  enqueue(responseNetwork_out, ResponseMsg, cacheResponseLatency()) {
 out_msg.addr := address;
 out_msg.Type := CoherenceResponseType:DATA;
 out_msg.Sender := machineID;
@@ -1001,7 +1011,7 @@
   action(dd_sendExclusiveDataToFwdGETS, "\d\d", desc="send data") {
 assert(is_valid(cache_entry));
 peek(requestNetwork_in, RequestMsg) {
-  enqueue(responseNetwork_out, ResponseMsg, response_latency) {
+  enqueue(responseNetwork_out, ResponseMsg, cacheResponseLatency()) {
 out_msg.addr := address;
 out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 out_msg.Sender := machineID;

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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Prevent response stalls on MOESI_CMP_directory

2019-04-26 Thread Tiago Mück (Gerrit)
,
-  TBEs[in_msg.LineAddress]);
-} else if (in_msg.Type == SequencerRequestType:ST) {
-  trigger(Event:WriteRequest, in_msg.LineAddress,
-  TBEs[in_msg.LineAddress]);
-} else {
-  error("Invalid request type");
-}
-  }
-}
-  }
-
   in_port(dmaResponseQueue_in, ResponseMsg, responseFromDir, desc="...") {
 if (dmaResponseQueue_in.isReady(clockEdge())) {
   peek( dmaResponseQueue_in, ResponseMsg) {
@@ -155,6 +151,22 @@
 }
   }

+  in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
+if (dmaRequestQueue_in.isReady(clockEdge())) {
+  peek(dmaRequestQueue_in, SequencerMsg) {
+if (in_msg.Type == SequencerRequestType:LD ) {
+  trigger(Event:ReadRequest, in_msg.LineAddress,
+  TBEs[in_msg.LineAddress]);
+} else if (in_msg.Type == SequencerRequestType:ST) {
+  trigger(Event:WriteRequest, in_msg.LineAddress,
+  TBEs[in_msg.LineAddress]);
+} else {
+  error("Invalid request type");
+}
+  }
+}
+  }
+
   action(s_sendReadRequest, "s", desc="Send a DMA read request to memory")  
{

 peek(dmaRequestQueue_in, SequencerMsg) {
   enqueue(reqToDirectory_out, RequestMsg, request_latency) {
diff --git a/src/mem/protocol/MOESI_CMP_directory-msg.sm  
b/src/mem/protocol/MOESI_CMP_directory-msg.sm

index 5f6f826..7dc5822 100644
--- a/src/mem/protocol/MOESI_CMP_directory-msg.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-msg.sm
@@ -1,5 +1,16 @@
-
 /*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
  * All rights reserved.
  *
@@ -40,11 +51,10 @@
   PUTO,  desc="Put Owned";
   PUTO_SHARERS,  desc="Put Owned, but sharers exist so don't remove  
from sharers list";

   PUTS,  desc="Put Shared";
-  WB_ACK,desc="Writeback ack";
-  WB_ACK_DATA,desc="Writeback ack";
-  WB_NACK,   desc="Writeback neg. ack";
   INV,   desc="Invalidation";
-
+  WRITEBACK_CLEAN_DATA,   desc="Clean writeback (contains data)";
+  WRITEBACK_CLEAN_ACK,desc="Clean writeback (contains no data)";
+  WRITEBACK_DIRTY_DATA,   desc="Dirty writeback (contains data)";
   DMA_READ,  desc="DMA Read";
   DMA_WRITE, desc="DMA Write";
 }
@@ -56,9 +66,9 @@
   DATA_EXCLUSIVE,desc="Data, no processor has a copy";
   UNBLOCK,   desc="Unblock";
   UNBLOCK_EXCLUSIVE, desc="Unblock, we're in E/M";
-  WRITEBACK_CLEAN_DATA,   desc="Clean writeback (contains data)";
-  WRITEBACK_CLEAN_ACK,   desc="Clean writeback (contains no data)";
-  WRITEBACK_DIRTY_DATA,   desc="Dirty writeback (contains data)";
+  WB_ACK,desc="Writeback ack";
+  WB_ACK_DATA,   desc="Writeback ack";
+  WB_NACK,   desc="Writeback neg. ack";
   DMA_ACK,   desc="Ack that a DMA write completed";
 }

@@ -100,7 +110,9 @@
   bool functionalRead(Packet *pkt) {
 // Read only those messages that contain the data
 if (Type == CoherenceRequestType:DMA_READ ||
-Type == CoherenceRequestType:DMA_WRITE) {
+Type == CoherenceRequestType:DMA_WRITE ||
+Type == CoherenceRequestType:WRITEBACK_CLEAN_DATA ||
+Type == CoherenceRequestType:WRITEBACK_DIRTY_DATA) {
 return testAndRead(addr, DataBlk, pkt);
     }
 return false;
@@ -127,9 +139,7 @@
   bool functionalRead(Packet *pkt) {
 // Read only those messages that contain the data
 if (Type == CoherenceResponseType:DATA ||
-Type == CoherenceResponseType:DATA_EXCLUSIVE ||
-Type == CoherenceResponseType:WRITEBACK_CLEAN_DATA ||
-Type == CoherenceResponseType:WRITEBACK_DIRTY_DATA) {
+Type == CoherenceResponseType:DATA_EXCLUSIVE) {
 return testAndRead(addr, DataBlk, pkt);
 }
 return false;

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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Unique ranks for MOESI_CMP_dir in ports

2019-04-26 Thread Tiago Mück (Gerrit)
 peek(unblockNetwork_in, ResponseMsg) {
 if (in_msg.Type == CoherenceResponseType:UNBLOCK) {
@@ -268,7 +268,7 @@
 }
   }

-  in_port(requestQueue_in, RequestMsg, requestToDir) {
+  in_port(requestQueue_in, RequestMsg, requestToDir, rank=1) {
 if (requestQueue_in.isReady(clockEdge())) {
   peek(requestQueue_in, RequestMsg) {
 if (in_msg.Type == CoherenceRequestType:GETS) {
@@ -301,7 +301,7 @@
   }

   // off-chip memory request/response is done
-  in_port(memQueue_in, MemoryMsg, responseFromMemory) {
+  in_port(memQueue_in, MemoryMsg, responseFromMemory, rank=0) {
 if (memQueue_in.isReady(clockEdge())) {
   peek(memQueue_in, MemoryMsg) {
 if (in_msg.Type == MemoryRequestType:MEMORY_READ) {
diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm  
b/src/mem/protocol/MOESI_CMP_directory-dma.sm

index 16dc32a..a3a9f63 100644
--- a/src/mem/protocol/MOESI_CMP_directory-dma.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm
@@ -118,7 +118,7 @@
   out_port(respToDirectory_out, ResponseMsg, respToDir, desc="...");
   out_port(triggerQueue_out, TriggerMsg, triggerQueue, desc="...");

-  in_port(dmaResponseQueue_in, ResponseMsg, responseFromDir, desc="...") {
+  in_port(dmaResponseQueue_in, ResponseMsg, responseFromDir, rank=2) {
 if (dmaResponseQueue_in.isReady(clockEdge())) {
   peek( dmaResponseQueue_in, ResponseMsg) {
 if (in_msg.Type == CoherenceResponseType:DMA_ACK) {
@@ -139,7 +139,7 @@
   }

   // Trigger Queue
-  in_port(triggerQueue_in, TriggerMsg, triggerQueue) {
+  in_port(triggerQueue_in, TriggerMsg, triggerQueue, rank=1) {
 if (triggerQueue_in.isReady(clockEdge())) {
   peek(triggerQueue_in, TriggerMsg) {
 if (in_msg.Type == TriggerType:ALL_ACKS) {
@@ -151,7 +151,7 @@
 }
   }

-  in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
+  in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, rank=0) {
 if (dmaRequestQueue_in.isReady(clockEdge())) {
   peek(dmaRequestQueue_in, SequencerMsg) {
 if (in_msg.Type == SequencerRequestType:LD ) {

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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: MOESI_CMP_dir cleanup

2019-04-26 Thread Tiago Mück (Gerrit)
*

-  transition({II, IFGX, IFGS, ISFGS, IFGXX, IFLXO, OFGX, ILOW, ILOXW,  
ILOSW, ILOSXW, SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO,  
IFLOX, IFLOXX, IFLOSX, OLSXS, IGS, IGM, IGMLS, IGMO, IGMIO, OGMIO, IGMIOF,  
OGMIOF, MM, SS, OO, OI, MI, MII, OLSI, ILSI, SLSS, OLSS, OLSF, IGMIOFS,  
ILOSD, ILOSXD, ILOD, ILXD, ILOXD}, {L1_PUTO, L1_PUTS, L1_PUTS_only,  
L1_PUTX}) {
+  transition({II, IFGX, IFGS, ISFGS, IFGXX, IFLXO, ILOW, ILOXW, ILOSW,  
ILOSXW, SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO, IFLOX,  
IFLOXX, IFLOSX, OLSXS, IGS, IGM, IGMLS, IGMO, IGMIO, OGMIO, IGMIOF, OGMIOF,  
MM, SS, OO, OI, MI, MII, OLSI, ILSI, SLSS, OLSS, OLSF, IGMIOFS, ILOSD,  
ILOSXD, ILOD, ILXD, ILOXD}, {L1_PUTO, L1_PUTS, L1_PUTS_only, L1_PUTX}) {

 st_stallAndWaitL1RequestQueue;
   }

-  transition({II, IFGX, IFGS, ISFGS, IFGXX, IFLXO, OFGX, ILOW, ILOXW,  
ILOSW, ILOSXW, SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO,  
IFLOX, IFLOXX, IFLOSX, OLSXS, IGS, IGM, IGMLS, IGMO, IGMIO, OGMIO, IGMIOF,  
OGMIOF, MM, SS, OO, OI, MI, MII, OLSI, ILSI, SLSS, OLSS, OLSF, IGMIOFS,  
ILOSD, ILOSXD, ILOD, ILXD, ILOXD}, {L1_GETX, L1_GETS}) {
+  transition({II, IFGX, IFGS, ISFGS, IFGXX, IFLXO, ILOW, ILOXW, ILOSW,  
ILOSXW, SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO, IFLOX,  
IFLOXX, IFLOSX, OLSXS, IGS, IGM, IGMLS, IGMO, IGMIO, OGMIO, IGMIOF, OGMIOF,  
MM, SS, OO, OI, MI, MII, OLSI, ILSI, SLSS, OLSS, OLSF, IGMIOFS, ILOSD,  
ILOSXD, ILOD, ILXD, ILOXD}, {L1_GETX, L1_GETS}) {

 st_stallAndWaitL1RequestQueue;
   }

-  transition({IFGX, IFGS, ISFGS, IFGXX, IFLXO, OFGX, ILOW, ILOXW, ILOSW,  
ILOSXW, SLSW, OLSW, ILSW, IW, ILXW, OW, SW, OXW, OLSXW, IFLS, IFLO, IFLOX,  
IFLOXX, IFLOSX,OLSXS,  IGS, IGM, IGMLS, IGMO, MM, SS, OO, OI, MI, MII,  
OLSI, ILSI, SLSS, OLSS, OLSF, IGMIOFS, ILOSD, ILOSXD, ILOD, ILXD, ILOXD},  
L2_Replacement) {
+  transition({IFGX, IFGS, ISFGS, IFGXX, IFLXO, ILOW, ILOXW, ILOSW, ILOSXW,  
SLSW, OLSW, ILSW, IW, ILXW, OW, SW, OXW, OLSXW, IFLS, IFLO, IFLOX, IFLOXX,  
IFLOSX,OLSXS,  IGS, IGM, IGMLS, IGMO, MM, SS, OO, OI, MI, MII, OLSI, ILSI,  
SLSS, OLSS, OLSF, IGMIOFS, ILOSD, ILOSXD, ILOD, ILXD, ILOXD},  
L2_Replacement) {

 zz_recycleL1RequestQueue;
   }

-  transition({IFGX, IFGS, ISFGS, IFGXX, IFLXO, OFGX, ILOW, ILOXW, ILOSW,  
ILOSXW, SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO, IFLOX,  
IFLOXX, IFLOSX,OLSXS, IGS, IGM, MM, SS, OO, SLSS, OLSS, OLSF, IGMIOFS,  
ILOSD, ILOSXD, ILOD, ILXD, ILOXD}, {Fwd_GETX, Fwd_GETS, Fwd_DMA}) {
+  transition({IFGX, IFGS, ISFGS, IFGXX, IFLXO, ILOW, ILOXW, ILOSW, ILOSXW,  
SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO, IFLOX, IFLOXX,  
IFLOSX,OLSXS, IGS, IGM, MM, SS, OO, SLSS, OLSS, OLSF, IGMIOFS, ILOSD,  
ILOSXD, ILOD, ILXD, ILOXD}, {Fwd_GETX, Fwd_GETS, Fwd_DMA}) {

 zz_recycleGlobalRequestQueue;
   }

@@ -1637,7 +1619,7 @@
 zz_recycleGlobalRequestQueue;
   }

-  transition({IFGX, IFGS, ISFGS, IFGXX, IFLXO, OFGX, ILOW, ILOXW, ILOSW,  
ILOSXW, SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO, IFLOX,  
IFLOXX, IFLOSX,OLSXS, MM, SS, OO, SLSS, OLSS, OLSF, IGMIOFS, ILOSD, ILOSXD,  
ILOD, ILXD, ILOXD}, {Inv}) {
+  transition({IFGX, IFGS, ISFGS, IFGXX, IFLXO, ILOW, ILOXW, ILOSW, ILOSXW,  
SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO, IFLOX, IFLOXX,  
IFLOSX,OLSXS, MM, SS, OO, SLSS, OLSS, OLSF, IGMIOFS, ILOSD, ILOSXD, ILOD,  
ILXD, ILOXD}, {Inv}) {

 zz_recycleGlobalRequestQueue;
   }

diff --git a/src/mem/protocol/MOESI_CMP_directory-dir.sm  
b/src/mem/protocol/MOESI_CMP_directory-dir.sm

index f6b880d..f12d166 100644
--- a/src/mem/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm
@@ -69,7 +69,6 @@
 OO, AccessPermission:Busy, desc="Blocked, was in owned";
 MO, AccessPermission:Busy, desc="Blocked, going to owner or maybe  
modified";

 MM, AccessPermission:Busy, desc="Blocked, going to modified";
-MM_DMA, AccessPermission:Busy, desc="Blocked, going to I";

 MI, AccessPermission:Busy, desc="Blocked on a writeback";
 MIS, AccessPermission:Busy, desc="Blocked on a writeback, but don't  
remove from sharers when received";


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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Fix MOESI_CMP_dir debug msg

2019-04-26 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18409



Change subject: mem-ruby: Fix MOESI_CMP_dir debug msg
..

mem-ruby: Fix MOESI_CMP_dir debug msg

Change-Id: I3fd32bd2e81dbf9a8ea49a43727564b8a9d64767
Signed-off-by: Tiago Muck 
---
M src/mem/protocol/MOESI_CMP_directory-L2cache.sm
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm  
b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm

index 379e609..e006e86 100644
--- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
@@ -626,7 +626,7 @@
   trigger(Event:Data_Exclusive, in_msg.addr,
   getCacheEntry(in_msg.addr), TBEs[in_msg.addr]);
 } else if (in_msg.Type == CoherenceResponseType:UNBLOCK) {
-  DPRINTF(ProtocolTrace, "Received Unblock from L1 addr: %x\n",  
in_msg.addr);
+  DPRINTF(RubySlicc, "Received Unblock from L1 addr: %x\n",  
in_msg.addr);

   trigger(Event:Unblock, in_msg.addr,
   getCacheEntry(in_msg.addr), TBEs[in_msg.addr]);
 } else if (in_msg.Type == CoherenceResponseType:UNBLOCK_EXCLUSIVE)  
{


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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Do not change blocked msg enqueue info

2019-04-26 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18412



Change subject: mem-ruby: Do not change blocked msg enqueue info
..

mem-ruby: Do not change blocked msg enqueue info

Updating the message counter and enqueue times when adding blocked
messages back to the queue does not make a lot of sense since these
messages are not new arrivals.
More importantly, this may lead to starvation. See the scenario below:

1) Request A for a blocked line X arrives
2) A is handled; X is blocked so A is stalled
3) Request B for X arrives; Reponse for X arrives
4) Response is handled; X unblocked; A added back to the request queue
5) B is handled ahead of A (since A's arrival was updated);
   X may become blocked again

If new requests keep comming for X, A may will be stalled forever.

Change-Id: Icad79f3f716a870e91cb3455437b8b3c35f130ac
Signed-off-by: Tiago Muck 
---
M src/mem/ruby/network/MessageBuffer.cc
1 file changed, 5 insertions(+), 3 deletions(-)



diff --git a/src/mem/ruby/network/MessageBuffer.cc  
b/src/mem/ruby/network/MessageBuffer.cc

index 560b69c..03d1bb0 100644
--- a/src/mem/ruby/network/MessageBuffer.cc
+++ b/src/mem/ruby/network/MessageBuffer.cc
@@ -297,16 +297,18 @@
 MessageBuffer::reanalyzeList(list , Tick schdTick)
 {
 while (!lt.empty()) {
-m_msg_counter++;
 MsgPtr m = lt.front();
-m->setLastEnqueueTime(schdTick);
-m->setMsgCounter(m_msg_counter);
+assert(m->getLastEnqueueTime() <= schdTick);

 m_prio_heap.push_back(m);
 push_heap(m_prio_heap.begin(), m_prio_heap.end(),
   greater());

 m_consumer->scheduleEventAbsolute(schdTick);
+
+DPRINTF(RubyQueue, "Requeue arrival_time: %lld, Message: %s\n",
+schdTick, *(m.get()));
+
 lt.pop_front();
 }
 }

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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Change MOESI_CMP_Dir L2 addressing

2019-04-26 Thread Tiago Mück (Gerrit)
_msg.Acks;
@@ -614,8 +613,8 @@
   out_msg.Type := CoherenceResponseType:ACK;
   out_msg.Sender := machineID;
   out_msg.SenderMachine := MachineType:L1Cache;
-  out_msg.Destination.add(mapAddressToRange(address,  
MachineType:L2Cache,

-  l2_select_low_bit, l2_select_num_bits, intToID(0)));
+  out_msg.Destination.add(mapAddressToMachine(address,
+   
MachineType:L2Cache));

   out_msg.Acks := 0 - 1; // -1
   out_msg.MessageSize := MessageSizeType:Response_Control;
 }
@@ -629,8 +628,8 @@
   out_msg.Type := CoherenceResponseType:UNBLOCK;
   out_msg.Sender := machineID;
   out_msg.SenderMachine := MachineType:L1Cache;
-  out_msg.Destination.add(mapAddressToRange(address,  
MachineType:L2Cache,

-  l2_select_low_bit, l2_select_num_bits, intToID(0)));
+  out_msg.Destination.add(mapAddressToMachine(address,
+  MachineType:L2Cache));
   out_msg.MessageSize := MessageSizeType:Unblock_Control;
 }
   }
@@ -641,8 +640,8 @@
   out_msg.Type := CoherenceResponseType:UNBLOCK_EXCLUSIVE;
   out_msg.Sender := machineID;
   out_msg.SenderMachine := MachineType:L1Cache;
-  out_msg.Destination.add(mapAddressToRange(address,  
MachineType:L2Cache,

-  l2_select_low_bit, l2_select_num_bits, intToID(0)));
+  out_msg.Destination.add(mapAddressToMachine(address,
+  MachineType:L2Cache));
   out_msg.MessageSize := MessageSizeType:Unblock_Control;
 }
   }
@@ -752,8 +751,8 @@
 out_msg.Type := CoherenceResponseType:DMA_ACK;
 out_msg.Sender := machineID;
 out_msg.SenderMachine := MachineType:L1Cache;
-out_msg.Destination.add(mapAddressToRange(address,  
MachineType:L2Cache,

-  l2_select_low_bit, l2_select_num_bits, intToID(0)));
+out_msg.Destination.add(mapAddressToMachine(address,
+MachineType:L2Cache));
 out_msg.Dirty := false;
 out_msg.Acks := 1;
 out_msg.MessageSize := MessageSizeType:Response_Control;
@@ -785,8 +784,8 @@
   out_msg.Type := CoherenceResponseType:DATA;
   out_msg.Sender := machineID;
   out_msg.SenderMachine := MachineType:L1Cache;
-  out_msg.Destination.add(mapAddressToRange(address,  
MachineType:L2Cache,

-  l2_select_low_bit, l2_select_num_bits, intToID(0)));
+  out_msg.Destination.add(mapAddressToMachine(address,
+   
MachineType:L2Cache));

   out_msg.DataBlk := tbe.DataBlk;
   // out_msg.Dirty := tbe.Dirty;
   out_msg.Dirty := false;
@@ -819,8 +818,8 @@
   out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
   out_msg.Sender := machineID;
   out_msg.SenderMachine := MachineType:L1Cache;
-  out_msg.Destination.add(mapAddressToRange(address,  
MachineType:L2Cache,

-  l2_select_low_bit, l2_select_num_bits, intToID(0)));
+  out_msg.Destination.add(mapAddressToMachine(address,
+   
MachineType:L2Cache));

   out_msg.DataBlk := tbe.DataBlk;
   out_msg.Dirty := tbe.Dirty;
   out_msg.Acks := in_msg.Acks;
@@ -837,8 +836,8 @@
   out_msg.addr := address;
   out_msg.Requestor := machineID;
   out_msg.RequestorMachine := MachineType:L1Cache;
-  out_msg.Destination.add(mapAddressToRange(address,  
MachineType:L2Cache,

-  l2_select_low_bit, l2_select_num_bits, intToID(0)));
+  out_msg.Destination.add(mapAddressToMachine(address,
+  MachineType:L2Cache));
   if (tbe.Dirty) {
 out_msg.Type := CoherenceRequestType:WRITEBACK_DIRTY_DATA;
   } else {

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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Fix MOESI_CMP_directory blocked line handling

2019-04-26 Thread Tiago Mück (Gerrit)
Hello Matthew Poremba, Bradford Beckmann, Xianwei Zhang, Anthony Gutierrez,  
Jason Lowe-Power, Nikos Nikoleris,


I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/17568

to look at the new patch set (#2).

Change subject: mem-ruby: Fix MOESI_CMP_directory blocked line handling
..

mem-ruby: Fix MOESI_CMP_directory blocked line handling

Using recycle in the L2 controllers to put messages back into the buffer
may lead to starvation when there are many L1 requests for the same line.
This can easily trigger the deadlock detection mechanism in configurations
with many cores (16+). Replacing recycle by stall_and_wait for L1
requests avoids this issue. wakeUpBuffers calls were added to all
transitions from transient to stable states.

Change-Id: I28b8aeacc48919ccf38e69653cd9205a4153514b
Signed-off-by: Tiago Muck 
---
M src/mem/protocol/MOESI_CMP_directory-L2cache.sm
1 file changed, 67 insertions(+), 10 deletions(-)


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Gerrit-PatchSet: 2
Gerrit-Owner: Tiago Mück 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Bradford Beckmann 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: Nikos Nikoleris 
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Gerrit-Reviewer: Xianwei Zhang 
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[gem5-dev] Change in gem5/gem5[master]: misc: Added dot_writer for Ruby's network topology

2019-04-03 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded a new patch set (#2) to the change originally  
created by Giacomo Travaglini. (  
https://gem5-review.googlesource.com/c/public/gem5/+/17548 )


Change subject: misc: Added dot_writer for Ruby's network topology
..

misc: Added dot_writer for Ruby's network topology

Change-Id: Ic71ca7bc2eb4174d70afa368bc9cc987f3df89e9
---
M src/python/SConscript
M src/python/m5/simulate.py
A src/python/m5/util/dot_writer_ruby.py
3 files changed, 137 insertions(+), 1 deletion(-)


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Gerrit-Change-Id: Ic71ca7bc2eb4174d70afa368bc9cc987f3df89e9
Gerrit-Change-Number: 17548
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: Pouya Fotouhi 
Gerrit-Reviewer: Tiago Mück 
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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Fix MOESI_CMP_directory blocked line handling

2019-03-22 Thread Tiago Mück (Gerrit)
c_sendDataFromTBEToFwdGETX;
 n_popTriggerQueue;
+wa_wakeUpDependents;
   }

   transition(OLSI, Fwd_GETS) {
@@ -2787,33 +2862,39 @@
 qq_sendDataFromTBEToMemory;
 s_deallocateTBE;
 m_popRequestQueue;
+wa_wakeUpDependents;
   }

   transition(MII, Writeback_Nack, I) {
 s_deallocateTBE;
 m_popRequestQueue;
+wa_wakeUpDependents;
   }

   transition(OI, Writeback_Nack) {
 b_issuePUTO;
 m_popRequestQueue;
+wa_wakeUpDependents;
   }

   transition(OLSI, Writeback_Ack, ILS) {
 qq_sendDataFromTBEToMemory;
 s_deallocateTBE;
 m_popRequestQueue;
+wa_wakeUpDependents;
   }

   transition(MII, Writeback_Ack, I) {
 f_sendUnblock;
 s_deallocateTBE;
 m_popRequestQueue;
+wa_wakeUpDependents;
   }

   transition(ILSI, Writeback_Ack, ILS) {
 f_sendUnblock;
 s_deallocateTBE;
 m_popRequestQueue;
+wa_wakeUpDependents;
   }
 }

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