[gem5-dev] Change in gem5/gem5[develop]: cpu: HTM Implementation for O3CPU
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/30328 ) Change subject: cpu: HTM Implementation for O3CPU .. cpu: HTM Implementation for O3CPU JIRA: https://gem5.atlassian.net/browse/GEM5-587 Change-Id: I83787f4594963a15d856b81ad283b4f032d1c007 Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30328 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/cpu/base_dyn_inst.hh M src/cpu/base_dyn_inst_impl.hh M src/cpu/o3/commit.hh M src/cpu/o3/commit_impl.hh M src/cpu/o3/cpu.cc M src/cpu/o3/cpu.hh M src/cpu/o3/iew.hh M src/cpu/o3/iew_impl.hh M src/cpu/o3/lsq.hh M src/cpu/o3/lsq_impl.hh M src/cpu/o3/lsq_unit.hh M src/cpu/o3/lsq_unit_impl.hh M src/cpu/o3/mem_dep_unit_impl.hh M src/cpu/o3/thread_context_impl.hh M src/cpu/o3/thread_state.hh 15 files changed, 684 insertions(+), 32 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index 31dee6c..b0e9ef2 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -61,6 +61,7 @@ #include "cpu/op_class.hh" #include "cpu/static_inst.hh" #include "cpu/translation.hh" +#include "debug/HtmCpu.hh" #include "mem/packet.hh" #include "mem/request.hh" #include "sim/byteswap.hh" @@ -140,6 +141,7 @@ IsStrictlyOrdered, ReqMade, MemOpDone, +HtmFromTransaction, MaxFlags }; @@ -240,6 +242,11 @@ // Need a copy of main request pointer to verify on writes. RequestPtr reqToVerify; + private: +// hardware transactional memory +uint64_t htmUid; +uint64_t htmDepth; + protected: /** Flattened register index of the destination registers of this * instruction. @@ -548,8 +555,8 @@ uint64_t getHtmTransactionUid() const override { -panic("Not yet implemented\n"); -return 0; +assert(instFlags[HtmFromTransaction]); +return this->htmUid; } uint64_t newHtmTransactionUid() const override @@ -560,14 +567,35 @@ bool inHtmTransactionalState() const override { -panic("Not yet implemented\n"); -return false; +return instFlags[HtmFromTransaction]; } uint64_t getHtmTransactionalDepth() const override { -panic("Not yet implemented\n"); -return 0; +if (inHtmTransactionalState()) +return this->htmDepth; +else +return 0; +} + +void setHtmTransactionalState(uint64_t htm_uid, uint64_t htm_depth) +{ +instFlags.set(HtmFromTransaction); +htmUid = htm_uid; +htmDepth = htm_depth; +} + +void clearHtmTransactionalState() +{ +if (inHtmTransactionalState()) { +DPRINTF(HtmCpu, +"clearing instuction's transactional state htmUid=%u\n", +getHtmTransactionUid()); + +instFlags.reset(HtmFromTransaction); +htmUid = -1; +htmDepth = 0; +} } /** Temporarily sets this instruction as a serialize before instruction. */ @@ -997,8 +1025,9 @@ Fault BaseDynInst::initiateHtmCmd(Request::Flags flags) { -panic("Not yet implemented\n"); -return NoFault; +return cpu->pushRequest( +dynamic_cast(this), +/* ld */ true, nullptr, 8, 0x0ul, flags, nullptr, nullptr); } template diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh index 45b938d..bfe8ff5 100644 --- a/src/cpu/base_dyn_inst_impl.hh +++ b/src/cpu/base_dyn_inst_impl.hh @@ -95,6 +95,9 @@ physEffAddr = 0; readyRegs = 0; memReqFlags = 0; +// hardware transactional memory +htmUid = -1; +htmDepth = 0; status.reset(); diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh index 69d1c86..85d00a9 100644 --- a/src/cpu/o3/commit.hh +++ b/src/cpu/o3/commit.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2012, 2014 ARM Limited + * Copyright (c) 2010-2012, 2014, 2019 ARM Limited * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -205,6 +205,12 @@ /** Deschedules a thread from scheduling */ void deactivateThread(ThreadID tid); +/** Is the CPU currently processing a HTM transaction? */ +bool executingHtmTransaction(ThreadID) const; + +/* Reset HTM tracking, e.g. after an abort */ +void resetHtmStartsStops(ThreadID); + /** Ticks the commit stage, which tries to commit instructions. */ void tick(); @@ -473,6 +479,11 @@ /** Updates commit stats based on this instruction. */ void updateComInstStats(const DynInstPtr &inst); + +// HTM +int htmStarts[Impl::MaxThreads]; +int htmStops[Impl::MaxThreads]; + /** Stat for the total n
[gem5-dev] Change in gem5/gem5[develop]: cpu: HTM Implementation for O3CPU
Hello Timothy Hayes, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/30328 to review the following change. Change subject: cpu: HTM Implementation for O3CPU .. cpu: HTM Implementation for O3CPU JIRA: https://gem5.atlassian.net/browse/GEM5-587 Change-Id: I83787f4594963a15d856b81ad283b4f032d1c007 Signed-off-by: Giacomo Travaglini --- M src/cpu/base_dyn_inst.hh M src/cpu/base_dyn_inst_impl.hh M src/cpu/o3/commit.hh M src/cpu/o3/commit_impl.hh M src/cpu/o3/cpu.cc M src/cpu/o3/cpu.hh M src/cpu/o3/iew.hh M src/cpu/o3/iew_impl.hh M src/cpu/o3/lsq.hh M src/cpu/o3/lsq_impl.hh M src/cpu/o3/lsq_unit.hh M src/cpu/o3/lsq_unit_impl.hh M src/cpu/o3/mem_dep_unit_impl.hh M src/cpu/o3/thread_context_impl.hh M src/cpu/o3/thread_state.hh 15 files changed, 676 insertions(+), 32 deletions(-) diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index 119b806..6d929ac 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -61,6 +61,7 @@ #include "cpu/op_class.hh" #include "cpu/static_inst.hh" #include "cpu/translation.hh" +#include "debug/HtmCpu.hh" #include "mem/packet.hh" #include "mem/request.hh" #include "sim/byteswap.hh" @@ -140,6 +141,7 @@ IsStrictlyOrdered, ReqMade, MemOpDone, +HtmFromTransaction, MaxFlags }; @@ -240,6 +242,11 @@ // Need a copy of main request pointer to verify on writes. RequestPtr reqToVerify; + private: +// hardware transactional memory +uint64_t htmUid; +uint64_t htmDepth; + protected: /** Flattened register index of the destination registers of this * instruction. @@ -548,8 +555,8 @@ uint64_t getHtmTransactionUid() const override { -panic("Not yet implemented\n"); -return 0; +assert(instFlags[HtmFromTransaction]); +return this->htmUid; } uint64_t newHtmTransactionUid() const override @@ -560,14 +567,35 @@ bool inHtmTransactionalState() const override { -panic("Not yet implemented\n"); -return false; +return instFlags[HtmFromTransaction]; } uint64_t getHtmTransactionalDepth() const override { -panic("Not yet implemented\n"); -return 0; +if (inHtmTransactionalState()) +return this->htmDepth; +else +return 0; +} + +void setHtmTransactionalState(uint64_t htm_uid, uint64_t htm_depth) +{ +instFlags.set(HtmFromTransaction); +htmUid = htm_uid; +htmDepth = htm_depth; +} + +void clearHtmTransactionalState() +{ +if (inHtmTransactionalState()) { +DPRINTF(HtmCpu, +"clearing instuction's transactional state htmUid=%u\n", +getHtmTransactionUid()); + +instFlags.reset(HtmFromTransaction); +htmUid = -1; +htmDepth = 0; +} } /** Temporarily sets this instruction as a serialize before instruction. */ @@ -997,8 +1025,9 @@ Fault BaseDynInst::initiateHtmCmd(Request::Flags flags) { -panic("Not yet implemented\n"); -return NoFault; +return cpu->pushRequest( +dynamic_cast(this), +/* ld */ true, nullptr, 8, 0x0ul, flags, nullptr, nullptr); } template diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh index 45b938d..bfe8ff5 100644 --- a/src/cpu/base_dyn_inst_impl.hh +++ b/src/cpu/base_dyn_inst_impl.hh @@ -95,6 +95,9 @@ physEffAddr = 0; readyRegs = 0; memReqFlags = 0; +// hardware transactional memory +htmUid = -1; +htmDepth = 0; status.reset(); diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh index 69d1c86..85d00a9 100644 --- a/src/cpu/o3/commit.hh +++ b/src/cpu/o3/commit.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2012, 2014 ARM Limited + * Copyright (c) 2010-2012, 2014, 2019 ARM Limited * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -205,6 +205,12 @@ /** Deschedules a thread from scheduling */ void deactivateThread(ThreadID tid); +/** Is the CPU currently processing a HTM transaction? */ +bool executingHtmTransaction(ThreadID) const; + +/* Reset HTM tracking, e.g. after an abort */ +void resetHtmStartsStops(ThreadID); + /** Ticks the commit stage, which tries to commit instructions. */ void tick(); @@ -473,6 +479,11 @@ /** Updates commit stats based on this instruction. */ void updateComInstStats(const DynInstPtr &inst); + +// HTM +int htmStarts[Impl::MaxThreads]; +int htmStops[Impl::MaxThreads]; + /** Stat for the total number of squashed instructions discarded by commit. */ Stats::Scalar commitSquashedInsts; diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index 667f42b..68823d6 100644 --- a/src